1d405a98cSShreyas B. Prabhu /* 2d405a98cSShreyas B. Prabhu * PowerNV cpuidle code 3d405a98cSShreyas B. Prabhu * 4d405a98cSShreyas B. Prabhu * Copyright 2015 IBM Corp. 5d405a98cSShreyas B. Prabhu * 6d405a98cSShreyas B. Prabhu * This program is free software; you can redistribute it and/or 7d405a98cSShreyas B. Prabhu * modify it under the terms of the GNU General Public License 8d405a98cSShreyas B. Prabhu * as published by the Free Software Foundation; either version 9d405a98cSShreyas B. Prabhu * 2 of the License, or (at your option) any later version. 10d405a98cSShreyas B. Prabhu */ 11d405a98cSShreyas B. Prabhu 12d405a98cSShreyas B. Prabhu #include <linux/types.h> 13d405a98cSShreyas B. Prabhu #include <linux/mm.h> 14d405a98cSShreyas B. Prabhu #include <linux/slab.h> 15d405a98cSShreyas B. Prabhu #include <linux/of.h> 165703d2f4SShreyas B. Prabhu #include <linux/device.h> 175703d2f4SShreyas B. Prabhu #include <linux/cpu.h> 18d405a98cSShreyas B. Prabhu 19d405a98cSShreyas B. Prabhu #include <asm/firmware.h> 204bece972SMichael Ellerman #include <asm/machdep.h> 21d405a98cSShreyas B. Prabhu #include <asm/opal.h> 22d405a98cSShreyas B. Prabhu #include <asm/cputhreads.h> 23d405a98cSShreyas B. Prabhu #include <asm/cpuidle.h> 24d405a98cSShreyas B. Prabhu #include <asm/code-patching.h> 25d405a98cSShreyas B. Prabhu #include <asm/smp.h> 262201f994SNicholas Piggin #include <asm/runlatch.h> 27d405a98cSShreyas B. Prabhu 28d405a98cSShreyas B. Prabhu #include "powernv.h" 29d405a98cSShreyas B. Prabhu #include "subcore.h" 30d405a98cSShreyas B. Prabhu 31bcef83a0SShreyas B. Prabhu /* Power ISA 3.0 allows for stop states 0x0 - 0xF */ 32bcef83a0SShreyas B. Prabhu #define MAX_STOP_STATE 0xF 33bcef83a0SShreyas B. Prabhu 341e1601b3SAkshay Adiga #define P9_STOP_SPR_MSR 2000 351e1601b3SAkshay Adiga #define P9_STOP_SPR_PSSCR 855 361e1601b3SAkshay Adiga 37d405a98cSShreyas B. Prabhu static u32 supported_cpuidle_states; 38d405a98cSShreyas B. Prabhu 391e1601b3SAkshay Adiga /* 401e1601b3SAkshay Adiga * The default stop state that will be used by ppc_md.power_save 411e1601b3SAkshay Adiga * function on platforms that support stop instruction. 421e1601b3SAkshay Adiga */ 431e1601b3SAkshay Adiga static u64 pnv_default_stop_val; 441e1601b3SAkshay Adiga static u64 pnv_default_stop_mask; 451e1601b3SAkshay Adiga static bool default_stop_found; 461e1601b3SAkshay Adiga 471e1601b3SAkshay Adiga /* 481e1601b3SAkshay Adiga * First deep stop state. Used to figure out when to save/restore 491e1601b3SAkshay Adiga * hypervisor context. 501e1601b3SAkshay Adiga */ 511e1601b3SAkshay Adiga u64 pnv_first_deep_stop_state = MAX_STOP_STATE; 521e1601b3SAkshay Adiga 531e1601b3SAkshay Adiga /* 541e1601b3SAkshay Adiga * psscr value and mask of the deepest stop idle state. 551e1601b3SAkshay Adiga * Used when a cpu is offlined. 561e1601b3SAkshay Adiga */ 571e1601b3SAkshay Adiga static u64 pnv_deepest_stop_psscr_val; 581e1601b3SAkshay Adiga static u64 pnv_deepest_stop_psscr_mask; 591e1601b3SAkshay Adiga static bool deepest_stop_found; 601e1601b3SAkshay Adiga 61bcef83a0SShreyas B. Prabhu static int pnv_save_sprs_for_deep_states(void) 62d405a98cSShreyas B. Prabhu { 63d405a98cSShreyas B. Prabhu int cpu; 64d405a98cSShreyas B. Prabhu int rc; 65d405a98cSShreyas B. Prabhu 66d405a98cSShreyas B. Prabhu /* 67446957baSAdam Buchbinder * hid0, hid1, hid4, hid5, hmeer and lpcr values are symmetric across 68d405a98cSShreyas B. Prabhu * all cpus at boot. Get these reg values of current cpu and use the 69446957baSAdam Buchbinder * same across all cpus. 70d405a98cSShreyas B. Prabhu */ 71d405a98cSShreyas B. Prabhu uint64_t lpcr_val = mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1; 72d405a98cSShreyas B. Prabhu uint64_t hid0_val = mfspr(SPRN_HID0); 73d405a98cSShreyas B. Prabhu uint64_t hid1_val = mfspr(SPRN_HID1); 74d405a98cSShreyas B. Prabhu uint64_t hid4_val = mfspr(SPRN_HID4); 75d405a98cSShreyas B. Prabhu uint64_t hid5_val = mfspr(SPRN_HID5); 76d405a98cSShreyas B. Prabhu uint64_t hmeer_val = mfspr(SPRN_HMEER); 771e1601b3SAkshay Adiga uint64_t msr_val = MSR_IDLE; 781e1601b3SAkshay Adiga uint64_t psscr_val = pnv_deepest_stop_psscr_val; 79d405a98cSShreyas B. Prabhu 80d405a98cSShreyas B. Prabhu for_each_possible_cpu(cpu) { 81d405a98cSShreyas B. Prabhu uint64_t pir = get_hard_smp_processor_id(cpu); 82d405a98cSShreyas B. Prabhu uint64_t hsprg0_val = (uint64_t)&paca[cpu]; 83d405a98cSShreyas B. Prabhu 84d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HSPRG0, hsprg0_val); 85d405a98cSShreyas B. Prabhu if (rc != 0) 86d405a98cSShreyas B. Prabhu return rc; 87d405a98cSShreyas B. Prabhu 88d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_LPCR, lpcr_val); 89d405a98cSShreyas B. Prabhu if (rc != 0) 90d405a98cSShreyas B. Prabhu return rc; 91d405a98cSShreyas B. Prabhu 921e1601b3SAkshay Adiga if (cpu_has_feature(CPU_FTR_ARCH_300)) { 931e1601b3SAkshay Adiga rc = opal_slw_set_reg(pir, P9_STOP_SPR_MSR, msr_val); 941e1601b3SAkshay Adiga if (rc) 951e1601b3SAkshay Adiga return rc; 961e1601b3SAkshay Adiga 971e1601b3SAkshay Adiga rc = opal_slw_set_reg(pir, 981e1601b3SAkshay Adiga P9_STOP_SPR_PSSCR, psscr_val); 991e1601b3SAkshay Adiga 1001e1601b3SAkshay Adiga if (rc) 1011e1601b3SAkshay Adiga return rc; 1021e1601b3SAkshay Adiga } 1031e1601b3SAkshay Adiga 104d405a98cSShreyas B. Prabhu /* HIDs are per core registers */ 105d405a98cSShreyas B. Prabhu if (cpu_thread_in_core(cpu) == 0) { 106d405a98cSShreyas B. Prabhu 107d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HMEER, hmeer_val); 108d405a98cSShreyas B. Prabhu if (rc != 0) 109d405a98cSShreyas B. Prabhu return rc; 110d405a98cSShreyas B. Prabhu 111d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID0, hid0_val); 112d405a98cSShreyas B. Prabhu if (rc != 0) 113d405a98cSShreyas B. Prabhu return rc; 114d405a98cSShreyas B. Prabhu 1151e1601b3SAkshay Adiga /* Only p8 needs to set extra HID regiters */ 1161e1601b3SAkshay Adiga if (!cpu_has_feature(CPU_FTR_ARCH_300)) { 1171e1601b3SAkshay Adiga 118d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID1, hid1_val); 119d405a98cSShreyas B. Prabhu if (rc != 0) 120d405a98cSShreyas B. Prabhu return rc; 121d405a98cSShreyas B. Prabhu 122d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID4, hid4_val); 123d405a98cSShreyas B. Prabhu if (rc != 0) 124d405a98cSShreyas B. Prabhu return rc; 125d405a98cSShreyas B. Prabhu 126d405a98cSShreyas B. Prabhu rc = opal_slw_set_reg(pir, SPRN_HID5, hid5_val); 127d405a98cSShreyas B. Prabhu if (rc != 0) 128d405a98cSShreyas B. Prabhu return rc; 129d405a98cSShreyas B. Prabhu } 130d405a98cSShreyas B. Prabhu } 1311e1601b3SAkshay Adiga } 132d405a98cSShreyas B. Prabhu 133d405a98cSShreyas B. Prabhu return 0; 134d405a98cSShreyas B. Prabhu } 135d405a98cSShreyas B. Prabhu 136d405a98cSShreyas B. Prabhu static void pnv_alloc_idle_core_states(void) 137d405a98cSShreyas B. Prabhu { 138d405a98cSShreyas B. Prabhu int i, j; 139d405a98cSShreyas B. Prabhu int nr_cores = cpu_nr_cores(); 140d405a98cSShreyas B. Prabhu u32 *core_idle_state; 141d405a98cSShreyas B. Prabhu 142d405a98cSShreyas B. Prabhu /* 1435f221c3cSGautham R. Shenoy * core_idle_state - The lower 8 bits track the idle state of 1445f221c3cSGautham R. Shenoy * each thread of the core. 1455f221c3cSGautham R. Shenoy * 1465f221c3cSGautham R. Shenoy * The most significant bit is the lock bit. 1475f221c3cSGautham R. Shenoy * 1485f221c3cSGautham R. Shenoy * Initially all the bits corresponding to threads_per_core 1495f221c3cSGautham R. Shenoy * are set. They are cleared when the thread enters deep idle 1505f221c3cSGautham R. Shenoy * state like sleep and winkle/stop. 1515f221c3cSGautham R. Shenoy * 1525f221c3cSGautham R. Shenoy * Initially the lock bit is cleared. The lock bit has 2 1535f221c3cSGautham R. Shenoy * purposes: 1545f221c3cSGautham R. Shenoy * a. While the first thread in the core waking up from 1555f221c3cSGautham R. Shenoy * idle is restoring core state, it prevents other 1565f221c3cSGautham R. Shenoy * threads in the core from switching to process 1575f221c3cSGautham R. Shenoy * context. 1585f221c3cSGautham R. Shenoy * b. While the last thread in the core is saving the 1595f221c3cSGautham R. Shenoy * core state, it prevents a different thread from 1605f221c3cSGautham R. Shenoy * waking up. 161d405a98cSShreyas B. Prabhu */ 162d405a98cSShreyas B. Prabhu for (i = 0; i < nr_cores; i++) { 163d405a98cSShreyas B. Prabhu int first_cpu = i * threads_per_core; 164d405a98cSShreyas B. Prabhu int node = cpu_to_node(first_cpu); 16517ed4c8fSGautham R. Shenoy size_t paca_ptr_array_size; 166d405a98cSShreyas B. Prabhu 167d405a98cSShreyas B. Prabhu core_idle_state = kmalloc_node(sizeof(u32), GFP_KERNEL, node); 1685f221c3cSGautham R. Shenoy *core_idle_state = (1 << threads_per_core) - 1; 16917ed4c8fSGautham R. Shenoy paca_ptr_array_size = (threads_per_core * 17017ed4c8fSGautham R. Shenoy sizeof(struct paca_struct *)); 171d405a98cSShreyas B. Prabhu 172d405a98cSShreyas B. Prabhu for (j = 0; j < threads_per_core; j++) { 173d405a98cSShreyas B. Prabhu int cpu = first_cpu + j; 174d405a98cSShreyas B. Prabhu 175d405a98cSShreyas B. Prabhu paca[cpu].core_idle_state_ptr = core_idle_state; 176d405a98cSShreyas B. Prabhu paca[cpu].thread_idle_state = PNV_THREAD_RUNNING; 177d405a98cSShreyas B. Prabhu paca[cpu].thread_mask = 1 << j; 17817ed4c8fSGautham R. Shenoy if (!cpu_has_feature(CPU_FTR_POWER9_DD1)) 17917ed4c8fSGautham R. Shenoy continue; 18017ed4c8fSGautham R. Shenoy paca[cpu].thread_sibling_pacas = 18117ed4c8fSGautham R. Shenoy kmalloc_node(paca_ptr_array_size, 18217ed4c8fSGautham R. Shenoy GFP_KERNEL, node); 183d405a98cSShreyas B. Prabhu } 184d405a98cSShreyas B. Prabhu } 185d405a98cSShreyas B. Prabhu 186d405a98cSShreyas B. Prabhu update_subcore_sibling_mask(); 187d405a98cSShreyas B. Prabhu 188bcef83a0SShreyas B. Prabhu if (supported_cpuidle_states & OPAL_PM_LOSE_FULL_CONTEXT) 189bcef83a0SShreyas B. Prabhu pnv_save_sprs_for_deep_states(); 190d405a98cSShreyas B. Prabhu } 191d405a98cSShreyas B. Prabhu 192d405a98cSShreyas B. Prabhu u32 pnv_get_supported_cpuidle_states(void) 193d405a98cSShreyas B. Prabhu { 194d405a98cSShreyas B. Prabhu return supported_cpuidle_states; 195d405a98cSShreyas B. Prabhu } 196d405a98cSShreyas B. Prabhu EXPORT_SYMBOL_GPL(pnv_get_supported_cpuidle_states); 197d405a98cSShreyas B. Prabhu 1985703d2f4SShreyas B. Prabhu static void pnv_fastsleep_workaround_apply(void *info) 1995703d2f4SShreyas B. Prabhu 2005703d2f4SShreyas B. Prabhu { 2015703d2f4SShreyas B. Prabhu int rc; 2025703d2f4SShreyas B. Prabhu int *err = info; 2035703d2f4SShreyas B. Prabhu 2045703d2f4SShreyas B. Prabhu rc = opal_config_cpu_idle_state(OPAL_CONFIG_IDLE_FASTSLEEP, 2055703d2f4SShreyas B. Prabhu OPAL_CONFIG_IDLE_APPLY); 2065703d2f4SShreyas B. Prabhu if (rc) 2075703d2f4SShreyas B. Prabhu *err = 1; 2085703d2f4SShreyas B. Prabhu } 2095703d2f4SShreyas B. Prabhu 2105703d2f4SShreyas B. Prabhu /* 2115703d2f4SShreyas B. Prabhu * Used to store fastsleep workaround state 2125703d2f4SShreyas B. Prabhu * 0 - Workaround applied/undone at fastsleep entry/exit path (Default) 2135703d2f4SShreyas B. Prabhu * 1 - Workaround applied once, never undone. 2145703d2f4SShreyas B. Prabhu */ 2155703d2f4SShreyas B. Prabhu static u8 fastsleep_workaround_applyonce; 2165703d2f4SShreyas B. Prabhu 2175703d2f4SShreyas B. Prabhu static ssize_t show_fastsleep_workaround_applyonce(struct device *dev, 2185703d2f4SShreyas B. Prabhu struct device_attribute *attr, char *buf) 2195703d2f4SShreyas B. Prabhu { 2205703d2f4SShreyas B. Prabhu return sprintf(buf, "%u\n", fastsleep_workaround_applyonce); 2215703d2f4SShreyas B. Prabhu } 2225703d2f4SShreyas B. Prabhu 2235703d2f4SShreyas B. Prabhu static ssize_t store_fastsleep_workaround_applyonce(struct device *dev, 2245703d2f4SShreyas B. Prabhu struct device_attribute *attr, const char *buf, 2255703d2f4SShreyas B. Prabhu size_t count) 2265703d2f4SShreyas B. Prabhu { 2275703d2f4SShreyas B. Prabhu cpumask_t primary_thread_mask; 2285703d2f4SShreyas B. Prabhu int err; 2295703d2f4SShreyas B. Prabhu u8 val; 2305703d2f4SShreyas B. Prabhu 2315703d2f4SShreyas B. Prabhu if (kstrtou8(buf, 0, &val) || val != 1) 2325703d2f4SShreyas B. Prabhu return -EINVAL; 2335703d2f4SShreyas B. Prabhu 2345703d2f4SShreyas B. Prabhu if (fastsleep_workaround_applyonce == 1) 2355703d2f4SShreyas B. Prabhu return count; 2365703d2f4SShreyas B. Prabhu 2375703d2f4SShreyas B. Prabhu /* 2385703d2f4SShreyas B. Prabhu * fastsleep_workaround_applyonce = 1 implies 2395703d2f4SShreyas B. Prabhu * fastsleep workaround needs to be left in 'applied' state on all 2405703d2f4SShreyas B. Prabhu * the cores. Do this by- 2415703d2f4SShreyas B. Prabhu * 1. Patching out the call to 'undo' workaround in fastsleep exit path 2425703d2f4SShreyas B. Prabhu * 2. Sending ipi to all the cores which have at least one online thread 2435703d2f4SShreyas B. Prabhu * 3. Patching out the call to 'apply' workaround in fastsleep entry 2445703d2f4SShreyas B. Prabhu * path 2455703d2f4SShreyas B. Prabhu * There is no need to send ipi to cores which have all threads 2465703d2f4SShreyas B. Prabhu * offlined, as last thread of the core entering fastsleep or deeper 2475703d2f4SShreyas B. Prabhu * state would have applied workaround. 2485703d2f4SShreyas B. Prabhu */ 2495703d2f4SShreyas B. Prabhu err = patch_instruction( 2505703d2f4SShreyas B. Prabhu (unsigned int *)pnv_fastsleep_workaround_at_exit, 2515703d2f4SShreyas B. Prabhu PPC_INST_NOP); 2525703d2f4SShreyas B. Prabhu if (err) { 2535703d2f4SShreyas B. Prabhu pr_err("fastsleep_workaround_applyonce change failed while patching pnv_fastsleep_workaround_at_exit"); 2545703d2f4SShreyas B. Prabhu goto fail; 2555703d2f4SShreyas B. Prabhu } 2565703d2f4SShreyas B. Prabhu 2575703d2f4SShreyas B. Prabhu get_online_cpus(); 2585703d2f4SShreyas B. Prabhu primary_thread_mask = cpu_online_cores_map(); 2595703d2f4SShreyas B. Prabhu on_each_cpu_mask(&primary_thread_mask, 2605703d2f4SShreyas B. Prabhu pnv_fastsleep_workaround_apply, 2615703d2f4SShreyas B. Prabhu &err, 1); 2625703d2f4SShreyas B. Prabhu put_online_cpus(); 2635703d2f4SShreyas B. Prabhu if (err) { 2645703d2f4SShreyas B. Prabhu pr_err("fastsleep_workaround_applyonce change failed while running pnv_fastsleep_workaround_apply"); 2655703d2f4SShreyas B. Prabhu goto fail; 2665703d2f4SShreyas B. Prabhu } 2675703d2f4SShreyas B. Prabhu 2685703d2f4SShreyas B. Prabhu err = patch_instruction( 2695703d2f4SShreyas B. Prabhu (unsigned int *)pnv_fastsleep_workaround_at_entry, 2705703d2f4SShreyas B. Prabhu PPC_INST_NOP); 2715703d2f4SShreyas B. Prabhu if (err) { 2725703d2f4SShreyas B. Prabhu pr_err("fastsleep_workaround_applyonce change failed while patching pnv_fastsleep_workaround_at_entry"); 2735703d2f4SShreyas B. Prabhu goto fail; 2745703d2f4SShreyas B. Prabhu } 2755703d2f4SShreyas B. Prabhu 2765703d2f4SShreyas B. Prabhu fastsleep_workaround_applyonce = 1; 2775703d2f4SShreyas B. Prabhu 2785703d2f4SShreyas B. Prabhu return count; 2795703d2f4SShreyas B. Prabhu fail: 2805703d2f4SShreyas B. Prabhu return -EIO; 2815703d2f4SShreyas B. Prabhu } 2825703d2f4SShreyas B. Prabhu 2835703d2f4SShreyas B. Prabhu static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600, 2845703d2f4SShreyas B. Prabhu show_fastsleep_workaround_applyonce, 2855703d2f4SShreyas B. Prabhu store_fastsleep_workaround_applyonce); 2865703d2f4SShreyas B. Prabhu 2872201f994SNicholas Piggin static unsigned long __power7_idle_type(unsigned long type) 2882201f994SNicholas Piggin { 2892201f994SNicholas Piggin unsigned long srr1; 2902201f994SNicholas Piggin 2912201f994SNicholas Piggin if (!prep_irq_for_idle_irqsoff()) 2922201f994SNicholas Piggin return 0; 2932201f994SNicholas Piggin 2942201f994SNicholas Piggin ppc64_runlatch_off(); 2952201f994SNicholas Piggin srr1 = power7_idle_insn(type); 2962201f994SNicholas Piggin ppc64_runlatch_on(); 2972201f994SNicholas Piggin 2982201f994SNicholas Piggin fini_irq_for_idle_irqsoff(); 2992201f994SNicholas Piggin 3002201f994SNicholas Piggin return srr1; 3012201f994SNicholas Piggin } 3022201f994SNicholas Piggin 3032201f994SNicholas Piggin void power7_idle_type(unsigned long type) 3042201f994SNicholas Piggin { 3052201f994SNicholas Piggin __power7_idle_type(type); 3062201f994SNicholas Piggin } 3072201f994SNicholas Piggin 3082201f994SNicholas Piggin void power7_idle(void) 3092201f994SNicholas Piggin { 3102201f994SNicholas Piggin if (!powersave_nap) 3112201f994SNicholas Piggin return; 3122201f994SNicholas Piggin 3132201f994SNicholas Piggin power7_idle_type(PNV_THREAD_NAP); 3142201f994SNicholas Piggin } 3152201f994SNicholas Piggin 3162201f994SNicholas Piggin static unsigned long __power9_idle_type(unsigned long stop_psscr_val, 3172201f994SNicholas Piggin unsigned long stop_psscr_mask) 3182201f994SNicholas Piggin { 3192201f994SNicholas Piggin unsigned long psscr; 3202201f994SNicholas Piggin unsigned long srr1; 3212201f994SNicholas Piggin 3222201f994SNicholas Piggin if (!prep_irq_for_idle_irqsoff()) 3232201f994SNicholas Piggin return 0; 3242201f994SNicholas Piggin 3252201f994SNicholas Piggin psscr = mfspr(SPRN_PSSCR); 3262201f994SNicholas Piggin psscr = (psscr & ~stop_psscr_mask) | stop_psscr_val; 3272201f994SNicholas Piggin 3282201f994SNicholas Piggin ppc64_runlatch_off(); 3292201f994SNicholas Piggin srr1 = power9_idle_stop(psscr); 3302201f994SNicholas Piggin ppc64_runlatch_on(); 3312201f994SNicholas Piggin 3322201f994SNicholas Piggin fini_irq_for_idle_irqsoff(); 3332201f994SNicholas Piggin 3342201f994SNicholas Piggin return srr1; 3352201f994SNicholas Piggin } 3362201f994SNicholas Piggin 3372201f994SNicholas Piggin void power9_idle_type(unsigned long stop_psscr_val, 3382201f994SNicholas Piggin unsigned long stop_psscr_mask) 3392201f994SNicholas Piggin { 3402201f994SNicholas Piggin __power9_idle_type(stop_psscr_val, stop_psscr_mask); 3412201f994SNicholas Piggin } 3422201f994SNicholas Piggin 34309206b60SGautham R. Shenoy /* 344bcef83a0SShreyas B. Prabhu * Used for ppc_md.power_save which needs a function with no parameters 345bcef83a0SShreyas B. Prabhu */ 3462201f994SNicholas Piggin void power9_idle(void) 347d405a98cSShreyas B. Prabhu { 3482201f994SNicholas Piggin power9_idle_type(pnv_default_stop_val, pnv_default_stop_mask); 349bcef83a0SShreyas B. Prabhu } 35009206b60SGautham R. Shenoy 35167d20418SNicholas Piggin #ifdef CONFIG_HOTPLUG_CPU 352c0691f9dSShreyas B. Prabhu /* 353a7cd88daSGautham R. Shenoy * pnv_cpu_offline: A function that puts the CPU into the deepest 354a7cd88daSGautham R. Shenoy * available platform idle state on a CPU-Offline. 3552525db04SNicholas Piggin * interrupts hard disabled and no lazy irq pending. 356a7cd88daSGautham R. Shenoy */ 357a7cd88daSGautham R. Shenoy unsigned long pnv_cpu_offline(unsigned int cpu) 358a7cd88daSGautham R. Shenoy { 359a7cd88daSGautham R. Shenoy unsigned long srr1; 360a7cd88daSGautham R. Shenoy u32 idle_states = pnv_get_supported_cpuidle_states(); 361a7cd88daSGautham R. Shenoy 3622525db04SNicholas Piggin ppc64_runlatch_off(); 3632525db04SNicholas Piggin 364f3b3f284SGautham R. Shenoy if (cpu_has_feature(CPU_FTR_ARCH_300) && deepest_stop_found) { 3652525db04SNicholas Piggin unsigned long psscr; 3662525db04SNicholas Piggin 3672525db04SNicholas Piggin psscr = mfspr(SPRN_PSSCR); 3682525db04SNicholas Piggin psscr = (psscr & ~pnv_deepest_stop_psscr_mask) | 3692525db04SNicholas Piggin pnv_deepest_stop_psscr_val; 3702525db04SNicholas Piggin srr1 = power9_idle_stop(psscr); 3712525db04SNicholas Piggin 372a7cd88daSGautham R. Shenoy } else if (idle_states & OPAL_PM_WINKLE_ENABLED) { 3732525db04SNicholas Piggin srr1 = power7_idle_insn(PNV_THREAD_WINKLE); 374a7cd88daSGautham R. Shenoy } else if ((idle_states & OPAL_PM_SLEEP_ENABLED) || 375a7cd88daSGautham R. Shenoy (idle_states & OPAL_PM_SLEEP_ENABLED_ER1)) { 3762525db04SNicholas Piggin srr1 = power7_idle_insn(PNV_THREAD_SLEEP); 37790061231SGautham R. Shenoy } else if (idle_states & OPAL_PM_NAP_ENABLED) { 3782525db04SNicholas Piggin srr1 = power7_idle_insn(PNV_THREAD_NAP); 37990061231SGautham R. Shenoy } else { 38090061231SGautham R. Shenoy /* This is the fallback method. We emulate snooze */ 38190061231SGautham R. Shenoy while (!generic_check_cpu_restart(cpu)) { 38290061231SGautham R. Shenoy HMT_low(); 38390061231SGautham R. Shenoy HMT_very_low(); 38490061231SGautham R. Shenoy } 38590061231SGautham R. Shenoy srr1 = 0; 38690061231SGautham R. Shenoy HMT_medium(); 387a7cd88daSGautham R. Shenoy } 388a7cd88daSGautham R. Shenoy 3892525db04SNicholas Piggin ppc64_runlatch_on(); 3902525db04SNicholas Piggin 391a7cd88daSGautham R. Shenoy return srr1; 392a7cd88daSGautham R. Shenoy } 39367d20418SNicholas Piggin #endif 394a7cd88daSGautham R. Shenoy 395a7cd88daSGautham R. Shenoy /* 396bcef83a0SShreyas B. Prabhu * Power ISA 3.0 idle initialization. 397bcef83a0SShreyas B. Prabhu * 398bcef83a0SShreyas B. Prabhu * POWER ISA 3.0 defines a new SPR Processor stop Status and Control 399bcef83a0SShreyas B. Prabhu * Register (PSSCR) to control idle behavior. 400bcef83a0SShreyas B. Prabhu * 401bcef83a0SShreyas B. Prabhu * PSSCR layout: 402bcef83a0SShreyas B. Prabhu * ---------------------------------------------------------- 403bcef83a0SShreyas B. Prabhu * | PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL | 404bcef83a0SShreyas B. Prabhu * ---------------------------------------------------------- 405bcef83a0SShreyas B. Prabhu * 0 4 41 42 43 44 48 54 56 60 406bcef83a0SShreyas B. Prabhu * 407bcef83a0SShreyas B. Prabhu * PSSCR key fields: 408bcef83a0SShreyas B. Prabhu * Bits 0:3 - Power-Saving Level Status (PLS). This field indicates the 409bcef83a0SShreyas B. Prabhu * lowest power-saving state the thread entered since stop instruction was 410bcef83a0SShreyas B. Prabhu * last executed. 411bcef83a0SShreyas B. Prabhu * 412bcef83a0SShreyas B. Prabhu * Bit 41 - Status Disable(SD) 413bcef83a0SShreyas B. Prabhu * 0 - Shows PLS entries 414bcef83a0SShreyas B. Prabhu * 1 - PLS entries are all 0 415bcef83a0SShreyas B. Prabhu * 416bcef83a0SShreyas B. Prabhu * Bit 42 - Enable State Loss 417bcef83a0SShreyas B. Prabhu * 0 - No state is lost irrespective of other fields 418bcef83a0SShreyas B. Prabhu * 1 - Allows state loss 419bcef83a0SShreyas B. Prabhu * 420bcef83a0SShreyas B. Prabhu * Bit 43 - Exit Criterion 421bcef83a0SShreyas B. Prabhu * 0 - Exit from power-save mode on any interrupt 422bcef83a0SShreyas B. Prabhu * 1 - Exit from power-save mode controlled by LPCR's PECE bits 423bcef83a0SShreyas B. Prabhu * 424bcef83a0SShreyas B. Prabhu * Bits 44:47 - Power-Saving Level Limit 425bcef83a0SShreyas B. Prabhu * This limits the power-saving level that can be entered into. 426bcef83a0SShreyas B. Prabhu * 427bcef83a0SShreyas B. Prabhu * Bits 60:63 - Requested Level 428bcef83a0SShreyas B. Prabhu * Used to specify which power-saving level must be entered on executing 429bcef83a0SShreyas B. Prabhu * stop instruction 43009206b60SGautham R. Shenoy */ 43109206b60SGautham R. Shenoy 43209206b60SGautham R. Shenoy int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags) 43309206b60SGautham R. Shenoy { 43409206b60SGautham R. Shenoy int err = 0; 43509206b60SGautham R. Shenoy 43609206b60SGautham R. Shenoy /* 43709206b60SGautham R. Shenoy * psscr_mask == 0xf indicates an older firmware. 43809206b60SGautham R. Shenoy * Set remaining fields of psscr to the default values. 43909206b60SGautham R. Shenoy * See NOTE above definition of PSSCR_HV_DEFAULT_VAL 44009206b60SGautham R. Shenoy */ 44109206b60SGautham R. Shenoy if (*psscr_mask == 0xf) { 44209206b60SGautham R. Shenoy *psscr_val = *psscr_val | PSSCR_HV_DEFAULT_VAL; 44309206b60SGautham R. Shenoy *psscr_mask = PSSCR_HV_DEFAULT_MASK; 44409206b60SGautham R. Shenoy return err; 44509206b60SGautham R. Shenoy } 44609206b60SGautham R. Shenoy 44709206b60SGautham R. Shenoy /* 44809206b60SGautham R. Shenoy * New firmware is expected to set the psscr_val bits correctly. 44909206b60SGautham R. Shenoy * Validate that the following invariants are correctly maintained by 45009206b60SGautham R. Shenoy * the new firmware. 45109206b60SGautham R. Shenoy * - ESL bit value matches the EC bit value. 45209206b60SGautham R. Shenoy * - ESL bit is set for all the deep stop states. 45309206b60SGautham R. Shenoy */ 45409206b60SGautham R. Shenoy if (GET_PSSCR_ESL(*psscr_val) != GET_PSSCR_EC(*psscr_val)) { 45509206b60SGautham R. Shenoy err = ERR_EC_ESL_MISMATCH; 45609206b60SGautham R. Shenoy } else if ((flags & OPAL_PM_LOSE_FULL_CONTEXT) && 45709206b60SGautham R. Shenoy GET_PSSCR_ESL(*psscr_val) == 0) { 45809206b60SGautham R. Shenoy err = ERR_DEEP_STATE_ESL_MISMATCH; 45909206b60SGautham R. Shenoy } 46009206b60SGautham R. Shenoy 46109206b60SGautham R. Shenoy return err; 46209206b60SGautham R. Shenoy } 46309206b60SGautham R. Shenoy 46409206b60SGautham R. Shenoy /* 46509206b60SGautham R. Shenoy * pnv_arch300_idle_init: Initializes the default idle state, first 46609206b60SGautham R. Shenoy * deep idle state and deepest idle state on 46709206b60SGautham R. Shenoy * ISA 3.0 CPUs. 468bcef83a0SShreyas B. Prabhu * 469bcef83a0SShreyas B. Prabhu * @np: /ibm,opal/power-mgt device node 470bcef83a0SShreyas B. Prabhu * @flags: cpu-idle-state-flags array 471bcef83a0SShreyas B. Prabhu * @dt_idle_states: Number of idle state entries 472bcef83a0SShreyas B. Prabhu * Returns 0 on success 473bcef83a0SShreyas B. Prabhu */ 474dd34c74cSGautham R. Shenoy static int __init pnv_power9_idle_init(struct device_node *np, u32 *flags, 475bcef83a0SShreyas B. Prabhu int dt_idle_states) 476bcef83a0SShreyas B. Prabhu { 477bcef83a0SShreyas B. Prabhu u64 *psscr_val = NULL; 47809206b60SGautham R. Shenoy u64 *psscr_mask = NULL; 47909206b60SGautham R. Shenoy u32 *residency_ns = NULL; 48009206b60SGautham R. Shenoy u64 max_residency_ns = 0; 481bcef83a0SShreyas B. Prabhu int rc = 0, i; 482bcef83a0SShreyas B. Prabhu 48309206b60SGautham R. Shenoy psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val), GFP_KERNEL); 48409206b60SGautham R. Shenoy psscr_mask = kcalloc(dt_idle_states, sizeof(*psscr_mask), GFP_KERNEL); 48509206b60SGautham R. Shenoy residency_ns = kcalloc(dt_idle_states, sizeof(*residency_ns), 486bcef83a0SShreyas B. Prabhu GFP_KERNEL); 48709206b60SGautham R. Shenoy 48809206b60SGautham R. Shenoy if (!psscr_val || !psscr_mask || !residency_ns) { 489bcef83a0SShreyas B. Prabhu rc = -1; 490bcef83a0SShreyas B. Prabhu goto out; 491bcef83a0SShreyas B. Prabhu } 49209206b60SGautham R. Shenoy 493bcef83a0SShreyas B. Prabhu if (of_property_read_u64_array(np, 494bcef83a0SShreyas B. Prabhu "ibm,cpu-idle-state-psscr", 495bcef83a0SShreyas B. Prabhu psscr_val, dt_idle_states)) { 49609206b60SGautham R. Shenoy pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr in DT\n"); 49709206b60SGautham R. Shenoy rc = -1; 49809206b60SGautham R. Shenoy goto out; 49909206b60SGautham R. Shenoy } 50009206b60SGautham R. Shenoy 50109206b60SGautham R. Shenoy if (of_property_read_u64_array(np, 50209206b60SGautham R. Shenoy "ibm,cpu-idle-state-psscr-mask", 50309206b60SGautham R. Shenoy psscr_mask, dt_idle_states)) { 50409206b60SGautham R. Shenoy pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr-mask in DT\n"); 50509206b60SGautham R. Shenoy rc = -1; 50609206b60SGautham R. Shenoy goto out; 50709206b60SGautham R. Shenoy } 50809206b60SGautham R. Shenoy 50909206b60SGautham R. Shenoy if (of_property_read_u32_array(np, 51009206b60SGautham R. Shenoy "ibm,cpu-idle-state-residency-ns", 51109206b60SGautham R. Shenoy residency_ns, dt_idle_states)) { 51209206b60SGautham R. Shenoy pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-residency-ns in DT\n"); 513bcef83a0SShreyas B. Prabhu rc = -1; 514bcef83a0SShreyas B. Prabhu goto out; 515bcef83a0SShreyas B. Prabhu } 516bcef83a0SShreyas B. Prabhu 517bcef83a0SShreyas B. Prabhu /* 51809206b60SGautham R. Shenoy * Set pnv_first_deep_stop_state, pnv_deepest_stop_psscr_{val,mask}, 51909206b60SGautham R. Shenoy * and the pnv_default_stop_{val,mask}. 52009206b60SGautham R. Shenoy * 521c0691f9dSShreyas B. Prabhu * pnv_first_deep_stop_state should be set to the first stop 522c0691f9dSShreyas B. Prabhu * level to cause hypervisor state loss. 52309206b60SGautham R. Shenoy * 52409206b60SGautham R. Shenoy * pnv_deepest_stop_{val,mask} should be set to values corresponding to 52509206b60SGautham R. Shenoy * the deepest stop state. 52609206b60SGautham R. Shenoy * 52709206b60SGautham R. Shenoy * pnv_default_stop_{val,mask} should be set to values corresponding to 52809206b60SGautham R. Shenoy * the shallowest (OPAL_PM_STOP_INST_FAST) loss-less stop state. 529bcef83a0SShreyas B. Prabhu */ 530bcef83a0SShreyas B. Prabhu pnv_first_deep_stop_state = MAX_STOP_STATE; 531bcef83a0SShreyas B. Prabhu for (i = 0; i < dt_idle_states; i++) { 53209206b60SGautham R. Shenoy int err; 533bcef83a0SShreyas B. Prabhu u64 psscr_rl = psscr_val[i] & PSSCR_RL_MASK; 534bcef83a0SShreyas B. Prabhu 535bcef83a0SShreyas B. Prabhu if ((flags[i] & OPAL_PM_LOSE_FULL_CONTEXT) && 536bcef83a0SShreyas B. Prabhu (pnv_first_deep_stop_state > psscr_rl)) 537bcef83a0SShreyas B. Prabhu pnv_first_deep_stop_state = psscr_rl; 538c0691f9dSShreyas B. Prabhu 53909206b60SGautham R. Shenoy err = validate_psscr_val_mask(&psscr_val[i], &psscr_mask[i], 54009206b60SGautham R. Shenoy flags[i]); 54109206b60SGautham R. Shenoy if (err) { 54209206b60SGautham R. Shenoy report_invalid_psscr_val(psscr_val[i], err); 54309206b60SGautham R. Shenoy continue; 54409206b60SGautham R. Shenoy } 54509206b60SGautham R. Shenoy 54609206b60SGautham R. Shenoy if (max_residency_ns < residency_ns[i]) { 54709206b60SGautham R. Shenoy max_residency_ns = residency_ns[i]; 54809206b60SGautham R. Shenoy pnv_deepest_stop_psscr_val = psscr_val[i]; 54909206b60SGautham R. Shenoy pnv_deepest_stop_psscr_mask = psscr_mask[i]; 55009206b60SGautham R. Shenoy deepest_stop_found = true; 55109206b60SGautham R. Shenoy } 55209206b60SGautham R. Shenoy 55309206b60SGautham R. Shenoy if (!default_stop_found && 55409206b60SGautham R. Shenoy (flags[i] & OPAL_PM_STOP_INST_FAST)) { 55509206b60SGautham R. Shenoy pnv_default_stop_val = psscr_val[i]; 55609206b60SGautham R. Shenoy pnv_default_stop_mask = psscr_mask[i]; 55709206b60SGautham R. Shenoy default_stop_found = true; 55809206b60SGautham R. Shenoy } 55909206b60SGautham R. Shenoy } 56009206b60SGautham R. Shenoy 561f3b3f284SGautham R. Shenoy if (unlikely(!default_stop_found)) { 562f3b3f284SGautham R. Shenoy pr_warn("cpuidle-powernv: No suitable default stop state found. Disabling platform idle.\n"); 563f3b3f284SGautham R. Shenoy } else { 564f3b3f284SGautham R. Shenoy ppc_md.power_save = power9_idle; 565f3b3f284SGautham R. Shenoy pr_info("cpuidle-powernv: Default stop: psscr = 0x%016llx,mask=0x%016llx\n", 56609206b60SGautham R. Shenoy pnv_default_stop_val, pnv_default_stop_mask); 56709206b60SGautham R. Shenoy } 56809206b60SGautham R. Shenoy 569f3b3f284SGautham R. Shenoy if (unlikely(!deepest_stop_found)) { 570f3b3f284SGautham R. Shenoy pr_warn("cpuidle-powernv: No suitable stop state for CPU-Hotplug. Offlined CPUs will busy wait"); 571f3b3f284SGautham R. Shenoy } else { 572f3b3f284SGautham R. Shenoy pr_info("cpuidle-powernv: Deepest stop: psscr = 0x%016llx,mask=0x%016llx\n", 57309206b60SGautham R. Shenoy pnv_deepest_stop_psscr_val, 57409206b60SGautham R. Shenoy pnv_deepest_stop_psscr_mask); 575bcef83a0SShreyas B. Prabhu } 576bcef83a0SShreyas B. Prabhu 577f3b3f284SGautham R. Shenoy pr_info("cpuidle-powernv: Requested Level (RL) value of first deep stop = 0x%llx\n", 578f3b3f284SGautham R. Shenoy pnv_first_deep_stop_state); 579bcef83a0SShreyas B. Prabhu out: 580bcef83a0SShreyas B. Prabhu kfree(psscr_val); 58109206b60SGautham R. Shenoy kfree(psscr_mask); 58209206b60SGautham R. Shenoy kfree(residency_ns); 583bcef83a0SShreyas B. Prabhu return rc; 584bcef83a0SShreyas B. Prabhu } 585bcef83a0SShreyas B. Prabhu 586bcef83a0SShreyas B. Prabhu /* 587bcef83a0SShreyas B. Prabhu * Probe device tree for supported idle states 588bcef83a0SShreyas B. Prabhu */ 589bcef83a0SShreyas B. Prabhu static void __init pnv_probe_idle_states(void) 590bcef83a0SShreyas B. Prabhu { 591bcef83a0SShreyas B. Prabhu struct device_node *np; 592d405a98cSShreyas B. Prabhu int dt_idle_states; 593bcef83a0SShreyas B. Prabhu u32 *flags = NULL; 594d405a98cSShreyas B. Prabhu int i; 595d405a98cSShreyas B. Prabhu 596bcef83a0SShreyas B. Prabhu np = of_find_node_by_path("/ibm,opal/power-mgt"); 597bcef83a0SShreyas B. Prabhu if (!np) { 598d405a98cSShreyas B. Prabhu pr_warn("opal: PowerMgmt Node not found\n"); 599d405a98cSShreyas B. Prabhu goto out; 600d405a98cSShreyas B. Prabhu } 601bcef83a0SShreyas B. Prabhu dt_idle_states = of_property_count_u32_elems(np, 602d405a98cSShreyas B. Prabhu "ibm,cpu-idle-state-flags"); 603d405a98cSShreyas B. Prabhu if (dt_idle_states < 0) { 604d405a98cSShreyas B. Prabhu pr_warn("cpuidle-powernv: no idle states found in the DT\n"); 605d405a98cSShreyas B. Prabhu goto out; 606d405a98cSShreyas B. Prabhu } 607d405a98cSShreyas B. Prabhu 608bcef83a0SShreyas B. Prabhu flags = kcalloc(dt_idle_states, sizeof(*flags), GFP_KERNEL); 609bcef83a0SShreyas B. Prabhu 610bcef83a0SShreyas B. Prabhu if (of_property_read_u32_array(np, 611d405a98cSShreyas B. Prabhu "ibm,cpu-idle-state-flags", flags, dt_idle_states)) { 612d405a98cSShreyas B. Prabhu pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n"); 613bcef83a0SShreyas B. Prabhu goto out; 614bcef83a0SShreyas B. Prabhu } 615bcef83a0SShreyas B. Prabhu 616bcef83a0SShreyas B. Prabhu if (cpu_has_feature(CPU_FTR_ARCH_300)) { 617dd34c74cSGautham R. Shenoy if (pnv_power9_idle_init(np, flags, dt_idle_states)) 618bcef83a0SShreyas B. Prabhu goto out; 619d405a98cSShreyas B. Prabhu } 620d405a98cSShreyas B. Prabhu 621d405a98cSShreyas B. Prabhu for (i = 0; i < dt_idle_states; i++) 622d405a98cSShreyas B. Prabhu supported_cpuidle_states |= flags[i]; 623d405a98cSShreyas B. Prabhu 624bcef83a0SShreyas B. Prabhu out: 625bcef83a0SShreyas B. Prabhu kfree(flags); 626bcef83a0SShreyas B. Prabhu } 627bcef83a0SShreyas B. Prabhu static int __init pnv_init_idle_states(void) 628bcef83a0SShreyas B. Prabhu { 629bcef83a0SShreyas B. Prabhu 630bcef83a0SShreyas B. Prabhu supported_cpuidle_states = 0; 631bcef83a0SShreyas B. Prabhu 632bcef83a0SShreyas B. Prabhu if (cpuidle_disable != IDLE_NO_OVERRIDE) 633bcef83a0SShreyas B. Prabhu goto out; 634bcef83a0SShreyas B. Prabhu 635bcef83a0SShreyas B. Prabhu pnv_probe_idle_states(); 636bcef83a0SShreyas B. Prabhu 637d405a98cSShreyas B. Prabhu if (!(supported_cpuidle_states & OPAL_PM_SLEEP_ENABLED_ER1)) { 638d405a98cSShreyas B. Prabhu patch_instruction( 639d405a98cSShreyas B. Prabhu (unsigned int *)pnv_fastsleep_workaround_at_entry, 640d405a98cSShreyas B. Prabhu PPC_INST_NOP); 641d405a98cSShreyas B. Prabhu patch_instruction( 642d405a98cSShreyas B. Prabhu (unsigned int *)pnv_fastsleep_workaround_at_exit, 643d405a98cSShreyas B. Prabhu PPC_INST_NOP); 6445703d2f4SShreyas B. Prabhu } else { 6455703d2f4SShreyas B. Prabhu /* 6465703d2f4SShreyas B. Prabhu * OPAL_PM_SLEEP_ENABLED_ER1 is set. It indicates that 6475703d2f4SShreyas B. Prabhu * workaround is needed to use fastsleep. Provide sysfs 6485703d2f4SShreyas B. Prabhu * control to choose how this workaround has to be applied. 6495703d2f4SShreyas B. Prabhu */ 6505703d2f4SShreyas B. Prabhu device_create_file(cpu_subsys.dev_root, 6515703d2f4SShreyas B. Prabhu &dev_attr_fastsleep_workaround_applyonce); 652d405a98cSShreyas B. Prabhu } 6535703d2f4SShreyas B. Prabhu 654d405a98cSShreyas B. Prabhu pnv_alloc_idle_core_states(); 6555593e303SShreyas B. Prabhu 65617ed4c8fSGautham R. Shenoy /* 65717ed4c8fSGautham R. Shenoy * For each CPU, record its PACA address in each of it's 65817ed4c8fSGautham R. Shenoy * sibling thread's PACA at the slot corresponding to this 65917ed4c8fSGautham R. Shenoy * CPU's index in the core. 66017ed4c8fSGautham R. Shenoy */ 66117ed4c8fSGautham R. Shenoy if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 66217ed4c8fSGautham R. Shenoy int cpu; 66317ed4c8fSGautham R. Shenoy 66417ed4c8fSGautham R. Shenoy pr_info("powernv: idle: Saving PACA pointers of all CPUs in their thread sibling PACA\n"); 66517ed4c8fSGautham R. Shenoy for_each_possible_cpu(cpu) { 66617ed4c8fSGautham R. Shenoy int base_cpu = cpu_first_thread_sibling(cpu); 66717ed4c8fSGautham R. Shenoy int idx = cpu_thread_in_core(cpu); 66817ed4c8fSGautham R. Shenoy int i; 66917ed4c8fSGautham R. Shenoy 67017ed4c8fSGautham R. Shenoy for (i = 0; i < threads_per_core; i++) { 67117ed4c8fSGautham R. Shenoy int j = base_cpu + i; 67217ed4c8fSGautham R. Shenoy 67317ed4c8fSGautham R. Shenoy paca[j].thread_sibling_pacas[idx] = &paca[cpu]; 67417ed4c8fSGautham R. Shenoy } 67517ed4c8fSGautham R. Shenoy } 67617ed4c8fSGautham R. Shenoy } 67717ed4c8fSGautham R. Shenoy 6785593e303SShreyas B. Prabhu if (supported_cpuidle_states & OPAL_PM_NAP_ENABLED) 6795593e303SShreyas B. Prabhu ppc_md.power_save = power7_idle; 680bcef83a0SShreyas B. Prabhu 681d405a98cSShreyas B. Prabhu out: 682d405a98cSShreyas B. Prabhu return 0; 683d405a98cSShreyas B. Prabhu } 6844bece972SMichael Ellerman machine_subsys_initcall(powernv, pnv_init_idle_states); 685