1 /* 2 * The file intends to implement the platform dependent EEH operations on 3 * powernv platform. Actually, the powernv was created in order to fully 4 * hypervisor support. 5 * 6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/atomic.h> 15 #include <linux/debugfs.h> 16 #include <linux/delay.h> 17 #include <linux/export.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/list.h> 21 #include <linux/msi.h> 22 #include <linux/of.h> 23 #include <linux/pci.h> 24 #include <linux/proc_fs.h> 25 #include <linux/rbtree.h> 26 #include <linux/sched.h> 27 #include <linux/seq_file.h> 28 #include <linux/spinlock.h> 29 30 #include <asm/eeh.h> 31 #include <asm/eeh_event.h> 32 #include <asm/firmware.h> 33 #include <asm/io.h> 34 #include <asm/iommu.h> 35 #include <asm/machdep.h> 36 #include <asm/msi_bitmap.h> 37 #include <asm/opal.h> 38 #include <asm/ppc-pci.h> 39 #include <asm/pnv-pci.h> 40 41 #include "powernv.h" 42 #include "pci.h" 43 44 static bool pnv_eeh_nb_init = false; 45 static int eeh_event_irq = -EINVAL; 46 47 static int pnv_eeh_init(void) 48 { 49 struct pci_controller *hose; 50 struct pnv_phb *phb; 51 int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 52 53 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 54 pr_warn("%s: OPAL is required !\n", 55 __func__); 56 return -EINVAL; 57 } 58 59 /* Set probe mode */ 60 eeh_add_flag(EEH_PROBE_MODE_DEV); 61 62 /* 63 * P7IOC blocks PCI config access to frozen PE, but PHB3 64 * doesn't do that. So we have to selectively enable I/O 65 * prior to collecting error log. 66 */ 67 list_for_each_entry(hose, &hose_list, list_node) { 68 phb = hose->private_data; 69 70 if (phb->model == PNV_PHB_MODEL_P7IOC) 71 eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 72 73 if (phb->diag_data_size > max_diag_size) 74 max_diag_size = phb->diag_data_size; 75 76 /* 77 * PE#0 should be regarded as valid by EEH core 78 * if it's not the reserved one. Currently, we 79 * have the reserved PE#255 and PE#127 for PHB3 80 * and P7IOC separately. So we should regard 81 * PE#0 as valid for PHB3 and P7IOC. 82 */ 83 if (phb->ioda.reserved_pe_idx != 0) 84 eeh_add_flag(EEH_VALID_PE_ZERO); 85 86 break; 87 } 88 89 eeh_set_pe_aux_size(max_diag_size); 90 91 return 0; 92 } 93 94 static irqreturn_t pnv_eeh_event(int irq, void *data) 95 { 96 /* 97 * We simply send a special EEH event if EEH has been 98 * enabled. We don't care about EEH events until we've 99 * finished processing the outstanding ones. Event processing 100 * gets unmasked in next_error() if EEH is enabled. 101 */ 102 disable_irq_nosync(irq); 103 104 if (eeh_enabled()) 105 eeh_send_failure_event(NULL); 106 107 return IRQ_HANDLED; 108 } 109 110 #ifdef CONFIG_DEBUG_FS 111 static ssize_t pnv_eeh_ei_write(struct file *filp, 112 const char __user *user_buf, 113 size_t count, loff_t *ppos) 114 { 115 struct pci_controller *hose = filp->private_data; 116 struct eeh_dev *edev; 117 struct eeh_pe *pe; 118 int pe_no, type, func; 119 unsigned long addr, mask; 120 char buf[50]; 121 int ret; 122 123 if (!eeh_ops || !eeh_ops->err_inject) 124 return -ENXIO; 125 126 /* Copy over argument buffer */ 127 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 128 if (!ret) 129 return -EFAULT; 130 131 /* Retrieve parameters */ 132 ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 133 &pe_no, &type, &func, &addr, &mask); 134 if (ret != 5) 135 return -EINVAL; 136 137 /* Retrieve PE */ 138 edev = kzalloc(sizeof(*edev), GFP_KERNEL); 139 if (!edev) 140 return -ENOMEM; 141 edev->phb = hose; 142 edev->pe_config_addr = pe_no; 143 pe = eeh_pe_get(edev); 144 kfree(edev); 145 if (!pe) 146 return -ENODEV; 147 148 /* Do error injection */ 149 ret = eeh_ops->err_inject(pe, type, func, addr, mask); 150 return ret < 0 ? ret : count; 151 } 152 153 static const struct file_operations pnv_eeh_ei_fops = { 154 .open = simple_open, 155 .llseek = no_llseek, 156 .write = pnv_eeh_ei_write, 157 }; 158 159 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 160 { 161 struct pci_controller *hose = data; 162 struct pnv_phb *phb = hose->private_data; 163 164 out_be64(phb->regs + offset, val); 165 return 0; 166 } 167 168 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 169 { 170 struct pci_controller *hose = data; 171 struct pnv_phb *phb = hose->private_data; 172 173 *val = in_be64(phb->regs + offset); 174 return 0; 175 } 176 177 #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 178 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 179 { \ 180 return pnv_eeh_dbgfs_set(data, reg, val); \ 181 } \ 182 \ 183 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 184 { \ 185 return pnv_eeh_dbgfs_get(data, reg, val); \ 186 } \ 187 \ 188 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 189 pnv_eeh_dbgfs_get_##name, \ 190 pnv_eeh_dbgfs_set_##name, \ 191 "0x%llx\n") 192 193 PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 194 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 195 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 196 197 #endif /* CONFIG_DEBUG_FS */ 198 199 /** 200 * pnv_eeh_post_init - EEH platform dependent post initialization 201 * 202 * EEH platform dependent post initialization on powernv. When 203 * the function is called, the EEH PEs and devices should have 204 * been built. If the I/O cache staff has been built, EEH is 205 * ready to supply service. 206 */ 207 static int pnv_eeh_post_init(void) 208 { 209 struct pci_controller *hose; 210 struct pnv_phb *phb; 211 int ret = 0; 212 213 /* Register OPAL event notifier */ 214 if (!pnv_eeh_nb_init) { 215 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 216 if (eeh_event_irq < 0) { 217 pr_err("%s: Can't register OPAL event interrupt (%d)\n", 218 __func__, eeh_event_irq); 219 return eeh_event_irq; 220 } 221 222 ret = request_irq(eeh_event_irq, pnv_eeh_event, 223 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 224 if (ret < 0) { 225 irq_dispose_mapping(eeh_event_irq); 226 pr_err("%s: Can't request OPAL event interrupt (%d)\n", 227 __func__, eeh_event_irq); 228 return ret; 229 } 230 231 pnv_eeh_nb_init = true; 232 } 233 234 if (!eeh_enabled()) 235 disable_irq(eeh_event_irq); 236 237 list_for_each_entry(hose, &hose_list, list_node) { 238 phb = hose->private_data; 239 240 /* 241 * If EEH is enabled, we're going to rely on that. 242 * Otherwise, we restore to conventional mechanism 243 * to clear frozen PE during PCI config access. 244 */ 245 if (eeh_enabled()) 246 phb->flags |= PNV_PHB_FLAG_EEH; 247 else 248 phb->flags &= ~PNV_PHB_FLAG_EEH; 249 250 /* Create debugfs entries */ 251 #ifdef CONFIG_DEBUG_FS 252 if (phb->has_dbgfs || !phb->dbgfs) 253 continue; 254 255 phb->has_dbgfs = 1; 256 debugfs_create_file("err_injct", 0200, 257 phb->dbgfs, hose, 258 &pnv_eeh_ei_fops); 259 260 debugfs_create_file("err_injct_outbound", 0600, 261 phb->dbgfs, hose, 262 &pnv_eeh_dbgfs_ops_outb); 263 debugfs_create_file("err_injct_inboundA", 0600, 264 phb->dbgfs, hose, 265 &pnv_eeh_dbgfs_ops_inbA); 266 debugfs_create_file("err_injct_inboundB", 0600, 267 phb->dbgfs, hose, 268 &pnv_eeh_dbgfs_ops_inbB); 269 #endif /* CONFIG_DEBUG_FS */ 270 } 271 272 return ret; 273 } 274 275 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 276 { 277 int pos = PCI_CAPABILITY_LIST; 278 int cnt = 48; /* Maximal number of capabilities */ 279 u32 status, id; 280 281 if (!pdn) 282 return 0; 283 284 /* Check if the device supports capabilities */ 285 pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 286 if (!(status & PCI_STATUS_CAP_LIST)) 287 return 0; 288 289 while (cnt--) { 290 pnv_pci_cfg_read(pdn, pos, 1, &pos); 291 if (pos < 0x40) 292 break; 293 294 pos &= ~3; 295 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 296 if (id == 0xff) 297 break; 298 299 /* Found */ 300 if (id == cap) 301 return pos; 302 303 /* Next one */ 304 pos += PCI_CAP_LIST_NEXT; 305 } 306 307 return 0; 308 } 309 310 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 311 { 312 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 313 u32 header; 314 int pos = 256, ttl = (4096 - 256) / 8; 315 316 if (!edev || !edev->pcie_cap) 317 return 0; 318 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 319 return 0; 320 else if (!header) 321 return 0; 322 323 while (ttl-- > 0) { 324 if (PCI_EXT_CAP_ID(header) == cap && pos) 325 return pos; 326 327 pos = PCI_EXT_CAP_NEXT(header); 328 if (pos < 256) 329 break; 330 331 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 332 break; 333 } 334 335 return 0; 336 } 337 338 /** 339 * pnv_eeh_probe - Do probe on PCI device 340 * @pdn: PCI device node 341 * @data: unused 342 * 343 * When EEH module is installed during system boot, all PCI devices 344 * are checked one by one to see if it supports EEH. The function 345 * is introduced for the purpose. By default, EEH has been enabled 346 * on all PCI devices. That's to say, we only need do necessary 347 * initialization on the corresponding eeh device and create PE 348 * accordingly. 349 * 350 * It's notable that's unsafe to retrieve the EEH device through 351 * the corresponding PCI device. During the PCI device hotplug, which 352 * was possiblly triggered by EEH core, the binding between EEH device 353 * and the PCI device isn't built yet. 354 */ 355 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 356 { 357 struct pci_controller *hose = pdn->phb; 358 struct pnv_phb *phb = hose->private_data; 359 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 360 uint32_t pcie_flags; 361 int ret; 362 363 /* 364 * When probing the root bridge, which doesn't have any 365 * subordinate PCI devices. We don't have OF node for 366 * the root bridge. So it's not reasonable to continue 367 * the probing. 368 */ 369 if (!edev || edev->pe) 370 return NULL; 371 372 /* Skip for PCI-ISA bridge */ 373 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 374 return NULL; 375 376 /* Initialize eeh device */ 377 edev->class_code = pdn->class_code; 378 edev->mode &= 0xFFFFFF00; 379 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 380 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 381 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 382 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 383 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 384 edev->mode |= EEH_DEV_BRIDGE; 385 if (edev->pcie_cap) { 386 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 387 2, &pcie_flags); 388 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 389 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 390 edev->mode |= EEH_DEV_ROOT_PORT; 391 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 392 edev->mode |= EEH_DEV_DS_PORT; 393 } 394 } 395 396 edev->config_addr = (pdn->busno << 8) | (pdn->devfn); 397 edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr]; 398 399 /* Create PE */ 400 ret = eeh_add_to_parent_pe(edev); 401 if (ret) { 402 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n", 403 __func__, hose->global_number, pdn->busno, 404 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 405 return NULL; 406 } 407 408 /* 409 * If the PE contains any one of following adapters, the 410 * PCI config space can't be accessed when dumping EEH log. 411 * Otherwise, we will run into fenced PHB caused by shortage 412 * of outbound credits in the adapter. The PCI config access 413 * should be blocked until PE reset. MMIO access is dropped 414 * by hardware certainly. In order to drop PCI config requests, 415 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 416 * will be checked in the backend for PE state retrival. If 417 * the PE becomes frozen for the first time and the flag has 418 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 419 * that PE to block its config space. 420 * 421 * Broadcom BCM5718 2-ports NICs (14e4:1656) 422 * Broadcom Austin 4-ports NICs (14e4:1657) 423 * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 424 * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 425 */ 426 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 427 pdn->device_id == 0x1656) || 428 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 429 pdn->device_id == 0x1657) || 430 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 431 pdn->device_id == 0x168a) || 432 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 433 pdn->device_id == 0x168e)) 434 edev->pe->state |= EEH_PE_CFG_RESTRICTED; 435 436 /* 437 * Cache the PE primary bus, which can't be fetched when 438 * full hotplug is in progress. In that case, all child 439 * PCI devices of the PE are expected to be removed prior 440 * to PE reset. 441 */ 442 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 443 edev->pe->bus = pci_find_bus(hose->global_number, 444 pdn->busno); 445 if (edev->pe->bus) 446 edev->pe->state |= EEH_PE_PRI_BUS; 447 } 448 449 /* 450 * Enable EEH explicitly so that we will do EEH check 451 * while accessing I/O stuff 452 */ 453 eeh_add_flag(EEH_ENABLED); 454 455 /* Save memory bars */ 456 eeh_save_bars(edev); 457 458 return NULL; 459 } 460 461 /** 462 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 463 * @pe: EEH PE 464 * @option: operation to be issued 465 * 466 * The function is used to control the EEH functionality globally. 467 * Currently, following options are support according to PAPR: 468 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 469 */ 470 static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 471 { 472 struct pci_controller *hose = pe->phb; 473 struct pnv_phb *phb = hose->private_data; 474 bool freeze_pe = false; 475 int opt; 476 s64 rc; 477 478 switch (option) { 479 case EEH_OPT_DISABLE: 480 return -EPERM; 481 case EEH_OPT_ENABLE: 482 return 0; 483 case EEH_OPT_THAW_MMIO: 484 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 485 break; 486 case EEH_OPT_THAW_DMA: 487 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 488 break; 489 case EEH_OPT_FREEZE_PE: 490 freeze_pe = true; 491 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 492 break; 493 default: 494 pr_warn("%s: Invalid option %d\n", __func__, option); 495 return -EINVAL; 496 } 497 498 /* Freeze master and slave PEs if PHB supports compound PEs */ 499 if (freeze_pe) { 500 if (phb->freeze_pe) { 501 phb->freeze_pe(phb, pe->addr); 502 return 0; 503 } 504 505 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 506 if (rc != OPAL_SUCCESS) { 507 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 508 __func__, rc, phb->hose->global_number, 509 pe->addr); 510 return -EIO; 511 } 512 513 return 0; 514 } 515 516 /* Unfreeze master and slave PEs if PHB supports */ 517 if (phb->unfreeze_pe) 518 return phb->unfreeze_pe(phb, pe->addr, opt); 519 520 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 521 if (rc != OPAL_SUCCESS) { 522 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 523 __func__, rc, option, phb->hose->global_number, 524 pe->addr); 525 return -EIO; 526 } 527 528 return 0; 529 } 530 531 /** 532 * pnv_eeh_get_pe_addr - Retrieve PE address 533 * @pe: EEH PE 534 * 535 * Retrieve the PE address according to the given tranditional 536 * PCI BDF (Bus/Device/Function) address. 537 */ 538 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 539 { 540 return pe->addr; 541 } 542 543 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 544 { 545 struct pnv_phb *phb = pe->phb->private_data; 546 s64 rc; 547 548 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 549 phb->diag_data_size); 550 if (rc != OPAL_SUCCESS) 551 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 552 __func__, rc, pe->phb->global_number); 553 } 554 555 static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 556 { 557 struct pnv_phb *phb = pe->phb->private_data; 558 u8 fstate; 559 __be16 pcierr; 560 s64 rc; 561 int result = 0; 562 563 rc = opal_pci_eeh_freeze_status(phb->opal_id, 564 pe->addr, 565 &fstate, 566 &pcierr, 567 NULL); 568 if (rc != OPAL_SUCCESS) { 569 pr_warn("%s: Failure %lld getting PHB#%x state\n", 570 __func__, rc, phb->hose->global_number); 571 return EEH_STATE_NOT_SUPPORT; 572 } 573 574 /* 575 * Check PHB state. If the PHB is frozen for the 576 * first time, to dump the PHB diag-data. 577 */ 578 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 579 result = (EEH_STATE_MMIO_ACTIVE | 580 EEH_STATE_DMA_ACTIVE | 581 EEH_STATE_MMIO_ENABLED | 582 EEH_STATE_DMA_ENABLED); 583 } else if (!(pe->state & EEH_PE_ISOLATED)) { 584 eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 585 pnv_eeh_get_phb_diag(pe); 586 587 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 588 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 589 } 590 591 return result; 592 } 593 594 static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 595 { 596 struct pnv_phb *phb = pe->phb->private_data; 597 u8 fstate; 598 __be16 pcierr; 599 s64 rc; 600 int result; 601 602 /* 603 * We don't clobber hardware frozen state until PE 604 * reset is completed. In order to keep EEH core 605 * moving forward, we have to return operational 606 * state during PE reset. 607 */ 608 if (pe->state & EEH_PE_RESET) { 609 result = (EEH_STATE_MMIO_ACTIVE | 610 EEH_STATE_DMA_ACTIVE | 611 EEH_STATE_MMIO_ENABLED | 612 EEH_STATE_DMA_ENABLED); 613 return result; 614 } 615 616 /* 617 * Fetch PE state from hardware. If the PHB 618 * supports compound PE, let it handle that. 619 */ 620 if (phb->get_pe_state) { 621 fstate = phb->get_pe_state(phb, pe->addr); 622 } else { 623 rc = opal_pci_eeh_freeze_status(phb->opal_id, 624 pe->addr, 625 &fstate, 626 &pcierr, 627 NULL); 628 if (rc != OPAL_SUCCESS) { 629 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 630 __func__, rc, phb->hose->global_number, 631 pe->addr); 632 return EEH_STATE_NOT_SUPPORT; 633 } 634 } 635 636 /* Figure out state */ 637 switch (fstate) { 638 case OPAL_EEH_STOPPED_NOT_FROZEN: 639 result = (EEH_STATE_MMIO_ACTIVE | 640 EEH_STATE_DMA_ACTIVE | 641 EEH_STATE_MMIO_ENABLED | 642 EEH_STATE_DMA_ENABLED); 643 break; 644 case OPAL_EEH_STOPPED_MMIO_FREEZE: 645 result = (EEH_STATE_DMA_ACTIVE | 646 EEH_STATE_DMA_ENABLED); 647 break; 648 case OPAL_EEH_STOPPED_DMA_FREEZE: 649 result = (EEH_STATE_MMIO_ACTIVE | 650 EEH_STATE_MMIO_ENABLED); 651 break; 652 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 653 result = 0; 654 break; 655 case OPAL_EEH_STOPPED_RESET: 656 result = EEH_STATE_RESET_ACTIVE; 657 break; 658 case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 659 result = EEH_STATE_UNAVAILABLE; 660 break; 661 case OPAL_EEH_STOPPED_PERM_UNAVAIL: 662 result = EEH_STATE_NOT_SUPPORT; 663 break; 664 default: 665 result = EEH_STATE_NOT_SUPPORT; 666 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 667 __func__, phb->hose->global_number, 668 pe->addr, fstate); 669 } 670 671 /* 672 * If PHB supports compound PE, to freeze all 673 * slave PEs for consistency. 674 * 675 * If the PE is switching to frozen state for the 676 * first time, to dump the PHB diag-data. 677 */ 678 if (!(result & EEH_STATE_NOT_SUPPORT) && 679 !(result & EEH_STATE_UNAVAILABLE) && 680 !(result & EEH_STATE_MMIO_ACTIVE) && 681 !(result & EEH_STATE_DMA_ACTIVE) && 682 !(pe->state & EEH_PE_ISOLATED)) { 683 if (phb->freeze_pe) 684 phb->freeze_pe(phb, pe->addr); 685 686 eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 687 pnv_eeh_get_phb_diag(pe); 688 689 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 690 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 691 } 692 693 return result; 694 } 695 696 /** 697 * pnv_eeh_get_state - Retrieve PE state 698 * @pe: EEH PE 699 * @delay: delay while PE state is temporarily unavailable 700 * 701 * Retrieve the state of the specified PE. For IODA-compitable 702 * platform, it should be retrieved from IODA table. Therefore, 703 * we prefer passing down to hardware implementation to handle 704 * it. 705 */ 706 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 707 { 708 int ret; 709 710 if (pe->type & EEH_PE_PHB) 711 ret = pnv_eeh_get_phb_state(pe); 712 else 713 ret = pnv_eeh_get_pe_state(pe); 714 715 if (!delay) 716 return ret; 717 718 /* 719 * If the PE state is temporarily unavailable, 720 * to inform the EEH core delay for default 721 * period (1 second) 722 */ 723 *delay = 0; 724 if (ret & EEH_STATE_UNAVAILABLE) 725 *delay = 1000; 726 727 return ret; 728 } 729 730 static s64 pnv_eeh_poll(unsigned long id) 731 { 732 s64 rc = OPAL_HARDWARE; 733 734 while (1) { 735 rc = opal_pci_poll(id); 736 if (rc <= 0) 737 break; 738 739 if (system_state < SYSTEM_RUNNING) 740 udelay(1000 * rc); 741 else 742 msleep(rc); 743 } 744 745 return rc; 746 } 747 748 int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 749 { 750 struct pnv_phb *phb = hose->private_data; 751 s64 rc = OPAL_HARDWARE; 752 753 pr_debug("%s: Reset PHB#%x, option=%d\n", 754 __func__, hose->global_number, option); 755 756 /* Issue PHB complete reset request */ 757 if (option == EEH_RESET_FUNDAMENTAL || 758 option == EEH_RESET_HOT) 759 rc = opal_pci_reset(phb->opal_id, 760 OPAL_RESET_PHB_COMPLETE, 761 OPAL_ASSERT_RESET); 762 else if (option == EEH_RESET_DEACTIVATE) 763 rc = opal_pci_reset(phb->opal_id, 764 OPAL_RESET_PHB_COMPLETE, 765 OPAL_DEASSERT_RESET); 766 if (rc < 0) 767 goto out; 768 769 /* 770 * Poll state of the PHB until the request is done 771 * successfully. The PHB reset is usually PHB complete 772 * reset followed by hot reset on root bus. So we also 773 * need the PCI bus settlement delay. 774 */ 775 if (rc > 0) 776 rc = pnv_eeh_poll(phb->opal_id); 777 if (option == EEH_RESET_DEACTIVATE) { 778 if (system_state < SYSTEM_RUNNING) 779 udelay(1000 * EEH_PE_RST_SETTLE_TIME); 780 else 781 msleep(EEH_PE_RST_SETTLE_TIME); 782 } 783 out: 784 if (rc != OPAL_SUCCESS) 785 return -EIO; 786 787 return 0; 788 } 789 790 static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 791 { 792 struct pnv_phb *phb = hose->private_data; 793 s64 rc = OPAL_HARDWARE; 794 795 pr_debug("%s: Reset PHB#%x, option=%d\n", 796 __func__, hose->global_number, option); 797 798 /* 799 * During the reset deassert time, we needn't care 800 * the reset scope because the firmware does nothing 801 * for fundamental or hot reset during deassert phase. 802 */ 803 if (option == EEH_RESET_FUNDAMENTAL) 804 rc = opal_pci_reset(phb->opal_id, 805 OPAL_RESET_PCI_FUNDAMENTAL, 806 OPAL_ASSERT_RESET); 807 else if (option == EEH_RESET_HOT) 808 rc = opal_pci_reset(phb->opal_id, 809 OPAL_RESET_PCI_HOT, 810 OPAL_ASSERT_RESET); 811 else if (option == EEH_RESET_DEACTIVATE) 812 rc = opal_pci_reset(phb->opal_id, 813 OPAL_RESET_PCI_HOT, 814 OPAL_DEASSERT_RESET); 815 if (rc < 0) 816 goto out; 817 818 /* Poll state of the PHB until the request is done */ 819 if (rc > 0) 820 rc = pnv_eeh_poll(phb->opal_id); 821 if (option == EEH_RESET_DEACTIVATE) 822 msleep(EEH_PE_RST_SETTLE_TIME); 823 out: 824 if (rc != OPAL_SUCCESS) 825 return -EIO; 826 827 return 0; 828 } 829 830 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 831 { 832 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 833 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 834 int aer = edev ? edev->aer_cap : 0; 835 u32 ctrl; 836 837 pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 838 __func__, pci_domain_nr(dev->bus), 839 dev->bus->number, option); 840 841 switch (option) { 842 case EEH_RESET_FUNDAMENTAL: 843 case EEH_RESET_HOT: 844 /* Don't report linkDown event */ 845 if (aer) { 846 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 847 4, &ctrl); 848 ctrl |= PCI_ERR_UNC_SURPDN; 849 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 850 4, ctrl); 851 } 852 853 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 854 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 855 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 856 857 msleep(EEH_PE_RST_HOLD_TIME); 858 break; 859 case EEH_RESET_DEACTIVATE: 860 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 861 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 862 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 863 864 msleep(EEH_PE_RST_SETTLE_TIME); 865 866 /* Continue reporting linkDown event */ 867 if (aer) { 868 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 869 4, &ctrl); 870 ctrl &= ~PCI_ERR_UNC_SURPDN; 871 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 872 4, ctrl); 873 } 874 875 break; 876 } 877 878 return 0; 879 } 880 881 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 882 { 883 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 884 struct pnv_phb *phb = hose->private_data; 885 struct device_node *dn = pci_device_to_OF_node(pdev); 886 uint64_t id = PCI_SLOT_ID(phb->opal_id, 887 (pdev->bus->number << 8) | pdev->devfn); 888 uint8_t scope; 889 int64_t rc; 890 891 /* Hot reset to the bus if firmware cannot handle */ 892 if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 893 return __pnv_eeh_bridge_reset(pdev, option); 894 895 switch (option) { 896 case EEH_RESET_FUNDAMENTAL: 897 scope = OPAL_RESET_PCI_FUNDAMENTAL; 898 break; 899 case EEH_RESET_HOT: 900 scope = OPAL_RESET_PCI_HOT; 901 break; 902 case EEH_RESET_DEACTIVATE: 903 return 0; 904 default: 905 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 906 __func__, option); 907 return -EINVAL; 908 } 909 910 rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 911 if (rc <= OPAL_SUCCESS) 912 goto out; 913 914 rc = pnv_eeh_poll(id); 915 out: 916 return (rc == OPAL_SUCCESS) ? 0 : -EIO; 917 } 918 919 void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 920 { 921 struct pci_controller *hose; 922 923 if (pci_is_root_bus(dev->bus)) { 924 hose = pci_bus_to_host(dev->bus); 925 pnv_eeh_root_reset(hose, EEH_RESET_HOT); 926 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 927 } else { 928 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 929 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 930 } 931 } 932 933 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 934 int pos, u16 mask) 935 { 936 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 937 int i, status = 0; 938 939 /* Wait for Transaction Pending bit to be cleared */ 940 for (i = 0; i < 4; i++) { 941 eeh_ops->read_config(pdn, pos, 2, &status); 942 if (!(status & mask)) 943 return; 944 945 msleep((1 << i) * 100); 946 } 947 948 pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 949 __func__, type, 950 edev->phb->global_number, pdn->busno, 951 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 952 } 953 954 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 955 { 956 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 957 u32 reg = 0; 958 959 if (WARN_ON(!edev->pcie_cap)) 960 return -ENOTTY; 961 962 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 963 if (!(reg & PCI_EXP_DEVCAP_FLR)) 964 return -ENOTTY; 965 966 switch (option) { 967 case EEH_RESET_HOT: 968 case EEH_RESET_FUNDAMENTAL: 969 pnv_eeh_wait_for_pending(pdn, "", 970 edev->pcie_cap + PCI_EXP_DEVSTA, 971 PCI_EXP_DEVSTA_TRPND); 972 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 973 4, ®); 974 reg |= PCI_EXP_DEVCTL_BCR_FLR; 975 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 976 4, reg); 977 msleep(EEH_PE_RST_HOLD_TIME); 978 break; 979 case EEH_RESET_DEACTIVATE: 980 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 981 4, ®); 982 reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 983 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 984 4, reg); 985 msleep(EEH_PE_RST_SETTLE_TIME); 986 break; 987 } 988 989 return 0; 990 } 991 992 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 993 { 994 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 995 u32 cap = 0; 996 997 if (WARN_ON(!edev->af_cap)) 998 return -ENOTTY; 999 1000 eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 1001 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 1002 return -ENOTTY; 1003 1004 switch (option) { 1005 case EEH_RESET_HOT: 1006 case EEH_RESET_FUNDAMENTAL: 1007 /* 1008 * Wait for Transaction Pending bit to clear. A word-aligned 1009 * test is used, so we use the conrol offset rather than status 1010 * and shift the test bit to match. 1011 */ 1012 pnv_eeh_wait_for_pending(pdn, "AF", 1013 edev->af_cap + PCI_AF_CTRL, 1014 PCI_AF_STATUS_TP << 8); 1015 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1016 1, PCI_AF_CTRL_FLR); 1017 msleep(EEH_PE_RST_HOLD_TIME); 1018 break; 1019 case EEH_RESET_DEACTIVATE: 1020 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 1021 msleep(EEH_PE_RST_SETTLE_TIME); 1022 break; 1023 } 1024 1025 return 0; 1026 } 1027 1028 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 1029 { 1030 struct eeh_dev *edev; 1031 struct pci_dn *pdn; 1032 int ret; 1033 1034 /* The VF PE should have only one child device */ 1035 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list); 1036 pdn = eeh_dev_to_pdn(edev); 1037 if (!pdn) 1038 return -ENXIO; 1039 1040 ret = pnv_eeh_do_flr(pdn, option); 1041 if (!ret) 1042 return ret; 1043 1044 return pnv_eeh_do_af_flr(pdn, option); 1045 } 1046 1047 /** 1048 * pnv_eeh_reset - Reset the specified PE 1049 * @pe: EEH PE 1050 * @option: reset option 1051 * 1052 * Do reset on the indicated PE. For PCI bus sensitive PE, 1053 * we need to reset the parent p2p bridge. The PHB has to 1054 * be reinitialized if the p2p bridge is root bridge. For 1055 * PCI device sensitive PE, we will try to reset the device 1056 * through FLR. For now, we don't have OPAL APIs to do HARD 1057 * reset yet, so all reset would be SOFT (HOT) reset. 1058 */ 1059 static int pnv_eeh_reset(struct eeh_pe *pe, int option) 1060 { 1061 struct pci_controller *hose = pe->phb; 1062 struct pnv_phb *phb; 1063 struct pci_bus *bus; 1064 int64_t rc; 1065 1066 /* 1067 * For PHB reset, we always have complete reset. For those PEs whose 1068 * primary bus derived from root complex (root bus) or root port 1069 * (usually bus#1), we apply hot or fundamental reset on the root port. 1070 * For other PEs, we always have hot reset on the PE primary bus. 1071 * 1072 * Here, we have different design to pHyp, which always clear the 1073 * frozen state during PE reset. However, the good idea here from 1074 * benh is to keep frozen state before we get PE reset done completely 1075 * (until BAR restore). With the frozen state, HW drops illegal IO 1076 * or MMIO access, which can incur recrusive frozen PE during PE 1077 * reset. The side effect is that EEH core has to clear the frozen 1078 * state explicitly after BAR restore. 1079 */ 1080 if (pe->type & EEH_PE_PHB) 1081 return pnv_eeh_phb_reset(hose, option); 1082 1083 /* 1084 * The frozen PE might be caused by PAPR error injection 1085 * registers, which are expected to be cleared after hitting 1086 * frozen PE as stated in the hardware spec. Unfortunately, 1087 * that's not true on P7IOC. So we have to clear it manually 1088 * to avoid recursive EEH errors during recovery. 1089 */ 1090 phb = hose->private_data; 1091 if (phb->model == PNV_PHB_MODEL_P7IOC && 1092 (option == EEH_RESET_HOT || 1093 option == EEH_RESET_FUNDAMENTAL)) { 1094 rc = opal_pci_reset(phb->opal_id, 1095 OPAL_RESET_PHB_ERROR, 1096 OPAL_ASSERT_RESET); 1097 if (rc != OPAL_SUCCESS) { 1098 pr_warn("%s: Failure %lld clearing error injection registers\n", 1099 __func__, rc); 1100 return -EIO; 1101 } 1102 } 1103 1104 if (pe->type & EEH_PE_VF) 1105 return pnv_eeh_reset_vf_pe(pe, option); 1106 1107 bus = eeh_pe_bus_get(pe); 1108 if (!bus) { 1109 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 1110 __func__, pe->phb->global_number, pe->addr); 1111 return -EIO; 1112 } 1113 1114 /* 1115 * If dealing with the root bus (or the bus underneath the 1116 * root port), we reset the bus underneath the root port. 1117 * 1118 * The cxl driver depends on this behaviour for bi-modal card 1119 * switching. 1120 */ 1121 if (pci_is_root_bus(bus) || 1122 pci_is_root_bus(bus->parent)) 1123 return pnv_eeh_root_reset(hose, option); 1124 1125 return pnv_eeh_bridge_reset(bus->self, option); 1126 } 1127 1128 /** 1129 * pnv_eeh_wait_state - Wait for PE state 1130 * @pe: EEH PE 1131 * @max_wait: maximal period in millisecond 1132 * 1133 * Wait for the state of associated PE. It might take some time 1134 * to retrieve the PE's state. 1135 */ 1136 static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) 1137 { 1138 int ret; 1139 int mwait; 1140 1141 while (1) { 1142 ret = pnv_eeh_get_state(pe, &mwait); 1143 1144 /* 1145 * If the PE's state is temporarily unavailable, 1146 * we have to wait for the specified time. Otherwise, 1147 * the PE's state will be returned immediately. 1148 */ 1149 if (ret != EEH_STATE_UNAVAILABLE) 1150 return ret; 1151 1152 if (max_wait <= 0) { 1153 pr_warn("%s: Timeout getting PE#%x's state (%d)\n", 1154 __func__, pe->addr, max_wait); 1155 return EEH_STATE_NOT_SUPPORT; 1156 } 1157 1158 max_wait -= mwait; 1159 msleep(mwait); 1160 } 1161 1162 return EEH_STATE_NOT_SUPPORT; 1163 } 1164 1165 /** 1166 * pnv_eeh_get_log - Retrieve error log 1167 * @pe: EEH PE 1168 * @severity: temporary or permanent error log 1169 * @drv_log: driver log to be combined with retrieved error log 1170 * @len: length of driver log 1171 * 1172 * Retrieve the temporary or permanent error from the PE. 1173 */ 1174 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 1175 char *drv_log, unsigned long len) 1176 { 1177 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1178 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 1179 1180 return 0; 1181 } 1182 1183 /** 1184 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 1185 * @pe: EEH PE 1186 * 1187 * The function will be called to reconfigure the bridges included 1188 * in the specified PE so that the mulfunctional PE would be recovered 1189 * again. 1190 */ 1191 static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 1192 { 1193 return 0; 1194 } 1195 1196 /** 1197 * pnv_pe_err_inject - Inject specified error to the indicated PE 1198 * @pe: the indicated PE 1199 * @type: error type 1200 * @func: specific error type 1201 * @addr: address 1202 * @mask: address mask 1203 * 1204 * The routine is called to inject specified error, which is 1205 * determined by @type and @func, to the indicated PE for 1206 * testing purpose. 1207 */ 1208 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1209 unsigned long addr, unsigned long mask) 1210 { 1211 struct pci_controller *hose = pe->phb; 1212 struct pnv_phb *phb = hose->private_data; 1213 s64 rc; 1214 1215 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1216 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1217 pr_warn("%s: Invalid error type %d\n", 1218 __func__, type); 1219 return -ERANGE; 1220 } 1221 1222 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1223 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1224 pr_warn("%s: Invalid error function %d\n", 1225 __func__, func); 1226 return -ERANGE; 1227 } 1228 1229 /* Firmware supports error injection ? */ 1230 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1231 pr_warn("%s: Firmware doesn't support error injection\n", 1232 __func__); 1233 return -ENXIO; 1234 } 1235 1236 /* Do error injection */ 1237 rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1238 type, func, addr, mask); 1239 if (rc != OPAL_SUCCESS) { 1240 pr_warn("%s: Failure %lld injecting error " 1241 "%d-%d to PHB#%x-PE#%x\n", 1242 __func__, rc, type, func, 1243 hose->global_number, pe->addr); 1244 return -EIO; 1245 } 1246 1247 return 0; 1248 } 1249 1250 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1251 { 1252 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1253 1254 if (!edev || !edev->pe) 1255 return false; 1256 1257 /* 1258 * We will issue FLR or AF FLR to all VFs, which are contained 1259 * in VF PE. It relies on the EEH PCI config accessors. So we 1260 * can't block them during the window. 1261 */ 1262 if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 1263 return false; 1264 1265 if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1266 return true; 1267 1268 return false; 1269 } 1270 1271 static int pnv_eeh_read_config(struct pci_dn *pdn, 1272 int where, int size, u32 *val) 1273 { 1274 if (!pdn) 1275 return PCIBIOS_DEVICE_NOT_FOUND; 1276 1277 if (pnv_eeh_cfg_blocked(pdn)) { 1278 *val = 0xFFFFFFFF; 1279 return PCIBIOS_SET_FAILED; 1280 } 1281 1282 return pnv_pci_cfg_read(pdn, where, size, val); 1283 } 1284 1285 static int pnv_eeh_write_config(struct pci_dn *pdn, 1286 int where, int size, u32 val) 1287 { 1288 if (!pdn) 1289 return PCIBIOS_DEVICE_NOT_FOUND; 1290 1291 if (pnv_eeh_cfg_blocked(pdn)) 1292 return PCIBIOS_SET_FAILED; 1293 1294 return pnv_pci_cfg_write(pdn, where, size, val); 1295 } 1296 1297 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 1298 { 1299 /* GEM */ 1300 if (data->gemXfir || data->gemRfir || 1301 data->gemRirqfir || data->gemMask || data->gemRwof) 1302 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 1303 be64_to_cpu(data->gemXfir), 1304 be64_to_cpu(data->gemRfir), 1305 be64_to_cpu(data->gemRirqfir), 1306 be64_to_cpu(data->gemMask), 1307 be64_to_cpu(data->gemRwof)); 1308 1309 /* LEM */ 1310 if (data->lemFir || data->lemErrMask || 1311 data->lemAction0 || data->lemAction1 || data->lemWof) 1312 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 1313 be64_to_cpu(data->lemFir), 1314 be64_to_cpu(data->lemErrMask), 1315 be64_to_cpu(data->lemAction0), 1316 be64_to_cpu(data->lemAction1), 1317 be64_to_cpu(data->lemWof)); 1318 } 1319 1320 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 1321 { 1322 struct pnv_phb *phb = hose->private_data; 1323 struct OpalIoP7IOCErrorData *data = 1324 (struct OpalIoP7IOCErrorData*)phb->diag_data; 1325 long rc; 1326 1327 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 1328 if (rc != OPAL_SUCCESS) { 1329 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 1330 __func__, phb->hub_id, rc); 1331 return; 1332 } 1333 1334 switch (be16_to_cpu(data->type)) { 1335 case OPAL_P7IOC_DIAG_TYPE_RGC: 1336 pr_info("P7IOC diag-data for RGC\n\n"); 1337 pnv_eeh_dump_hub_diag_common(data); 1338 if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 1339 pr_info(" RGC: %016llx %016llx\n", 1340 be64_to_cpu(data->rgc.rgcStatus), 1341 be64_to_cpu(data->rgc.rgcLdcp)); 1342 break; 1343 case OPAL_P7IOC_DIAG_TYPE_BI: 1344 pr_info("P7IOC diag-data for BI %s\n\n", 1345 data->bi.biDownbound ? "Downbound" : "Upbound"); 1346 pnv_eeh_dump_hub_diag_common(data); 1347 if (data->bi.biLdcp0 || data->bi.biLdcp1 || 1348 data->bi.biLdcp2 || data->bi.biFenceStatus) 1349 pr_info(" BI: %016llx %016llx %016llx %016llx\n", 1350 be64_to_cpu(data->bi.biLdcp0), 1351 be64_to_cpu(data->bi.biLdcp1), 1352 be64_to_cpu(data->bi.biLdcp2), 1353 be64_to_cpu(data->bi.biFenceStatus)); 1354 break; 1355 case OPAL_P7IOC_DIAG_TYPE_CI: 1356 pr_info("P7IOC diag-data for CI Port %d\n\n", 1357 data->ci.ciPort); 1358 pnv_eeh_dump_hub_diag_common(data); 1359 if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 1360 pr_info(" CI: %016llx %016llx\n", 1361 be64_to_cpu(data->ci.ciPortStatus), 1362 be64_to_cpu(data->ci.ciPortLdcp)); 1363 break; 1364 case OPAL_P7IOC_DIAG_TYPE_MISC: 1365 pr_info("P7IOC diag-data for MISC\n\n"); 1366 pnv_eeh_dump_hub_diag_common(data); 1367 break; 1368 case OPAL_P7IOC_DIAG_TYPE_I2C: 1369 pr_info("P7IOC diag-data for I2C\n\n"); 1370 pnv_eeh_dump_hub_diag_common(data); 1371 break; 1372 default: 1373 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 1374 __func__, phb->hub_id, data->type); 1375 } 1376 } 1377 1378 static int pnv_eeh_get_pe(struct pci_controller *hose, 1379 u16 pe_no, struct eeh_pe **pe) 1380 { 1381 struct pnv_phb *phb = hose->private_data; 1382 struct pnv_ioda_pe *pnv_pe; 1383 struct eeh_pe *dev_pe; 1384 struct eeh_dev edev; 1385 1386 /* 1387 * If PHB supports compound PE, to fetch 1388 * the master PE because slave PE is invisible 1389 * to EEH core. 1390 */ 1391 pnv_pe = &phb->ioda.pe_array[pe_no]; 1392 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 1393 pnv_pe = pnv_pe->master; 1394 WARN_ON(!pnv_pe || 1395 !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 1396 pe_no = pnv_pe->pe_number; 1397 } 1398 1399 /* Find the PE according to PE# */ 1400 memset(&edev, 0, sizeof(struct eeh_dev)); 1401 edev.phb = hose; 1402 edev.pe_config_addr = pe_no; 1403 dev_pe = eeh_pe_get(&edev); 1404 if (!dev_pe) 1405 return -EEXIST; 1406 1407 /* Freeze the (compound) PE */ 1408 *pe = dev_pe; 1409 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1410 phb->freeze_pe(phb, pe_no); 1411 1412 /* 1413 * At this point, we're sure the (compound) PE should 1414 * have been frozen. However, we still need poke until 1415 * hitting the frozen PE on top level. 1416 */ 1417 dev_pe = dev_pe->parent; 1418 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 1419 int ret; 1420 int active_flags = (EEH_STATE_MMIO_ACTIVE | 1421 EEH_STATE_DMA_ACTIVE); 1422 1423 ret = eeh_ops->get_state(dev_pe, NULL); 1424 if (ret <= 0 || (ret & active_flags) == active_flags) { 1425 dev_pe = dev_pe->parent; 1426 continue; 1427 } 1428 1429 /* Frozen parent PE */ 1430 *pe = dev_pe; 1431 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1432 phb->freeze_pe(phb, dev_pe->addr); 1433 1434 /* Next one */ 1435 dev_pe = dev_pe->parent; 1436 } 1437 1438 return 0; 1439 } 1440 1441 /** 1442 * pnv_eeh_next_error - Retrieve next EEH error to handle 1443 * @pe: Affected PE 1444 * 1445 * The function is expected to be called by EEH core while it gets 1446 * special EEH event (without binding PE). The function calls to 1447 * OPAL APIs for next error to handle. The informational error is 1448 * handled internally by platform. However, the dead IOC, dead PHB, 1449 * fenced PHB and frozen PE should be handled by EEH core eventually. 1450 */ 1451 static int pnv_eeh_next_error(struct eeh_pe **pe) 1452 { 1453 struct pci_controller *hose; 1454 struct pnv_phb *phb; 1455 struct eeh_pe *phb_pe, *parent_pe; 1456 __be64 frozen_pe_no; 1457 __be16 err_type, severity; 1458 int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 1459 long rc; 1460 int state, ret = EEH_NEXT_ERR_NONE; 1461 1462 /* 1463 * While running here, it's safe to purge the event queue. The 1464 * event should still be masked. 1465 */ 1466 eeh_remove_event(NULL, false); 1467 1468 list_for_each_entry(hose, &hose_list, list_node) { 1469 /* 1470 * If the subordinate PCI buses of the PHB has been 1471 * removed or is exactly under error recovery, we 1472 * needn't take care of it any more. 1473 */ 1474 phb = hose->private_data; 1475 phb_pe = eeh_phb_pe_get(hose); 1476 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 1477 continue; 1478 1479 rc = opal_pci_next_error(phb->opal_id, 1480 &frozen_pe_no, &err_type, &severity); 1481 if (rc != OPAL_SUCCESS) { 1482 pr_devel("%s: Invalid return value on " 1483 "PHB#%x (0x%lx) from opal_pci_next_error", 1484 __func__, hose->global_number, rc); 1485 continue; 1486 } 1487 1488 /* If the PHB doesn't have error, stop processing */ 1489 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 1490 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 1491 pr_devel("%s: No error found on PHB#%x\n", 1492 __func__, hose->global_number); 1493 continue; 1494 } 1495 1496 /* 1497 * Processing the error. We're expecting the error with 1498 * highest priority reported upon multiple errors on the 1499 * specific PHB. 1500 */ 1501 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 1502 __func__, be16_to_cpu(err_type), 1503 be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 1504 hose->global_number); 1505 switch (be16_to_cpu(err_type)) { 1506 case OPAL_EEH_IOC_ERROR: 1507 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 1508 pr_err("EEH: dead IOC detected\n"); 1509 ret = EEH_NEXT_ERR_DEAD_IOC; 1510 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1511 pr_info("EEH: IOC informative error " 1512 "detected\n"); 1513 pnv_eeh_get_and_dump_hub_diag(hose); 1514 ret = EEH_NEXT_ERR_NONE; 1515 } 1516 1517 break; 1518 case OPAL_EEH_PHB_ERROR: 1519 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 1520 *pe = phb_pe; 1521 pr_err("EEH: dead PHB#%x detected, " 1522 "location: %s\n", 1523 hose->global_number, 1524 eeh_pe_loc_get(phb_pe)); 1525 ret = EEH_NEXT_ERR_DEAD_PHB; 1526 } else if (be16_to_cpu(severity) == 1527 OPAL_EEH_SEV_PHB_FENCED) { 1528 *pe = phb_pe; 1529 pr_err("EEH: Fenced PHB#%x detected, " 1530 "location: %s\n", 1531 hose->global_number, 1532 eeh_pe_loc_get(phb_pe)); 1533 ret = EEH_NEXT_ERR_FENCED_PHB; 1534 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1535 pr_info("EEH: PHB#%x informative error " 1536 "detected, location: %s\n", 1537 hose->global_number, 1538 eeh_pe_loc_get(phb_pe)); 1539 pnv_eeh_get_phb_diag(phb_pe); 1540 pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 1541 ret = EEH_NEXT_ERR_NONE; 1542 } 1543 1544 break; 1545 case OPAL_EEH_PE_ERROR: 1546 /* 1547 * If we can't find the corresponding PE, we 1548 * just try to unfreeze. 1549 */ 1550 if (pnv_eeh_get_pe(hose, 1551 be64_to_cpu(frozen_pe_no), pe)) { 1552 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 1553 hose->global_number, be64_to_cpu(frozen_pe_no)); 1554 pr_info("EEH: PHB location: %s\n", 1555 eeh_pe_loc_get(phb_pe)); 1556 1557 /* Dump PHB diag-data */ 1558 rc = opal_pci_get_phb_diag_data2(phb->opal_id, 1559 phb->diag_data, phb->diag_data_size); 1560 if (rc == OPAL_SUCCESS) 1561 pnv_pci_dump_phb_diag_data(hose, 1562 phb->diag_data); 1563 1564 /* Try best to clear it */ 1565 opal_pci_eeh_freeze_clear(phb->opal_id, 1566 be64_to_cpu(frozen_pe_no), 1567 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 1568 ret = EEH_NEXT_ERR_NONE; 1569 } else if ((*pe)->state & EEH_PE_ISOLATED || 1570 eeh_pe_passed(*pe)) { 1571 ret = EEH_NEXT_ERR_NONE; 1572 } else { 1573 pr_err("EEH: Frozen PE#%x " 1574 "on PHB#%x detected\n", 1575 (*pe)->addr, 1576 (*pe)->phb->global_number); 1577 pr_err("EEH: PE location: %s, " 1578 "PHB location: %s\n", 1579 eeh_pe_loc_get(*pe), 1580 eeh_pe_loc_get(phb_pe)); 1581 ret = EEH_NEXT_ERR_FROZEN_PE; 1582 } 1583 1584 break; 1585 default: 1586 pr_warn("%s: Unexpected error type %d\n", 1587 __func__, be16_to_cpu(err_type)); 1588 } 1589 1590 /* 1591 * EEH core will try recover from fenced PHB or 1592 * frozen PE. In the time for frozen PE, EEH core 1593 * enable IO path for that before collecting logs, 1594 * but it ruins the site. So we have to dump the 1595 * log in advance here. 1596 */ 1597 if ((ret == EEH_NEXT_ERR_FROZEN_PE || 1598 ret == EEH_NEXT_ERR_FENCED_PHB) && 1599 !((*pe)->state & EEH_PE_ISOLATED)) { 1600 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 1601 pnv_eeh_get_phb_diag(*pe); 1602 1603 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1604 pnv_pci_dump_phb_diag_data((*pe)->phb, 1605 (*pe)->data); 1606 } 1607 1608 /* 1609 * We probably have the frozen parent PE out there and 1610 * we need have to handle frozen parent PE firstly. 1611 */ 1612 if (ret == EEH_NEXT_ERR_FROZEN_PE) { 1613 parent_pe = (*pe)->parent; 1614 while (parent_pe) { 1615 /* Hit the ceiling ? */ 1616 if (parent_pe->type & EEH_PE_PHB) 1617 break; 1618 1619 /* Frozen parent PE ? */ 1620 state = eeh_ops->get_state(parent_pe, NULL); 1621 if (state > 0 && 1622 (state & active_flags) != active_flags) 1623 *pe = parent_pe; 1624 1625 /* Next parent level */ 1626 parent_pe = parent_pe->parent; 1627 } 1628 1629 /* We possibly migrate to another PE */ 1630 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 1631 } 1632 1633 /* 1634 * If we have no errors on the specific PHB or only 1635 * informative error there, we continue poking it. 1636 * Otherwise, we need actions to be taken by upper 1637 * layer. 1638 */ 1639 if (ret > EEH_NEXT_ERR_INF) 1640 break; 1641 } 1642 1643 /* Unmask the event */ 1644 if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 1645 enable_irq(eeh_event_irq); 1646 1647 return ret; 1648 } 1649 1650 static int pnv_eeh_restore_vf_config(struct pci_dn *pdn) 1651 { 1652 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1653 u32 devctl, cmd, cap2, aer_capctl; 1654 int old_mps; 1655 1656 if (edev->pcie_cap) { 1657 /* Restore MPS */ 1658 old_mps = (ffs(pdn->mps) - 8) << 5; 1659 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1660 2, &devctl); 1661 devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; 1662 devctl |= old_mps; 1663 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1664 2, devctl); 1665 1666 /* Disable Completion Timeout */ 1667 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2, 1668 4, &cap2); 1669 if (cap2 & 0x10) { 1670 eeh_ops->read_config(pdn, 1671 edev->pcie_cap + PCI_EXP_DEVCTL2, 1672 4, &cap2); 1673 cap2 |= 0x10; 1674 eeh_ops->write_config(pdn, 1675 edev->pcie_cap + PCI_EXP_DEVCTL2, 1676 4, cap2); 1677 } 1678 } 1679 1680 /* Enable SERR and parity checking */ 1681 eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd); 1682 cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 1683 eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd); 1684 1685 /* Enable report various errors */ 1686 if (edev->pcie_cap) { 1687 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1688 2, &devctl); 1689 devctl &= ~PCI_EXP_DEVCTL_CERE; 1690 devctl |= (PCI_EXP_DEVCTL_NFERE | 1691 PCI_EXP_DEVCTL_FERE | 1692 PCI_EXP_DEVCTL_URRE); 1693 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1694 2, devctl); 1695 } 1696 1697 /* Enable ECRC generation and check */ 1698 if (edev->pcie_cap && edev->aer_cap) { 1699 eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP, 1700 4, &aer_capctl); 1701 aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 1702 eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP, 1703 4, aer_capctl); 1704 } 1705 1706 return 0; 1707 } 1708 1709 static int pnv_eeh_restore_config(struct pci_dn *pdn) 1710 { 1711 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1712 struct pnv_phb *phb; 1713 s64 ret; 1714 1715 if (!edev) 1716 return -EEXIST; 1717 1718 /* 1719 * We have to restore the PCI config space after reset since the 1720 * firmware can't see SRIOV VFs. 1721 * 1722 * FIXME: The MPS, error routing rules, timeout setting are worthy 1723 * to be exported by firmware in extendible way. 1724 */ 1725 if (edev->physfn) { 1726 ret = pnv_eeh_restore_vf_config(pdn); 1727 } else { 1728 phb = edev->phb->private_data; 1729 ret = opal_pci_reinit(phb->opal_id, 1730 OPAL_REINIT_PCI_DEV, edev->config_addr); 1731 } 1732 1733 if (ret) { 1734 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 1735 __func__, edev->config_addr, ret); 1736 return -EIO; 1737 } 1738 1739 return 0; 1740 } 1741 1742 static struct eeh_ops pnv_eeh_ops = { 1743 .name = "powernv", 1744 .init = pnv_eeh_init, 1745 .post_init = pnv_eeh_post_init, 1746 .probe = pnv_eeh_probe, 1747 .set_option = pnv_eeh_set_option, 1748 .get_pe_addr = pnv_eeh_get_pe_addr, 1749 .get_state = pnv_eeh_get_state, 1750 .reset = pnv_eeh_reset, 1751 .wait_state = pnv_eeh_wait_state, 1752 .get_log = pnv_eeh_get_log, 1753 .configure_bridge = pnv_eeh_configure_bridge, 1754 .err_inject = pnv_eeh_err_inject, 1755 .read_config = pnv_eeh_read_config, 1756 .write_config = pnv_eeh_write_config, 1757 .next_error = pnv_eeh_next_error, 1758 .restore_config = pnv_eeh_restore_config 1759 }; 1760 1761 void pcibios_bus_add_device(struct pci_dev *pdev) 1762 { 1763 struct pci_dn *pdn = pci_get_pdn(pdev); 1764 1765 if (!pdev->is_virtfn) 1766 return; 1767 1768 /* 1769 * The following operations will fail if VF's sysfs files 1770 * aren't created or its resources aren't finalized. 1771 */ 1772 eeh_add_device_early(pdn); 1773 eeh_add_device_late(pdev); 1774 eeh_sysfs_add_device(pdev); 1775 } 1776 1777 #ifdef CONFIG_PCI_IOV 1778 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 1779 { 1780 struct pci_dn *pdn = pci_get_pdn(pdev); 1781 int parent_mps; 1782 1783 if (!pdev->is_virtfn) 1784 return; 1785 1786 /* Synchronize MPS for VF and PF */ 1787 parent_mps = pcie_get_mps(pdev->physfn); 1788 if ((128 << pdev->pcie_mpss) >= parent_mps) 1789 pcie_set_mps(pdev, parent_mps); 1790 pdn->mps = pcie_get_mps(pdev); 1791 } 1792 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 1793 #endif /* CONFIG_PCI_IOV */ 1794 1795 /** 1796 * eeh_powernv_init - Register platform dependent EEH operations 1797 * 1798 * EEH initialization on powernv platform. This function should be 1799 * called before any EEH related functions. 1800 */ 1801 static int __init eeh_powernv_init(void) 1802 { 1803 int ret = -EINVAL; 1804 1805 ret = eeh_ops_register(&pnv_eeh_ops); 1806 if (!ret) 1807 pr_info("EEH: PowerNV platform initialized\n"); 1808 else 1809 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 1810 1811 return ret; 1812 } 1813 machine_early_initcall(powernv, eeh_powernv_init); 1814