1 /* 2 * The file intends to implement the platform dependent EEH operations on 3 * powernv platform. Actually, the powernv was created in order to fully 4 * hypervisor support. 5 * 6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/atomic.h> 15 #include <linux/delay.h> 16 #include <linux/export.h> 17 #include <linux/init.h> 18 #include <linux/list.h> 19 #include <linux/msi.h> 20 #include <linux/of.h> 21 #include <linux/pci.h> 22 #include <linux/proc_fs.h> 23 #include <linux/rbtree.h> 24 #include <linux/sched.h> 25 #include <linux/seq_file.h> 26 #include <linux/spinlock.h> 27 28 #include <asm/eeh.h> 29 #include <asm/eeh_event.h> 30 #include <asm/firmware.h> 31 #include <asm/io.h> 32 #include <asm/iommu.h> 33 #include <asm/machdep.h> 34 #include <asm/msi_bitmap.h> 35 #include <asm/opal.h> 36 #include <asm/ppc-pci.h> 37 38 #include "powernv.h" 39 #include "pci.h" 40 41 /** 42 * powernv_eeh_init - EEH platform dependent initialization 43 * 44 * EEH platform dependent initialization on powernv 45 */ 46 static int powernv_eeh_init(void) 47 { 48 /* We require OPALv3 */ 49 if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 50 pr_warning("%s: OPALv3 is required !\n", __func__); 51 return -EINVAL; 52 } 53 54 /* Set EEH probe mode */ 55 eeh_probe_mode_set(EEH_PROBE_MODE_DEV); 56 57 return 0; 58 } 59 60 /** 61 * powernv_eeh_post_init - EEH platform dependent post initialization 62 * 63 * EEH platform dependent post initialization on powernv. When 64 * the function is called, the EEH PEs and devices should have 65 * been built. If the I/O cache staff has been built, EEH is 66 * ready to supply service. 67 */ 68 static int powernv_eeh_post_init(void) 69 { 70 struct pci_controller *hose; 71 struct pnv_phb *phb; 72 int ret = 0; 73 74 list_for_each_entry(hose, &hose_list, list_node) { 75 phb = hose->private_data; 76 77 if (phb->eeh_ops && phb->eeh_ops->post_init) { 78 ret = phb->eeh_ops->post_init(hose); 79 if (ret) 80 break; 81 } 82 } 83 84 return ret; 85 } 86 87 /** 88 * powernv_eeh_dev_probe - Do probe on PCI device 89 * @dev: PCI device 90 * @flag: unused 91 * 92 * When EEH module is installed during system boot, all PCI devices 93 * are checked one by one to see if it supports EEH. The function 94 * is introduced for the purpose. By default, EEH has been enabled 95 * on all PCI devices. That's to say, we only need do necessary 96 * initialization on the corresponding eeh device and create PE 97 * accordingly. 98 * 99 * It's notable that's unsafe to retrieve the EEH device through 100 * the corresponding PCI device. During the PCI device hotplug, which 101 * was possiblly triggered by EEH core, the binding between EEH device 102 * and the PCI device isn't built yet. 103 */ 104 static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag) 105 { 106 struct pci_controller *hose = pci_bus_to_host(dev->bus); 107 struct pnv_phb *phb = hose->private_data; 108 struct device_node *dn = pci_device_to_OF_node(dev); 109 struct eeh_dev *edev = of_node_to_eeh_dev(dn); 110 int ret; 111 112 /* 113 * When probing the root bridge, which doesn't have any 114 * subordinate PCI devices. We don't have OF node for 115 * the root bridge. So it's not reasonable to continue 116 * the probing. 117 */ 118 if (!dn || !edev || edev->pe) 119 return 0; 120 121 /* Skip for PCI-ISA bridge */ 122 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_ISA) 123 return 0; 124 125 /* Initialize eeh device */ 126 edev->class_code = dev->class; 127 edev->mode &= 0xFFFFFF00; 128 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 129 edev->mode |= EEH_DEV_BRIDGE; 130 edev->pcix_cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 131 if (pci_is_pcie(dev)) { 132 edev->pcie_cap = pci_pcie_cap(dev); 133 134 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 135 edev->mode |= EEH_DEV_ROOT_PORT; 136 else if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) 137 edev->mode |= EEH_DEV_DS_PORT; 138 139 edev->aer_cap = pci_find_ext_capability(dev, 140 PCI_EXT_CAP_ID_ERR); 141 } 142 143 edev->config_addr = ((dev->bus->number << 8) | dev->devfn); 144 edev->pe_config_addr = phb->bdfn_to_pe(phb, dev->bus, dev->devfn & 0xff); 145 146 /* Create PE */ 147 ret = eeh_add_to_parent_pe(edev); 148 if (ret) { 149 pr_warn("%s: Can't add PCI dev %s to parent PE (%d)\n", 150 __func__, pci_name(dev), ret); 151 return ret; 152 } 153 154 /* 155 * Cache the PE primary bus, which can't be fetched when 156 * full hotplug is in progress. In that case, all child 157 * PCI devices of the PE are expected to be removed prior 158 * to PE reset. 159 */ 160 if (!edev->pe->bus) 161 edev->pe->bus = dev->bus; 162 163 /* 164 * Enable EEH explicitly so that we will do EEH check 165 * while accessing I/O stuff 166 */ 167 eeh_set_enable(true); 168 169 /* Save memory bars */ 170 eeh_save_bars(edev); 171 172 return 0; 173 } 174 175 /** 176 * powernv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 177 * @pe: EEH PE 178 * @option: operation to be issued 179 * 180 * The function is used to control the EEH functionality globally. 181 * Currently, following options are support according to PAPR: 182 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 183 */ 184 static int powernv_eeh_set_option(struct eeh_pe *pe, int option) 185 { 186 struct pci_controller *hose = pe->phb; 187 struct pnv_phb *phb = hose->private_data; 188 int ret = -EEXIST; 189 190 /* 191 * What we need do is pass it down for hardware 192 * implementation to handle it. 193 */ 194 if (phb->eeh_ops && phb->eeh_ops->set_option) 195 ret = phb->eeh_ops->set_option(pe, option); 196 197 return ret; 198 } 199 200 /** 201 * powernv_eeh_get_pe_addr - Retrieve PE address 202 * @pe: EEH PE 203 * 204 * Retrieve the PE address according to the given tranditional 205 * PCI BDF (Bus/Device/Function) address. 206 */ 207 static int powernv_eeh_get_pe_addr(struct eeh_pe *pe) 208 { 209 return pe->addr; 210 } 211 212 /** 213 * powernv_eeh_get_state - Retrieve PE state 214 * @pe: EEH PE 215 * @delay: delay while PE state is temporarily unavailable 216 * 217 * Retrieve the state of the specified PE. For IODA-compitable 218 * platform, it should be retrieved from IODA table. Therefore, 219 * we prefer passing down to hardware implementation to handle 220 * it. 221 */ 222 static int powernv_eeh_get_state(struct eeh_pe *pe, int *delay) 223 { 224 struct pci_controller *hose = pe->phb; 225 struct pnv_phb *phb = hose->private_data; 226 int ret = EEH_STATE_NOT_SUPPORT; 227 228 if (phb->eeh_ops && phb->eeh_ops->get_state) { 229 ret = phb->eeh_ops->get_state(pe); 230 231 /* 232 * If the PE state is temporarily unavailable, 233 * to inform the EEH core delay for default 234 * period (1 second) 235 */ 236 if (delay) { 237 *delay = 0; 238 if (ret & EEH_STATE_UNAVAILABLE) 239 *delay = 1000; 240 } 241 } 242 243 return ret; 244 } 245 246 /** 247 * powernv_eeh_reset - Reset the specified PE 248 * @pe: EEH PE 249 * @option: reset option 250 * 251 * Reset the specified PE 252 */ 253 static int powernv_eeh_reset(struct eeh_pe *pe, int option) 254 { 255 struct pci_controller *hose = pe->phb; 256 struct pnv_phb *phb = hose->private_data; 257 int ret = -EEXIST; 258 259 if (phb->eeh_ops && phb->eeh_ops->reset) 260 ret = phb->eeh_ops->reset(pe, option); 261 262 return ret; 263 } 264 265 /** 266 * powernv_eeh_wait_state - Wait for PE state 267 * @pe: EEH PE 268 * @max_wait: maximal period in microsecond 269 * 270 * Wait for the state of associated PE. It might take some time 271 * to retrieve the PE's state. 272 */ 273 static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait) 274 { 275 int ret; 276 int mwait; 277 278 while (1) { 279 ret = powernv_eeh_get_state(pe, &mwait); 280 281 /* 282 * If the PE's state is temporarily unavailable, 283 * we have to wait for the specified time. Otherwise, 284 * the PE's state will be returned immediately. 285 */ 286 if (ret != EEH_STATE_UNAVAILABLE) 287 return ret; 288 289 max_wait -= mwait; 290 if (max_wait <= 0) { 291 pr_warning("%s: Timeout getting PE#%x's state (%d)\n", 292 __func__, pe->addr, max_wait); 293 return EEH_STATE_NOT_SUPPORT; 294 } 295 296 msleep(mwait); 297 } 298 299 return EEH_STATE_NOT_SUPPORT; 300 } 301 302 /** 303 * powernv_eeh_get_log - Retrieve error log 304 * @pe: EEH PE 305 * @severity: temporary or permanent error log 306 * @drv_log: driver log to be combined with retrieved error log 307 * @len: length of driver log 308 * 309 * Retrieve the temporary or permanent error from the PE. 310 */ 311 static int powernv_eeh_get_log(struct eeh_pe *pe, int severity, 312 char *drv_log, unsigned long len) 313 { 314 struct pci_controller *hose = pe->phb; 315 struct pnv_phb *phb = hose->private_data; 316 int ret = -EEXIST; 317 318 if (phb->eeh_ops && phb->eeh_ops->get_log) 319 ret = phb->eeh_ops->get_log(pe, severity, drv_log, len); 320 321 return ret; 322 } 323 324 /** 325 * powernv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 326 * @pe: EEH PE 327 * 328 * The function will be called to reconfigure the bridges included 329 * in the specified PE so that the mulfunctional PE would be recovered 330 * again. 331 */ 332 static int powernv_eeh_configure_bridge(struct eeh_pe *pe) 333 { 334 struct pci_controller *hose = pe->phb; 335 struct pnv_phb *phb = hose->private_data; 336 int ret = 0; 337 338 if (phb->eeh_ops && phb->eeh_ops->configure_bridge) 339 ret = phb->eeh_ops->configure_bridge(pe); 340 341 return ret; 342 } 343 344 /** 345 * powernv_eeh_next_error - Retrieve next EEH error to handle 346 * @pe: Affected PE 347 * 348 * Using OPAL API, to retrieve next EEH error for EEH core to handle 349 */ 350 static int powernv_eeh_next_error(struct eeh_pe **pe) 351 { 352 struct pci_controller *hose; 353 struct pnv_phb *phb = NULL; 354 355 list_for_each_entry(hose, &hose_list, list_node) { 356 phb = hose->private_data; 357 break; 358 } 359 360 if (phb && phb->eeh_ops->next_error) 361 return phb->eeh_ops->next_error(pe); 362 363 return -EEXIST; 364 } 365 366 static int powernv_eeh_restore_config(struct device_node *dn) 367 { 368 struct eeh_dev *edev = of_node_to_eeh_dev(dn); 369 struct pnv_phb *phb; 370 s64 ret; 371 372 if (!edev) 373 return -EEXIST; 374 375 phb = edev->phb->private_data; 376 ret = opal_pci_reinit(phb->opal_id, 377 OPAL_REINIT_PCI_DEV, edev->config_addr); 378 if (ret) { 379 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 380 __func__, edev->config_addr, ret); 381 return -EIO; 382 } 383 384 return 0; 385 } 386 387 static struct eeh_ops powernv_eeh_ops = { 388 .name = "powernv", 389 .init = powernv_eeh_init, 390 .post_init = powernv_eeh_post_init, 391 .of_probe = NULL, 392 .dev_probe = powernv_eeh_dev_probe, 393 .set_option = powernv_eeh_set_option, 394 .get_pe_addr = powernv_eeh_get_pe_addr, 395 .get_state = powernv_eeh_get_state, 396 .reset = powernv_eeh_reset, 397 .wait_state = powernv_eeh_wait_state, 398 .get_log = powernv_eeh_get_log, 399 .configure_bridge = powernv_eeh_configure_bridge, 400 .read_config = pnv_pci_cfg_read, 401 .write_config = pnv_pci_cfg_write, 402 .next_error = powernv_eeh_next_error, 403 .restore_config = powernv_eeh_restore_config 404 }; 405 406 /** 407 * eeh_powernv_init - Register platform dependent EEH operations 408 * 409 * EEH initialization on powernv platform. This function should be 410 * called before any EEH related functions. 411 */ 412 static int __init eeh_powernv_init(void) 413 { 414 int ret = -EINVAL; 415 416 ret = eeh_ops_register(&powernv_eeh_ops); 417 if (!ret) 418 pr_info("EEH: PowerNV platform initialized\n"); 419 else 420 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 421 422 return ret; 423 } 424 machine_early_initcall(powernv, eeh_powernv_init); 425