1 /*
2  * The file intends to implement the platform dependent EEH operations on
3  * powernv platform. Actually, the powernv was created in order to fully
4  * hypervisor support.
5  *
6  * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13 
14 #include <linux/atomic.h>
15 #include <linux/delay.h>
16 #include <linux/export.h>
17 #include <linux/init.h>
18 #include <linux/list.h>
19 #include <linux/msi.h>
20 #include <linux/of.h>
21 #include <linux/pci.h>
22 #include <linux/proc_fs.h>
23 #include <linux/rbtree.h>
24 #include <linux/sched.h>
25 #include <linux/seq_file.h>
26 #include <linux/spinlock.h>
27 
28 #include <asm/eeh.h>
29 #include <asm/eeh_event.h>
30 #include <asm/firmware.h>
31 #include <asm/io.h>
32 #include <asm/iommu.h>
33 #include <asm/machdep.h>
34 #include <asm/msi_bitmap.h>
35 #include <asm/opal.h>
36 #include <asm/ppc-pci.h>
37 
38 #include "powernv.h"
39 #include "pci.h"
40 
41 /**
42  * powernv_eeh_init - EEH platform dependent initialization
43  *
44  * EEH platform dependent initialization on powernv
45  */
46 static int powernv_eeh_init(void)
47 {
48 	/* We require OPALv3 */
49 	if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
50 		pr_warning("%s: OPALv3 is required !\n", __func__);
51 		return -EINVAL;
52 	}
53 
54 	/* Set EEH probe mode */
55 	eeh_probe_mode_set(EEH_PROBE_MODE_DEV);
56 
57 	return 0;
58 }
59 
60 /**
61  * powernv_eeh_post_init - EEH platform dependent post initialization
62  *
63  * EEH platform dependent post initialization on powernv. When
64  * the function is called, the EEH PEs and devices should have
65  * been built. If the I/O cache staff has been built, EEH is
66  * ready to supply service.
67  */
68 static int powernv_eeh_post_init(void)
69 {
70 	struct pci_controller *hose;
71 	struct pnv_phb *phb;
72 	int ret = 0;
73 
74 	list_for_each_entry(hose, &hose_list, list_node) {
75 		phb = hose->private_data;
76 
77 		if (phb->eeh_ops && phb->eeh_ops->post_init) {
78 			ret = phb->eeh_ops->post_init(hose);
79 			if (ret)
80 				break;
81 		}
82 	}
83 
84 	return ret;
85 }
86 
87 /**
88  * powernv_eeh_dev_probe - Do probe on PCI device
89  * @dev: PCI device
90  * @flag: unused
91  *
92  * When EEH module is installed during system boot, all PCI devices
93  * are checked one by one to see if it supports EEH. The function
94  * is introduced for the purpose. By default, EEH has been enabled
95  * on all PCI devices. That's to say, we only need do necessary
96  * initialization on the corresponding eeh device and create PE
97  * accordingly.
98  *
99  * It's notable that's unsafe to retrieve the EEH device through
100  * the corresponding PCI device. During the PCI device hotplug, which
101  * was possiblly triggered by EEH core, the binding between EEH device
102  * and the PCI device isn't built yet.
103  */
104 static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
105 {
106 	struct pci_controller *hose = pci_bus_to_host(dev->bus);
107 	struct pnv_phb *phb = hose->private_data;
108 	struct device_node *dn = pci_device_to_OF_node(dev);
109 	struct eeh_dev *edev = of_node_to_eeh_dev(dn);
110 
111 	/*
112 	 * When probing the root bridge, which doesn't have any
113 	 * subordinate PCI devices. We don't have OF node for
114 	 * the root bridge. So it's not reasonable to continue
115 	 * the probing.
116 	 */
117 	if (!dn || !edev || edev->pe)
118 		return 0;
119 
120 	/* Skip for PCI-ISA bridge */
121 	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
122 		return 0;
123 
124 	/* Initialize eeh device */
125 	edev->class_code = dev->class;
126 	edev->mode	&= 0xFFFFFF00;
127 	if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
128 		edev->mode |= EEH_DEV_BRIDGE;
129 	edev->pcix_cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
130 	if (pci_is_pcie(dev)) {
131 		edev->pcie_cap = pci_pcie_cap(dev);
132 
133 		if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
134 			edev->mode |= EEH_DEV_ROOT_PORT;
135 		else if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)
136 			edev->mode |= EEH_DEV_DS_PORT;
137 
138 		edev->aer_cap = pci_find_ext_capability(dev,
139 							PCI_EXT_CAP_ID_ERR);
140 	}
141 
142 	edev->config_addr	= ((dev->bus->number << 8) | dev->devfn);
143 	edev->pe_config_addr	= phb->bdfn_to_pe(phb, dev->bus, dev->devfn & 0xff);
144 
145 	/* Create PE */
146 	eeh_add_to_parent_pe(edev);
147 
148 	/*
149 	 * Enable EEH explicitly so that we will do EEH check
150 	 * while accessing I/O stuff
151 	 */
152 	eeh_set_enable(true);
153 
154 	/* Save memory bars */
155 	eeh_save_bars(edev);
156 
157 	return 0;
158 }
159 
160 /**
161  * powernv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
162  * @pe: EEH PE
163  * @option: operation to be issued
164  *
165  * The function is used to control the EEH functionality globally.
166  * Currently, following options are support according to PAPR:
167  * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
168  */
169 static int powernv_eeh_set_option(struct eeh_pe *pe, int option)
170 {
171 	struct pci_controller *hose = pe->phb;
172 	struct pnv_phb *phb = hose->private_data;
173 	int ret = -EEXIST;
174 
175 	/*
176 	 * What we need do is pass it down for hardware
177 	 * implementation to handle it.
178 	 */
179 	if (phb->eeh_ops && phb->eeh_ops->set_option)
180 		ret = phb->eeh_ops->set_option(pe, option);
181 
182 	return ret;
183 }
184 
185 /**
186  * powernv_eeh_get_pe_addr - Retrieve PE address
187  * @pe: EEH PE
188  *
189  * Retrieve the PE address according to the given tranditional
190  * PCI BDF (Bus/Device/Function) address.
191  */
192 static int powernv_eeh_get_pe_addr(struct eeh_pe *pe)
193 {
194 	return pe->addr;
195 }
196 
197 /**
198  * powernv_eeh_get_state - Retrieve PE state
199  * @pe: EEH PE
200  * @delay: delay while PE state is temporarily unavailable
201  *
202  * Retrieve the state of the specified PE. For IODA-compitable
203  * platform, it should be retrieved from IODA table. Therefore,
204  * we prefer passing down to hardware implementation to handle
205  * it.
206  */
207 static int powernv_eeh_get_state(struct eeh_pe *pe, int *delay)
208 {
209 	struct pci_controller *hose = pe->phb;
210 	struct pnv_phb *phb = hose->private_data;
211 	int ret = EEH_STATE_NOT_SUPPORT;
212 
213 	if (phb->eeh_ops && phb->eeh_ops->get_state) {
214 		ret = phb->eeh_ops->get_state(pe);
215 
216 		/*
217 		 * If the PE state is temporarily unavailable,
218 		 * to inform the EEH core delay for default
219 		 * period (1 second)
220 		 */
221 		if (delay) {
222 			*delay = 0;
223 			if (ret & EEH_STATE_UNAVAILABLE)
224 				*delay = 1000;
225 		}
226 	}
227 
228 	return ret;
229 }
230 
231 /**
232  * powernv_eeh_reset - Reset the specified PE
233  * @pe: EEH PE
234  * @option: reset option
235  *
236  * Reset the specified PE
237  */
238 static int powernv_eeh_reset(struct eeh_pe *pe, int option)
239 {
240 	struct pci_controller *hose = pe->phb;
241 	struct pnv_phb *phb = hose->private_data;
242 	int ret = -EEXIST;
243 
244 	if (phb->eeh_ops && phb->eeh_ops->reset)
245 		ret = phb->eeh_ops->reset(pe, option);
246 
247 	return ret;
248 }
249 
250 /**
251  * powernv_eeh_wait_state - Wait for PE state
252  * @pe: EEH PE
253  * @max_wait: maximal period in microsecond
254  *
255  * Wait for the state of associated PE. It might take some time
256  * to retrieve the PE's state.
257  */
258 static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
259 {
260 	int ret;
261 	int mwait;
262 
263 	while (1) {
264 		ret = powernv_eeh_get_state(pe, &mwait);
265 
266 		/*
267 		 * If the PE's state is temporarily unavailable,
268 		 * we have to wait for the specified time. Otherwise,
269 		 * the PE's state will be returned immediately.
270 		 */
271 		if (ret != EEH_STATE_UNAVAILABLE)
272 			return ret;
273 
274 		max_wait -= mwait;
275 		if (max_wait <= 0) {
276 			pr_warning("%s: Timeout getting PE#%x's state (%d)\n",
277 				   __func__, pe->addr, max_wait);
278 			return EEH_STATE_NOT_SUPPORT;
279 		}
280 
281 		msleep(mwait);
282 	}
283 
284 	return EEH_STATE_NOT_SUPPORT;
285 }
286 
287 /**
288  * powernv_eeh_get_log - Retrieve error log
289  * @pe: EEH PE
290  * @severity: temporary or permanent error log
291  * @drv_log: driver log to be combined with retrieved error log
292  * @len: length of driver log
293  *
294  * Retrieve the temporary or permanent error from the PE.
295  */
296 static int powernv_eeh_get_log(struct eeh_pe *pe, int severity,
297 			char *drv_log, unsigned long len)
298 {
299 	struct pci_controller *hose = pe->phb;
300 	struct pnv_phb *phb = hose->private_data;
301 	int ret = -EEXIST;
302 
303 	if (phb->eeh_ops && phb->eeh_ops->get_log)
304 		ret = phb->eeh_ops->get_log(pe, severity, drv_log, len);
305 
306 	return ret;
307 }
308 
309 /**
310  * powernv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
311  * @pe: EEH PE
312  *
313  * The function will be called to reconfigure the bridges included
314  * in the specified PE so that the mulfunctional PE would be recovered
315  * again.
316  */
317 static int powernv_eeh_configure_bridge(struct eeh_pe *pe)
318 {
319 	struct pci_controller *hose = pe->phb;
320 	struct pnv_phb *phb = hose->private_data;
321 	int ret = 0;
322 
323 	if (phb->eeh_ops && phb->eeh_ops->configure_bridge)
324 		ret = phb->eeh_ops->configure_bridge(pe);
325 
326 	return ret;
327 }
328 
329 /**
330  * powernv_eeh_next_error - Retrieve next EEH error to handle
331  * @pe: Affected PE
332  *
333  * Using OPAL API, to retrieve next EEH error for EEH core to handle
334  */
335 static int powernv_eeh_next_error(struct eeh_pe **pe)
336 {
337 	struct pci_controller *hose;
338 	struct pnv_phb *phb = NULL;
339 
340 	list_for_each_entry(hose, &hose_list, list_node) {
341 		phb = hose->private_data;
342 		break;
343 	}
344 
345 	if (phb && phb->eeh_ops->next_error)
346 		return phb->eeh_ops->next_error(pe);
347 
348 	return -EEXIST;
349 }
350 
351 static int powernv_eeh_restore_config(struct device_node *dn)
352 {
353 	struct eeh_dev *edev = of_node_to_eeh_dev(dn);
354 	struct pnv_phb *phb;
355 	s64 ret;
356 
357 	if (!edev)
358 		return -EEXIST;
359 
360 	phb = edev->phb->private_data;
361 	ret = opal_pci_reinit(phb->opal_id,
362 			      OPAL_REINIT_PCI_DEV, edev->config_addr);
363 	if (ret) {
364 		pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n",
365 			__func__, edev->config_addr, ret);
366 		return -EIO;
367 	}
368 
369 	return 0;
370 }
371 
372 static struct eeh_ops powernv_eeh_ops = {
373 	.name                   = "powernv",
374 	.init                   = powernv_eeh_init,
375 	.post_init              = powernv_eeh_post_init,
376 	.of_probe               = NULL,
377 	.dev_probe              = powernv_eeh_dev_probe,
378 	.set_option             = powernv_eeh_set_option,
379 	.get_pe_addr            = powernv_eeh_get_pe_addr,
380 	.get_state              = powernv_eeh_get_state,
381 	.reset                  = powernv_eeh_reset,
382 	.wait_state             = powernv_eeh_wait_state,
383 	.get_log                = powernv_eeh_get_log,
384 	.configure_bridge       = powernv_eeh_configure_bridge,
385 	.read_config            = pnv_pci_cfg_read,
386 	.write_config           = pnv_pci_cfg_write,
387 	.next_error		= powernv_eeh_next_error,
388 	.restore_config		= powernv_eeh_restore_config
389 };
390 
391 /**
392  * eeh_powernv_init - Register platform dependent EEH operations
393  *
394  * EEH initialization on powernv platform. This function should be
395  * called before any EEH related functions.
396  */
397 static int __init eeh_powernv_init(void)
398 {
399 	int ret = -EINVAL;
400 
401 	if (!machine_is(powernv))
402 		return ret;
403 
404 	ret = eeh_ops_register(&powernv_eeh_ops);
405 	if (!ret)
406 		pr_info("EEH: PowerNV platform initialized\n");
407 	else
408 		pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
409 
410 	return ret;
411 }
412 
413 early_initcall(eeh_powernv_init);
414