1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerNV Platform dependent EEH operations 4 * 5 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 6 */ 7 8 #include <linux/atomic.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/list.h> 15 #include <linux/msi.h> 16 #include <linux/of.h> 17 #include <linux/pci.h> 18 #include <linux/proc_fs.h> 19 #include <linux/rbtree.h> 20 #include <linux/sched.h> 21 #include <linux/seq_file.h> 22 #include <linux/spinlock.h> 23 24 #include <asm/eeh.h> 25 #include <asm/eeh_event.h> 26 #include <asm/firmware.h> 27 #include <asm/io.h> 28 #include <asm/iommu.h> 29 #include <asm/machdep.h> 30 #include <asm/msi_bitmap.h> 31 #include <asm/opal.h> 32 #include <asm/ppc-pci.h> 33 #include <asm/pnv-pci.h> 34 35 #include "powernv.h" 36 #include "pci.h" 37 38 static int eeh_event_irq = -EINVAL; 39 40 void pnv_pcibios_bus_add_device(struct pci_dev *pdev) 41 { 42 struct pci_dn *pdn = pci_get_pdn(pdev); 43 44 if (eeh_has_flag(EEH_FORCE_DISABLED)) 45 return; 46 47 pr_debug("%s: EEH: Setting up device %s.\n", __func__, pci_name(pdev)); 48 eeh_add_device_early(pdn); 49 eeh_add_device_late(pdev); 50 eeh_sysfs_add_device(pdev); 51 } 52 53 static int pnv_eeh_init(void) 54 { 55 struct pci_controller *hose; 56 struct pnv_phb *phb; 57 int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 58 59 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 60 pr_warn("%s: OPAL is required !\n", 61 __func__); 62 return -EINVAL; 63 } 64 65 /* Set probe mode */ 66 eeh_add_flag(EEH_PROBE_MODE_DEV); 67 68 /* 69 * P7IOC blocks PCI config access to frozen PE, but PHB3 70 * doesn't do that. So we have to selectively enable I/O 71 * prior to collecting error log. 72 */ 73 list_for_each_entry(hose, &hose_list, list_node) { 74 phb = hose->private_data; 75 76 if (phb->model == PNV_PHB_MODEL_P7IOC) 77 eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 78 79 if (phb->diag_data_size > max_diag_size) 80 max_diag_size = phb->diag_data_size; 81 82 /* 83 * PE#0 should be regarded as valid by EEH core 84 * if it's not the reserved one. Currently, we 85 * have the reserved PE#255 and PE#127 for PHB3 86 * and P7IOC separately. So we should regard 87 * PE#0 as valid for PHB3 and P7IOC. 88 */ 89 if (phb->ioda.reserved_pe_idx != 0) 90 eeh_add_flag(EEH_VALID_PE_ZERO); 91 92 break; 93 } 94 95 eeh_set_pe_aux_size(max_diag_size); 96 ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device; 97 98 return 0; 99 } 100 101 static irqreturn_t pnv_eeh_event(int irq, void *data) 102 { 103 /* 104 * We simply send a special EEH event if EEH has been 105 * enabled. We don't care about EEH events until we've 106 * finished processing the outstanding ones. Event processing 107 * gets unmasked in next_error() if EEH is enabled. 108 */ 109 disable_irq_nosync(irq); 110 111 if (eeh_enabled()) 112 eeh_send_failure_event(NULL); 113 114 return IRQ_HANDLED; 115 } 116 117 #ifdef CONFIG_DEBUG_FS 118 static ssize_t pnv_eeh_ei_write(struct file *filp, 119 const char __user *user_buf, 120 size_t count, loff_t *ppos) 121 { 122 struct pci_controller *hose = filp->private_data; 123 struct eeh_pe *pe; 124 int pe_no, type, func; 125 unsigned long addr, mask; 126 char buf[50]; 127 int ret; 128 129 if (!eeh_ops || !eeh_ops->err_inject) 130 return -ENXIO; 131 132 /* Copy over argument buffer */ 133 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 134 if (!ret) 135 return -EFAULT; 136 137 /* Retrieve parameters */ 138 ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 139 &pe_no, &type, &func, &addr, &mask); 140 if (ret != 5) 141 return -EINVAL; 142 143 /* Retrieve PE */ 144 pe = eeh_pe_get(hose, pe_no, 0); 145 if (!pe) 146 return -ENODEV; 147 148 /* Do error injection */ 149 ret = eeh_ops->err_inject(pe, type, func, addr, mask); 150 return ret < 0 ? ret : count; 151 } 152 153 static const struct file_operations pnv_eeh_ei_fops = { 154 .open = simple_open, 155 .llseek = no_llseek, 156 .write = pnv_eeh_ei_write, 157 }; 158 159 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 160 { 161 struct pci_controller *hose = data; 162 struct pnv_phb *phb = hose->private_data; 163 164 out_be64(phb->regs + offset, val); 165 return 0; 166 } 167 168 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 169 { 170 struct pci_controller *hose = data; 171 struct pnv_phb *phb = hose->private_data; 172 173 *val = in_be64(phb->regs + offset); 174 return 0; 175 } 176 177 #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 178 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 179 { \ 180 return pnv_eeh_dbgfs_set(data, reg, val); \ 181 } \ 182 \ 183 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 184 { \ 185 return pnv_eeh_dbgfs_get(data, reg, val); \ 186 } \ 187 \ 188 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 189 pnv_eeh_dbgfs_get_##name, \ 190 pnv_eeh_dbgfs_set_##name, \ 191 "0x%llx\n") 192 193 PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 194 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 195 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 196 197 #endif /* CONFIG_DEBUG_FS */ 198 199 void pnv_eeh_enable_phbs(void) 200 { 201 struct pci_controller *hose; 202 struct pnv_phb *phb; 203 204 list_for_each_entry(hose, &hose_list, list_node) { 205 phb = hose->private_data; 206 /* 207 * If EEH is enabled, we're going to rely on that. 208 * Otherwise, we restore to conventional mechanism 209 * to clear frozen PE during PCI config access. 210 */ 211 if (eeh_enabled()) 212 phb->flags |= PNV_PHB_FLAG_EEH; 213 else 214 phb->flags &= ~PNV_PHB_FLAG_EEH; 215 } 216 } 217 218 /** 219 * pnv_eeh_post_init - EEH platform dependent post initialization 220 * 221 * EEH platform dependent post initialization on powernv. When 222 * the function is called, the EEH PEs and devices should have 223 * been built. If the I/O cache staff has been built, EEH is 224 * ready to supply service. 225 */ 226 int pnv_eeh_post_init(void) 227 { 228 struct pci_controller *hose; 229 struct pnv_phb *phb; 230 int ret = 0; 231 232 eeh_show_enabled(); 233 234 /* Register OPAL event notifier */ 235 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 236 if (eeh_event_irq < 0) { 237 pr_err("%s: Can't register OPAL event interrupt (%d)\n", 238 __func__, eeh_event_irq); 239 return eeh_event_irq; 240 } 241 242 ret = request_irq(eeh_event_irq, pnv_eeh_event, 243 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 244 if (ret < 0) { 245 irq_dispose_mapping(eeh_event_irq); 246 pr_err("%s: Can't request OPAL event interrupt (%d)\n", 247 __func__, eeh_event_irq); 248 return ret; 249 } 250 251 if (!eeh_enabled()) 252 disable_irq(eeh_event_irq); 253 254 pnv_eeh_enable_phbs(); 255 256 list_for_each_entry(hose, &hose_list, list_node) { 257 phb = hose->private_data; 258 259 /* Create debugfs entries */ 260 #ifdef CONFIG_DEBUG_FS 261 if (phb->has_dbgfs || !phb->dbgfs) 262 continue; 263 264 phb->has_dbgfs = 1; 265 debugfs_create_file("err_injct", 0200, 266 phb->dbgfs, hose, 267 &pnv_eeh_ei_fops); 268 269 debugfs_create_file("err_injct_outbound", 0600, 270 phb->dbgfs, hose, 271 &pnv_eeh_dbgfs_ops_outb); 272 debugfs_create_file("err_injct_inboundA", 0600, 273 phb->dbgfs, hose, 274 &pnv_eeh_dbgfs_ops_inbA); 275 debugfs_create_file("err_injct_inboundB", 0600, 276 phb->dbgfs, hose, 277 &pnv_eeh_dbgfs_ops_inbB); 278 #endif /* CONFIG_DEBUG_FS */ 279 } 280 281 return ret; 282 } 283 284 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 285 { 286 int pos = PCI_CAPABILITY_LIST; 287 int cnt = 48; /* Maximal number of capabilities */ 288 u32 status, id; 289 290 if (!pdn) 291 return 0; 292 293 /* Check if the device supports capabilities */ 294 pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 295 if (!(status & PCI_STATUS_CAP_LIST)) 296 return 0; 297 298 while (cnt--) { 299 pnv_pci_cfg_read(pdn, pos, 1, &pos); 300 if (pos < 0x40) 301 break; 302 303 pos &= ~3; 304 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 305 if (id == 0xff) 306 break; 307 308 /* Found */ 309 if (id == cap) 310 return pos; 311 312 /* Next one */ 313 pos += PCI_CAP_LIST_NEXT; 314 } 315 316 return 0; 317 } 318 319 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 320 { 321 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 322 u32 header; 323 int pos = 256, ttl = (4096 - 256) / 8; 324 325 if (!edev || !edev->pcie_cap) 326 return 0; 327 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 328 return 0; 329 else if (!header) 330 return 0; 331 332 while (ttl-- > 0) { 333 if (PCI_EXT_CAP_ID(header) == cap && pos) 334 return pos; 335 336 pos = PCI_EXT_CAP_NEXT(header); 337 if (pos < 256) 338 break; 339 340 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 341 break; 342 } 343 344 return 0; 345 } 346 347 /** 348 * pnv_eeh_probe - Do probe on PCI device 349 * @pdn: PCI device node 350 * @data: unused 351 * 352 * When EEH module is installed during system boot, all PCI devices 353 * are checked one by one to see if it supports EEH. The function 354 * is introduced for the purpose. By default, EEH has been enabled 355 * on all PCI devices. That's to say, we only need do necessary 356 * initialization on the corresponding eeh device and create PE 357 * accordingly. 358 * 359 * It's notable that's unsafe to retrieve the EEH device through 360 * the corresponding PCI device. During the PCI device hotplug, which 361 * was possiblly triggered by EEH core, the binding between EEH device 362 * and the PCI device isn't built yet. 363 */ 364 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 365 { 366 struct pci_controller *hose = pdn->phb; 367 struct pnv_phb *phb = hose->private_data; 368 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 369 uint32_t pcie_flags; 370 int ret; 371 int config_addr = (pdn->busno << 8) | (pdn->devfn); 372 373 pr_debug("%s: probing %04x:%02x:%02x.%01x\n", 374 __func__, hose->global_number, pdn->busno, 375 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 376 377 /* 378 * When probing the root bridge, which doesn't have any 379 * subordinate PCI devices. We don't have OF node for 380 * the root bridge. So it's not reasonable to continue 381 * the probing. 382 */ 383 if (!edev || edev->pe) 384 return NULL; 385 386 /* Skip for PCI-ISA bridge */ 387 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 388 return NULL; 389 390 /* Initialize eeh device */ 391 edev->class_code = pdn->class_code; 392 edev->mode &= 0xFFFFFF00; 393 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 394 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 395 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 396 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 397 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 398 edev->mode |= EEH_DEV_BRIDGE; 399 if (edev->pcie_cap) { 400 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 401 2, &pcie_flags); 402 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 403 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 404 edev->mode |= EEH_DEV_ROOT_PORT; 405 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 406 edev->mode |= EEH_DEV_DS_PORT; 407 } 408 } 409 410 edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; 411 412 /* Create PE */ 413 ret = eeh_add_to_parent_pe(edev); 414 if (ret) { 415 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n", 416 __func__, hose->global_number, pdn->busno, 417 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 418 return NULL; 419 } 420 421 /* 422 * If the PE contains any one of following adapters, the 423 * PCI config space can't be accessed when dumping EEH log. 424 * Otherwise, we will run into fenced PHB caused by shortage 425 * of outbound credits in the adapter. The PCI config access 426 * should be blocked until PE reset. MMIO access is dropped 427 * by hardware certainly. In order to drop PCI config requests, 428 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 429 * will be checked in the backend for PE state retrival. If 430 * the PE becomes frozen for the first time and the flag has 431 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 432 * that PE to block its config space. 433 * 434 * Broadcom BCM5718 2-ports NICs (14e4:1656) 435 * Broadcom Austin 4-ports NICs (14e4:1657) 436 * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 437 * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 438 */ 439 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 440 pdn->device_id == 0x1656) || 441 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 442 pdn->device_id == 0x1657) || 443 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 444 pdn->device_id == 0x168a) || 445 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 446 pdn->device_id == 0x168e)) 447 edev->pe->state |= EEH_PE_CFG_RESTRICTED; 448 449 /* 450 * Cache the PE primary bus, which can't be fetched when 451 * full hotplug is in progress. In that case, all child 452 * PCI devices of the PE are expected to be removed prior 453 * to PE reset. 454 */ 455 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 456 edev->pe->bus = pci_find_bus(hose->global_number, 457 pdn->busno); 458 if (edev->pe->bus) 459 edev->pe->state |= EEH_PE_PRI_BUS; 460 } 461 462 /* 463 * Enable EEH explicitly so that we will do EEH check 464 * while accessing I/O stuff 465 */ 466 if (!eeh_has_flag(EEH_ENABLED)) { 467 enable_irq(eeh_event_irq); 468 pnv_eeh_enable_phbs(); 469 eeh_add_flag(EEH_ENABLED); 470 } 471 472 /* Save memory bars */ 473 eeh_save_bars(edev); 474 475 pr_debug("%s: EEH enabled on %02x:%02x.%01x PHB#%x-PE#%x\n", 476 __func__, pdn->busno, PCI_SLOT(pdn->devfn), 477 PCI_FUNC(pdn->devfn), edev->pe->phb->global_number, 478 edev->pe->addr); 479 480 return NULL; 481 } 482 483 /** 484 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 485 * @pe: EEH PE 486 * @option: operation to be issued 487 * 488 * The function is used to control the EEH functionality globally. 489 * Currently, following options are support according to PAPR: 490 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 491 */ 492 static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 493 { 494 struct pci_controller *hose = pe->phb; 495 struct pnv_phb *phb = hose->private_data; 496 bool freeze_pe = false; 497 int opt; 498 s64 rc; 499 500 switch (option) { 501 case EEH_OPT_DISABLE: 502 return -EPERM; 503 case EEH_OPT_ENABLE: 504 return 0; 505 case EEH_OPT_THAW_MMIO: 506 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 507 break; 508 case EEH_OPT_THAW_DMA: 509 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 510 break; 511 case EEH_OPT_FREEZE_PE: 512 freeze_pe = true; 513 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 514 break; 515 default: 516 pr_warn("%s: Invalid option %d\n", __func__, option); 517 return -EINVAL; 518 } 519 520 /* Freeze master and slave PEs if PHB supports compound PEs */ 521 if (freeze_pe) { 522 if (phb->freeze_pe) { 523 phb->freeze_pe(phb, pe->addr); 524 return 0; 525 } 526 527 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 528 if (rc != OPAL_SUCCESS) { 529 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 530 __func__, rc, phb->hose->global_number, 531 pe->addr); 532 return -EIO; 533 } 534 535 return 0; 536 } 537 538 /* Unfreeze master and slave PEs if PHB supports */ 539 if (phb->unfreeze_pe) 540 return phb->unfreeze_pe(phb, pe->addr, opt); 541 542 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 543 if (rc != OPAL_SUCCESS) { 544 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 545 __func__, rc, option, phb->hose->global_number, 546 pe->addr); 547 return -EIO; 548 } 549 550 return 0; 551 } 552 553 /** 554 * pnv_eeh_get_pe_addr - Retrieve PE address 555 * @pe: EEH PE 556 * 557 * Retrieve the PE address according to the given tranditional 558 * PCI BDF (Bus/Device/Function) address. 559 */ 560 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 561 { 562 return pe->addr; 563 } 564 565 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 566 { 567 struct pnv_phb *phb = pe->phb->private_data; 568 s64 rc; 569 570 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 571 phb->diag_data_size); 572 if (rc != OPAL_SUCCESS) 573 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 574 __func__, rc, pe->phb->global_number); 575 } 576 577 static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 578 { 579 struct pnv_phb *phb = pe->phb->private_data; 580 u8 fstate = 0; 581 __be16 pcierr = 0; 582 s64 rc; 583 int result = 0; 584 585 rc = opal_pci_eeh_freeze_status(phb->opal_id, 586 pe->addr, 587 &fstate, 588 &pcierr, 589 NULL); 590 if (rc != OPAL_SUCCESS) { 591 pr_warn("%s: Failure %lld getting PHB#%x state\n", 592 __func__, rc, phb->hose->global_number); 593 return EEH_STATE_NOT_SUPPORT; 594 } 595 596 /* 597 * Check PHB state. If the PHB is frozen for the 598 * first time, to dump the PHB diag-data. 599 */ 600 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 601 result = (EEH_STATE_MMIO_ACTIVE | 602 EEH_STATE_DMA_ACTIVE | 603 EEH_STATE_MMIO_ENABLED | 604 EEH_STATE_DMA_ENABLED); 605 } else if (!(pe->state & EEH_PE_ISOLATED)) { 606 eeh_pe_mark_isolated(pe); 607 pnv_eeh_get_phb_diag(pe); 608 609 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 610 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 611 } 612 613 return result; 614 } 615 616 static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 617 { 618 struct pnv_phb *phb = pe->phb->private_data; 619 u8 fstate = 0; 620 __be16 pcierr = 0; 621 s64 rc; 622 int result; 623 624 /* 625 * We don't clobber hardware frozen state until PE 626 * reset is completed. In order to keep EEH core 627 * moving forward, we have to return operational 628 * state during PE reset. 629 */ 630 if (pe->state & EEH_PE_RESET) { 631 result = (EEH_STATE_MMIO_ACTIVE | 632 EEH_STATE_DMA_ACTIVE | 633 EEH_STATE_MMIO_ENABLED | 634 EEH_STATE_DMA_ENABLED); 635 return result; 636 } 637 638 /* 639 * Fetch PE state from hardware. If the PHB 640 * supports compound PE, let it handle that. 641 */ 642 if (phb->get_pe_state) { 643 fstate = phb->get_pe_state(phb, pe->addr); 644 } else { 645 rc = opal_pci_eeh_freeze_status(phb->opal_id, 646 pe->addr, 647 &fstate, 648 &pcierr, 649 NULL); 650 if (rc != OPAL_SUCCESS) { 651 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 652 __func__, rc, phb->hose->global_number, 653 pe->addr); 654 return EEH_STATE_NOT_SUPPORT; 655 } 656 } 657 658 /* Figure out state */ 659 switch (fstate) { 660 case OPAL_EEH_STOPPED_NOT_FROZEN: 661 result = (EEH_STATE_MMIO_ACTIVE | 662 EEH_STATE_DMA_ACTIVE | 663 EEH_STATE_MMIO_ENABLED | 664 EEH_STATE_DMA_ENABLED); 665 break; 666 case OPAL_EEH_STOPPED_MMIO_FREEZE: 667 result = (EEH_STATE_DMA_ACTIVE | 668 EEH_STATE_DMA_ENABLED); 669 break; 670 case OPAL_EEH_STOPPED_DMA_FREEZE: 671 result = (EEH_STATE_MMIO_ACTIVE | 672 EEH_STATE_MMIO_ENABLED); 673 break; 674 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 675 result = 0; 676 break; 677 case OPAL_EEH_STOPPED_RESET: 678 result = EEH_STATE_RESET_ACTIVE; 679 break; 680 case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 681 result = EEH_STATE_UNAVAILABLE; 682 break; 683 case OPAL_EEH_STOPPED_PERM_UNAVAIL: 684 result = EEH_STATE_NOT_SUPPORT; 685 break; 686 default: 687 result = EEH_STATE_NOT_SUPPORT; 688 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 689 __func__, phb->hose->global_number, 690 pe->addr, fstate); 691 } 692 693 /* 694 * If PHB supports compound PE, to freeze all 695 * slave PEs for consistency. 696 * 697 * If the PE is switching to frozen state for the 698 * first time, to dump the PHB diag-data. 699 */ 700 if (!(result & EEH_STATE_NOT_SUPPORT) && 701 !(result & EEH_STATE_UNAVAILABLE) && 702 !(result & EEH_STATE_MMIO_ACTIVE) && 703 !(result & EEH_STATE_DMA_ACTIVE) && 704 !(pe->state & EEH_PE_ISOLATED)) { 705 if (phb->freeze_pe) 706 phb->freeze_pe(phb, pe->addr); 707 708 eeh_pe_mark_isolated(pe); 709 pnv_eeh_get_phb_diag(pe); 710 711 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 712 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 713 } 714 715 return result; 716 } 717 718 /** 719 * pnv_eeh_get_state - Retrieve PE state 720 * @pe: EEH PE 721 * @delay: delay while PE state is temporarily unavailable 722 * 723 * Retrieve the state of the specified PE. For IODA-compitable 724 * platform, it should be retrieved from IODA table. Therefore, 725 * we prefer passing down to hardware implementation to handle 726 * it. 727 */ 728 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 729 { 730 int ret; 731 732 if (pe->type & EEH_PE_PHB) 733 ret = pnv_eeh_get_phb_state(pe); 734 else 735 ret = pnv_eeh_get_pe_state(pe); 736 737 if (!delay) 738 return ret; 739 740 /* 741 * If the PE state is temporarily unavailable, 742 * to inform the EEH core delay for default 743 * period (1 second) 744 */ 745 *delay = 0; 746 if (ret & EEH_STATE_UNAVAILABLE) 747 *delay = 1000; 748 749 return ret; 750 } 751 752 static s64 pnv_eeh_poll(unsigned long id) 753 { 754 s64 rc = OPAL_HARDWARE; 755 756 while (1) { 757 rc = opal_pci_poll(id); 758 if (rc <= 0) 759 break; 760 761 if (system_state < SYSTEM_RUNNING) 762 udelay(1000 * rc); 763 else 764 msleep(rc); 765 } 766 767 return rc; 768 } 769 770 int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 771 { 772 struct pnv_phb *phb = hose->private_data; 773 s64 rc = OPAL_HARDWARE; 774 775 pr_debug("%s: Reset PHB#%x, option=%d\n", 776 __func__, hose->global_number, option); 777 778 /* Issue PHB complete reset request */ 779 if (option == EEH_RESET_FUNDAMENTAL || 780 option == EEH_RESET_HOT) 781 rc = opal_pci_reset(phb->opal_id, 782 OPAL_RESET_PHB_COMPLETE, 783 OPAL_ASSERT_RESET); 784 else if (option == EEH_RESET_DEACTIVATE) 785 rc = opal_pci_reset(phb->opal_id, 786 OPAL_RESET_PHB_COMPLETE, 787 OPAL_DEASSERT_RESET); 788 if (rc < 0) 789 goto out; 790 791 /* 792 * Poll state of the PHB until the request is done 793 * successfully. The PHB reset is usually PHB complete 794 * reset followed by hot reset on root bus. So we also 795 * need the PCI bus settlement delay. 796 */ 797 if (rc > 0) 798 rc = pnv_eeh_poll(phb->opal_id); 799 if (option == EEH_RESET_DEACTIVATE) { 800 if (system_state < SYSTEM_RUNNING) 801 udelay(1000 * EEH_PE_RST_SETTLE_TIME); 802 else 803 msleep(EEH_PE_RST_SETTLE_TIME); 804 } 805 out: 806 if (rc != OPAL_SUCCESS) 807 return -EIO; 808 809 return 0; 810 } 811 812 static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 813 { 814 struct pnv_phb *phb = hose->private_data; 815 s64 rc = OPAL_HARDWARE; 816 817 pr_debug("%s: Reset PHB#%x, option=%d\n", 818 __func__, hose->global_number, option); 819 820 /* 821 * During the reset deassert time, we needn't care 822 * the reset scope because the firmware does nothing 823 * for fundamental or hot reset during deassert phase. 824 */ 825 if (option == EEH_RESET_FUNDAMENTAL) 826 rc = opal_pci_reset(phb->opal_id, 827 OPAL_RESET_PCI_FUNDAMENTAL, 828 OPAL_ASSERT_RESET); 829 else if (option == EEH_RESET_HOT) 830 rc = opal_pci_reset(phb->opal_id, 831 OPAL_RESET_PCI_HOT, 832 OPAL_ASSERT_RESET); 833 else if (option == EEH_RESET_DEACTIVATE) 834 rc = opal_pci_reset(phb->opal_id, 835 OPAL_RESET_PCI_HOT, 836 OPAL_DEASSERT_RESET); 837 if (rc < 0) 838 goto out; 839 840 /* Poll state of the PHB until the request is done */ 841 if (rc > 0) 842 rc = pnv_eeh_poll(phb->opal_id); 843 if (option == EEH_RESET_DEACTIVATE) 844 msleep(EEH_PE_RST_SETTLE_TIME); 845 out: 846 if (rc != OPAL_SUCCESS) 847 return -EIO; 848 849 return 0; 850 } 851 852 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 853 { 854 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 855 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 856 int aer = edev ? edev->aer_cap : 0; 857 u32 ctrl; 858 859 pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 860 __func__, pci_domain_nr(dev->bus), 861 dev->bus->number, option); 862 863 switch (option) { 864 case EEH_RESET_FUNDAMENTAL: 865 case EEH_RESET_HOT: 866 /* Don't report linkDown event */ 867 if (aer) { 868 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 869 4, &ctrl); 870 ctrl |= PCI_ERR_UNC_SURPDN; 871 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 872 4, ctrl); 873 } 874 875 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 876 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 877 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 878 879 msleep(EEH_PE_RST_HOLD_TIME); 880 break; 881 case EEH_RESET_DEACTIVATE: 882 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 883 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 884 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 885 886 msleep(EEH_PE_RST_SETTLE_TIME); 887 888 /* Continue reporting linkDown event */ 889 if (aer) { 890 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 891 4, &ctrl); 892 ctrl &= ~PCI_ERR_UNC_SURPDN; 893 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 894 4, ctrl); 895 } 896 897 break; 898 } 899 900 return 0; 901 } 902 903 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 904 { 905 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 906 struct pnv_phb *phb = hose->private_data; 907 struct device_node *dn = pci_device_to_OF_node(pdev); 908 uint64_t id = PCI_SLOT_ID(phb->opal_id, 909 (pdev->bus->number << 8) | pdev->devfn); 910 uint8_t scope; 911 int64_t rc; 912 913 /* Hot reset to the bus if firmware cannot handle */ 914 if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 915 return __pnv_eeh_bridge_reset(pdev, option); 916 917 switch (option) { 918 case EEH_RESET_FUNDAMENTAL: 919 scope = OPAL_RESET_PCI_FUNDAMENTAL; 920 break; 921 case EEH_RESET_HOT: 922 scope = OPAL_RESET_PCI_HOT; 923 break; 924 case EEH_RESET_DEACTIVATE: 925 return 0; 926 default: 927 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 928 __func__, option); 929 return -EINVAL; 930 } 931 932 rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 933 if (rc <= OPAL_SUCCESS) 934 goto out; 935 936 rc = pnv_eeh_poll(id); 937 out: 938 return (rc == OPAL_SUCCESS) ? 0 : -EIO; 939 } 940 941 void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 942 { 943 struct pci_controller *hose; 944 945 if (pci_is_root_bus(dev->bus)) { 946 hose = pci_bus_to_host(dev->bus); 947 pnv_eeh_root_reset(hose, EEH_RESET_HOT); 948 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 949 } else { 950 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 951 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 952 } 953 } 954 955 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 956 int pos, u16 mask) 957 { 958 int i, status = 0; 959 960 /* Wait for Transaction Pending bit to be cleared */ 961 for (i = 0; i < 4; i++) { 962 eeh_ops->read_config(pdn, pos, 2, &status); 963 if (!(status & mask)) 964 return; 965 966 msleep((1 << i) * 100); 967 } 968 969 pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 970 __func__, type, 971 pdn->phb->global_number, pdn->busno, 972 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 973 } 974 975 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 976 { 977 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 978 u32 reg = 0; 979 980 if (WARN_ON(!edev->pcie_cap)) 981 return -ENOTTY; 982 983 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 984 if (!(reg & PCI_EXP_DEVCAP_FLR)) 985 return -ENOTTY; 986 987 switch (option) { 988 case EEH_RESET_HOT: 989 case EEH_RESET_FUNDAMENTAL: 990 pnv_eeh_wait_for_pending(pdn, "", 991 edev->pcie_cap + PCI_EXP_DEVSTA, 992 PCI_EXP_DEVSTA_TRPND); 993 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 994 4, ®); 995 reg |= PCI_EXP_DEVCTL_BCR_FLR; 996 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 997 4, reg); 998 msleep(EEH_PE_RST_HOLD_TIME); 999 break; 1000 case EEH_RESET_DEACTIVATE: 1001 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1002 4, ®); 1003 reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 1004 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1005 4, reg); 1006 msleep(EEH_PE_RST_SETTLE_TIME); 1007 break; 1008 } 1009 1010 return 0; 1011 } 1012 1013 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 1014 { 1015 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1016 u32 cap = 0; 1017 1018 if (WARN_ON(!edev->af_cap)) 1019 return -ENOTTY; 1020 1021 eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 1022 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 1023 return -ENOTTY; 1024 1025 switch (option) { 1026 case EEH_RESET_HOT: 1027 case EEH_RESET_FUNDAMENTAL: 1028 /* 1029 * Wait for Transaction Pending bit to clear. A word-aligned 1030 * test is used, so we use the conrol offset rather than status 1031 * and shift the test bit to match. 1032 */ 1033 pnv_eeh_wait_for_pending(pdn, "AF", 1034 edev->af_cap + PCI_AF_CTRL, 1035 PCI_AF_STATUS_TP << 8); 1036 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1037 1, PCI_AF_CTRL_FLR); 1038 msleep(EEH_PE_RST_HOLD_TIME); 1039 break; 1040 case EEH_RESET_DEACTIVATE: 1041 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 1042 msleep(EEH_PE_RST_SETTLE_TIME); 1043 break; 1044 } 1045 1046 return 0; 1047 } 1048 1049 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 1050 { 1051 struct eeh_dev *edev; 1052 struct pci_dn *pdn; 1053 int ret; 1054 1055 /* The VF PE should have only one child device */ 1056 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); 1057 pdn = eeh_dev_to_pdn(edev); 1058 if (!pdn) 1059 return -ENXIO; 1060 1061 ret = pnv_eeh_do_flr(pdn, option); 1062 if (!ret) 1063 return ret; 1064 1065 return pnv_eeh_do_af_flr(pdn, option); 1066 } 1067 1068 /** 1069 * pnv_eeh_reset - Reset the specified PE 1070 * @pe: EEH PE 1071 * @option: reset option 1072 * 1073 * Do reset on the indicated PE. For PCI bus sensitive PE, 1074 * we need to reset the parent p2p bridge. The PHB has to 1075 * be reinitialized if the p2p bridge is root bridge. For 1076 * PCI device sensitive PE, we will try to reset the device 1077 * through FLR. For now, we don't have OPAL APIs to do HARD 1078 * reset yet, so all reset would be SOFT (HOT) reset. 1079 */ 1080 static int pnv_eeh_reset(struct eeh_pe *pe, int option) 1081 { 1082 struct pci_controller *hose = pe->phb; 1083 struct pnv_phb *phb; 1084 struct pci_bus *bus; 1085 int64_t rc; 1086 1087 /* 1088 * For PHB reset, we always have complete reset. For those PEs whose 1089 * primary bus derived from root complex (root bus) or root port 1090 * (usually bus#1), we apply hot or fundamental reset on the root port. 1091 * For other PEs, we always have hot reset on the PE primary bus. 1092 * 1093 * Here, we have different design to pHyp, which always clear the 1094 * frozen state during PE reset. However, the good idea here from 1095 * benh is to keep frozen state before we get PE reset done completely 1096 * (until BAR restore). With the frozen state, HW drops illegal IO 1097 * or MMIO access, which can incur recrusive frozen PE during PE 1098 * reset. The side effect is that EEH core has to clear the frozen 1099 * state explicitly after BAR restore. 1100 */ 1101 if (pe->type & EEH_PE_PHB) 1102 return pnv_eeh_phb_reset(hose, option); 1103 1104 /* 1105 * The frozen PE might be caused by PAPR error injection 1106 * registers, which are expected to be cleared after hitting 1107 * frozen PE as stated in the hardware spec. Unfortunately, 1108 * that's not true on P7IOC. So we have to clear it manually 1109 * to avoid recursive EEH errors during recovery. 1110 */ 1111 phb = hose->private_data; 1112 if (phb->model == PNV_PHB_MODEL_P7IOC && 1113 (option == EEH_RESET_HOT || 1114 option == EEH_RESET_FUNDAMENTAL)) { 1115 rc = opal_pci_reset(phb->opal_id, 1116 OPAL_RESET_PHB_ERROR, 1117 OPAL_ASSERT_RESET); 1118 if (rc != OPAL_SUCCESS) { 1119 pr_warn("%s: Failure %lld clearing error injection registers\n", 1120 __func__, rc); 1121 return -EIO; 1122 } 1123 } 1124 1125 if (pe->type & EEH_PE_VF) 1126 return pnv_eeh_reset_vf_pe(pe, option); 1127 1128 bus = eeh_pe_bus_get(pe); 1129 if (!bus) { 1130 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 1131 __func__, pe->phb->global_number, pe->addr); 1132 return -EIO; 1133 } 1134 1135 /* 1136 * If dealing with the root bus (or the bus underneath the 1137 * root port), we reset the bus underneath the root port. 1138 * 1139 * The cxl driver depends on this behaviour for bi-modal card 1140 * switching. 1141 */ 1142 if (pci_is_root_bus(bus) || 1143 pci_is_root_bus(bus->parent)) 1144 return pnv_eeh_root_reset(hose, option); 1145 1146 return pnv_eeh_bridge_reset(bus->self, option); 1147 } 1148 1149 /** 1150 * pnv_eeh_get_log - Retrieve error log 1151 * @pe: EEH PE 1152 * @severity: temporary or permanent error log 1153 * @drv_log: driver log to be combined with retrieved error log 1154 * @len: length of driver log 1155 * 1156 * Retrieve the temporary or permanent error from the PE. 1157 */ 1158 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 1159 char *drv_log, unsigned long len) 1160 { 1161 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1162 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 1163 1164 return 0; 1165 } 1166 1167 /** 1168 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 1169 * @pe: EEH PE 1170 * 1171 * The function will be called to reconfigure the bridges included 1172 * in the specified PE so that the mulfunctional PE would be recovered 1173 * again. 1174 */ 1175 static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 1176 { 1177 return 0; 1178 } 1179 1180 /** 1181 * pnv_pe_err_inject - Inject specified error to the indicated PE 1182 * @pe: the indicated PE 1183 * @type: error type 1184 * @func: specific error type 1185 * @addr: address 1186 * @mask: address mask 1187 * 1188 * The routine is called to inject specified error, which is 1189 * determined by @type and @func, to the indicated PE for 1190 * testing purpose. 1191 */ 1192 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1193 unsigned long addr, unsigned long mask) 1194 { 1195 struct pci_controller *hose = pe->phb; 1196 struct pnv_phb *phb = hose->private_data; 1197 s64 rc; 1198 1199 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1200 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1201 pr_warn("%s: Invalid error type %d\n", 1202 __func__, type); 1203 return -ERANGE; 1204 } 1205 1206 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1207 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1208 pr_warn("%s: Invalid error function %d\n", 1209 __func__, func); 1210 return -ERANGE; 1211 } 1212 1213 /* Firmware supports error injection ? */ 1214 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1215 pr_warn("%s: Firmware doesn't support error injection\n", 1216 __func__); 1217 return -ENXIO; 1218 } 1219 1220 /* Do error injection */ 1221 rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1222 type, func, addr, mask); 1223 if (rc != OPAL_SUCCESS) { 1224 pr_warn("%s: Failure %lld injecting error " 1225 "%d-%d to PHB#%x-PE#%x\n", 1226 __func__, rc, type, func, 1227 hose->global_number, pe->addr); 1228 return -EIO; 1229 } 1230 1231 return 0; 1232 } 1233 1234 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1235 { 1236 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1237 1238 if (!edev || !edev->pe) 1239 return false; 1240 1241 /* 1242 * We will issue FLR or AF FLR to all VFs, which are contained 1243 * in VF PE. It relies on the EEH PCI config accessors. So we 1244 * can't block them during the window. 1245 */ 1246 if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 1247 return false; 1248 1249 if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1250 return true; 1251 1252 return false; 1253 } 1254 1255 static int pnv_eeh_read_config(struct pci_dn *pdn, 1256 int where, int size, u32 *val) 1257 { 1258 if (!pdn) 1259 return PCIBIOS_DEVICE_NOT_FOUND; 1260 1261 if (pnv_eeh_cfg_blocked(pdn)) { 1262 *val = 0xFFFFFFFF; 1263 return PCIBIOS_SET_FAILED; 1264 } 1265 1266 return pnv_pci_cfg_read(pdn, where, size, val); 1267 } 1268 1269 static int pnv_eeh_write_config(struct pci_dn *pdn, 1270 int where, int size, u32 val) 1271 { 1272 if (!pdn) 1273 return PCIBIOS_DEVICE_NOT_FOUND; 1274 1275 if (pnv_eeh_cfg_blocked(pdn)) 1276 return PCIBIOS_SET_FAILED; 1277 1278 return pnv_pci_cfg_write(pdn, where, size, val); 1279 } 1280 1281 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 1282 { 1283 /* GEM */ 1284 if (data->gemXfir || data->gemRfir || 1285 data->gemRirqfir || data->gemMask || data->gemRwof) 1286 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 1287 be64_to_cpu(data->gemXfir), 1288 be64_to_cpu(data->gemRfir), 1289 be64_to_cpu(data->gemRirqfir), 1290 be64_to_cpu(data->gemMask), 1291 be64_to_cpu(data->gemRwof)); 1292 1293 /* LEM */ 1294 if (data->lemFir || data->lemErrMask || 1295 data->lemAction0 || data->lemAction1 || data->lemWof) 1296 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 1297 be64_to_cpu(data->lemFir), 1298 be64_to_cpu(data->lemErrMask), 1299 be64_to_cpu(data->lemAction0), 1300 be64_to_cpu(data->lemAction1), 1301 be64_to_cpu(data->lemWof)); 1302 } 1303 1304 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 1305 { 1306 struct pnv_phb *phb = hose->private_data; 1307 struct OpalIoP7IOCErrorData *data = 1308 (struct OpalIoP7IOCErrorData*)phb->diag_data; 1309 long rc; 1310 1311 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 1312 if (rc != OPAL_SUCCESS) { 1313 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 1314 __func__, phb->hub_id, rc); 1315 return; 1316 } 1317 1318 switch (be16_to_cpu(data->type)) { 1319 case OPAL_P7IOC_DIAG_TYPE_RGC: 1320 pr_info("P7IOC diag-data for RGC\n\n"); 1321 pnv_eeh_dump_hub_diag_common(data); 1322 if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 1323 pr_info(" RGC: %016llx %016llx\n", 1324 be64_to_cpu(data->rgc.rgcStatus), 1325 be64_to_cpu(data->rgc.rgcLdcp)); 1326 break; 1327 case OPAL_P7IOC_DIAG_TYPE_BI: 1328 pr_info("P7IOC diag-data for BI %s\n\n", 1329 data->bi.biDownbound ? "Downbound" : "Upbound"); 1330 pnv_eeh_dump_hub_diag_common(data); 1331 if (data->bi.biLdcp0 || data->bi.biLdcp1 || 1332 data->bi.biLdcp2 || data->bi.biFenceStatus) 1333 pr_info(" BI: %016llx %016llx %016llx %016llx\n", 1334 be64_to_cpu(data->bi.biLdcp0), 1335 be64_to_cpu(data->bi.biLdcp1), 1336 be64_to_cpu(data->bi.biLdcp2), 1337 be64_to_cpu(data->bi.biFenceStatus)); 1338 break; 1339 case OPAL_P7IOC_DIAG_TYPE_CI: 1340 pr_info("P7IOC diag-data for CI Port %d\n\n", 1341 data->ci.ciPort); 1342 pnv_eeh_dump_hub_diag_common(data); 1343 if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 1344 pr_info(" CI: %016llx %016llx\n", 1345 be64_to_cpu(data->ci.ciPortStatus), 1346 be64_to_cpu(data->ci.ciPortLdcp)); 1347 break; 1348 case OPAL_P7IOC_DIAG_TYPE_MISC: 1349 pr_info("P7IOC diag-data for MISC\n\n"); 1350 pnv_eeh_dump_hub_diag_common(data); 1351 break; 1352 case OPAL_P7IOC_DIAG_TYPE_I2C: 1353 pr_info("P7IOC diag-data for I2C\n\n"); 1354 pnv_eeh_dump_hub_diag_common(data); 1355 break; 1356 default: 1357 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 1358 __func__, phb->hub_id, data->type); 1359 } 1360 } 1361 1362 static int pnv_eeh_get_pe(struct pci_controller *hose, 1363 u16 pe_no, struct eeh_pe **pe) 1364 { 1365 struct pnv_phb *phb = hose->private_data; 1366 struct pnv_ioda_pe *pnv_pe; 1367 struct eeh_pe *dev_pe; 1368 1369 /* 1370 * If PHB supports compound PE, to fetch 1371 * the master PE because slave PE is invisible 1372 * to EEH core. 1373 */ 1374 pnv_pe = &phb->ioda.pe_array[pe_no]; 1375 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 1376 pnv_pe = pnv_pe->master; 1377 WARN_ON(!pnv_pe || 1378 !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 1379 pe_no = pnv_pe->pe_number; 1380 } 1381 1382 /* Find the PE according to PE# */ 1383 dev_pe = eeh_pe_get(hose, pe_no, 0); 1384 if (!dev_pe) 1385 return -EEXIST; 1386 1387 /* Freeze the (compound) PE */ 1388 *pe = dev_pe; 1389 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1390 phb->freeze_pe(phb, pe_no); 1391 1392 /* 1393 * At this point, we're sure the (compound) PE should 1394 * have been frozen. However, we still need poke until 1395 * hitting the frozen PE on top level. 1396 */ 1397 dev_pe = dev_pe->parent; 1398 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 1399 int ret; 1400 ret = eeh_ops->get_state(dev_pe, NULL); 1401 if (ret <= 0 || eeh_state_active(ret)) { 1402 dev_pe = dev_pe->parent; 1403 continue; 1404 } 1405 1406 /* Frozen parent PE */ 1407 *pe = dev_pe; 1408 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1409 phb->freeze_pe(phb, dev_pe->addr); 1410 1411 /* Next one */ 1412 dev_pe = dev_pe->parent; 1413 } 1414 1415 return 0; 1416 } 1417 1418 /** 1419 * pnv_eeh_next_error - Retrieve next EEH error to handle 1420 * @pe: Affected PE 1421 * 1422 * The function is expected to be called by EEH core while it gets 1423 * special EEH event (without binding PE). The function calls to 1424 * OPAL APIs for next error to handle. The informational error is 1425 * handled internally by platform. However, the dead IOC, dead PHB, 1426 * fenced PHB and frozen PE should be handled by EEH core eventually. 1427 */ 1428 static int pnv_eeh_next_error(struct eeh_pe **pe) 1429 { 1430 struct pci_controller *hose; 1431 struct pnv_phb *phb; 1432 struct eeh_pe *phb_pe, *parent_pe; 1433 __be64 frozen_pe_no; 1434 __be16 err_type, severity; 1435 long rc; 1436 int state, ret = EEH_NEXT_ERR_NONE; 1437 1438 /* 1439 * While running here, it's safe to purge the event queue. The 1440 * event should still be masked. 1441 */ 1442 eeh_remove_event(NULL, false); 1443 1444 list_for_each_entry(hose, &hose_list, list_node) { 1445 /* 1446 * If the subordinate PCI buses of the PHB has been 1447 * removed or is exactly under error recovery, we 1448 * needn't take care of it any more. 1449 */ 1450 phb = hose->private_data; 1451 phb_pe = eeh_phb_pe_get(hose); 1452 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 1453 continue; 1454 1455 rc = opal_pci_next_error(phb->opal_id, 1456 &frozen_pe_no, &err_type, &severity); 1457 if (rc != OPAL_SUCCESS) { 1458 pr_devel("%s: Invalid return value on " 1459 "PHB#%x (0x%lx) from opal_pci_next_error", 1460 __func__, hose->global_number, rc); 1461 continue; 1462 } 1463 1464 /* If the PHB doesn't have error, stop processing */ 1465 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 1466 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 1467 pr_devel("%s: No error found on PHB#%x\n", 1468 __func__, hose->global_number); 1469 continue; 1470 } 1471 1472 /* 1473 * Processing the error. We're expecting the error with 1474 * highest priority reported upon multiple errors on the 1475 * specific PHB. 1476 */ 1477 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 1478 __func__, be16_to_cpu(err_type), 1479 be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 1480 hose->global_number); 1481 switch (be16_to_cpu(err_type)) { 1482 case OPAL_EEH_IOC_ERROR: 1483 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 1484 pr_err("EEH: dead IOC detected\n"); 1485 ret = EEH_NEXT_ERR_DEAD_IOC; 1486 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1487 pr_info("EEH: IOC informative error " 1488 "detected\n"); 1489 pnv_eeh_get_and_dump_hub_diag(hose); 1490 ret = EEH_NEXT_ERR_NONE; 1491 } 1492 1493 break; 1494 case OPAL_EEH_PHB_ERROR: 1495 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 1496 *pe = phb_pe; 1497 pr_err("EEH: dead PHB#%x detected, " 1498 "location: %s\n", 1499 hose->global_number, 1500 eeh_pe_loc_get(phb_pe)); 1501 ret = EEH_NEXT_ERR_DEAD_PHB; 1502 } else if (be16_to_cpu(severity) == 1503 OPAL_EEH_SEV_PHB_FENCED) { 1504 *pe = phb_pe; 1505 pr_err("EEH: Fenced PHB#%x detected, " 1506 "location: %s\n", 1507 hose->global_number, 1508 eeh_pe_loc_get(phb_pe)); 1509 ret = EEH_NEXT_ERR_FENCED_PHB; 1510 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1511 pr_info("EEH: PHB#%x informative error " 1512 "detected, location: %s\n", 1513 hose->global_number, 1514 eeh_pe_loc_get(phb_pe)); 1515 pnv_eeh_get_phb_diag(phb_pe); 1516 pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 1517 ret = EEH_NEXT_ERR_NONE; 1518 } 1519 1520 break; 1521 case OPAL_EEH_PE_ERROR: 1522 /* 1523 * If we can't find the corresponding PE, we 1524 * just try to unfreeze. 1525 */ 1526 if (pnv_eeh_get_pe(hose, 1527 be64_to_cpu(frozen_pe_no), pe)) { 1528 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 1529 hose->global_number, be64_to_cpu(frozen_pe_no)); 1530 pr_info("EEH: PHB location: %s\n", 1531 eeh_pe_loc_get(phb_pe)); 1532 1533 /* Dump PHB diag-data */ 1534 rc = opal_pci_get_phb_diag_data2(phb->opal_id, 1535 phb->diag_data, phb->diag_data_size); 1536 if (rc == OPAL_SUCCESS) 1537 pnv_pci_dump_phb_diag_data(hose, 1538 phb->diag_data); 1539 1540 /* Try best to clear it */ 1541 opal_pci_eeh_freeze_clear(phb->opal_id, 1542 be64_to_cpu(frozen_pe_no), 1543 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 1544 ret = EEH_NEXT_ERR_NONE; 1545 } else if ((*pe)->state & EEH_PE_ISOLATED || 1546 eeh_pe_passed(*pe)) { 1547 ret = EEH_NEXT_ERR_NONE; 1548 } else { 1549 pr_err("EEH: Frozen PE#%x " 1550 "on PHB#%x detected\n", 1551 (*pe)->addr, 1552 (*pe)->phb->global_number); 1553 pr_err("EEH: PE location: %s, " 1554 "PHB location: %s\n", 1555 eeh_pe_loc_get(*pe), 1556 eeh_pe_loc_get(phb_pe)); 1557 ret = EEH_NEXT_ERR_FROZEN_PE; 1558 } 1559 1560 break; 1561 default: 1562 pr_warn("%s: Unexpected error type %d\n", 1563 __func__, be16_to_cpu(err_type)); 1564 } 1565 1566 /* 1567 * EEH core will try recover from fenced PHB or 1568 * frozen PE. In the time for frozen PE, EEH core 1569 * enable IO path for that before collecting logs, 1570 * but it ruins the site. So we have to dump the 1571 * log in advance here. 1572 */ 1573 if ((ret == EEH_NEXT_ERR_FROZEN_PE || 1574 ret == EEH_NEXT_ERR_FENCED_PHB) && 1575 !((*pe)->state & EEH_PE_ISOLATED)) { 1576 eeh_pe_mark_isolated(*pe); 1577 pnv_eeh_get_phb_diag(*pe); 1578 1579 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1580 pnv_pci_dump_phb_diag_data((*pe)->phb, 1581 (*pe)->data); 1582 } 1583 1584 /* 1585 * We probably have the frozen parent PE out there and 1586 * we need have to handle frozen parent PE firstly. 1587 */ 1588 if (ret == EEH_NEXT_ERR_FROZEN_PE) { 1589 parent_pe = (*pe)->parent; 1590 while (parent_pe) { 1591 /* Hit the ceiling ? */ 1592 if (parent_pe->type & EEH_PE_PHB) 1593 break; 1594 1595 /* Frozen parent PE ? */ 1596 state = eeh_ops->get_state(parent_pe, NULL); 1597 if (state > 0 && !eeh_state_active(state)) 1598 *pe = parent_pe; 1599 1600 /* Next parent level */ 1601 parent_pe = parent_pe->parent; 1602 } 1603 1604 /* We possibly migrate to another PE */ 1605 eeh_pe_mark_isolated(*pe); 1606 } 1607 1608 /* 1609 * If we have no errors on the specific PHB or only 1610 * informative error there, we continue poking it. 1611 * Otherwise, we need actions to be taken by upper 1612 * layer. 1613 */ 1614 if (ret > EEH_NEXT_ERR_INF) 1615 break; 1616 } 1617 1618 /* Unmask the event */ 1619 if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 1620 enable_irq(eeh_event_irq); 1621 1622 return ret; 1623 } 1624 1625 static int pnv_eeh_restore_config(struct pci_dn *pdn) 1626 { 1627 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1628 struct pnv_phb *phb; 1629 s64 ret = 0; 1630 int config_addr = (pdn->busno << 8) | (pdn->devfn); 1631 1632 if (!edev) 1633 return -EEXIST; 1634 1635 /* 1636 * We have to restore the PCI config space after reset since the 1637 * firmware can't see SRIOV VFs. 1638 * 1639 * FIXME: The MPS, error routing rules, timeout setting are worthy 1640 * to be exported by firmware in extendible way. 1641 */ 1642 if (edev->physfn) { 1643 ret = eeh_restore_vf_config(pdn); 1644 } else { 1645 phb = pdn->phb->private_data; 1646 ret = opal_pci_reinit(phb->opal_id, 1647 OPAL_REINIT_PCI_DEV, config_addr); 1648 } 1649 1650 if (ret) { 1651 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 1652 __func__, config_addr, ret); 1653 return -EIO; 1654 } 1655 1656 return ret; 1657 } 1658 1659 static struct eeh_ops pnv_eeh_ops = { 1660 .name = "powernv", 1661 .init = pnv_eeh_init, 1662 .probe = pnv_eeh_probe, 1663 .set_option = pnv_eeh_set_option, 1664 .get_pe_addr = pnv_eeh_get_pe_addr, 1665 .get_state = pnv_eeh_get_state, 1666 .reset = pnv_eeh_reset, 1667 .get_log = pnv_eeh_get_log, 1668 .configure_bridge = pnv_eeh_configure_bridge, 1669 .err_inject = pnv_eeh_err_inject, 1670 .read_config = pnv_eeh_read_config, 1671 .write_config = pnv_eeh_write_config, 1672 .next_error = pnv_eeh_next_error, 1673 .restore_config = pnv_eeh_restore_config, 1674 .notify_resume = NULL 1675 }; 1676 1677 #ifdef CONFIG_PCI_IOV 1678 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 1679 { 1680 struct pci_dn *pdn = pci_get_pdn(pdev); 1681 int parent_mps; 1682 1683 if (!pdev->is_virtfn) 1684 return; 1685 1686 /* Synchronize MPS for VF and PF */ 1687 parent_mps = pcie_get_mps(pdev->physfn); 1688 if ((128 << pdev->pcie_mpss) >= parent_mps) 1689 pcie_set_mps(pdev, parent_mps); 1690 pdn->mps = pcie_get_mps(pdev); 1691 } 1692 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 1693 #endif /* CONFIG_PCI_IOV */ 1694 1695 /** 1696 * eeh_powernv_init - Register platform dependent EEH operations 1697 * 1698 * EEH initialization on powernv platform. This function should be 1699 * called before any EEH related functions. 1700 */ 1701 static int __init eeh_powernv_init(void) 1702 { 1703 int ret = -EINVAL; 1704 1705 ret = eeh_ops_register(&pnv_eeh_ops); 1706 if (!ret) 1707 pr_info("EEH: PowerNV platform initialized\n"); 1708 else 1709 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 1710 1711 return ret; 1712 } 1713 machine_early_initcall(powernv, eeh_powernv_init); 1714