1 /* 2 * The file intends to implement the platform dependent EEH operations on 3 * powernv platform. Actually, the powernv was created in order to fully 4 * hypervisor support. 5 * 6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/atomic.h> 15 #include <linux/debugfs.h> 16 #include <linux/delay.h> 17 #include <linux/export.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/list.h> 21 #include <linux/msi.h> 22 #include <linux/of.h> 23 #include <linux/pci.h> 24 #include <linux/proc_fs.h> 25 #include <linux/rbtree.h> 26 #include <linux/sched.h> 27 #include <linux/seq_file.h> 28 #include <linux/spinlock.h> 29 30 #include <asm/eeh.h> 31 #include <asm/eeh_event.h> 32 #include <asm/firmware.h> 33 #include <asm/io.h> 34 #include <asm/iommu.h> 35 #include <asm/machdep.h> 36 #include <asm/msi_bitmap.h> 37 #include <asm/opal.h> 38 #include <asm/ppc-pci.h> 39 #include <asm/pnv-pci.h> 40 41 #include "powernv.h" 42 #include "pci.h" 43 44 static int eeh_event_irq = -EINVAL; 45 46 static int pnv_eeh_init(void) 47 { 48 struct pci_controller *hose; 49 struct pnv_phb *phb; 50 int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 51 52 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 53 pr_warn("%s: OPAL is required !\n", 54 __func__); 55 return -EINVAL; 56 } 57 58 /* Set probe mode */ 59 eeh_add_flag(EEH_PROBE_MODE_DEV); 60 61 /* 62 * P7IOC blocks PCI config access to frozen PE, but PHB3 63 * doesn't do that. So we have to selectively enable I/O 64 * prior to collecting error log. 65 */ 66 list_for_each_entry(hose, &hose_list, list_node) { 67 phb = hose->private_data; 68 69 if (phb->model == PNV_PHB_MODEL_P7IOC) 70 eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 71 72 if (phb->diag_data_size > max_diag_size) 73 max_diag_size = phb->diag_data_size; 74 75 /* 76 * PE#0 should be regarded as valid by EEH core 77 * if it's not the reserved one. Currently, we 78 * have the reserved PE#255 and PE#127 for PHB3 79 * and P7IOC separately. So we should regard 80 * PE#0 as valid for PHB3 and P7IOC. 81 */ 82 if (phb->ioda.reserved_pe_idx != 0) 83 eeh_add_flag(EEH_VALID_PE_ZERO); 84 85 break; 86 } 87 88 eeh_set_pe_aux_size(max_diag_size); 89 90 return 0; 91 } 92 93 static irqreturn_t pnv_eeh_event(int irq, void *data) 94 { 95 /* 96 * We simply send a special EEH event if EEH has been 97 * enabled. We don't care about EEH events until we've 98 * finished processing the outstanding ones. Event processing 99 * gets unmasked in next_error() if EEH is enabled. 100 */ 101 disable_irq_nosync(irq); 102 103 if (eeh_enabled()) 104 eeh_send_failure_event(NULL); 105 106 return IRQ_HANDLED; 107 } 108 109 #ifdef CONFIG_DEBUG_FS 110 static ssize_t pnv_eeh_ei_write(struct file *filp, 111 const char __user *user_buf, 112 size_t count, loff_t *ppos) 113 { 114 struct pci_controller *hose = filp->private_data; 115 struct eeh_pe *pe; 116 int pe_no, type, func; 117 unsigned long addr, mask; 118 char buf[50]; 119 int ret; 120 121 if (!eeh_ops || !eeh_ops->err_inject) 122 return -ENXIO; 123 124 /* Copy over argument buffer */ 125 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 126 if (!ret) 127 return -EFAULT; 128 129 /* Retrieve parameters */ 130 ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 131 &pe_no, &type, &func, &addr, &mask); 132 if (ret != 5) 133 return -EINVAL; 134 135 /* Retrieve PE */ 136 pe = eeh_pe_get(hose, pe_no, 0); 137 if (!pe) 138 return -ENODEV; 139 140 /* Do error injection */ 141 ret = eeh_ops->err_inject(pe, type, func, addr, mask); 142 return ret < 0 ? ret : count; 143 } 144 145 static const struct file_operations pnv_eeh_ei_fops = { 146 .open = simple_open, 147 .llseek = no_llseek, 148 .write = pnv_eeh_ei_write, 149 }; 150 151 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 152 { 153 struct pci_controller *hose = data; 154 struct pnv_phb *phb = hose->private_data; 155 156 out_be64(phb->regs + offset, val); 157 return 0; 158 } 159 160 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 161 { 162 struct pci_controller *hose = data; 163 struct pnv_phb *phb = hose->private_data; 164 165 *val = in_be64(phb->regs + offset); 166 return 0; 167 } 168 169 #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 170 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 171 { \ 172 return pnv_eeh_dbgfs_set(data, reg, val); \ 173 } \ 174 \ 175 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 176 { \ 177 return pnv_eeh_dbgfs_get(data, reg, val); \ 178 } \ 179 \ 180 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 181 pnv_eeh_dbgfs_get_##name, \ 182 pnv_eeh_dbgfs_set_##name, \ 183 "0x%llx\n") 184 185 PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 186 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 187 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 188 189 #endif /* CONFIG_DEBUG_FS */ 190 191 /** 192 * pnv_eeh_post_init - EEH platform dependent post initialization 193 * 194 * EEH platform dependent post initialization on powernv. When 195 * the function is called, the EEH PEs and devices should have 196 * been built. If the I/O cache staff has been built, EEH is 197 * ready to supply service. 198 */ 199 int pnv_eeh_post_init(void) 200 { 201 struct pci_controller *hose; 202 struct pnv_phb *phb; 203 int ret = 0; 204 205 /* Probe devices & build address cache */ 206 eeh_probe_devices(); 207 eeh_addr_cache_build(); 208 209 /* Register OPAL event notifier */ 210 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 211 if (eeh_event_irq < 0) { 212 pr_err("%s: Can't register OPAL event interrupt (%d)\n", 213 __func__, eeh_event_irq); 214 return eeh_event_irq; 215 } 216 217 ret = request_irq(eeh_event_irq, pnv_eeh_event, 218 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 219 if (ret < 0) { 220 irq_dispose_mapping(eeh_event_irq); 221 pr_err("%s: Can't request OPAL event interrupt (%d)\n", 222 __func__, eeh_event_irq); 223 return ret; 224 } 225 226 if (!eeh_enabled()) 227 disable_irq(eeh_event_irq); 228 229 list_for_each_entry(hose, &hose_list, list_node) { 230 phb = hose->private_data; 231 232 /* 233 * If EEH is enabled, we're going to rely on that. 234 * Otherwise, we restore to conventional mechanism 235 * to clear frozen PE during PCI config access. 236 */ 237 if (eeh_enabled()) 238 phb->flags |= PNV_PHB_FLAG_EEH; 239 else 240 phb->flags &= ~PNV_PHB_FLAG_EEH; 241 242 /* Create debugfs entries */ 243 #ifdef CONFIG_DEBUG_FS 244 if (phb->has_dbgfs || !phb->dbgfs) 245 continue; 246 247 phb->has_dbgfs = 1; 248 debugfs_create_file("err_injct", 0200, 249 phb->dbgfs, hose, 250 &pnv_eeh_ei_fops); 251 252 debugfs_create_file("err_injct_outbound", 0600, 253 phb->dbgfs, hose, 254 &pnv_eeh_dbgfs_ops_outb); 255 debugfs_create_file("err_injct_inboundA", 0600, 256 phb->dbgfs, hose, 257 &pnv_eeh_dbgfs_ops_inbA); 258 debugfs_create_file("err_injct_inboundB", 0600, 259 phb->dbgfs, hose, 260 &pnv_eeh_dbgfs_ops_inbB); 261 #endif /* CONFIG_DEBUG_FS */ 262 } 263 264 return ret; 265 } 266 267 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 268 { 269 int pos = PCI_CAPABILITY_LIST; 270 int cnt = 48; /* Maximal number of capabilities */ 271 u32 status, id; 272 273 if (!pdn) 274 return 0; 275 276 /* Check if the device supports capabilities */ 277 pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 278 if (!(status & PCI_STATUS_CAP_LIST)) 279 return 0; 280 281 while (cnt--) { 282 pnv_pci_cfg_read(pdn, pos, 1, &pos); 283 if (pos < 0x40) 284 break; 285 286 pos &= ~3; 287 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 288 if (id == 0xff) 289 break; 290 291 /* Found */ 292 if (id == cap) 293 return pos; 294 295 /* Next one */ 296 pos += PCI_CAP_LIST_NEXT; 297 } 298 299 return 0; 300 } 301 302 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 303 { 304 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 305 u32 header; 306 int pos = 256, ttl = (4096 - 256) / 8; 307 308 if (!edev || !edev->pcie_cap) 309 return 0; 310 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 311 return 0; 312 else if (!header) 313 return 0; 314 315 while (ttl-- > 0) { 316 if (PCI_EXT_CAP_ID(header) == cap && pos) 317 return pos; 318 319 pos = PCI_EXT_CAP_NEXT(header); 320 if (pos < 256) 321 break; 322 323 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 324 break; 325 } 326 327 return 0; 328 } 329 330 /** 331 * pnv_eeh_probe - Do probe on PCI device 332 * @pdn: PCI device node 333 * @data: unused 334 * 335 * When EEH module is installed during system boot, all PCI devices 336 * are checked one by one to see if it supports EEH. The function 337 * is introduced for the purpose. By default, EEH has been enabled 338 * on all PCI devices. That's to say, we only need do necessary 339 * initialization on the corresponding eeh device and create PE 340 * accordingly. 341 * 342 * It's notable that's unsafe to retrieve the EEH device through 343 * the corresponding PCI device. During the PCI device hotplug, which 344 * was possiblly triggered by EEH core, the binding between EEH device 345 * and the PCI device isn't built yet. 346 */ 347 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 348 { 349 struct pci_controller *hose = pdn->phb; 350 struct pnv_phb *phb = hose->private_data; 351 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 352 uint32_t pcie_flags; 353 int ret; 354 int config_addr = (pdn->busno << 8) | (pdn->devfn); 355 356 /* 357 * When probing the root bridge, which doesn't have any 358 * subordinate PCI devices. We don't have OF node for 359 * the root bridge. So it's not reasonable to continue 360 * the probing. 361 */ 362 if (!edev || edev->pe) 363 return NULL; 364 365 /* Skip for PCI-ISA bridge */ 366 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 367 return NULL; 368 369 /* Skip if we haven't probed yet */ 370 if (phb->ioda.pe_rmap[config_addr] == IODA_INVALID_PE) 371 return NULL; 372 373 /* Initialize eeh device */ 374 edev->class_code = pdn->class_code; 375 edev->mode &= 0xFFFFFF00; 376 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 377 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 378 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 379 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 380 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 381 edev->mode |= EEH_DEV_BRIDGE; 382 if (edev->pcie_cap) { 383 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 384 2, &pcie_flags); 385 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 386 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 387 edev->mode |= EEH_DEV_ROOT_PORT; 388 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 389 edev->mode |= EEH_DEV_DS_PORT; 390 } 391 } 392 393 edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; 394 395 /* Create PE */ 396 ret = eeh_add_to_parent_pe(edev); 397 if (ret) { 398 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n", 399 __func__, hose->global_number, pdn->busno, 400 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 401 return NULL; 402 } 403 404 /* 405 * If the PE contains any one of following adapters, the 406 * PCI config space can't be accessed when dumping EEH log. 407 * Otherwise, we will run into fenced PHB caused by shortage 408 * of outbound credits in the adapter. The PCI config access 409 * should be blocked until PE reset. MMIO access is dropped 410 * by hardware certainly. In order to drop PCI config requests, 411 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 412 * will be checked in the backend for PE state retrival. If 413 * the PE becomes frozen for the first time and the flag has 414 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 415 * that PE to block its config space. 416 * 417 * Broadcom BCM5718 2-ports NICs (14e4:1656) 418 * Broadcom Austin 4-ports NICs (14e4:1657) 419 * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 420 * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 421 */ 422 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 423 pdn->device_id == 0x1656) || 424 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 425 pdn->device_id == 0x1657) || 426 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 427 pdn->device_id == 0x168a) || 428 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 429 pdn->device_id == 0x168e)) 430 edev->pe->state |= EEH_PE_CFG_RESTRICTED; 431 432 /* 433 * Cache the PE primary bus, which can't be fetched when 434 * full hotplug is in progress. In that case, all child 435 * PCI devices of the PE are expected to be removed prior 436 * to PE reset. 437 */ 438 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 439 edev->pe->bus = pci_find_bus(hose->global_number, 440 pdn->busno); 441 if (edev->pe->bus) 442 edev->pe->state |= EEH_PE_PRI_BUS; 443 } 444 445 /* 446 * Enable EEH explicitly so that we will do EEH check 447 * while accessing I/O stuff 448 */ 449 eeh_add_flag(EEH_ENABLED); 450 451 /* Save memory bars */ 452 eeh_save_bars(edev); 453 454 return NULL; 455 } 456 457 /** 458 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 459 * @pe: EEH PE 460 * @option: operation to be issued 461 * 462 * The function is used to control the EEH functionality globally. 463 * Currently, following options are support according to PAPR: 464 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 465 */ 466 static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 467 { 468 struct pci_controller *hose = pe->phb; 469 struct pnv_phb *phb = hose->private_data; 470 bool freeze_pe = false; 471 int opt; 472 s64 rc; 473 474 switch (option) { 475 case EEH_OPT_DISABLE: 476 return -EPERM; 477 case EEH_OPT_ENABLE: 478 return 0; 479 case EEH_OPT_THAW_MMIO: 480 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 481 break; 482 case EEH_OPT_THAW_DMA: 483 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 484 break; 485 case EEH_OPT_FREEZE_PE: 486 freeze_pe = true; 487 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 488 break; 489 default: 490 pr_warn("%s: Invalid option %d\n", __func__, option); 491 return -EINVAL; 492 } 493 494 /* Freeze master and slave PEs if PHB supports compound PEs */ 495 if (freeze_pe) { 496 if (phb->freeze_pe) { 497 phb->freeze_pe(phb, pe->addr); 498 return 0; 499 } 500 501 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 502 if (rc != OPAL_SUCCESS) { 503 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 504 __func__, rc, phb->hose->global_number, 505 pe->addr); 506 return -EIO; 507 } 508 509 return 0; 510 } 511 512 /* Unfreeze master and slave PEs if PHB supports */ 513 if (phb->unfreeze_pe) 514 return phb->unfreeze_pe(phb, pe->addr, opt); 515 516 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 517 if (rc != OPAL_SUCCESS) { 518 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 519 __func__, rc, option, phb->hose->global_number, 520 pe->addr); 521 return -EIO; 522 } 523 524 return 0; 525 } 526 527 /** 528 * pnv_eeh_get_pe_addr - Retrieve PE address 529 * @pe: EEH PE 530 * 531 * Retrieve the PE address according to the given tranditional 532 * PCI BDF (Bus/Device/Function) address. 533 */ 534 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 535 { 536 return pe->addr; 537 } 538 539 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 540 { 541 struct pnv_phb *phb = pe->phb->private_data; 542 s64 rc; 543 544 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 545 phb->diag_data_size); 546 if (rc != OPAL_SUCCESS) 547 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 548 __func__, rc, pe->phb->global_number); 549 } 550 551 static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 552 { 553 struct pnv_phb *phb = pe->phb->private_data; 554 u8 fstate; 555 __be16 pcierr; 556 s64 rc; 557 int result = 0; 558 559 rc = opal_pci_eeh_freeze_status(phb->opal_id, 560 pe->addr, 561 &fstate, 562 &pcierr, 563 NULL); 564 if (rc != OPAL_SUCCESS) { 565 pr_warn("%s: Failure %lld getting PHB#%x state\n", 566 __func__, rc, phb->hose->global_number); 567 return EEH_STATE_NOT_SUPPORT; 568 } 569 570 /* 571 * Check PHB state. If the PHB is frozen for the 572 * first time, to dump the PHB diag-data. 573 */ 574 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 575 result = (EEH_STATE_MMIO_ACTIVE | 576 EEH_STATE_DMA_ACTIVE | 577 EEH_STATE_MMIO_ENABLED | 578 EEH_STATE_DMA_ENABLED); 579 } else if (!(pe->state & EEH_PE_ISOLATED)) { 580 eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 581 pnv_eeh_get_phb_diag(pe); 582 583 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 584 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 585 } 586 587 return result; 588 } 589 590 static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 591 { 592 struct pnv_phb *phb = pe->phb->private_data; 593 u8 fstate; 594 __be16 pcierr; 595 s64 rc; 596 int result; 597 598 /* 599 * We don't clobber hardware frozen state until PE 600 * reset is completed. In order to keep EEH core 601 * moving forward, we have to return operational 602 * state during PE reset. 603 */ 604 if (pe->state & EEH_PE_RESET) { 605 result = (EEH_STATE_MMIO_ACTIVE | 606 EEH_STATE_DMA_ACTIVE | 607 EEH_STATE_MMIO_ENABLED | 608 EEH_STATE_DMA_ENABLED); 609 return result; 610 } 611 612 /* 613 * Fetch PE state from hardware. If the PHB 614 * supports compound PE, let it handle that. 615 */ 616 if (phb->get_pe_state) { 617 fstate = phb->get_pe_state(phb, pe->addr); 618 } else { 619 rc = opal_pci_eeh_freeze_status(phb->opal_id, 620 pe->addr, 621 &fstate, 622 &pcierr, 623 NULL); 624 if (rc != OPAL_SUCCESS) { 625 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 626 __func__, rc, phb->hose->global_number, 627 pe->addr); 628 return EEH_STATE_NOT_SUPPORT; 629 } 630 } 631 632 /* Figure out state */ 633 switch (fstate) { 634 case OPAL_EEH_STOPPED_NOT_FROZEN: 635 result = (EEH_STATE_MMIO_ACTIVE | 636 EEH_STATE_DMA_ACTIVE | 637 EEH_STATE_MMIO_ENABLED | 638 EEH_STATE_DMA_ENABLED); 639 break; 640 case OPAL_EEH_STOPPED_MMIO_FREEZE: 641 result = (EEH_STATE_DMA_ACTIVE | 642 EEH_STATE_DMA_ENABLED); 643 break; 644 case OPAL_EEH_STOPPED_DMA_FREEZE: 645 result = (EEH_STATE_MMIO_ACTIVE | 646 EEH_STATE_MMIO_ENABLED); 647 break; 648 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 649 result = 0; 650 break; 651 case OPAL_EEH_STOPPED_RESET: 652 result = EEH_STATE_RESET_ACTIVE; 653 break; 654 case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 655 result = EEH_STATE_UNAVAILABLE; 656 break; 657 case OPAL_EEH_STOPPED_PERM_UNAVAIL: 658 result = EEH_STATE_NOT_SUPPORT; 659 break; 660 default: 661 result = EEH_STATE_NOT_SUPPORT; 662 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 663 __func__, phb->hose->global_number, 664 pe->addr, fstate); 665 } 666 667 /* 668 * If PHB supports compound PE, to freeze all 669 * slave PEs for consistency. 670 * 671 * If the PE is switching to frozen state for the 672 * first time, to dump the PHB diag-data. 673 */ 674 if (!(result & EEH_STATE_NOT_SUPPORT) && 675 !(result & EEH_STATE_UNAVAILABLE) && 676 !(result & EEH_STATE_MMIO_ACTIVE) && 677 !(result & EEH_STATE_DMA_ACTIVE) && 678 !(pe->state & EEH_PE_ISOLATED)) { 679 if (phb->freeze_pe) 680 phb->freeze_pe(phb, pe->addr); 681 682 eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 683 pnv_eeh_get_phb_diag(pe); 684 685 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 686 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 687 } 688 689 return result; 690 } 691 692 /** 693 * pnv_eeh_get_state - Retrieve PE state 694 * @pe: EEH PE 695 * @delay: delay while PE state is temporarily unavailable 696 * 697 * Retrieve the state of the specified PE. For IODA-compitable 698 * platform, it should be retrieved from IODA table. Therefore, 699 * we prefer passing down to hardware implementation to handle 700 * it. 701 */ 702 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 703 { 704 int ret; 705 706 if (pe->type & EEH_PE_PHB) 707 ret = pnv_eeh_get_phb_state(pe); 708 else 709 ret = pnv_eeh_get_pe_state(pe); 710 711 if (!delay) 712 return ret; 713 714 /* 715 * If the PE state is temporarily unavailable, 716 * to inform the EEH core delay for default 717 * period (1 second) 718 */ 719 *delay = 0; 720 if (ret & EEH_STATE_UNAVAILABLE) 721 *delay = 1000; 722 723 return ret; 724 } 725 726 static s64 pnv_eeh_poll(unsigned long id) 727 { 728 s64 rc = OPAL_HARDWARE; 729 730 while (1) { 731 rc = opal_pci_poll(id); 732 if (rc <= 0) 733 break; 734 735 if (system_state < SYSTEM_RUNNING) 736 udelay(1000 * rc); 737 else 738 msleep(rc); 739 } 740 741 return rc; 742 } 743 744 int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 745 { 746 struct pnv_phb *phb = hose->private_data; 747 s64 rc = OPAL_HARDWARE; 748 749 pr_debug("%s: Reset PHB#%x, option=%d\n", 750 __func__, hose->global_number, option); 751 752 /* Issue PHB complete reset request */ 753 if (option == EEH_RESET_FUNDAMENTAL || 754 option == EEH_RESET_HOT) 755 rc = opal_pci_reset(phb->opal_id, 756 OPAL_RESET_PHB_COMPLETE, 757 OPAL_ASSERT_RESET); 758 else if (option == EEH_RESET_DEACTIVATE) 759 rc = opal_pci_reset(phb->opal_id, 760 OPAL_RESET_PHB_COMPLETE, 761 OPAL_DEASSERT_RESET); 762 if (rc < 0) 763 goto out; 764 765 /* 766 * Poll state of the PHB until the request is done 767 * successfully. The PHB reset is usually PHB complete 768 * reset followed by hot reset on root bus. So we also 769 * need the PCI bus settlement delay. 770 */ 771 if (rc > 0) 772 rc = pnv_eeh_poll(phb->opal_id); 773 if (option == EEH_RESET_DEACTIVATE) { 774 if (system_state < SYSTEM_RUNNING) 775 udelay(1000 * EEH_PE_RST_SETTLE_TIME); 776 else 777 msleep(EEH_PE_RST_SETTLE_TIME); 778 } 779 out: 780 if (rc != OPAL_SUCCESS) 781 return -EIO; 782 783 return 0; 784 } 785 786 static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 787 { 788 struct pnv_phb *phb = hose->private_data; 789 s64 rc = OPAL_HARDWARE; 790 791 pr_debug("%s: Reset PHB#%x, option=%d\n", 792 __func__, hose->global_number, option); 793 794 /* 795 * During the reset deassert time, we needn't care 796 * the reset scope because the firmware does nothing 797 * for fundamental or hot reset during deassert phase. 798 */ 799 if (option == EEH_RESET_FUNDAMENTAL) 800 rc = opal_pci_reset(phb->opal_id, 801 OPAL_RESET_PCI_FUNDAMENTAL, 802 OPAL_ASSERT_RESET); 803 else if (option == EEH_RESET_HOT) 804 rc = opal_pci_reset(phb->opal_id, 805 OPAL_RESET_PCI_HOT, 806 OPAL_ASSERT_RESET); 807 else if (option == EEH_RESET_DEACTIVATE) 808 rc = opal_pci_reset(phb->opal_id, 809 OPAL_RESET_PCI_HOT, 810 OPAL_DEASSERT_RESET); 811 if (rc < 0) 812 goto out; 813 814 /* Poll state of the PHB until the request is done */ 815 if (rc > 0) 816 rc = pnv_eeh_poll(phb->opal_id); 817 if (option == EEH_RESET_DEACTIVATE) 818 msleep(EEH_PE_RST_SETTLE_TIME); 819 out: 820 if (rc != OPAL_SUCCESS) 821 return -EIO; 822 823 return 0; 824 } 825 826 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 827 { 828 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 829 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 830 int aer = edev ? edev->aer_cap : 0; 831 u32 ctrl; 832 833 pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 834 __func__, pci_domain_nr(dev->bus), 835 dev->bus->number, option); 836 837 switch (option) { 838 case EEH_RESET_FUNDAMENTAL: 839 case EEH_RESET_HOT: 840 /* Don't report linkDown event */ 841 if (aer) { 842 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 843 4, &ctrl); 844 ctrl |= PCI_ERR_UNC_SURPDN; 845 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 846 4, ctrl); 847 } 848 849 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 850 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 851 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 852 853 msleep(EEH_PE_RST_HOLD_TIME); 854 break; 855 case EEH_RESET_DEACTIVATE: 856 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 857 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 858 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 859 860 msleep(EEH_PE_RST_SETTLE_TIME); 861 862 /* Continue reporting linkDown event */ 863 if (aer) { 864 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 865 4, &ctrl); 866 ctrl &= ~PCI_ERR_UNC_SURPDN; 867 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 868 4, ctrl); 869 } 870 871 break; 872 } 873 874 return 0; 875 } 876 877 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 878 { 879 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 880 struct pnv_phb *phb = hose->private_data; 881 struct device_node *dn = pci_device_to_OF_node(pdev); 882 uint64_t id = PCI_SLOT_ID(phb->opal_id, 883 (pdev->bus->number << 8) | pdev->devfn); 884 uint8_t scope; 885 int64_t rc; 886 887 /* Hot reset to the bus if firmware cannot handle */ 888 if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 889 return __pnv_eeh_bridge_reset(pdev, option); 890 891 switch (option) { 892 case EEH_RESET_FUNDAMENTAL: 893 scope = OPAL_RESET_PCI_FUNDAMENTAL; 894 break; 895 case EEH_RESET_HOT: 896 scope = OPAL_RESET_PCI_HOT; 897 break; 898 case EEH_RESET_DEACTIVATE: 899 return 0; 900 default: 901 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 902 __func__, option); 903 return -EINVAL; 904 } 905 906 rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 907 if (rc <= OPAL_SUCCESS) 908 goto out; 909 910 rc = pnv_eeh_poll(id); 911 out: 912 return (rc == OPAL_SUCCESS) ? 0 : -EIO; 913 } 914 915 void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 916 { 917 struct pci_controller *hose; 918 919 if (pci_is_root_bus(dev->bus)) { 920 hose = pci_bus_to_host(dev->bus); 921 pnv_eeh_root_reset(hose, EEH_RESET_HOT); 922 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 923 } else { 924 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 925 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 926 } 927 } 928 929 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 930 int pos, u16 mask) 931 { 932 int i, status = 0; 933 934 /* Wait for Transaction Pending bit to be cleared */ 935 for (i = 0; i < 4; i++) { 936 eeh_ops->read_config(pdn, pos, 2, &status); 937 if (!(status & mask)) 938 return; 939 940 msleep((1 << i) * 100); 941 } 942 943 pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 944 __func__, type, 945 pdn->phb->global_number, pdn->busno, 946 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 947 } 948 949 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 950 { 951 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 952 u32 reg = 0; 953 954 if (WARN_ON(!edev->pcie_cap)) 955 return -ENOTTY; 956 957 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 958 if (!(reg & PCI_EXP_DEVCAP_FLR)) 959 return -ENOTTY; 960 961 switch (option) { 962 case EEH_RESET_HOT: 963 case EEH_RESET_FUNDAMENTAL: 964 pnv_eeh_wait_for_pending(pdn, "", 965 edev->pcie_cap + PCI_EXP_DEVSTA, 966 PCI_EXP_DEVSTA_TRPND); 967 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 968 4, ®); 969 reg |= PCI_EXP_DEVCTL_BCR_FLR; 970 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 971 4, reg); 972 msleep(EEH_PE_RST_HOLD_TIME); 973 break; 974 case EEH_RESET_DEACTIVATE: 975 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 976 4, ®); 977 reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 978 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 979 4, reg); 980 msleep(EEH_PE_RST_SETTLE_TIME); 981 break; 982 } 983 984 return 0; 985 } 986 987 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 988 { 989 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 990 u32 cap = 0; 991 992 if (WARN_ON(!edev->af_cap)) 993 return -ENOTTY; 994 995 eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 996 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 997 return -ENOTTY; 998 999 switch (option) { 1000 case EEH_RESET_HOT: 1001 case EEH_RESET_FUNDAMENTAL: 1002 /* 1003 * Wait for Transaction Pending bit to clear. A word-aligned 1004 * test is used, so we use the conrol offset rather than status 1005 * and shift the test bit to match. 1006 */ 1007 pnv_eeh_wait_for_pending(pdn, "AF", 1008 edev->af_cap + PCI_AF_CTRL, 1009 PCI_AF_STATUS_TP << 8); 1010 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1011 1, PCI_AF_CTRL_FLR); 1012 msleep(EEH_PE_RST_HOLD_TIME); 1013 break; 1014 case EEH_RESET_DEACTIVATE: 1015 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 1016 msleep(EEH_PE_RST_SETTLE_TIME); 1017 break; 1018 } 1019 1020 return 0; 1021 } 1022 1023 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 1024 { 1025 struct eeh_dev *edev; 1026 struct pci_dn *pdn; 1027 int ret; 1028 1029 /* The VF PE should have only one child device */ 1030 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list); 1031 pdn = eeh_dev_to_pdn(edev); 1032 if (!pdn) 1033 return -ENXIO; 1034 1035 ret = pnv_eeh_do_flr(pdn, option); 1036 if (!ret) 1037 return ret; 1038 1039 return pnv_eeh_do_af_flr(pdn, option); 1040 } 1041 1042 /** 1043 * pnv_eeh_reset - Reset the specified PE 1044 * @pe: EEH PE 1045 * @option: reset option 1046 * 1047 * Do reset on the indicated PE. For PCI bus sensitive PE, 1048 * we need to reset the parent p2p bridge. The PHB has to 1049 * be reinitialized if the p2p bridge is root bridge. For 1050 * PCI device sensitive PE, we will try to reset the device 1051 * through FLR. For now, we don't have OPAL APIs to do HARD 1052 * reset yet, so all reset would be SOFT (HOT) reset. 1053 */ 1054 static int pnv_eeh_reset(struct eeh_pe *pe, int option) 1055 { 1056 struct pci_controller *hose = pe->phb; 1057 struct pnv_phb *phb; 1058 struct pci_bus *bus; 1059 int64_t rc; 1060 1061 /* 1062 * For PHB reset, we always have complete reset. For those PEs whose 1063 * primary bus derived from root complex (root bus) or root port 1064 * (usually bus#1), we apply hot or fundamental reset on the root port. 1065 * For other PEs, we always have hot reset on the PE primary bus. 1066 * 1067 * Here, we have different design to pHyp, which always clear the 1068 * frozen state during PE reset. However, the good idea here from 1069 * benh is to keep frozen state before we get PE reset done completely 1070 * (until BAR restore). With the frozen state, HW drops illegal IO 1071 * or MMIO access, which can incur recrusive frozen PE during PE 1072 * reset. The side effect is that EEH core has to clear the frozen 1073 * state explicitly after BAR restore. 1074 */ 1075 if (pe->type & EEH_PE_PHB) 1076 return pnv_eeh_phb_reset(hose, option); 1077 1078 /* 1079 * The frozen PE might be caused by PAPR error injection 1080 * registers, which are expected to be cleared after hitting 1081 * frozen PE as stated in the hardware spec. Unfortunately, 1082 * that's not true on P7IOC. So we have to clear it manually 1083 * to avoid recursive EEH errors during recovery. 1084 */ 1085 phb = hose->private_data; 1086 if (phb->model == PNV_PHB_MODEL_P7IOC && 1087 (option == EEH_RESET_HOT || 1088 option == EEH_RESET_FUNDAMENTAL)) { 1089 rc = opal_pci_reset(phb->opal_id, 1090 OPAL_RESET_PHB_ERROR, 1091 OPAL_ASSERT_RESET); 1092 if (rc != OPAL_SUCCESS) { 1093 pr_warn("%s: Failure %lld clearing error injection registers\n", 1094 __func__, rc); 1095 return -EIO; 1096 } 1097 } 1098 1099 if (pe->type & EEH_PE_VF) 1100 return pnv_eeh_reset_vf_pe(pe, option); 1101 1102 bus = eeh_pe_bus_get(pe); 1103 if (!bus) { 1104 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 1105 __func__, pe->phb->global_number, pe->addr); 1106 return -EIO; 1107 } 1108 1109 /* 1110 * If dealing with the root bus (or the bus underneath the 1111 * root port), we reset the bus underneath the root port. 1112 * 1113 * The cxl driver depends on this behaviour for bi-modal card 1114 * switching. 1115 */ 1116 if (pci_is_root_bus(bus) || 1117 pci_is_root_bus(bus->parent)) 1118 return pnv_eeh_root_reset(hose, option); 1119 1120 return pnv_eeh_bridge_reset(bus->self, option); 1121 } 1122 1123 /** 1124 * pnv_eeh_wait_state - Wait for PE state 1125 * @pe: EEH PE 1126 * @max_wait: maximal period in millisecond 1127 * 1128 * Wait for the state of associated PE. It might take some time 1129 * to retrieve the PE's state. 1130 */ 1131 static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) 1132 { 1133 int ret; 1134 int mwait; 1135 1136 while (1) { 1137 ret = pnv_eeh_get_state(pe, &mwait); 1138 1139 /* 1140 * If the PE's state is temporarily unavailable, 1141 * we have to wait for the specified time. Otherwise, 1142 * the PE's state will be returned immediately. 1143 */ 1144 if (ret != EEH_STATE_UNAVAILABLE) 1145 return ret; 1146 1147 if (max_wait <= 0) { 1148 pr_warn("%s: Timeout getting PE#%x's state (%d)\n", 1149 __func__, pe->addr, max_wait); 1150 return EEH_STATE_NOT_SUPPORT; 1151 } 1152 1153 max_wait -= mwait; 1154 msleep(mwait); 1155 } 1156 1157 return EEH_STATE_NOT_SUPPORT; 1158 } 1159 1160 /** 1161 * pnv_eeh_get_log - Retrieve error log 1162 * @pe: EEH PE 1163 * @severity: temporary or permanent error log 1164 * @drv_log: driver log to be combined with retrieved error log 1165 * @len: length of driver log 1166 * 1167 * Retrieve the temporary or permanent error from the PE. 1168 */ 1169 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 1170 char *drv_log, unsigned long len) 1171 { 1172 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1173 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 1174 1175 return 0; 1176 } 1177 1178 /** 1179 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 1180 * @pe: EEH PE 1181 * 1182 * The function will be called to reconfigure the bridges included 1183 * in the specified PE so that the mulfunctional PE would be recovered 1184 * again. 1185 */ 1186 static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 1187 { 1188 return 0; 1189 } 1190 1191 /** 1192 * pnv_pe_err_inject - Inject specified error to the indicated PE 1193 * @pe: the indicated PE 1194 * @type: error type 1195 * @func: specific error type 1196 * @addr: address 1197 * @mask: address mask 1198 * 1199 * The routine is called to inject specified error, which is 1200 * determined by @type and @func, to the indicated PE for 1201 * testing purpose. 1202 */ 1203 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1204 unsigned long addr, unsigned long mask) 1205 { 1206 struct pci_controller *hose = pe->phb; 1207 struct pnv_phb *phb = hose->private_data; 1208 s64 rc; 1209 1210 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1211 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1212 pr_warn("%s: Invalid error type %d\n", 1213 __func__, type); 1214 return -ERANGE; 1215 } 1216 1217 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1218 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1219 pr_warn("%s: Invalid error function %d\n", 1220 __func__, func); 1221 return -ERANGE; 1222 } 1223 1224 /* Firmware supports error injection ? */ 1225 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1226 pr_warn("%s: Firmware doesn't support error injection\n", 1227 __func__); 1228 return -ENXIO; 1229 } 1230 1231 /* Do error injection */ 1232 rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1233 type, func, addr, mask); 1234 if (rc != OPAL_SUCCESS) { 1235 pr_warn("%s: Failure %lld injecting error " 1236 "%d-%d to PHB#%x-PE#%x\n", 1237 __func__, rc, type, func, 1238 hose->global_number, pe->addr); 1239 return -EIO; 1240 } 1241 1242 return 0; 1243 } 1244 1245 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1246 { 1247 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1248 1249 if (!edev || !edev->pe) 1250 return false; 1251 1252 /* 1253 * We will issue FLR or AF FLR to all VFs, which are contained 1254 * in VF PE. It relies on the EEH PCI config accessors. So we 1255 * can't block them during the window. 1256 */ 1257 if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 1258 return false; 1259 1260 if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1261 return true; 1262 1263 return false; 1264 } 1265 1266 static int pnv_eeh_read_config(struct pci_dn *pdn, 1267 int where, int size, u32 *val) 1268 { 1269 if (!pdn) 1270 return PCIBIOS_DEVICE_NOT_FOUND; 1271 1272 if (pnv_eeh_cfg_blocked(pdn)) { 1273 *val = 0xFFFFFFFF; 1274 return PCIBIOS_SET_FAILED; 1275 } 1276 1277 return pnv_pci_cfg_read(pdn, where, size, val); 1278 } 1279 1280 static int pnv_eeh_write_config(struct pci_dn *pdn, 1281 int where, int size, u32 val) 1282 { 1283 if (!pdn) 1284 return PCIBIOS_DEVICE_NOT_FOUND; 1285 1286 if (pnv_eeh_cfg_blocked(pdn)) 1287 return PCIBIOS_SET_FAILED; 1288 1289 return pnv_pci_cfg_write(pdn, where, size, val); 1290 } 1291 1292 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 1293 { 1294 /* GEM */ 1295 if (data->gemXfir || data->gemRfir || 1296 data->gemRirqfir || data->gemMask || data->gemRwof) 1297 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 1298 be64_to_cpu(data->gemXfir), 1299 be64_to_cpu(data->gemRfir), 1300 be64_to_cpu(data->gemRirqfir), 1301 be64_to_cpu(data->gemMask), 1302 be64_to_cpu(data->gemRwof)); 1303 1304 /* LEM */ 1305 if (data->lemFir || data->lemErrMask || 1306 data->lemAction0 || data->lemAction1 || data->lemWof) 1307 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 1308 be64_to_cpu(data->lemFir), 1309 be64_to_cpu(data->lemErrMask), 1310 be64_to_cpu(data->lemAction0), 1311 be64_to_cpu(data->lemAction1), 1312 be64_to_cpu(data->lemWof)); 1313 } 1314 1315 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 1316 { 1317 struct pnv_phb *phb = hose->private_data; 1318 struct OpalIoP7IOCErrorData *data = 1319 (struct OpalIoP7IOCErrorData*)phb->diag_data; 1320 long rc; 1321 1322 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 1323 if (rc != OPAL_SUCCESS) { 1324 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 1325 __func__, phb->hub_id, rc); 1326 return; 1327 } 1328 1329 switch (be16_to_cpu(data->type)) { 1330 case OPAL_P7IOC_DIAG_TYPE_RGC: 1331 pr_info("P7IOC diag-data for RGC\n\n"); 1332 pnv_eeh_dump_hub_diag_common(data); 1333 if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 1334 pr_info(" RGC: %016llx %016llx\n", 1335 be64_to_cpu(data->rgc.rgcStatus), 1336 be64_to_cpu(data->rgc.rgcLdcp)); 1337 break; 1338 case OPAL_P7IOC_DIAG_TYPE_BI: 1339 pr_info("P7IOC diag-data for BI %s\n\n", 1340 data->bi.biDownbound ? "Downbound" : "Upbound"); 1341 pnv_eeh_dump_hub_diag_common(data); 1342 if (data->bi.biLdcp0 || data->bi.biLdcp1 || 1343 data->bi.biLdcp2 || data->bi.biFenceStatus) 1344 pr_info(" BI: %016llx %016llx %016llx %016llx\n", 1345 be64_to_cpu(data->bi.biLdcp0), 1346 be64_to_cpu(data->bi.biLdcp1), 1347 be64_to_cpu(data->bi.biLdcp2), 1348 be64_to_cpu(data->bi.biFenceStatus)); 1349 break; 1350 case OPAL_P7IOC_DIAG_TYPE_CI: 1351 pr_info("P7IOC diag-data for CI Port %d\n\n", 1352 data->ci.ciPort); 1353 pnv_eeh_dump_hub_diag_common(data); 1354 if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 1355 pr_info(" CI: %016llx %016llx\n", 1356 be64_to_cpu(data->ci.ciPortStatus), 1357 be64_to_cpu(data->ci.ciPortLdcp)); 1358 break; 1359 case OPAL_P7IOC_DIAG_TYPE_MISC: 1360 pr_info("P7IOC diag-data for MISC\n\n"); 1361 pnv_eeh_dump_hub_diag_common(data); 1362 break; 1363 case OPAL_P7IOC_DIAG_TYPE_I2C: 1364 pr_info("P7IOC diag-data for I2C\n\n"); 1365 pnv_eeh_dump_hub_diag_common(data); 1366 break; 1367 default: 1368 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 1369 __func__, phb->hub_id, data->type); 1370 } 1371 } 1372 1373 static int pnv_eeh_get_pe(struct pci_controller *hose, 1374 u16 pe_no, struct eeh_pe **pe) 1375 { 1376 struct pnv_phb *phb = hose->private_data; 1377 struct pnv_ioda_pe *pnv_pe; 1378 struct eeh_pe *dev_pe; 1379 1380 /* 1381 * If PHB supports compound PE, to fetch 1382 * the master PE because slave PE is invisible 1383 * to EEH core. 1384 */ 1385 pnv_pe = &phb->ioda.pe_array[pe_no]; 1386 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 1387 pnv_pe = pnv_pe->master; 1388 WARN_ON(!pnv_pe || 1389 !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 1390 pe_no = pnv_pe->pe_number; 1391 } 1392 1393 /* Find the PE according to PE# */ 1394 dev_pe = eeh_pe_get(hose, pe_no, 0); 1395 if (!dev_pe) 1396 return -EEXIST; 1397 1398 /* Freeze the (compound) PE */ 1399 *pe = dev_pe; 1400 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1401 phb->freeze_pe(phb, pe_no); 1402 1403 /* 1404 * At this point, we're sure the (compound) PE should 1405 * have been frozen. However, we still need poke until 1406 * hitting the frozen PE on top level. 1407 */ 1408 dev_pe = dev_pe->parent; 1409 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 1410 int ret; 1411 int active_flags = (EEH_STATE_MMIO_ACTIVE | 1412 EEH_STATE_DMA_ACTIVE); 1413 1414 ret = eeh_ops->get_state(dev_pe, NULL); 1415 if (ret <= 0 || (ret & active_flags) == active_flags) { 1416 dev_pe = dev_pe->parent; 1417 continue; 1418 } 1419 1420 /* Frozen parent PE */ 1421 *pe = dev_pe; 1422 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1423 phb->freeze_pe(phb, dev_pe->addr); 1424 1425 /* Next one */ 1426 dev_pe = dev_pe->parent; 1427 } 1428 1429 return 0; 1430 } 1431 1432 /** 1433 * pnv_eeh_next_error - Retrieve next EEH error to handle 1434 * @pe: Affected PE 1435 * 1436 * The function is expected to be called by EEH core while it gets 1437 * special EEH event (without binding PE). The function calls to 1438 * OPAL APIs for next error to handle. The informational error is 1439 * handled internally by platform. However, the dead IOC, dead PHB, 1440 * fenced PHB and frozen PE should be handled by EEH core eventually. 1441 */ 1442 static int pnv_eeh_next_error(struct eeh_pe **pe) 1443 { 1444 struct pci_controller *hose; 1445 struct pnv_phb *phb; 1446 struct eeh_pe *phb_pe, *parent_pe; 1447 __be64 frozen_pe_no; 1448 __be16 err_type, severity; 1449 int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 1450 long rc; 1451 int state, ret = EEH_NEXT_ERR_NONE; 1452 1453 /* 1454 * While running here, it's safe to purge the event queue. The 1455 * event should still be masked. 1456 */ 1457 eeh_remove_event(NULL, false); 1458 1459 list_for_each_entry(hose, &hose_list, list_node) { 1460 /* 1461 * If the subordinate PCI buses of the PHB has been 1462 * removed or is exactly under error recovery, we 1463 * needn't take care of it any more. 1464 */ 1465 phb = hose->private_data; 1466 phb_pe = eeh_phb_pe_get(hose); 1467 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 1468 continue; 1469 1470 rc = opal_pci_next_error(phb->opal_id, 1471 &frozen_pe_no, &err_type, &severity); 1472 if (rc != OPAL_SUCCESS) { 1473 pr_devel("%s: Invalid return value on " 1474 "PHB#%x (0x%lx) from opal_pci_next_error", 1475 __func__, hose->global_number, rc); 1476 continue; 1477 } 1478 1479 /* If the PHB doesn't have error, stop processing */ 1480 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 1481 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 1482 pr_devel("%s: No error found on PHB#%x\n", 1483 __func__, hose->global_number); 1484 continue; 1485 } 1486 1487 /* 1488 * Processing the error. We're expecting the error with 1489 * highest priority reported upon multiple errors on the 1490 * specific PHB. 1491 */ 1492 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 1493 __func__, be16_to_cpu(err_type), 1494 be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 1495 hose->global_number); 1496 switch (be16_to_cpu(err_type)) { 1497 case OPAL_EEH_IOC_ERROR: 1498 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 1499 pr_err("EEH: dead IOC detected\n"); 1500 ret = EEH_NEXT_ERR_DEAD_IOC; 1501 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1502 pr_info("EEH: IOC informative error " 1503 "detected\n"); 1504 pnv_eeh_get_and_dump_hub_diag(hose); 1505 ret = EEH_NEXT_ERR_NONE; 1506 } 1507 1508 break; 1509 case OPAL_EEH_PHB_ERROR: 1510 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 1511 *pe = phb_pe; 1512 pr_err("EEH: dead PHB#%x detected, " 1513 "location: %s\n", 1514 hose->global_number, 1515 eeh_pe_loc_get(phb_pe)); 1516 ret = EEH_NEXT_ERR_DEAD_PHB; 1517 } else if (be16_to_cpu(severity) == 1518 OPAL_EEH_SEV_PHB_FENCED) { 1519 *pe = phb_pe; 1520 pr_err("EEH: Fenced PHB#%x detected, " 1521 "location: %s\n", 1522 hose->global_number, 1523 eeh_pe_loc_get(phb_pe)); 1524 ret = EEH_NEXT_ERR_FENCED_PHB; 1525 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1526 pr_info("EEH: PHB#%x informative error " 1527 "detected, location: %s\n", 1528 hose->global_number, 1529 eeh_pe_loc_get(phb_pe)); 1530 pnv_eeh_get_phb_diag(phb_pe); 1531 pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 1532 ret = EEH_NEXT_ERR_NONE; 1533 } 1534 1535 break; 1536 case OPAL_EEH_PE_ERROR: 1537 /* 1538 * If we can't find the corresponding PE, we 1539 * just try to unfreeze. 1540 */ 1541 if (pnv_eeh_get_pe(hose, 1542 be64_to_cpu(frozen_pe_no), pe)) { 1543 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 1544 hose->global_number, be64_to_cpu(frozen_pe_no)); 1545 pr_info("EEH: PHB location: %s\n", 1546 eeh_pe_loc_get(phb_pe)); 1547 1548 /* Dump PHB diag-data */ 1549 rc = opal_pci_get_phb_diag_data2(phb->opal_id, 1550 phb->diag_data, phb->diag_data_size); 1551 if (rc == OPAL_SUCCESS) 1552 pnv_pci_dump_phb_diag_data(hose, 1553 phb->diag_data); 1554 1555 /* Try best to clear it */ 1556 opal_pci_eeh_freeze_clear(phb->opal_id, 1557 be64_to_cpu(frozen_pe_no), 1558 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 1559 ret = EEH_NEXT_ERR_NONE; 1560 } else if ((*pe)->state & EEH_PE_ISOLATED || 1561 eeh_pe_passed(*pe)) { 1562 ret = EEH_NEXT_ERR_NONE; 1563 } else { 1564 pr_err("EEH: Frozen PE#%x " 1565 "on PHB#%x detected\n", 1566 (*pe)->addr, 1567 (*pe)->phb->global_number); 1568 pr_err("EEH: PE location: %s, " 1569 "PHB location: %s\n", 1570 eeh_pe_loc_get(*pe), 1571 eeh_pe_loc_get(phb_pe)); 1572 ret = EEH_NEXT_ERR_FROZEN_PE; 1573 } 1574 1575 break; 1576 default: 1577 pr_warn("%s: Unexpected error type %d\n", 1578 __func__, be16_to_cpu(err_type)); 1579 } 1580 1581 /* 1582 * EEH core will try recover from fenced PHB or 1583 * frozen PE. In the time for frozen PE, EEH core 1584 * enable IO path for that before collecting logs, 1585 * but it ruins the site. So we have to dump the 1586 * log in advance here. 1587 */ 1588 if ((ret == EEH_NEXT_ERR_FROZEN_PE || 1589 ret == EEH_NEXT_ERR_FENCED_PHB) && 1590 !((*pe)->state & EEH_PE_ISOLATED)) { 1591 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 1592 pnv_eeh_get_phb_diag(*pe); 1593 1594 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1595 pnv_pci_dump_phb_diag_data((*pe)->phb, 1596 (*pe)->data); 1597 } 1598 1599 /* 1600 * We probably have the frozen parent PE out there and 1601 * we need have to handle frozen parent PE firstly. 1602 */ 1603 if (ret == EEH_NEXT_ERR_FROZEN_PE) { 1604 parent_pe = (*pe)->parent; 1605 while (parent_pe) { 1606 /* Hit the ceiling ? */ 1607 if (parent_pe->type & EEH_PE_PHB) 1608 break; 1609 1610 /* Frozen parent PE ? */ 1611 state = eeh_ops->get_state(parent_pe, NULL); 1612 if (state > 0 && 1613 (state & active_flags) != active_flags) 1614 *pe = parent_pe; 1615 1616 /* Next parent level */ 1617 parent_pe = parent_pe->parent; 1618 } 1619 1620 /* We possibly migrate to another PE */ 1621 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 1622 } 1623 1624 /* 1625 * If we have no errors on the specific PHB or only 1626 * informative error there, we continue poking it. 1627 * Otherwise, we need actions to be taken by upper 1628 * layer. 1629 */ 1630 if (ret > EEH_NEXT_ERR_INF) 1631 break; 1632 } 1633 1634 /* Unmask the event */ 1635 if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 1636 enable_irq(eeh_event_irq); 1637 1638 return ret; 1639 } 1640 1641 static int pnv_eeh_restore_vf_config(struct pci_dn *pdn) 1642 { 1643 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1644 u32 devctl, cmd, cap2, aer_capctl; 1645 int old_mps; 1646 1647 if (edev->pcie_cap) { 1648 /* Restore MPS */ 1649 old_mps = (ffs(pdn->mps) - 8) << 5; 1650 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1651 2, &devctl); 1652 devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; 1653 devctl |= old_mps; 1654 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1655 2, devctl); 1656 1657 /* Disable Completion Timeout */ 1658 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2, 1659 4, &cap2); 1660 if (cap2 & 0x10) { 1661 eeh_ops->read_config(pdn, 1662 edev->pcie_cap + PCI_EXP_DEVCTL2, 1663 4, &cap2); 1664 cap2 |= 0x10; 1665 eeh_ops->write_config(pdn, 1666 edev->pcie_cap + PCI_EXP_DEVCTL2, 1667 4, cap2); 1668 } 1669 } 1670 1671 /* Enable SERR and parity checking */ 1672 eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd); 1673 cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 1674 eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd); 1675 1676 /* Enable report various errors */ 1677 if (edev->pcie_cap) { 1678 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1679 2, &devctl); 1680 devctl &= ~PCI_EXP_DEVCTL_CERE; 1681 devctl |= (PCI_EXP_DEVCTL_NFERE | 1682 PCI_EXP_DEVCTL_FERE | 1683 PCI_EXP_DEVCTL_URRE); 1684 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1685 2, devctl); 1686 } 1687 1688 /* Enable ECRC generation and check */ 1689 if (edev->pcie_cap && edev->aer_cap) { 1690 eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP, 1691 4, &aer_capctl); 1692 aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 1693 eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP, 1694 4, aer_capctl); 1695 } 1696 1697 return 0; 1698 } 1699 1700 static int pnv_eeh_restore_config(struct pci_dn *pdn) 1701 { 1702 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1703 struct pnv_phb *phb; 1704 s64 ret; 1705 int config_addr = (pdn->busno << 8) | (pdn->devfn); 1706 1707 if (!edev) 1708 return -EEXIST; 1709 1710 /* 1711 * We have to restore the PCI config space after reset since the 1712 * firmware can't see SRIOV VFs. 1713 * 1714 * FIXME: The MPS, error routing rules, timeout setting are worthy 1715 * to be exported by firmware in extendible way. 1716 */ 1717 if (edev->physfn) { 1718 ret = pnv_eeh_restore_vf_config(pdn); 1719 } else { 1720 phb = pdn->phb->private_data; 1721 ret = opal_pci_reinit(phb->opal_id, 1722 OPAL_REINIT_PCI_DEV, config_addr); 1723 } 1724 1725 if (ret) { 1726 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 1727 __func__, config_addr, ret); 1728 return -EIO; 1729 } 1730 1731 return 0; 1732 } 1733 1734 static struct eeh_ops pnv_eeh_ops = { 1735 .name = "powernv", 1736 .init = pnv_eeh_init, 1737 .probe = pnv_eeh_probe, 1738 .set_option = pnv_eeh_set_option, 1739 .get_pe_addr = pnv_eeh_get_pe_addr, 1740 .get_state = pnv_eeh_get_state, 1741 .reset = pnv_eeh_reset, 1742 .wait_state = pnv_eeh_wait_state, 1743 .get_log = pnv_eeh_get_log, 1744 .configure_bridge = pnv_eeh_configure_bridge, 1745 .err_inject = pnv_eeh_err_inject, 1746 .read_config = pnv_eeh_read_config, 1747 .write_config = pnv_eeh_write_config, 1748 .next_error = pnv_eeh_next_error, 1749 .restore_config = pnv_eeh_restore_config 1750 }; 1751 1752 void pcibios_bus_add_device(struct pci_dev *pdev) 1753 { 1754 struct pci_dn *pdn = pci_get_pdn(pdev); 1755 1756 if (!pdev->is_virtfn) 1757 return; 1758 1759 /* 1760 * The following operations will fail if VF's sysfs files 1761 * aren't created or its resources aren't finalized. 1762 */ 1763 eeh_add_device_early(pdn); 1764 eeh_add_device_late(pdev); 1765 eeh_sysfs_add_device(pdev); 1766 } 1767 1768 #ifdef CONFIG_PCI_IOV 1769 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 1770 { 1771 struct pci_dn *pdn = pci_get_pdn(pdev); 1772 int parent_mps; 1773 1774 if (!pdev->is_virtfn) 1775 return; 1776 1777 /* Synchronize MPS for VF and PF */ 1778 parent_mps = pcie_get_mps(pdev->physfn); 1779 if ((128 << pdev->pcie_mpss) >= parent_mps) 1780 pcie_set_mps(pdev, parent_mps); 1781 pdn->mps = pcie_get_mps(pdev); 1782 } 1783 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 1784 #endif /* CONFIG_PCI_IOV */ 1785 1786 /** 1787 * eeh_powernv_init - Register platform dependent EEH operations 1788 * 1789 * EEH initialization on powernv platform. This function should be 1790 * called before any EEH related functions. 1791 */ 1792 static int __init eeh_powernv_init(void) 1793 { 1794 int ret = -EINVAL; 1795 1796 ret = eeh_ops_register(&pnv_eeh_ops); 1797 if (!ret) 1798 pr_info("EEH: PowerNV platform initialized\n"); 1799 else 1800 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 1801 1802 return ret; 1803 } 1804 machine_early_initcall(powernv, eeh_powernv_init); 1805