1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerNV Platform dependent EEH operations 4 * 5 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 6 */ 7 8 #include <linux/atomic.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/list.h> 15 #include <linux/msi.h> 16 #include <linux/of.h> 17 #include <linux/pci.h> 18 #include <linux/proc_fs.h> 19 #include <linux/rbtree.h> 20 #include <linux/sched.h> 21 #include <linux/seq_file.h> 22 #include <linux/spinlock.h> 23 24 #include <asm/eeh.h> 25 #include <asm/eeh_event.h> 26 #include <asm/firmware.h> 27 #include <asm/io.h> 28 #include <asm/iommu.h> 29 #include <asm/machdep.h> 30 #include <asm/msi_bitmap.h> 31 #include <asm/opal.h> 32 #include <asm/ppc-pci.h> 33 #include <asm/pnv-pci.h> 34 35 #include "powernv.h" 36 #include "pci.h" 37 38 static int eeh_event_irq = -EINVAL; 39 40 void pnv_pcibios_bus_add_device(struct pci_dev *pdev) 41 { 42 struct pci_dn *pdn = pci_get_pdn(pdev); 43 44 if (!pdev->is_virtfn) 45 return; 46 47 /* 48 * The following operations will fail if VF's sysfs files 49 * aren't created or its resources aren't finalized. 50 */ 51 eeh_add_device_early(pdn); 52 eeh_add_device_late(pdev); 53 eeh_sysfs_add_device(pdev); 54 } 55 56 static int pnv_eeh_init(void) 57 { 58 struct pci_controller *hose; 59 struct pnv_phb *phb; 60 int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 61 62 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 63 pr_warn("%s: OPAL is required !\n", 64 __func__); 65 return -EINVAL; 66 } 67 68 /* Set probe mode */ 69 eeh_add_flag(EEH_PROBE_MODE_DEV); 70 71 /* 72 * P7IOC blocks PCI config access to frozen PE, but PHB3 73 * doesn't do that. So we have to selectively enable I/O 74 * prior to collecting error log. 75 */ 76 list_for_each_entry(hose, &hose_list, list_node) { 77 phb = hose->private_data; 78 79 if (phb->model == PNV_PHB_MODEL_P7IOC) 80 eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 81 82 if (phb->diag_data_size > max_diag_size) 83 max_diag_size = phb->diag_data_size; 84 85 /* 86 * PE#0 should be regarded as valid by EEH core 87 * if it's not the reserved one. Currently, we 88 * have the reserved PE#255 and PE#127 for PHB3 89 * and P7IOC separately. So we should regard 90 * PE#0 as valid for PHB3 and P7IOC. 91 */ 92 if (phb->ioda.reserved_pe_idx != 0) 93 eeh_add_flag(EEH_VALID_PE_ZERO); 94 95 break; 96 } 97 98 eeh_set_pe_aux_size(max_diag_size); 99 ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device; 100 101 return 0; 102 } 103 104 static irqreturn_t pnv_eeh_event(int irq, void *data) 105 { 106 /* 107 * We simply send a special EEH event if EEH has been 108 * enabled. We don't care about EEH events until we've 109 * finished processing the outstanding ones. Event processing 110 * gets unmasked in next_error() if EEH is enabled. 111 */ 112 disable_irq_nosync(irq); 113 114 if (eeh_enabled()) 115 eeh_send_failure_event(NULL); 116 117 return IRQ_HANDLED; 118 } 119 120 #ifdef CONFIG_DEBUG_FS 121 static ssize_t pnv_eeh_ei_write(struct file *filp, 122 const char __user *user_buf, 123 size_t count, loff_t *ppos) 124 { 125 struct pci_controller *hose = filp->private_data; 126 struct eeh_pe *pe; 127 int pe_no, type, func; 128 unsigned long addr, mask; 129 char buf[50]; 130 int ret; 131 132 if (!eeh_ops || !eeh_ops->err_inject) 133 return -ENXIO; 134 135 /* Copy over argument buffer */ 136 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 137 if (!ret) 138 return -EFAULT; 139 140 /* Retrieve parameters */ 141 ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 142 &pe_no, &type, &func, &addr, &mask); 143 if (ret != 5) 144 return -EINVAL; 145 146 /* Retrieve PE */ 147 pe = eeh_pe_get(hose, pe_no, 0); 148 if (!pe) 149 return -ENODEV; 150 151 /* Do error injection */ 152 ret = eeh_ops->err_inject(pe, type, func, addr, mask); 153 return ret < 0 ? ret : count; 154 } 155 156 static const struct file_operations pnv_eeh_ei_fops = { 157 .open = simple_open, 158 .llseek = no_llseek, 159 .write = pnv_eeh_ei_write, 160 }; 161 162 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 163 { 164 struct pci_controller *hose = data; 165 struct pnv_phb *phb = hose->private_data; 166 167 out_be64(phb->regs + offset, val); 168 return 0; 169 } 170 171 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 172 { 173 struct pci_controller *hose = data; 174 struct pnv_phb *phb = hose->private_data; 175 176 *val = in_be64(phb->regs + offset); 177 return 0; 178 } 179 180 #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 181 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 182 { \ 183 return pnv_eeh_dbgfs_set(data, reg, val); \ 184 } \ 185 \ 186 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 187 { \ 188 return pnv_eeh_dbgfs_get(data, reg, val); \ 189 } \ 190 \ 191 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 192 pnv_eeh_dbgfs_get_##name, \ 193 pnv_eeh_dbgfs_set_##name, \ 194 "0x%llx\n") 195 196 PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 197 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 198 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 199 200 #endif /* CONFIG_DEBUG_FS */ 201 202 /** 203 * pnv_eeh_post_init - EEH platform dependent post initialization 204 * 205 * EEH platform dependent post initialization on powernv. When 206 * the function is called, the EEH PEs and devices should have 207 * been built. If the I/O cache staff has been built, EEH is 208 * ready to supply service. 209 */ 210 int pnv_eeh_post_init(void) 211 { 212 struct pci_controller *hose; 213 struct pnv_phb *phb; 214 int ret = 0; 215 216 /* Probe devices & build address cache */ 217 eeh_probe_devices(); 218 eeh_addr_cache_build(); 219 220 /* Register OPAL event notifier */ 221 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 222 if (eeh_event_irq < 0) { 223 pr_err("%s: Can't register OPAL event interrupt (%d)\n", 224 __func__, eeh_event_irq); 225 return eeh_event_irq; 226 } 227 228 ret = request_irq(eeh_event_irq, pnv_eeh_event, 229 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 230 if (ret < 0) { 231 irq_dispose_mapping(eeh_event_irq); 232 pr_err("%s: Can't request OPAL event interrupt (%d)\n", 233 __func__, eeh_event_irq); 234 return ret; 235 } 236 237 if (!eeh_enabled()) 238 disable_irq(eeh_event_irq); 239 240 list_for_each_entry(hose, &hose_list, list_node) { 241 phb = hose->private_data; 242 243 /* 244 * If EEH is enabled, we're going to rely on that. 245 * Otherwise, we restore to conventional mechanism 246 * to clear frozen PE during PCI config access. 247 */ 248 if (eeh_enabled()) 249 phb->flags |= PNV_PHB_FLAG_EEH; 250 else 251 phb->flags &= ~PNV_PHB_FLAG_EEH; 252 253 /* Create debugfs entries */ 254 #ifdef CONFIG_DEBUG_FS 255 if (phb->has_dbgfs || !phb->dbgfs) 256 continue; 257 258 phb->has_dbgfs = 1; 259 debugfs_create_file("err_injct", 0200, 260 phb->dbgfs, hose, 261 &pnv_eeh_ei_fops); 262 263 debugfs_create_file("err_injct_outbound", 0600, 264 phb->dbgfs, hose, 265 &pnv_eeh_dbgfs_ops_outb); 266 debugfs_create_file("err_injct_inboundA", 0600, 267 phb->dbgfs, hose, 268 &pnv_eeh_dbgfs_ops_inbA); 269 debugfs_create_file("err_injct_inboundB", 0600, 270 phb->dbgfs, hose, 271 &pnv_eeh_dbgfs_ops_inbB); 272 #endif /* CONFIG_DEBUG_FS */ 273 } 274 275 return ret; 276 } 277 278 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 279 { 280 int pos = PCI_CAPABILITY_LIST; 281 int cnt = 48; /* Maximal number of capabilities */ 282 u32 status, id; 283 284 if (!pdn) 285 return 0; 286 287 /* Check if the device supports capabilities */ 288 pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 289 if (!(status & PCI_STATUS_CAP_LIST)) 290 return 0; 291 292 while (cnt--) { 293 pnv_pci_cfg_read(pdn, pos, 1, &pos); 294 if (pos < 0x40) 295 break; 296 297 pos &= ~3; 298 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 299 if (id == 0xff) 300 break; 301 302 /* Found */ 303 if (id == cap) 304 return pos; 305 306 /* Next one */ 307 pos += PCI_CAP_LIST_NEXT; 308 } 309 310 return 0; 311 } 312 313 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 314 { 315 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 316 u32 header; 317 int pos = 256, ttl = (4096 - 256) / 8; 318 319 if (!edev || !edev->pcie_cap) 320 return 0; 321 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 322 return 0; 323 else if (!header) 324 return 0; 325 326 while (ttl-- > 0) { 327 if (PCI_EXT_CAP_ID(header) == cap && pos) 328 return pos; 329 330 pos = PCI_EXT_CAP_NEXT(header); 331 if (pos < 256) 332 break; 333 334 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 335 break; 336 } 337 338 return 0; 339 } 340 341 /** 342 * pnv_eeh_probe - Do probe on PCI device 343 * @pdn: PCI device node 344 * @data: unused 345 * 346 * When EEH module is installed during system boot, all PCI devices 347 * are checked one by one to see if it supports EEH. The function 348 * is introduced for the purpose. By default, EEH has been enabled 349 * on all PCI devices. That's to say, we only need do necessary 350 * initialization on the corresponding eeh device and create PE 351 * accordingly. 352 * 353 * It's notable that's unsafe to retrieve the EEH device through 354 * the corresponding PCI device. During the PCI device hotplug, which 355 * was possiblly triggered by EEH core, the binding between EEH device 356 * and the PCI device isn't built yet. 357 */ 358 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 359 { 360 struct pci_controller *hose = pdn->phb; 361 struct pnv_phb *phb = hose->private_data; 362 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 363 uint32_t pcie_flags; 364 int ret; 365 int config_addr = (pdn->busno << 8) | (pdn->devfn); 366 367 /* 368 * When probing the root bridge, which doesn't have any 369 * subordinate PCI devices. We don't have OF node for 370 * the root bridge. So it's not reasonable to continue 371 * the probing. 372 */ 373 if (!edev || edev->pe) 374 return NULL; 375 376 /* Skip for PCI-ISA bridge */ 377 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 378 return NULL; 379 380 /* Initialize eeh device */ 381 edev->class_code = pdn->class_code; 382 edev->mode &= 0xFFFFFF00; 383 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 384 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 385 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 386 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 387 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 388 edev->mode |= EEH_DEV_BRIDGE; 389 if (edev->pcie_cap) { 390 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 391 2, &pcie_flags); 392 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 393 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 394 edev->mode |= EEH_DEV_ROOT_PORT; 395 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 396 edev->mode |= EEH_DEV_DS_PORT; 397 } 398 } 399 400 edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; 401 402 /* Create PE */ 403 ret = eeh_add_to_parent_pe(edev); 404 if (ret) { 405 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n", 406 __func__, hose->global_number, pdn->busno, 407 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 408 return NULL; 409 } 410 411 /* 412 * If the PE contains any one of following adapters, the 413 * PCI config space can't be accessed when dumping EEH log. 414 * Otherwise, we will run into fenced PHB caused by shortage 415 * of outbound credits in the adapter. The PCI config access 416 * should be blocked until PE reset. MMIO access is dropped 417 * by hardware certainly. In order to drop PCI config requests, 418 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 419 * will be checked in the backend for PE state retrival. If 420 * the PE becomes frozen for the first time and the flag has 421 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 422 * that PE to block its config space. 423 * 424 * Broadcom BCM5718 2-ports NICs (14e4:1656) 425 * Broadcom Austin 4-ports NICs (14e4:1657) 426 * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 427 * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 428 */ 429 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 430 pdn->device_id == 0x1656) || 431 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 432 pdn->device_id == 0x1657) || 433 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 434 pdn->device_id == 0x168a) || 435 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 436 pdn->device_id == 0x168e)) 437 edev->pe->state |= EEH_PE_CFG_RESTRICTED; 438 439 /* 440 * Cache the PE primary bus, which can't be fetched when 441 * full hotplug is in progress. In that case, all child 442 * PCI devices of the PE are expected to be removed prior 443 * to PE reset. 444 */ 445 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 446 edev->pe->bus = pci_find_bus(hose->global_number, 447 pdn->busno); 448 if (edev->pe->bus) 449 edev->pe->state |= EEH_PE_PRI_BUS; 450 } 451 452 /* 453 * Enable EEH explicitly so that we will do EEH check 454 * while accessing I/O stuff 455 */ 456 eeh_add_flag(EEH_ENABLED); 457 458 /* Save memory bars */ 459 eeh_save_bars(edev); 460 461 return NULL; 462 } 463 464 /** 465 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 466 * @pe: EEH PE 467 * @option: operation to be issued 468 * 469 * The function is used to control the EEH functionality globally. 470 * Currently, following options are support according to PAPR: 471 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 472 */ 473 static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 474 { 475 struct pci_controller *hose = pe->phb; 476 struct pnv_phb *phb = hose->private_data; 477 bool freeze_pe = false; 478 int opt; 479 s64 rc; 480 481 switch (option) { 482 case EEH_OPT_DISABLE: 483 return -EPERM; 484 case EEH_OPT_ENABLE: 485 return 0; 486 case EEH_OPT_THAW_MMIO: 487 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 488 break; 489 case EEH_OPT_THAW_DMA: 490 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 491 break; 492 case EEH_OPT_FREEZE_PE: 493 freeze_pe = true; 494 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 495 break; 496 default: 497 pr_warn("%s: Invalid option %d\n", __func__, option); 498 return -EINVAL; 499 } 500 501 /* Freeze master and slave PEs if PHB supports compound PEs */ 502 if (freeze_pe) { 503 if (phb->freeze_pe) { 504 phb->freeze_pe(phb, pe->addr); 505 return 0; 506 } 507 508 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 509 if (rc != OPAL_SUCCESS) { 510 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 511 __func__, rc, phb->hose->global_number, 512 pe->addr); 513 return -EIO; 514 } 515 516 return 0; 517 } 518 519 /* Unfreeze master and slave PEs if PHB supports */ 520 if (phb->unfreeze_pe) 521 return phb->unfreeze_pe(phb, pe->addr, opt); 522 523 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 524 if (rc != OPAL_SUCCESS) { 525 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 526 __func__, rc, option, phb->hose->global_number, 527 pe->addr); 528 return -EIO; 529 } 530 531 return 0; 532 } 533 534 /** 535 * pnv_eeh_get_pe_addr - Retrieve PE address 536 * @pe: EEH PE 537 * 538 * Retrieve the PE address according to the given tranditional 539 * PCI BDF (Bus/Device/Function) address. 540 */ 541 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 542 { 543 return pe->addr; 544 } 545 546 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 547 { 548 struct pnv_phb *phb = pe->phb->private_data; 549 s64 rc; 550 551 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 552 phb->diag_data_size); 553 if (rc != OPAL_SUCCESS) 554 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 555 __func__, rc, pe->phb->global_number); 556 } 557 558 static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 559 { 560 struct pnv_phb *phb = pe->phb->private_data; 561 u8 fstate = 0; 562 __be16 pcierr = 0; 563 s64 rc; 564 int result = 0; 565 566 rc = opal_pci_eeh_freeze_status(phb->opal_id, 567 pe->addr, 568 &fstate, 569 &pcierr, 570 NULL); 571 if (rc != OPAL_SUCCESS) { 572 pr_warn("%s: Failure %lld getting PHB#%x state\n", 573 __func__, rc, phb->hose->global_number); 574 return EEH_STATE_NOT_SUPPORT; 575 } 576 577 /* 578 * Check PHB state. If the PHB is frozen for the 579 * first time, to dump the PHB diag-data. 580 */ 581 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 582 result = (EEH_STATE_MMIO_ACTIVE | 583 EEH_STATE_DMA_ACTIVE | 584 EEH_STATE_MMIO_ENABLED | 585 EEH_STATE_DMA_ENABLED); 586 } else if (!(pe->state & EEH_PE_ISOLATED)) { 587 eeh_pe_mark_isolated(pe); 588 pnv_eeh_get_phb_diag(pe); 589 590 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 591 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 592 } 593 594 return result; 595 } 596 597 static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 598 { 599 struct pnv_phb *phb = pe->phb->private_data; 600 u8 fstate = 0; 601 __be16 pcierr = 0; 602 s64 rc; 603 int result; 604 605 /* 606 * We don't clobber hardware frozen state until PE 607 * reset is completed. In order to keep EEH core 608 * moving forward, we have to return operational 609 * state during PE reset. 610 */ 611 if (pe->state & EEH_PE_RESET) { 612 result = (EEH_STATE_MMIO_ACTIVE | 613 EEH_STATE_DMA_ACTIVE | 614 EEH_STATE_MMIO_ENABLED | 615 EEH_STATE_DMA_ENABLED); 616 return result; 617 } 618 619 /* 620 * Fetch PE state from hardware. If the PHB 621 * supports compound PE, let it handle that. 622 */ 623 if (phb->get_pe_state) { 624 fstate = phb->get_pe_state(phb, pe->addr); 625 } else { 626 rc = opal_pci_eeh_freeze_status(phb->opal_id, 627 pe->addr, 628 &fstate, 629 &pcierr, 630 NULL); 631 if (rc != OPAL_SUCCESS) { 632 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 633 __func__, rc, phb->hose->global_number, 634 pe->addr); 635 return EEH_STATE_NOT_SUPPORT; 636 } 637 } 638 639 /* Figure out state */ 640 switch (fstate) { 641 case OPAL_EEH_STOPPED_NOT_FROZEN: 642 result = (EEH_STATE_MMIO_ACTIVE | 643 EEH_STATE_DMA_ACTIVE | 644 EEH_STATE_MMIO_ENABLED | 645 EEH_STATE_DMA_ENABLED); 646 break; 647 case OPAL_EEH_STOPPED_MMIO_FREEZE: 648 result = (EEH_STATE_DMA_ACTIVE | 649 EEH_STATE_DMA_ENABLED); 650 break; 651 case OPAL_EEH_STOPPED_DMA_FREEZE: 652 result = (EEH_STATE_MMIO_ACTIVE | 653 EEH_STATE_MMIO_ENABLED); 654 break; 655 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 656 result = 0; 657 break; 658 case OPAL_EEH_STOPPED_RESET: 659 result = EEH_STATE_RESET_ACTIVE; 660 break; 661 case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 662 result = EEH_STATE_UNAVAILABLE; 663 break; 664 case OPAL_EEH_STOPPED_PERM_UNAVAIL: 665 result = EEH_STATE_NOT_SUPPORT; 666 break; 667 default: 668 result = EEH_STATE_NOT_SUPPORT; 669 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 670 __func__, phb->hose->global_number, 671 pe->addr, fstate); 672 } 673 674 /* 675 * If PHB supports compound PE, to freeze all 676 * slave PEs for consistency. 677 * 678 * If the PE is switching to frozen state for the 679 * first time, to dump the PHB diag-data. 680 */ 681 if (!(result & EEH_STATE_NOT_SUPPORT) && 682 !(result & EEH_STATE_UNAVAILABLE) && 683 !(result & EEH_STATE_MMIO_ACTIVE) && 684 !(result & EEH_STATE_DMA_ACTIVE) && 685 !(pe->state & EEH_PE_ISOLATED)) { 686 if (phb->freeze_pe) 687 phb->freeze_pe(phb, pe->addr); 688 689 eeh_pe_mark_isolated(pe); 690 pnv_eeh_get_phb_diag(pe); 691 692 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 693 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 694 } 695 696 return result; 697 } 698 699 /** 700 * pnv_eeh_get_state - Retrieve PE state 701 * @pe: EEH PE 702 * @delay: delay while PE state is temporarily unavailable 703 * 704 * Retrieve the state of the specified PE. For IODA-compitable 705 * platform, it should be retrieved from IODA table. Therefore, 706 * we prefer passing down to hardware implementation to handle 707 * it. 708 */ 709 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 710 { 711 int ret; 712 713 if (pe->type & EEH_PE_PHB) 714 ret = pnv_eeh_get_phb_state(pe); 715 else 716 ret = pnv_eeh_get_pe_state(pe); 717 718 if (!delay) 719 return ret; 720 721 /* 722 * If the PE state is temporarily unavailable, 723 * to inform the EEH core delay for default 724 * period (1 second) 725 */ 726 *delay = 0; 727 if (ret & EEH_STATE_UNAVAILABLE) 728 *delay = 1000; 729 730 return ret; 731 } 732 733 static s64 pnv_eeh_poll(unsigned long id) 734 { 735 s64 rc = OPAL_HARDWARE; 736 737 while (1) { 738 rc = opal_pci_poll(id); 739 if (rc <= 0) 740 break; 741 742 if (system_state < SYSTEM_RUNNING) 743 udelay(1000 * rc); 744 else 745 msleep(rc); 746 } 747 748 return rc; 749 } 750 751 int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 752 { 753 struct pnv_phb *phb = hose->private_data; 754 s64 rc = OPAL_HARDWARE; 755 756 pr_debug("%s: Reset PHB#%x, option=%d\n", 757 __func__, hose->global_number, option); 758 759 /* Issue PHB complete reset request */ 760 if (option == EEH_RESET_FUNDAMENTAL || 761 option == EEH_RESET_HOT) 762 rc = opal_pci_reset(phb->opal_id, 763 OPAL_RESET_PHB_COMPLETE, 764 OPAL_ASSERT_RESET); 765 else if (option == EEH_RESET_DEACTIVATE) 766 rc = opal_pci_reset(phb->opal_id, 767 OPAL_RESET_PHB_COMPLETE, 768 OPAL_DEASSERT_RESET); 769 if (rc < 0) 770 goto out; 771 772 /* 773 * Poll state of the PHB until the request is done 774 * successfully. The PHB reset is usually PHB complete 775 * reset followed by hot reset on root bus. So we also 776 * need the PCI bus settlement delay. 777 */ 778 if (rc > 0) 779 rc = pnv_eeh_poll(phb->opal_id); 780 if (option == EEH_RESET_DEACTIVATE) { 781 if (system_state < SYSTEM_RUNNING) 782 udelay(1000 * EEH_PE_RST_SETTLE_TIME); 783 else 784 msleep(EEH_PE_RST_SETTLE_TIME); 785 } 786 out: 787 if (rc != OPAL_SUCCESS) 788 return -EIO; 789 790 return 0; 791 } 792 793 static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 794 { 795 struct pnv_phb *phb = hose->private_data; 796 s64 rc = OPAL_HARDWARE; 797 798 pr_debug("%s: Reset PHB#%x, option=%d\n", 799 __func__, hose->global_number, option); 800 801 /* 802 * During the reset deassert time, we needn't care 803 * the reset scope because the firmware does nothing 804 * for fundamental or hot reset during deassert phase. 805 */ 806 if (option == EEH_RESET_FUNDAMENTAL) 807 rc = opal_pci_reset(phb->opal_id, 808 OPAL_RESET_PCI_FUNDAMENTAL, 809 OPAL_ASSERT_RESET); 810 else if (option == EEH_RESET_HOT) 811 rc = opal_pci_reset(phb->opal_id, 812 OPAL_RESET_PCI_HOT, 813 OPAL_ASSERT_RESET); 814 else if (option == EEH_RESET_DEACTIVATE) 815 rc = opal_pci_reset(phb->opal_id, 816 OPAL_RESET_PCI_HOT, 817 OPAL_DEASSERT_RESET); 818 if (rc < 0) 819 goto out; 820 821 /* Poll state of the PHB until the request is done */ 822 if (rc > 0) 823 rc = pnv_eeh_poll(phb->opal_id); 824 if (option == EEH_RESET_DEACTIVATE) 825 msleep(EEH_PE_RST_SETTLE_TIME); 826 out: 827 if (rc != OPAL_SUCCESS) 828 return -EIO; 829 830 return 0; 831 } 832 833 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 834 { 835 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 836 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 837 int aer = edev ? edev->aer_cap : 0; 838 u32 ctrl; 839 840 pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 841 __func__, pci_domain_nr(dev->bus), 842 dev->bus->number, option); 843 844 switch (option) { 845 case EEH_RESET_FUNDAMENTAL: 846 case EEH_RESET_HOT: 847 /* Don't report linkDown event */ 848 if (aer) { 849 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 850 4, &ctrl); 851 ctrl |= PCI_ERR_UNC_SURPDN; 852 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 853 4, ctrl); 854 } 855 856 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 857 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 858 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 859 860 msleep(EEH_PE_RST_HOLD_TIME); 861 break; 862 case EEH_RESET_DEACTIVATE: 863 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 864 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 865 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 866 867 msleep(EEH_PE_RST_SETTLE_TIME); 868 869 /* Continue reporting linkDown event */ 870 if (aer) { 871 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 872 4, &ctrl); 873 ctrl &= ~PCI_ERR_UNC_SURPDN; 874 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 875 4, ctrl); 876 } 877 878 break; 879 } 880 881 return 0; 882 } 883 884 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 885 { 886 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 887 struct pnv_phb *phb = hose->private_data; 888 struct device_node *dn = pci_device_to_OF_node(pdev); 889 uint64_t id = PCI_SLOT_ID(phb->opal_id, 890 (pdev->bus->number << 8) | pdev->devfn); 891 uint8_t scope; 892 int64_t rc; 893 894 /* Hot reset to the bus if firmware cannot handle */ 895 if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 896 return __pnv_eeh_bridge_reset(pdev, option); 897 898 switch (option) { 899 case EEH_RESET_FUNDAMENTAL: 900 scope = OPAL_RESET_PCI_FUNDAMENTAL; 901 break; 902 case EEH_RESET_HOT: 903 scope = OPAL_RESET_PCI_HOT; 904 break; 905 case EEH_RESET_DEACTIVATE: 906 return 0; 907 default: 908 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 909 __func__, option); 910 return -EINVAL; 911 } 912 913 rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 914 if (rc <= OPAL_SUCCESS) 915 goto out; 916 917 rc = pnv_eeh_poll(id); 918 out: 919 return (rc == OPAL_SUCCESS) ? 0 : -EIO; 920 } 921 922 void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 923 { 924 struct pci_controller *hose; 925 926 if (pci_is_root_bus(dev->bus)) { 927 hose = pci_bus_to_host(dev->bus); 928 pnv_eeh_root_reset(hose, EEH_RESET_HOT); 929 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 930 } else { 931 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 932 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 933 } 934 } 935 936 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 937 int pos, u16 mask) 938 { 939 int i, status = 0; 940 941 /* Wait for Transaction Pending bit to be cleared */ 942 for (i = 0; i < 4; i++) { 943 eeh_ops->read_config(pdn, pos, 2, &status); 944 if (!(status & mask)) 945 return; 946 947 msleep((1 << i) * 100); 948 } 949 950 pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 951 __func__, type, 952 pdn->phb->global_number, pdn->busno, 953 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 954 } 955 956 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 957 { 958 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 959 u32 reg = 0; 960 961 if (WARN_ON(!edev->pcie_cap)) 962 return -ENOTTY; 963 964 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 965 if (!(reg & PCI_EXP_DEVCAP_FLR)) 966 return -ENOTTY; 967 968 switch (option) { 969 case EEH_RESET_HOT: 970 case EEH_RESET_FUNDAMENTAL: 971 pnv_eeh_wait_for_pending(pdn, "", 972 edev->pcie_cap + PCI_EXP_DEVSTA, 973 PCI_EXP_DEVSTA_TRPND); 974 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 975 4, ®); 976 reg |= PCI_EXP_DEVCTL_BCR_FLR; 977 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 978 4, reg); 979 msleep(EEH_PE_RST_HOLD_TIME); 980 break; 981 case EEH_RESET_DEACTIVATE: 982 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 983 4, ®); 984 reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 985 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 986 4, reg); 987 msleep(EEH_PE_RST_SETTLE_TIME); 988 break; 989 } 990 991 return 0; 992 } 993 994 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 995 { 996 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 997 u32 cap = 0; 998 999 if (WARN_ON(!edev->af_cap)) 1000 return -ENOTTY; 1001 1002 eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 1003 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 1004 return -ENOTTY; 1005 1006 switch (option) { 1007 case EEH_RESET_HOT: 1008 case EEH_RESET_FUNDAMENTAL: 1009 /* 1010 * Wait for Transaction Pending bit to clear. A word-aligned 1011 * test is used, so we use the conrol offset rather than status 1012 * and shift the test bit to match. 1013 */ 1014 pnv_eeh_wait_for_pending(pdn, "AF", 1015 edev->af_cap + PCI_AF_CTRL, 1016 PCI_AF_STATUS_TP << 8); 1017 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1018 1, PCI_AF_CTRL_FLR); 1019 msleep(EEH_PE_RST_HOLD_TIME); 1020 break; 1021 case EEH_RESET_DEACTIVATE: 1022 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 1023 msleep(EEH_PE_RST_SETTLE_TIME); 1024 break; 1025 } 1026 1027 return 0; 1028 } 1029 1030 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 1031 { 1032 struct eeh_dev *edev; 1033 struct pci_dn *pdn; 1034 int ret; 1035 1036 /* The VF PE should have only one child device */ 1037 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); 1038 pdn = eeh_dev_to_pdn(edev); 1039 if (!pdn) 1040 return -ENXIO; 1041 1042 ret = pnv_eeh_do_flr(pdn, option); 1043 if (!ret) 1044 return ret; 1045 1046 return pnv_eeh_do_af_flr(pdn, option); 1047 } 1048 1049 /** 1050 * pnv_eeh_reset - Reset the specified PE 1051 * @pe: EEH PE 1052 * @option: reset option 1053 * 1054 * Do reset on the indicated PE. For PCI bus sensitive PE, 1055 * we need to reset the parent p2p bridge. The PHB has to 1056 * be reinitialized if the p2p bridge is root bridge. For 1057 * PCI device sensitive PE, we will try to reset the device 1058 * through FLR. For now, we don't have OPAL APIs to do HARD 1059 * reset yet, so all reset would be SOFT (HOT) reset. 1060 */ 1061 static int pnv_eeh_reset(struct eeh_pe *pe, int option) 1062 { 1063 struct pci_controller *hose = pe->phb; 1064 struct pnv_phb *phb; 1065 struct pci_bus *bus; 1066 int64_t rc; 1067 1068 /* 1069 * For PHB reset, we always have complete reset. For those PEs whose 1070 * primary bus derived from root complex (root bus) or root port 1071 * (usually bus#1), we apply hot or fundamental reset on the root port. 1072 * For other PEs, we always have hot reset on the PE primary bus. 1073 * 1074 * Here, we have different design to pHyp, which always clear the 1075 * frozen state during PE reset. However, the good idea here from 1076 * benh is to keep frozen state before we get PE reset done completely 1077 * (until BAR restore). With the frozen state, HW drops illegal IO 1078 * or MMIO access, which can incur recrusive frozen PE during PE 1079 * reset. The side effect is that EEH core has to clear the frozen 1080 * state explicitly after BAR restore. 1081 */ 1082 if (pe->type & EEH_PE_PHB) 1083 return pnv_eeh_phb_reset(hose, option); 1084 1085 /* 1086 * The frozen PE might be caused by PAPR error injection 1087 * registers, which are expected to be cleared after hitting 1088 * frozen PE as stated in the hardware spec. Unfortunately, 1089 * that's not true on P7IOC. So we have to clear it manually 1090 * to avoid recursive EEH errors during recovery. 1091 */ 1092 phb = hose->private_data; 1093 if (phb->model == PNV_PHB_MODEL_P7IOC && 1094 (option == EEH_RESET_HOT || 1095 option == EEH_RESET_FUNDAMENTAL)) { 1096 rc = opal_pci_reset(phb->opal_id, 1097 OPAL_RESET_PHB_ERROR, 1098 OPAL_ASSERT_RESET); 1099 if (rc != OPAL_SUCCESS) { 1100 pr_warn("%s: Failure %lld clearing error injection registers\n", 1101 __func__, rc); 1102 return -EIO; 1103 } 1104 } 1105 1106 if (pe->type & EEH_PE_VF) 1107 return pnv_eeh_reset_vf_pe(pe, option); 1108 1109 bus = eeh_pe_bus_get(pe); 1110 if (!bus) { 1111 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 1112 __func__, pe->phb->global_number, pe->addr); 1113 return -EIO; 1114 } 1115 1116 /* 1117 * If dealing with the root bus (or the bus underneath the 1118 * root port), we reset the bus underneath the root port. 1119 * 1120 * The cxl driver depends on this behaviour for bi-modal card 1121 * switching. 1122 */ 1123 if (pci_is_root_bus(bus) || 1124 pci_is_root_bus(bus->parent)) 1125 return pnv_eeh_root_reset(hose, option); 1126 1127 return pnv_eeh_bridge_reset(bus->self, option); 1128 } 1129 1130 /** 1131 * pnv_eeh_get_log - Retrieve error log 1132 * @pe: EEH PE 1133 * @severity: temporary or permanent error log 1134 * @drv_log: driver log to be combined with retrieved error log 1135 * @len: length of driver log 1136 * 1137 * Retrieve the temporary or permanent error from the PE. 1138 */ 1139 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 1140 char *drv_log, unsigned long len) 1141 { 1142 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1143 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 1144 1145 return 0; 1146 } 1147 1148 /** 1149 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 1150 * @pe: EEH PE 1151 * 1152 * The function will be called to reconfigure the bridges included 1153 * in the specified PE so that the mulfunctional PE would be recovered 1154 * again. 1155 */ 1156 static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 1157 { 1158 return 0; 1159 } 1160 1161 /** 1162 * pnv_pe_err_inject - Inject specified error to the indicated PE 1163 * @pe: the indicated PE 1164 * @type: error type 1165 * @func: specific error type 1166 * @addr: address 1167 * @mask: address mask 1168 * 1169 * The routine is called to inject specified error, which is 1170 * determined by @type and @func, to the indicated PE for 1171 * testing purpose. 1172 */ 1173 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1174 unsigned long addr, unsigned long mask) 1175 { 1176 struct pci_controller *hose = pe->phb; 1177 struct pnv_phb *phb = hose->private_data; 1178 s64 rc; 1179 1180 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1181 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1182 pr_warn("%s: Invalid error type %d\n", 1183 __func__, type); 1184 return -ERANGE; 1185 } 1186 1187 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1188 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1189 pr_warn("%s: Invalid error function %d\n", 1190 __func__, func); 1191 return -ERANGE; 1192 } 1193 1194 /* Firmware supports error injection ? */ 1195 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1196 pr_warn("%s: Firmware doesn't support error injection\n", 1197 __func__); 1198 return -ENXIO; 1199 } 1200 1201 /* Do error injection */ 1202 rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1203 type, func, addr, mask); 1204 if (rc != OPAL_SUCCESS) { 1205 pr_warn("%s: Failure %lld injecting error " 1206 "%d-%d to PHB#%x-PE#%x\n", 1207 __func__, rc, type, func, 1208 hose->global_number, pe->addr); 1209 return -EIO; 1210 } 1211 1212 return 0; 1213 } 1214 1215 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1216 { 1217 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1218 1219 if (!edev || !edev->pe) 1220 return false; 1221 1222 /* 1223 * We will issue FLR or AF FLR to all VFs, which are contained 1224 * in VF PE. It relies on the EEH PCI config accessors. So we 1225 * can't block them during the window. 1226 */ 1227 if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 1228 return false; 1229 1230 if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1231 return true; 1232 1233 return false; 1234 } 1235 1236 static int pnv_eeh_read_config(struct pci_dn *pdn, 1237 int where, int size, u32 *val) 1238 { 1239 if (!pdn) 1240 return PCIBIOS_DEVICE_NOT_FOUND; 1241 1242 if (pnv_eeh_cfg_blocked(pdn)) { 1243 *val = 0xFFFFFFFF; 1244 return PCIBIOS_SET_FAILED; 1245 } 1246 1247 return pnv_pci_cfg_read(pdn, where, size, val); 1248 } 1249 1250 static int pnv_eeh_write_config(struct pci_dn *pdn, 1251 int where, int size, u32 val) 1252 { 1253 if (!pdn) 1254 return PCIBIOS_DEVICE_NOT_FOUND; 1255 1256 if (pnv_eeh_cfg_blocked(pdn)) 1257 return PCIBIOS_SET_FAILED; 1258 1259 return pnv_pci_cfg_write(pdn, where, size, val); 1260 } 1261 1262 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 1263 { 1264 /* GEM */ 1265 if (data->gemXfir || data->gemRfir || 1266 data->gemRirqfir || data->gemMask || data->gemRwof) 1267 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 1268 be64_to_cpu(data->gemXfir), 1269 be64_to_cpu(data->gemRfir), 1270 be64_to_cpu(data->gemRirqfir), 1271 be64_to_cpu(data->gemMask), 1272 be64_to_cpu(data->gemRwof)); 1273 1274 /* LEM */ 1275 if (data->lemFir || data->lemErrMask || 1276 data->lemAction0 || data->lemAction1 || data->lemWof) 1277 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 1278 be64_to_cpu(data->lemFir), 1279 be64_to_cpu(data->lemErrMask), 1280 be64_to_cpu(data->lemAction0), 1281 be64_to_cpu(data->lemAction1), 1282 be64_to_cpu(data->lemWof)); 1283 } 1284 1285 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 1286 { 1287 struct pnv_phb *phb = hose->private_data; 1288 struct OpalIoP7IOCErrorData *data = 1289 (struct OpalIoP7IOCErrorData*)phb->diag_data; 1290 long rc; 1291 1292 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 1293 if (rc != OPAL_SUCCESS) { 1294 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 1295 __func__, phb->hub_id, rc); 1296 return; 1297 } 1298 1299 switch (be16_to_cpu(data->type)) { 1300 case OPAL_P7IOC_DIAG_TYPE_RGC: 1301 pr_info("P7IOC diag-data for RGC\n\n"); 1302 pnv_eeh_dump_hub_diag_common(data); 1303 if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 1304 pr_info(" RGC: %016llx %016llx\n", 1305 be64_to_cpu(data->rgc.rgcStatus), 1306 be64_to_cpu(data->rgc.rgcLdcp)); 1307 break; 1308 case OPAL_P7IOC_DIAG_TYPE_BI: 1309 pr_info("P7IOC diag-data for BI %s\n\n", 1310 data->bi.biDownbound ? "Downbound" : "Upbound"); 1311 pnv_eeh_dump_hub_diag_common(data); 1312 if (data->bi.biLdcp0 || data->bi.biLdcp1 || 1313 data->bi.biLdcp2 || data->bi.biFenceStatus) 1314 pr_info(" BI: %016llx %016llx %016llx %016llx\n", 1315 be64_to_cpu(data->bi.biLdcp0), 1316 be64_to_cpu(data->bi.biLdcp1), 1317 be64_to_cpu(data->bi.biLdcp2), 1318 be64_to_cpu(data->bi.biFenceStatus)); 1319 break; 1320 case OPAL_P7IOC_DIAG_TYPE_CI: 1321 pr_info("P7IOC diag-data for CI Port %d\n\n", 1322 data->ci.ciPort); 1323 pnv_eeh_dump_hub_diag_common(data); 1324 if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 1325 pr_info(" CI: %016llx %016llx\n", 1326 be64_to_cpu(data->ci.ciPortStatus), 1327 be64_to_cpu(data->ci.ciPortLdcp)); 1328 break; 1329 case OPAL_P7IOC_DIAG_TYPE_MISC: 1330 pr_info("P7IOC diag-data for MISC\n\n"); 1331 pnv_eeh_dump_hub_diag_common(data); 1332 break; 1333 case OPAL_P7IOC_DIAG_TYPE_I2C: 1334 pr_info("P7IOC diag-data for I2C\n\n"); 1335 pnv_eeh_dump_hub_diag_common(data); 1336 break; 1337 default: 1338 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 1339 __func__, phb->hub_id, data->type); 1340 } 1341 } 1342 1343 static int pnv_eeh_get_pe(struct pci_controller *hose, 1344 u16 pe_no, struct eeh_pe **pe) 1345 { 1346 struct pnv_phb *phb = hose->private_data; 1347 struct pnv_ioda_pe *pnv_pe; 1348 struct eeh_pe *dev_pe; 1349 1350 /* 1351 * If PHB supports compound PE, to fetch 1352 * the master PE because slave PE is invisible 1353 * to EEH core. 1354 */ 1355 pnv_pe = &phb->ioda.pe_array[pe_no]; 1356 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 1357 pnv_pe = pnv_pe->master; 1358 WARN_ON(!pnv_pe || 1359 !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 1360 pe_no = pnv_pe->pe_number; 1361 } 1362 1363 /* Find the PE according to PE# */ 1364 dev_pe = eeh_pe_get(hose, pe_no, 0); 1365 if (!dev_pe) 1366 return -EEXIST; 1367 1368 /* Freeze the (compound) PE */ 1369 *pe = dev_pe; 1370 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1371 phb->freeze_pe(phb, pe_no); 1372 1373 /* 1374 * At this point, we're sure the (compound) PE should 1375 * have been frozen. However, we still need poke until 1376 * hitting the frozen PE on top level. 1377 */ 1378 dev_pe = dev_pe->parent; 1379 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 1380 int ret; 1381 ret = eeh_ops->get_state(dev_pe, NULL); 1382 if (ret <= 0 || eeh_state_active(ret)) { 1383 dev_pe = dev_pe->parent; 1384 continue; 1385 } 1386 1387 /* Frozen parent PE */ 1388 *pe = dev_pe; 1389 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1390 phb->freeze_pe(phb, dev_pe->addr); 1391 1392 /* Next one */ 1393 dev_pe = dev_pe->parent; 1394 } 1395 1396 return 0; 1397 } 1398 1399 /** 1400 * pnv_eeh_next_error - Retrieve next EEH error to handle 1401 * @pe: Affected PE 1402 * 1403 * The function is expected to be called by EEH core while it gets 1404 * special EEH event (without binding PE). The function calls to 1405 * OPAL APIs for next error to handle. The informational error is 1406 * handled internally by platform. However, the dead IOC, dead PHB, 1407 * fenced PHB and frozen PE should be handled by EEH core eventually. 1408 */ 1409 static int pnv_eeh_next_error(struct eeh_pe **pe) 1410 { 1411 struct pci_controller *hose; 1412 struct pnv_phb *phb; 1413 struct eeh_pe *phb_pe, *parent_pe; 1414 __be64 frozen_pe_no; 1415 __be16 err_type, severity; 1416 long rc; 1417 int state, ret = EEH_NEXT_ERR_NONE; 1418 1419 /* 1420 * While running here, it's safe to purge the event queue. The 1421 * event should still be masked. 1422 */ 1423 eeh_remove_event(NULL, false); 1424 1425 list_for_each_entry(hose, &hose_list, list_node) { 1426 /* 1427 * If the subordinate PCI buses of the PHB has been 1428 * removed or is exactly under error recovery, we 1429 * needn't take care of it any more. 1430 */ 1431 phb = hose->private_data; 1432 phb_pe = eeh_phb_pe_get(hose); 1433 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 1434 continue; 1435 1436 rc = opal_pci_next_error(phb->opal_id, 1437 &frozen_pe_no, &err_type, &severity); 1438 if (rc != OPAL_SUCCESS) { 1439 pr_devel("%s: Invalid return value on " 1440 "PHB#%x (0x%lx) from opal_pci_next_error", 1441 __func__, hose->global_number, rc); 1442 continue; 1443 } 1444 1445 /* If the PHB doesn't have error, stop processing */ 1446 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 1447 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 1448 pr_devel("%s: No error found on PHB#%x\n", 1449 __func__, hose->global_number); 1450 continue; 1451 } 1452 1453 /* 1454 * Processing the error. We're expecting the error with 1455 * highest priority reported upon multiple errors on the 1456 * specific PHB. 1457 */ 1458 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 1459 __func__, be16_to_cpu(err_type), 1460 be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 1461 hose->global_number); 1462 switch (be16_to_cpu(err_type)) { 1463 case OPAL_EEH_IOC_ERROR: 1464 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 1465 pr_err("EEH: dead IOC detected\n"); 1466 ret = EEH_NEXT_ERR_DEAD_IOC; 1467 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1468 pr_info("EEH: IOC informative error " 1469 "detected\n"); 1470 pnv_eeh_get_and_dump_hub_diag(hose); 1471 ret = EEH_NEXT_ERR_NONE; 1472 } 1473 1474 break; 1475 case OPAL_EEH_PHB_ERROR: 1476 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 1477 *pe = phb_pe; 1478 pr_err("EEH: dead PHB#%x detected, " 1479 "location: %s\n", 1480 hose->global_number, 1481 eeh_pe_loc_get(phb_pe)); 1482 ret = EEH_NEXT_ERR_DEAD_PHB; 1483 } else if (be16_to_cpu(severity) == 1484 OPAL_EEH_SEV_PHB_FENCED) { 1485 *pe = phb_pe; 1486 pr_err("EEH: Fenced PHB#%x detected, " 1487 "location: %s\n", 1488 hose->global_number, 1489 eeh_pe_loc_get(phb_pe)); 1490 ret = EEH_NEXT_ERR_FENCED_PHB; 1491 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1492 pr_info("EEH: PHB#%x informative error " 1493 "detected, location: %s\n", 1494 hose->global_number, 1495 eeh_pe_loc_get(phb_pe)); 1496 pnv_eeh_get_phb_diag(phb_pe); 1497 pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 1498 ret = EEH_NEXT_ERR_NONE; 1499 } 1500 1501 break; 1502 case OPAL_EEH_PE_ERROR: 1503 /* 1504 * If we can't find the corresponding PE, we 1505 * just try to unfreeze. 1506 */ 1507 if (pnv_eeh_get_pe(hose, 1508 be64_to_cpu(frozen_pe_no), pe)) { 1509 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 1510 hose->global_number, be64_to_cpu(frozen_pe_no)); 1511 pr_info("EEH: PHB location: %s\n", 1512 eeh_pe_loc_get(phb_pe)); 1513 1514 /* Dump PHB diag-data */ 1515 rc = opal_pci_get_phb_diag_data2(phb->opal_id, 1516 phb->diag_data, phb->diag_data_size); 1517 if (rc == OPAL_SUCCESS) 1518 pnv_pci_dump_phb_diag_data(hose, 1519 phb->diag_data); 1520 1521 /* Try best to clear it */ 1522 opal_pci_eeh_freeze_clear(phb->opal_id, 1523 be64_to_cpu(frozen_pe_no), 1524 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 1525 ret = EEH_NEXT_ERR_NONE; 1526 } else if ((*pe)->state & EEH_PE_ISOLATED || 1527 eeh_pe_passed(*pe)) { 1528 ret = EEH_NEXT_ERR_NONE; 1529 } else { 1530 pr_err("EEH: Frozen PE#%x " 1531 "on PHB#%x detected\n", 1532 (*pe)->addr, 1533 (*pe)->phb->global_number); 1534 pr_err("EEH: PE location: %s, " 1535 "PHB location: %s\n", 1536 eeh_pe_loc_get(*pe), 1537 eeh_pe_loc_get(phb_pe)); 1538 ret = EEH_NEXT_ERR_FROZEN_PE; 1539 } 1540 1541 break; 1542 default: 1543 pr_warn("%s: Unexpected error type %d\n", 1544 __func__, be16_to_cpu(err_type)); 1545 } 1546 1547 /* 1548 * EEH core will try recover from fenced PHB or 1549 * frozen PE. In the time for frozen PE, EEH core 1550 * enable IO path for that before collecting logs, 1551 * but it ruins the site. So we have to dump the 1552 * log in advance here. 1553 */ 1554 if ((ret == EEH_NEXT_ERR_FROZEN_PE || 1555 ret == EEH_NEXT_ERR_FENCED_PHB) && 1556 !((*pe)->state & EEH_PE_ISOLATED)) { 1557 eeh_pe_mark_isolated(*pe); 1558 pnv_eeh_get_phb_diag(*pe); 1559 1560 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1561 pnv_pci_dump_phb_diag_data((*pe)->phb, 1562 (*pe)->data); 1563 } 1564 1565 /* 1566 * We probably have the frozen parent PE out there and 1567 * we need have to handle frozen parent PE firstly. 1568 */ 1569 if (ret == EEH_NEXT_ERR_FROZEN_PE) { 1570 parent_pe = (*pe)->parent; 1571 while (parent_pe) { 1572 /* Hit the ceiling ? */ 1573 if (parent_pe->type & EEH_PE_PHB) 1574 break; 1575 1576 /* Frozen parent PE ? */ 1577 state = eeh_ops->get_state(parent_pe, NULL); 1578 if (state > 0 && !eeh_state_active(state)) 1579 *pe = parent_pe; 1580 1581 /* Next parent level */ 1582 parent_pe = parent_pe->parent; 1583 } 1584 1585 /* We possibly migrate to another PE */ 1586 eeh_pe_mark_isolated(*pe); 1587 } 1588 1589 /* 1590 * If we have no errors on the specific PHB or only 1591 * informative error there, we continue poking it. 1592 * Otherwise, we need actions to be taken by upper 1593 * layer. 1594 */ 1595 if (ret > EEH_NEXT_ERR_INF) 1596 break; 1597 } 1598 1599 /* Unmask the event */ 1600 if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 1601 enable_irq(eeh_event_irq); 1602 1603 return ret; 1604 } 1605 1606 static int pnv_eeh_restore_config(struct pci_dn *pdn) 1607 { 1608 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1609 struct pnv_phb *phb; 1610 s64 ret = 0; 1611 int config_addr = (pdn->busno << 8) | (pdn->devfn); 1612 1613 if (!edev) 1614 return -EEXIST; 1615 1616 /* 1617 * We have to restore the PCI config space after reset since the 1618 * firmware can't see SRIOV VFs. 1619 * 1620 * FIXME: The MPS, error routing rules, timeout setting are worthy 1621 * to be exported by firmware in extendible way. 1622 */ 1623 if (edev->physfn) { 1624 ret = eeh_restore_vf_config(pdn); 1625 } else { 1626 phb = pdn->phb->private_data; 1627 ret = opal_pci_reinit(phb->opal_id, 1628 OPAL_REINIT_PCI_DEV, config_addr); 1629 } 1630 1631 if (ret) { 1632 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 1633 __func__, config_addr, ret); 1634 return -EIO; 1635 } 1636 1637 return ret; 1638 } 1639 1640 static struct eeh_ops pnv_eeh_ops = { 1641 .name = "powernv", 1642 .init = pnv_eeh_init, 1643 .probe = pnv_eeh_probe, 1644 .set_option = pnv_eeh_set_option, 1645 .get_pe_addr = pnv_eeh_get_pe_addr, 1646 .get_state = pnv_eeh_get_state, 1647 .reset = pnv_eeh_reset, 1648 .get_log = pnv_eeh_get_log, 1649 .configure_bridge = pnv_eeh_configure_bridge, 1650 .err_inject = pnv_eeh_err_inject, 1651 .read_config = pnv_eeh_read_config, 1652 .write_config = pnv_eeh_write_config, 1653 .next_error = pnv_eeh_next_error, 1654 .restore_config = pnv_eeh_restore_config, 1655 .notify_resume = NULL 1656 }; 1657 1658 #ifdef CONFIG_PCI_IOV 1659 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 1660 { 1661 struct pci_dn *pdn = pci_get_pdn(pdev); 1662 int parent_mps; 1663 1664 if (!pdev->is_virtfn) 1665 return; 1666 1667 /* Synchronize MPS for VF and PF */ 1668 parent_mps = pcie_get_mps(pdev->physfn); 1669 if ((128 << pdev->pcie_mpss) >= parent_mps) 1670 pcie_set_mps(pdev, parent_mps); 1671 pdn->mps = pcie_get_mps(pdev); 1672 } 1673 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 1674 #endif /* CONFIG_PCI_IOV */ 1675 1676 /** 1677 * eeh_powernv_init - Register platform dependent EEH operations 1678 * 1679 * EEH initialization on powernv platform. This function should be 1680 * called before any EEH related functions. 1681 */ 1682 static int __init eeh_powernv_init(void) 1683 { 1684 int ret = -EINVAL; 1685 1686 ret = eeh_ops_register(&pnv_eeh_ops); 1687 if (!ret) 1688 pr_info("EEH: PowerNV platform initialized\n"); 1689 else 1690 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 1691 1692 return ret; 1693 } 1694 machine_early_initcall(powernv, eeh_powernv_init); 1695