1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerNV Platform dependent EEH operations 4 * 5 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 6 */ 7 8 #include <linux/atomic.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/list.h> 15 #include <linux/msi.h> 16 #include <linux/of.h> 17 #include <linux/pci.h> 18 #include <linux/proc_fs.h> 19 #include <linux/rbtree.h> 20 #include <linux/sched.h> 21 #include <linux/seq_file.h> 22 #include <linux/spinlock.h> 23 24 #include <asm/eeh.h> 25 #include <asm/eeh_event.h> 26 #include <asm/firmware.h> 27 #include <asm/io.h> 28 #include <asm/iommu.h> 29 #include <asm/machdep.h> 30 #include <asm/msi_bitmap.h> 31 #include <asm/opal.h> 32 #include <asm/ppc-pci.h> 33 #include <asm/pnv-pci.h> 34 35 #include "powernv.h" 36 #include "pci.h" 37 #include "../../../../drivers/pci/pci.h" 38 39 static int eeh_event_irq = -EINVAL; 40 41 void pnv_pcibios_bus_add_device(struct pci_dev *pdev) 42 { 43 struct pci_dn *pdn = pci_get_pdn(pdev); 44 45 if (!pdn || eeh_has_flag(EEH_FORCE_DISABLED)) 46 return; 47 48 dev_dbg(&pdev->dev, "EEH: Setting up device\n"); 49 eeh_add_device_early(pdn); 50 eeh_add_device_late(pdev); 51 eeh_sysfs_add_device(pdev); 52 } 53 54 static int pnv_eeh_init(void) 55 { 56 struct pci_controller *hose; 57 struct pnv_phb *phb; 58 int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 59 60 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 61 pr_warn("%s: OPAL is required !\n", 62 __func__); 63 return -EINVAL; 64 } 65 66 /* Set probe mode */ 67 eeh_add_flag(EEH_PROBE_MODE_DEV); 68 69 /* 70 * P7IOC blocks PCI config access to frozen PE, but PHB3 71 * doesn't do that. So we have to selectively enable I/O 72 * prior to collecting error log. 73 */ 74 list_for_each_entry(hose, &hose_list, list_node) { 75 phb = hose->private_data; 76 77 if (phb->model == PNV_PHB_MODEL_P7IOC) 78 eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 79 80 if (phb->diag_data_size > max_diag_size) 81 max_diag_size = phb->diag_data_size; 82 83 /* 84 * PE#0 should be regarded as valid by EEH core 85 * if it's not the reserved one. Currently, we 86 * have the reserved PE#255 and PE#127 for PHB3 87 * and P7IOC separately. So we should regard 88 * PE#0 as valid for PHB3 and P7IOC. 89 */ 90 if (phb->ioda.reserved_pe_idx != 0) 91 eeh_add_flag(EEH_VALID_PE_ZERO); 92 93 break; 94 } 95 96 eeh_set_pe_aux_size(max_diag_size); 97 ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device; 98 99 return 0; 100 } 101 102 static irqreturn_t pnv_eeh_event(int irq, void *data) 103 { 104 /* 105 * We simply send a special EEH event if EEH has been 106 * enabled. We don't care about EEH events until we've 107 * finished processing the outstanding ones. Event processing 108 * gets unmasked in next_error() if EEH is enabled. 109 */ 110 disable_irq_nosync(irq); 111 112 if (eeh_enabled()) 113 eeh_send_failure_event(NULL); 114 115 return IRQ_HANDLED; 116 } 117 118 #ifdef CONFIG_DEBUG_FS 119 static ssize_t pnv_eeh_ei_write(struct file *filp, 120 const char __user *user_buf, 121 size_t count, loff_t *ppos) 122 { 123 struct pci_controller *hose = filp->private_data; 124 struct eeh_pe *pe; 125 int pe_no, type, func; 126 unsigned long addr, mask; 127 char buf[50]; 128 int ret; 129 130 if (!eeh_ops || !eeh_ops->err_inject) 131 return -ENXIO; 132 133 /* Copy over argument buffer */ 134 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 135 if (!ret) 136 return -EFAULT; 137 138 /* Retrieve parameters */ 139 ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 140 &pe_no, &type, &func, &addr, &mask); 141 if (ret != 5) 142 return -EINVAL; 143 144 /* Retrieve PE */ 145 pe = eeh_pe_get(hose, pe_no, 0); 146 if (!pe) 147 return -ENODEV; 148 149 /* Do error injection */ 150 ret = eeh_ops->err_inject(pe, type, func, addr, mask); 151 return ret < 0 ? ret : count; 152 } 153 154 static const struct file_operations pnv_eeh_ei_fops = { 155 .open = simple_open, 156 .llseek = no_llseek, 157 .write = pnv_eeh_ei_write, 158 }; 159 160 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 161 { 162 struct pci_controller *hose = data; 163 struct pnv_phb *phb = hose->private_data; 164 165 out_be64(phb->regs + offset, val); 166 return 0; 167 } 168 169 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 170 { 171 struct pci_controller *hose = data; 172 struct pnv_phb *phb = hose->private_data; 173 174 *val = in_be64(phb->regs + offset); 175 return 0; 176 } 177 178 #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 179 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 180 { \ 181 return pnv_eeh_dbgfs_set(data, reg, val); \ 182 } \ 183 \ 184 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 185 { \ 186 return pnv_eeh_dbgfs_get(data, reg, val); \ 187 } \ 188 \ 189 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 190 pnv_eeh_dbgfs_get_##name, \ 191 pnv_eeh_dbgfs_set_##name, \ 192 "0x%llx\n") 193 194 PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 195 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 196 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 197 198 #endif /* CONFIG_DEBUG_FS */ 199 200 void pnv_eeh_enable_phbs(void) 201 { 202 struct pci_controller *hose; 203 struct pnv_phb *phb; 204 205 list_for_each_entry(hose, &hose_list, list_node) { 206 phb = hose->private_data; 207 /* 208 * If EEH is enabled, we're going to rely on that. 209 * Otherwise, we restore to conventional mechanism 210 * to clear frozen PE during PCI config access. 211 */ 212 if (eeh_enabled()) 213 phb->flags |= PNV_PHB_FLAG_EEH; 214 else 215 phb->flags &= ~PNV_PHB_FLAG_EEH; 216 } 217 } 218 219 /** 220 * pnv_eeh_post_init - EEH platform dependent post initialization 221 * 222 * EEH platform dependent post initialization on powernv. When 223 * the function is called, the EEH PEs and devices should have 224 * been built. If the I/O cache staff has been built, EEH is 225 * ready to supply service. 226 */ 227 int pnv_eeh_post_init(void) 228 { 229 struct pci_controller *hose; 230 struct pnv_phb *phb; 231 int ret = 0; 232 233 eeh_show_enabled(); 234 235 /* Register OPAL event notifier */ 236 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 237 if (eeh_event_irq < 0) { 238 pr_err("%s: Can't register OPAL event interrupt (%d)\n", 239 __func__, eeh_event_irq); 240 return eeh_event_irq; 241 } 242 243 ret = request_irq(eeh_event_irq, pnv_eeh_event, 244 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 245 if (ret < 0) { 246 irq_dispose_mapping(eeh_event_irq); 247 pr_err("%s: Can't request OPAL event interrupt (%d)\n", 248 __func__, eeh_event_irq); 249 return ret; 250 } 251 252 if (!eeh_enabled()) 253 disable_irq(eeh_event_irq); 254 255 pnv_eeh_enable_phbs(); 256 257 list_for_each_entry(hose, &hose_list, list_node) { 258 phb = hose->private_data; 259 260 /* Create debugfs entries */ 261 #ifdef CONFIG_DEBUG_FS 262 if (phb->has_dbgfs || !phb->dbgfs) 263 continue; 264 265 phb->has_dbgfs = 1; 266 debugfs_create_file("err_injct", 0200, 267 phb->dbgfs, hose, 268 &pnv_eeh_ei_fops); 269 270 debugfs_create_file("err_injct_outbound", 0600, 271 phb->dbgfs, hose, 272 &pnv_eeh_dbgfs_ops_outb); 273 debugfs_create_file("err_injct_inboundA", 0600, 274 phb->dbgfs, hose, 275 &pnv_eeh_dbgfs_ops_inbA); 276 debugfs_create_file("err_injct_inboundB", 0600, 277 phb->dbgfs, hose, 278 &pnv_eeh_dbgfs_ops_inbB); 279 #endif /* CONFIG_DEBUG_FS */ 280 } 281 282 return ret; 283 } 284 285 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 286 { 287 int pos = PCI_CAPABILITY_LIST; 288 int cnt = 48; /* Maximal number of capabilities */ 289 u32 status, id; 290 291 if (!pdn) 292 return 0; 293 294 /* Check if the device supports capabilities */ 295 pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 296 if (!(status & PCI_STATUS_CAP_LIST)) 297 return 0; 298 299 while (cnt--) { 300 pnv_pci_cfg_read(pdn, pos, 1, &pos); 301 if (pos < 0x40) 302 break; 303 304 pos &= ~3; 305 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 306 if (id == 0xff) 307 break; 308 309 /* Found */ 310 if (id == cap) 311 return pos; 312 313 /* Next one */ 314 pos += PCI_CAP_LIST_NEXT; 315 } 316 317 return 0; 318 } 319 320 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 321 { 322 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 323 u32 header; 324 int pos = 256, ttl = (4096 - 256) / 8; 325 326 if (!edev || !edev->pcie_cap) 327 return 0; 328 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 329 return 0; 330 else if (!header) 331 return 0; 332 333 while (ttl-- > 0) { 334 if (PCI_EXT_CAP_ID(header) == cap && pos) 335 return pos; 336 337 pos = PCI_EXT_CAP_NEXT(header); 338 if (pos < 256) 339 break; 340 341 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 342 break; 343 } 344 345 return 0; 346 } 347 348 /** 349 * pnv_eeh_probe - Do probe on PCI device 350 * @pdn: PCI device node 351 * @data: unused 352 * 353 * When EEH module is installed during system boot, all PCI devices 354 * are checked one by one to see if it supports EEH. The function 355 * is introduced for the purpose. By default, EEH has been enabled 356 * on all PCI devices. That's to say, we only need do necessary 357 * initialization on the corresponding eeh device and create PE 358 * accordingly. 359 * 360 * It's notable that's unsafe to retrieve the EEH device through 361 * the corresponding PCI device. During the PCI device hotplug, which 362 * was possiblly triggered by EEH core, the binding between EEH device 363 * and the PCI device isn't built yet. 364 */ 365 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 366 { 367 struct pci_controller *hose = pdn->phb; 368 struct pnv_phb *phb = hose->private_data; 369 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 370 uint32_t pcie_flags; 371 int ret; 372 int config_addr = (pdn->busno << 8) | (pdn->devfn); 373 374 /* 375 * When probing the root bridge, which doesn't have any 376 * subordinate PCI devices. We don't have OF node for 377 * the root bridge. So it's not reasonable to continue 378 * the probing. 379 */ 380 if (!edev || edev->pe) 381 return NULL; 382 383 /* Skip for PCI-ISA bridge */ 384 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 385 return NULL; 386 387 eeh_edev_dbg(edev, "Probing device\n"); 388 389 /* Initialize eeh device */ 390 edev->class_code = pdn->class_code; 391 edev->mode &= 0xFFFFFF00; 392 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 393 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 394 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 395 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 396 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 397 edev->mode |= EEH_DEV_BRIDGE; 398 if (edev->pcie_cap) { 399 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 400 2, &pcie_flags); 401 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 402 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 403 edev->mode |= EEH_DEV_ROOT_PORT; 404 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 405 edev->mode |= EEH_DEV_DS_PORT; 406 } 407 } 408 409 edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; 410 411 /* Create PE */ 412 ret = eeh_add_to_parent_pe(edev); 413 if (ret) { 414 eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n", ret); 415 return NULL; 416 } 417 418 /* 419 * If the PE contains any one of following adapters, the 420 * PCI config space can't be accessed when dumping EEH log. 421 * Otherwise, we will run into fenced PHB caused by shortage 422 * of outbound credits in the adapter. The PCI config access 423 * should be blocked until PE reset. MMIO access is dropped 424 * by hardware certainly. In order to drop PCI config requests, 425 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 426 * will be checked in the backend for PE state retrival. If 427 * the PE becomes frozen for the first time and the flag has 428 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 429 * that PE to block its config space. 430 * 431 * Broadcom BCM5718 2-ports NICs (14e4:1656) 432 * Broadcom Austin 4-ports NICs (14e4:1657) 433 * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 434 * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 435 */ 436 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 437 pdn->device_id == 0x1656) || 438 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 439 pdn->device_id == 0x1657) || 440 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 441 pdn->device_id == 0x168a) || 442 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 443 pdn->device_id == 0x168e)) 444 edev->pe->state |= EEH_PE_CFG_RESTRICTED; 445 446 /* 447 * Cache the PE primary bus, which can't be fetched when 448 * full hotplug is in progress. In that case, all child 449 * PCI devices of the PE are expected to be removed prior 450 * to PE reset. 451 */ 452 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 453 edev->pe->bus = pci_find_bus(hose->global_number, 454 pdn->busno); 455 if (edev->pe->bus) 456 edev->pe->state |= EEH_PE_PRI_BUS; 457 } 458 459 /* 460 * Enable EEH explicitly so that we will do EEH check 461 * while accessing I/O stuff 462 */ 463 if (!eeh_has_flag(EEH_ENABLED)) { 464 enable_irq(eeh_event_irq); 465 pnv_eeh_enable_phbs(); 466 eeh_add_flag(EEH_ENABLED); 467 } 468 469 /* Save memory bars */ 470 eeh_save_bars(edev); 471 472 eeh_edev_dbg(edev, "EEH enabled on device\n"); 473 474 return NULL; 475 } 476 477 /** 478 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 479 * @pe: EEH PE 480 * @option: operation to be issued 481 * 482 * The function is used to control the EEH functionality globally. 483 * Currently, following options are support according to PAPR: 484 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 485 */ 486 static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 487 { 488 struct pci_controller *hose = pe->phb; 489 struct pnv_phb *phb = hose->private_data; 490 bool freeze_pe = false; 491 int opt; 492 s64 rc; 493 494 switch (option) { 495 case EEH_OPT_DISABLE: 496 return -EPERM; 497 case EEH_OPT_ENABLE: 498 return 0; 499 case EEH_OPT_THAW_MMIO: 500 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 501 break; 502 case EEH_OPT_THAW_DMA: 503 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 504 break; 505 case EEH_OPT_FREEZE_PE: 506 freeze_pe = true; 507 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 508 break; 509 default: 510 pr_warn("%s: Invalid option %d\n", __func__, option); 511 return -EINVAL; 512 } 513 514 /* Freeze master and slave PEs if PHB supports compound PEs */ 515 if (freeze_pe) { 516 if (phb->freeze_pe) { 517 phb->freeze_pe(phb, pe->addr); 518 return 0; 519 } 520 521 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 522 if (rc != OPAL_SUCCESS) { 523 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 524 __func__, rc, phb->hose->global_number, 525 pe->addr); 526 return -EIO; 527 } 528 529 return 0; 530 } 531 532 /* Unfreeze master and slave PEs if PHB supports */ 533 if (phb->unfreeze_pe) 534 return phb->unfreeze_pe(phb, pe->addr, opt); 535 536 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 537 if (rc != OPAL_SUCCESS) { 538 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 539 __func__, rc, option, phb->hose->global_number, 540 pe->addr); 541 return -EIO; 542 } 543 544 return 0; 545 } 546 547 /** 548 * pnv_eeh_get_pe_addr - Retrieve PE address 549 * @pe: EEH PE 550 * 551 * Retrieve the PE address according to the given tranditional 552 * PCI BDF (Bus/Device/Function) address. 553 */ 554 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 555 { 556 return pe->addr; 557 } 558 559 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 560 { 561 struct pnv_phb *phb = pe->phb->private_data; 562 s64 rc; 563 564 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 565 phb->diag_data_size); 566 if (rc != OPAL_SUCCESS) 567 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 568 __func__, rc, pe->phb->global_number); 569 } 570 571 static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 572 { 573 struct pnv_phb *phb = pe->phb->private_data; 574 u8 fstate = 0; 575 __be16 pcierr = 0; 576 s64 rc; 577 int result = 0; 578 579 rc = opal_pci_eeh_freeze_status(phb->opal_id, 580 pe->addr, 581 &fstate, 582 &pcierr, 583 NULL); 584 if (rc != OPAL_SUCCESS) { 585 pr_warn("%s: Failure %lld getting PHB#%x state\n", 586 __func__, rc, phb->hose->global_number); 587 return EEH_STATE_NOT_SUPPORT; 588 } 589 590 /* 591 * Check PHB state. If the PHB is frozen for the 592 * first time, to dump the PHB diag-data. 593 */ 594 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 595 result = (EEH_STATE_MMIO_ACTIVE | 596 EEH_STATE_DMA_ACTIVE | 597 EEH_STATE_MMIO_ENABLED | 598 EEH_STATE_DMA_ENABLED); 599 } else if (!(pe->state & EEH_PE_ISOLATED)) { 600 eeh_pe_mark_isolated(pe); 601 pnv_eeh_get_phb_diag(pe); 602 603 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 604 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 605 } 606 607 return result; 608 } 609 610 static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 611 { 612 struct pnv_phb *phb = pe->phb->private_data; 613 u8 fstate = 0; 614 __be16 pcierr = 0; 615 s64 rc; 616 int result; 617 618 /* 619 * We don't clobber hardware frozen state until PE 620 * reset is completed. In order to keep EEH core 621 * moving forward, we have to return operational 622 * state during PE reset. 623 */ 624 if (pe->state & EEH_PE_RESET) { 625 result = (EEH_STATE_MMIO_ACTIVE | 626 EEH_STATE_DMA_ACTIVE | 627 EEH_STATE_MMIO_ENABLED | 628 EEH_STATE_DMA_ENABLED); 629 return result; 630 } 631 632 /* 633 * Fetch PE state from hardware. If the PHB 634 * supports compound PE, let it handle that. 635 */ 636 if (phb->get_pe_state) { 637 fstate = phb->get_pe_state(phb, pe->addr); 638 } else { 639 rc = opal_pci_eeh_freeze_status(phb->opal_id, 640 pe->addr, 641 &fstate, 642 &pcierr, 643 NULL); 644 if (rc != OPAL_SUCCESS) { 645 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 646 __func__, rc, phb->hose->global_number, 647 pe->addr); 648 return EEH_STATE_NOT_SUPPORT; 649 } 650 } 651 652 /* Figure out state */ 653 switch (fstate) { 654 case OPAL_EEH_STOPPED_NOT_FROZEN: 655 result = (EEH_STATE_MMIO_ACTIVE | 656 EEH_STATE_DMA_ACTIVE | 657 EEH_STATE_MMIO_ENABLED | 658 EEH_STATE_DMA_ENABLED); 659 break; 660 case OPAL_EEH_STOPPED_MMIO_FREEZE: 661 result = (EEH_STATE_DMA_ACTIVE | 662 EEH_STATE_DMA_ENABLED); 663 break; 664 case OPAL_EEH_STOPPED_DMA_FREEZE: 665 result = (EEH_STATE_MMIO_ACTIVE | 666 EEH_STATE_MMIO_ENABLED); 667 break; 668 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 669 result = 0; 670 break; 671 case OPAL_EEH_STOPPED_RESET: 672 result = EEH_STATE_RESET_ACTIVE; 673 break; 674 case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 675 result = EEH_STATE_UNAVAILABLE; 676 break; 677 case OPAL_EEH_STOPPED_PERM_UNAVAIL: 678 result = EEH_STATE_NOT_SUPPORT; 679 break; 680 default: 681 result = EEH_STATE_NOT_SUPPORT; 682 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 683 __func__, phb->hose->global_number, 684 pe->addr, fstate); 685 } 686 687 /* 688 * If PHB supports compound PE, to freeze all 689 * slave PEs for consistency. 690 * 691 * If the PE is switching to frozen state for the 692 * first time, to dump the PHB diag-data. 693 */ 694 if (!(result & EEH_STATE_NOT_SUPPORT) && 695 !(result & EEH_STATE_UNAVAILABLE) && 696 !(result & EEH_STATE_MMIO_ACTIVE) && 697 !(result & EEH_STATE_DMA_ACTIVE) && 698 !(pe->state & EEH_PE_ISOLATED)) { 699 if (phb->freeze_pe) 700 phb->freeze_pe(phb, pe->addr); 701 702 eeh_pe_mark_isolated(pe); 703 pnv_eeh_get_phb_diag(pe); 704 705 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 706 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 707 } 708 709 return result; 710 } 711 712 /** 713 * pnv_eeh_get_state - Retrieve PE state 714 * @pe: EEH PE 715 * @delay: delay while PE state is temporarily unavailable 716 * 717 * Retrieve the state of the specified PE. For IODA-compitable 718 * platform, it should be retrieved from IODA table. Therefore, 719 * we prefer passing down to hardware implementation to handle 720 * it. 721 */ 722 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 723 { 724 int ret; 725 726 if (pe->type & EEH_PE_PHB) 727 ret = pnv_eeh_get_phb_state(pe); 728 else 729 ret = pnv_eeh_get_pe_state(pe); 730 731 if (!delay) 732 return ret; 733 734 /* 735 * If the PE state is temporarily unavailable, 736 * to inform the EEH core delay for default 737 * period (1 second) 738 */ 739 *delay = 0; 740 if (ret & EEH_STATE_UNAVAILABLE) 741 *delay = 1000; 742 743 return ret; 744 } 745 746 static s64 pnv_eeh_poll(unsigned long id) 747 { 748 s64 rc = OPAL_HARDWARE; 749 750 while (1) { 751 rc = opal_pci_poll(id); 752 if (rc <= 0) 753 break; 754 755 if (system_state < SYSTEM_RUNNING) 756 udelay(1000 * rc); 757 else 758 msleep(rc); 759 } 760 761 return rc; 762 } 763 764 int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 765 { 766 struct pnv_phb *phb = hose->private_data; 767 s64 rc = OPAL_HARDWARE; 768 769 pr_debug("%s: Reset PHB#%x, option=%d\n", 770 __func__, hose->global_number, option); 771 772 /* Issue PHB complete reset request */ 773 if (option == EEH_RESET_FUNDAMENTAL || 774 option == EEH_RESET_HOT) 775 rc = opal_pci_reset(phb->opal_id, 776 OPAL_RESET_PHB_COMPLETE, 777 OPAL_ASSERT_RESET); 778 else if (option == EEH_RESET_DEACTIVATE) 779 rc = opal_pci_reset(phb->opal_id, 780 OPAL_RESET_PHB_COMPLETE, 781 OPAL_DEASSERT_RESET); 782 if (rc < 0) 783 goto out; 784 785 /* 786 * Poll state of the PHB until the request is done 787 * successfully. The PHB reset is usually PHB complete 788 * reset followed by hot reset on root bus. So we also 789 * need the PCI bus settlement delay. 790 */ 791 if (rc > 0) 792 rc = pnv_eeh_poll(phb->opal_id); 793 if (option == EEH_RESET_DEACTIVATE) { 794 if (system_state < SYSTEM_RUNNING) 795 udelay(1000 * EEH_PE_RST_SETTLE_TIME); 796 else 797 msleep(EEH_PE_RST_SETTLE_TIME); 798 } 799 out: 800 if (rc != OPAL_SUCCESS) 801 return -EIO; 802 803 return 0; 804 } 805 806 static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 807 { 808 struct pnv_phb *phb = hose->private_data; 809 s64 rc = OPAL_HARDWARE; 810 811 pr_debug("%s: Reset PHB#%x, option=%d\n", 812 __func__, hose->global_number, option); 813 814 /* 815 * During the reset deassert time, we needn't care 816 * the reset scope because the firmware does nothing 817 * for fundamental or hot reset during deassert phase. 818 */ 819 if (option == EEH_RESET_FUNDAMENTAL) 820 rc = opal_pci_reset(phb->opal_id, 821 OPAL_RESET_PCI_FUNDAMENTAL, 822 OPAL_ASSERT_RESET); 823 else if (option == EEH_RESET_HOT) 824 rc = opal_pci_reset(phb->opal_id, 825 OPAL_RESET_PCI_HOT, 826 OPAL_ASSERT_RESET); 827 else if (option == EEH_RESET_DEACTIVATE) 828 rc = opal_pci_reset(phb->opal_id, 829 OPAL_RESET_PCI_HOT, 830 OPAL_DEASSERT_RESET); 831 if (rc < 0) 832 goto out; 833 834 /* Poll state of the PHB until the request is done */ 835 if (rc > 0) 836 rc = pnv_eeh_poll(phb->opal_id); 837 if (option == EEH_RESET_DEACTIVATE) 838 msleep(EEH_PE_RST_SETTLE_TIME); 839 out: 840 if (rc != OPAL_SUCCESS) 841 return -EIO; 842 843 return 0; 844 } 845 846 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 847 { 848 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 849 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 850 int aer = edev ? edev->aer_cap : 0; 851 u32 ctrl; 852 853 pr_debug("%s: Secondary Reset PCI bus %04x:%02x with option %d\n", 854 __func__, pci_domain_nr(dev->bus), 855 dev->bus->number, option); 856 857 switch (option) { 858 case EEH_RESET_FUNDAMENTAL: 859 case EEH_RESET_HOT: 860 /* Don't report linkDown event */ 861 if (aer) { 862 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 863 4, &ctrl); 864 ctrl |= PCI_ERR_UNC_SURPDN; 865 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 866 4, ctrl); 867 } 868 869 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 870 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 871 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 872 873 msleep(EEH_PE_RST_HOLD_TIME); 874 break; 875 case EEH_RESET_DEACTIVATE: 876 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 877 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 878 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 879 880 msleep(EEH_PE_RST_SETTLE_TIME); 881 882 /* Continue reporting linkDown event */ 883 if (aer) { 884 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 885 4, &ctrl); 886 ctrl &= ~PCI_ERR_UNC_SURPDN; 887 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 888 4, ctrl); 889 } 890 891 break; 892 } 893 894 return 0; 895 } 896 897 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 898 { 899 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 900 struct pnv_phb *phb = hose->private_data; 901 struct device_node *dn = pci_device_to_OF_node(pdev); 902 uint64_t id = PCI_SLOT_ID(phb->opal_id, 903 (pdev->bus->number << 8) | pdev->devfn); 904 uint8_t scope; 905 int64_t rc; 906 907 /* Hot reset to the bus if firmware cannot handle */ 908 if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 909 return __pnv_eeh_bridge_reset(pdev, option); 910 911 pr_debug("%s: FW reset PCI bus %04x:%02x with option %d\n", 912 __func__, pci_domain_nr(pdev->bus), 913 pdev->bus->number, option); 914 915 switch (option) { 916 case EEH_RESET_FUNDAMENTAL: 917 scope = OPAL_RESET_PCI_FUNDAMENTAL; 918 break; 919 case EEH_RESET_HOT: 920 scope = OPAL_RESET_PCI_HOT; 921 break; 922 case EEH_RESET_DEACTIVATE: 923 return 0; 924 default: 925 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 926 __func__, option); 927 return -EINVAL; 928 } 929 930 rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 931 if (rc <= OPAL_SUCCESS) 932 goto out; 933 934 rc = pnv_eeh_poll(id); 935 out: 936 return (rc == OPAL_SUCCESS) ? 0 : -EIO; 937 } 938 939 void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 940 { 941 struct pci_controller *hose; 942 943 if (pci_is_root_bus(dev->bus)) { 944 hose = pci_bus_to_host(dev->bus); 945 pnv_eeh_root_reset(hose, EEH_RESET_HOT); 946 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 947 } else { 948 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 949 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 950 } 951 } 952 953 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 954 int pos, u16 mask) 955 { 956 int i, status = 0; 957 958 /* Wait for Transaction Pending bit to be cleared */ 959 for (i = 0; i < 4; i++) { 960 eeh_ops->read_config(pdn, pos, 2, &status); 961 if (!(status & mask)) 962 return; 963 964 msleep((1 << i) * 100); 965 } 966 967 pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 968 __func__, type, 969 pdn->phb->global_number, pdn->busno, 970 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 971 } 972 973 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 974 { 975 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 976 u32 reg = 0; 977 978 if (WARN_ON(!edev->pcie_cap)) 979 return -ENOTTY; 980 981 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 982 if (!(reg & PCI_EXP_DEVCAP_FLR)) 983 return -ENOTTY; 984 985 switch (option) { 986 case EEH_RESET_HOT: 987 case EEH_RESET_FUNDAMENTAL: 988 pnv_eeh_wait_for_pending(pdn, "", 989 edev->pcie_cap + PCI_EXP_DEVSTA, 990 PCI_EXP_DEVSTA_TRPND); 991 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 992 4, ®); 993 reg |= PCI_EXP_DEVCTL_BCR_FLR; 994 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 995 4, reg); 996 msleep(EEH_PE_RST_HOLD_TIME); 997 break; 998 case EEH_RESET_DEACTIVATE: 999 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1000 4, ®); 1001 reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 1002 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1003 4, reg); 1004 msleep(EEH_PE_RST_SETTLE_TIME); 1005 break; 1006 } 1007 1008 return 0; 1009 } 1010 1011 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 1012 { 1013 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1014 u32 cap = 0; 1015 1016 if (WARN_ON(!edev->af_cap)) 1017 return -ENOTTY; 1018 1019 eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 1020 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 1021 return -ENOTTY; 1022 1023 switch (option) { 1024 case EEH_RESET_HOT: 1025 case EEH_RESET_FUNDAMENTAL: 1026 /* 1027 * Wait for Transaction Pending bit to clear. A word-aligned 1028 * test is used, so we use the conrol offset rather than status 1029 * and shift the test bit to match. 1030 */ 1031 pnv_eeh_wait_for_pending(pdn, "AF", 1032 edev->af_cap + PCI_AF_CTRL, 1033 PCI_AF_STATUS_TP << 8); 1034 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1035 1, PCI_AF_CTRL_FLR); 1036 msleep(EEH_PE_RST_HOLD_TIME); 1037 break; 1038 case EEH_RESET_DEACTIVATE: 1039 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 1040 msleep(EEH_PE_RST_SETTLE_TIME); 1041 break; 1042 } 1043 1044 return 0; 1045 } 1046 1047 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 1048 { 1049 struct eeh_dev *edev; 1050 struct pci_dn *pdn; 1051 int ret; 1052 1053 /* The VF PE should have only one child device */ 1054 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); 1055 pdn = eeh_dev_to_pdn(edev); 1056 if (!pdn) 1057 return -ENXIO; 1058 1059 ret = pnv_eeh_do_flr(pdn, option); 1060 if (!ret) 1061 return ret; 1062 1063 return pnv_eeh_do_af_flr(pdn, option); 1064 } 1065 1066 /** 1067 * pnv_eeh_reset - Reset the specified PE 1068 * @pe: EEH PE 1069 * @option: reset option 1070 * 1071 * Do reset on the indicated PE. For PCI bus sensitive PE, 1072 * we need to reset the parent p2p bridge. The PHB has to 1073 * be reinitialized if the p2p bridge is root bridge. For 1074 * PCI device sensitive PE, we will try to reset the device 1075 * through FLR. For now, we don't have OPAL APIs to do HARD 1076 * reset yet, so all reset would be SOFT (HOT) reset. 1077 */ 1078 static int pnv_eeh_reset(struct eeh_pe *pe, int option) 1079 { 1080 struct pci_controller *hose = pe->phb; 1081 struct pnv_phb *phb; 1082 struct pci_bus *bus; 1083 int64_t rc; 1084 1085 /* 1086 * For PHB reset, we always have complete reset. For those PEs whose 1087 * primary bus derived from root complex (root bus) or root port 1088 * (usually bus#1), we apply hot or fundamental reset on the root port. 1089 * For other PEs, we always have hot reset on the PE primary bus. 1090 * 1091 * Here, we have different design to pHyp, which always clear the 1092 * frozen state during PE reset. However, the good idea here from 1093 * benh is to keep frozen state before we get PE reset done completely 1094 * (until BAR restore). With the frozen state, HW drops illegal IO 1095 * or MMIO access, which can incur recrusive frozen PE during PE 1096 * reset. The side effect is that EEH core has to clear the frozen 1097 * state explicitly after BAR restore. 1098 */ 1099 if (pe->type & EEH_PE_PHB) 1100 return pnv_eeh_phb_reset(hose, option); 1101 1102 /* 1103 * The frozen PE might be caused by PAPR error injection 1104 * registers, which are expected to be cleared after hitting 1105 * frozen PE as stated in the hardware spec. Unfortunately, 1106 * that's not true on P7IOC. So we have to clear it manually 1107 * to avoid recursive EEH errors during recovery. 1108 */ 1109 phb = hose->private_data; 1110 if (phb->model == PNV_PHB_MODEL_P7IOC && 1111 (option == EEH_RESET_HOT || 1112 option == EEH_RESET_FUNDAMENTAL)) { 1113 rc = opal_pci_reset(phb->opal_id, 1114 OPAL_RESET_PHB_ERROR, 1115 OPAL_ASSERT_RESET); 1116 if (rc != OPAL_SUCCESS) { 1117 pr_warn("%s: Failure %lld clearing error injection registers\n", 1118 __func__, rc); 1119 return -EIO; 1120 } 1121 } 1122 1123 if (pe->type & EEH_PE_VF) 1124 return pnv_eeh_reset_vf_pe(pe, option); 1125 1126 bus = eeh_pe_bus_get(pe); 1127 if (!bus) { 1128 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 1129 __func__, pe->phb->global_number, pe->addr); 1130 return -EIO; 1131 } 1132 1133 if (pci_is_root_bus(bus)) 1134 return pnv_eeh_root_reset(hose, option); 1135 1136 /* 1137 * For hot resets try use the generic PCI error recovery reset 1138 * functions. These correctly handles the case where the secondary 1139 * bus is behind a hotplug slot and it will use the slot provided 1140 * reset methods to prevent spurious hotplug events during the reset. 1141 * 1142 * Fundemental resets need to be handled internally to EEH since the 1143 * PCI core doesn't really have a concept of a fundemental reset, 1144 * mainly because there's no standard way to generate one. Only a 1145 * few devices require an FRESET so it should be fine. 1146 */ 1147 if (option != EEH_RESET_FUNDAMENTAL) { 1148 /* 1149 * NB: Skiboot and pnv_eeh_bridge_reset() also no-op the 1150 * de-assert step. It's like the OPAL reset API was 1151 * poorly designed or something... 1152 */ 1153 if (option == EEH_RESET_DEACTIVATE) 1154 return 0; 1155 1156 rc = pci_bus_error_reset(bus->self); 1157 if (!rc) 1158 return 0; 1159 } 1160 1161 /* otherwise, use the generic bridge reset. this might call into FW */ 1162 if (pci_is_root_bus(bus->parent)) 1163 return pnv_eeh_root_reset(hose, option); 1164 return pnv_eeh_bridge_reset(bus->self, option); 1165 } 1166 1167 /** 1168 * pnv_eeh_get_log - Retrieve error log 1169 * @pe: EEH PE 1170 * @severity: temporary or permanent error log 1171 * @drv_log: driver log to be combined with retrieved error log 1172 * @len: length of driver log 1173 * 1174 * Retrieve the temporary or permanent error from the PE. 1175 */ 1176 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 1177 char *drv_log, unsigned long len) 1178 { 1179 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1180 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 1181 1182 return 0; 1183 } 1184 1185 /** 1186 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 1187 * @pe: EEH PE 1188 * 1189 * The function will be called to reconfigure the bridges included 1190 * in the specified PE so that the mulfunctional PE would be recovered 1191 * again. 1192 */ 1193 static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 1194 { 1195 return 0; 1196 } 1197 1198 /** 1199 * pnv_pe_err_inject - Inject specified error to the indicated PE 1200 * @pe: the indicated PE 1201 * @type: error type 1202 * @func: specific error type 1203 * @addr: address 1204 * @mask: address mask 1205 * 1206 * The routine is called to inject specified error, which is 1207 * determined by @type and @func, to the indicated PE for 1208 * testing purpose. 1209 */ 1210 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1211 unsigned long addr, unsigned long mask) 1212 { 1213 struct pci_controller *hose = pe->phb; 1214 struct pnv_phb *phb = hose->private_data; 1215 s64 rc; 1216 1217 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1218 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1219 pr_warn("%s: Invalid error type %d\n", 1220 __func__, type); 1221 return -ERANGE; 1222 } 1223 1224 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1225 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1226 pr_warn("%s: Invalid error function %d\n", 1227 __func__, func); 1228 return -ERANGE; 1229 } 1230 1231 /* Firmware supports error injection ? */ 1232 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1233 pr_warn("%s: Firmware doesn't support error injection\n", 1234 __func__); 1235 return -ENXIO; 1236 } 1237 1238 /* Do error injection */ 1239 rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1240 type, func, addr, mask); 1241 if (rc != OPAL_SUCCESS) { 1242 pr_warn("%s: Failure %lld injecting error " 1243 "%d-%d to PHB#%x-PE#%x\n", 1244 __func__, rc, type, func, 1245 hose->global_number, pe->addr); 1246 return -EIO; 1247 } 1248 1249 return 0; 1250 } 1251 1252 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1253 { 1254 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1255 1256 if (!edev || !edev->pe) 1257 return false; 1258 1259 /* 1260 * We will issue FLR or AF FLR to all VFs, which are contained 1261 * in VF PE. It relies on the EEH PCI config accessors. So we 1262 * can't block them during the window. 1263 */ 1264 if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 1265 return false; 1266 1267 if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1268 return true; 1269 1270 return false; 1271 } 1272 1273 static int pnv_eeh_read_config(struct pci_dn *pdn, 1274 int where, int size, u32 *val) 1275 { 1276 if (!pdn) 1277 return PCIBIOS_DEVICE_NOT_FOUND; 1278 1279 if (pnv_eeh_cfg_blocked(pdn)) { 1280 *val = 0xFFFFFFFF; 1281 return PCIBIOS_SET_FAILED; 1282 } 1283 1284 return pnv_pci_cfg_read(pdn, where, size, val); 1285 } 1286 1287 static int pnv_eeh_write_config(struct pci_dn *pdn, 1288 int where, int size, u32 val) 1289 { 1290 if (!pdn) 1291 return PCIBIOS_DEVICE_NOT_FOUND; 1292 1293 if (pnv_eeh_cfg_blocked(pdn)) 1294 return PCIBIOS_SET_FAILED; 1295 1296 return pnv_pci_cfg_write(pdn, where, size, val); 1297 } 1298 1299 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 1300 { 1301 /* GEM */ 1302 if (data->gemXfir || data->gemRfir || 1303 data->gemRirqfir || data->gemMask || data->gemRwof) 1304 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 1305 be64_to_cpu(data->gemXfir), 1306 be64_to_cpu(data->gemRfir), 1307 be64_to_cpu(data->gemRirqfir), 1308 be64_to_cpu(data->gemMask), 1309 be64_to_cpu(data->gemRwof)); 1310 1311 /* LEM */ 1312 if (data->lemFir || data->lemErrMask || 1313 data->lemAction0 || data->lemAction1 || data->lemWof) 1314 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 1315 be64_to_cpu(data->lemFir), 1316 be64_to_cpu(data->lemErrMask), 1317 be64_to_cpu(data->lemAction0), 1318 be64_to_cpu(data->lemAction1), 1319 be64_to_cpu(data->lemWof)); 1320 } 1321 1322 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 1323 { 1324 struct pnv_phb *phb = hose->private_data; 1325 struct OpalIoP7IOCErrorData *data = 1326 (struct OpalIoP7IOCErrorData*)phb->diag_data; 1327 long rc; 1328 1329 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 1330 if (rc != OPAL_SUCCESS) { 1331 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 1332 __func__, phb->hub_id, rc); 1333 return; 1334 } 1335 1336 switch (be16_to_cpu(data->type)) { 1337 case OPAL_P7IOC_DIAG_TYPE_RGC: 1338 pr_info("P7IOC diag-data for RGC\n\n"); 1339 pnv_eeh_dump_hub_diag_common(data); 1340 if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 1341 pr_info(" RGC: %016llx %016llx\n", 1342 be64_to_cpu(data->rgc.rgcStatus), 1343 be64_to_cpu(data->rgc.rgcLdcp)); 1344 break; 1345 case OPAL_P7IOC_DIAG_TYPE_BI: 1346 pr_info("P7IOC diag-data for BI %s\n\n", 1347 data->bi.biDownbound ? "Downbound" : "Upbound"); 1348 pnv_eeh_dump_hub_diag_common(data); 1349 if (data->bi.biLdcp0 || data->bi.biLdcp1 || 1350 data->bi.biLdcp2 || data->bi.biFenceStatus) 1351 pr_info(" BI: %016llx %016llx %016llx %016llx\n", 1352 be64_to_cpu(data->bi.biLdcp0), 1353 be64_to_cpu(data->bi.biLdcp1), 1354 be64_to_cpu(data->bi.biLdcp2), 1355 be64_to_cpu(data->bi.biFenceStatus)); 1356 break; 1357 case OPAL_P7IOC_DIAG_TYPE_CI: 1358 pr_info("P7IOC diag-data for CI Port %d\n\n", 1359 data->ci.ciPort); 1360 pnv_eeh_dump_hub_diag_common(data); 1361 if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 1362 pr_info(" CI: %016llx %016llx\n", 1363 be64_to_cpu(data->ci.ciPortStatus), 1364 be64_to_cpu(data->ci.ciPortLdcp)); 1365 break; 1366 case OPAL_P7IOC_DIAG_TYPE_MISC: 1367 pr_info("P7IOC diag-data for MISC\n\n"); 1368 pnv_eeh_dump_hub_diag_common(data); 1369 break; 1370 case OPAL_P7IOC_DIAG_TYPE_I2C: 1371 pr_info("P7IOC diag-data for I2C\n\n"); 1372 pnv_eeh_dump_hub_diag_common(data); 1373 break; 1374 default: 1375 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 1376 __func__, phb->hub_id, data->type); 1377 } 1378 } 1379 1380 static int pnv_eeh_get_pe(struct pci_controller *hose, 1381 u16 pe_no, struct eeh_pe **pe) 1382 { 1383 struct pnv_phb *phb = hose->private_data; 1384 struct pnv_ioda_pe *pnv_pe; 1385 struct eeh_pe *dev_pe; 1386 1387 /* 1388 * If PHB supports compound PE, to fetch 1389 * the master PE because slave PE is invisible 1390 * to EEH core. 1391 */ 1392 pnv_pe = &phb->ioda.pe_array[pe_no]; 1393 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 1394 pnv_pe = pnv_pe->master; 1395 WARN_ON(!pnv_pe || 1396 !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 1397 pe_no = pnv_pe->pe_number; 1398 } 1399 1400 /* Find the PE according to PE# */ 1401 dev_pe = eeh_pe_get(hose, pe_no, 0); 1402 if (!dev_pe) 1403 return -EEXIST; 1404 1405 /* Freeze the (compound) PE */ 1406 *pe = dev_pe; 1407 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1408 phb->freeze_pe(phb, pe_no); 1409 1410 /* 1411 * At this point, we're sure the (compound) PE should 1412 * have been frozen. However, we still need poke until 1413 * hitting the frozen PE on top level. 1414 */ 1415 dev_pe = dev_pe->parent; 1416 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 1417 int ret; 1418 ret = eeh_ops->get_state(dev_pe, NULL); 1419 if (ret <= 0 || eeh_state_active(ret)) { 1420 dev_pe = dev_pe->parent; 1421 continue; 1422 } 1423 1424 /* Frozen parent PE */ 1425 *pe = dev_pe; 1426 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1427 phb->freeze_pe(phb, dev_pe->addr); 1428 1429 /* Next one */ 1430 dev_pe = dev_pe->parent; 1431 } 1432 1433 return 0; 1434 } 1435 1436 /** 1437 * pnv_eeh_next_error - Retrieve next EEH error to handle 1438 * @pe: Affected PE 1439 * 1440 * The function is expected to be called by EEH core while it gets 1441 * special EEH event (without binding PE). The function calls to 1442 * OPAL APIs for next error to handle. The informational error is 1443 * handled internally by platform. However, the dead IOC, dead PHB, 1444 * fenced PHB and frozen PE should be handled by EEH core eventually. 1445 */ 1446 static int pnv_eeh_next_error(struct eeh_pe **pe) 1447 { 1448 struct pci_controller *hose; 1449 struct pnv_phb *phb; 1450 struct eeh_pe *phb_pe, *parent_pe; 1451 __be64 frozen_pe_no; 1452 __be16 err_type, severity; 1453 long rc; 1454 int state, ret = EEH_NEXT_ERR_NONE; 1455 1456 /* 1457 * While running here, it's safe to purge the event queue. The 1458 * event should still be masked. 1459 */ 1460 eeh_remove_event(NULL, false); 1461 1462 list_for_each_entry(hose, &hose_list, list_node) { 1463 /* 1464 * If the subordinate PCI buses of the PHB has been 1465 * removed or is exactly under error recovery, we 1466 * needn't take care of it any more. 1467 */ 1468 phb = hose->private_data; 1469 phb_pe = eeh_phb_pe_get(hose); 1470 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 1471 continue; 1472 1473 rc = opal_pci_next_error(phb->opal_id, 1474 &frozen_pe_no, &err_type, &severity); 1475 if (rc != OPAL_SUCCESS) { 1476 pr_devel("%s: Invalid return value on " 1477 "PHB#%x (0x%lx) from opal_pci_next_error", 1478 __func__, hose->global_number, rc); 1479 continue; 1480 } 1481 1482 /* If the PHB doesn't have error, stop processing */ 1483 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 1484 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 1485 pr_devel("%s: No error found on PHB#%x\n", 1486 __func__, hose->global_number); 1487 continue; 1488 } 1489 1490 /* 1491 * Processing the error. We're expecting the error with 1492 * highest priority reported upon multiple errors on the 1493 * specific PHB. 1494 */ 1495 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 1496 __func__, be16_to_cpu(err_type), 1497 be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 1498 hose->global_number); 1499 switch (be16_to_cpu(err_type)) { 1500 case OPAL_EEH_IOC_ERROR: 1501 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 1502 pr_err("EEH: dead IOC detected\n"); 1503 ret = EEH_NEXT_ERR_DEAD_IOC; 1504 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1505 pr_info("EEH: IOC informative error " 1506 "detected\n"); 1507 pnv_eeh_get_and_dump_hub_diag(hose); 1508 ret = EEH_NEXT_ERR_NONE; 1509 } 1510 1511 break; 1512 case OPAL_EEH_PHB_ERROR: 1513 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 1514 *pe = phb_pe; 1515 pr_err("EEH: dead PHB#%x detected, " 1516 "location: %s\n", 1517 hose->global_number, 1518 eeh_pe_loc_get(phb_pe)); 1519 ret = EEH_NEXT_ERR_DEAD_PHB; 1520 } else if (be16_to_cpu(severity) == 1521 OPAL_EEH_SEV_PHB_FENCED) { 1522 *pe = phb_pe; 1523 pr_err("EEH: Fenced PHB#%x detected, " 1524 "location: %s\n", 1525 hose->global_number, 1526 eeh_pe_loc_get(phb_pe)); 1527 ret = EEH_NEXT_ERR_FENCED_PHB; 1528 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1529 pr_info("EEH: PHB#%x informative error " 1530 "detected, location: %s\n", 1531 hose->global_number, 1532 eeh_pe_loc_get(phb_pe)); 1533 pnv_eeh_get_phb_diag(phb_pe); 1534 pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 1535 ret = EEH_NEXT_ERR_NONE; 1536 } 1537 1538 break; 1539 case OPAL_EEH_PE_ERROR: 1540 /* 1541 * If we can't find the corresponding PE, we 1542 * just try to unfreeze. 1543 */ 1544 if (pnv_eeh_get_pe(hose, 1545 be64_to_cpu(frozen_pe_no), pe)) { 1546 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 1547 hose->global_number, be64_to_cpu(frozen_pe_no)); 1548 pr_info("EEH: PHB location: %s\n", 1549 eeh_pe_loc_get(phb_pe)); 1550 1551 /* Dump PHB diag-data */ 1552 rc = opal_pci_get_phb_diag_data2(phb->opal_id, 1553 phb->diag_data, phb->diag_data_size); 1554 if (rc == OPAL_SUCCESS) 1555 pnv_pci_dump_phb_diag_data(hose, 1556 phb->diag_data); 1557 1558 /* Try best to clear it */ 1559 opal_pci_eeh_freeze_clear(phb->opal_id, 1560 be64_to_cpu(frozen_pe_no), 1561 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 1562 ret = EEH_NEXT_ERR_NONE; 1563 } else if ((*pe)->state & EEH_PE_ISOLATED || 1564 eeh_pe_passed(*pe)) { 1565 ret = EEH_NEXT_ERR_NONE; 1566 } else { 1567 pr_err("EEH: Frozen PE#%x " 1568 "on PHB#%x detected\n", 1569 (*pe)->addr, 1570 (*pe)->phb->global_number); 1571 pr_err("EEH: PE location: %s, " 1572 "PHB location: %s\n", 1573 eeh_pe_loc_get(*pe), 1574 eeh_pe_loc_get(phb_pe)); 1575 ret = EEH_NEXT_ERR_FROZEN_PE; 1576 } 1577 1578 break; 1579 default: 1580 pr_warn("%s: Unexpected error type %d\n", 1581 __func__, be16_to_cpu(err_type)); 1582 } 1583 1584 /* 1585 * EEH core will try recover from fenced PHB or 1586 * frozen PE. In the time for frozen PE, EEH core 1587 * enable IO path for that before collecting logs, 1588 * but it ruins the site. So we have to dump the 1589 * log in advance here. 1590 */ 1591 if ((ret == EEH_NEXT_ERR_FROZEN_PE || 1592 ret == EEH_NEXT_ERR_FENCED_PHB) && 1593 !((*pe)->state & EEH_PE_ISOLATED)) { 1594 eeh_pe_mark_isolated(*pe); 1595 pnv_eeh_get_phb_diag(*pe); 1596 1597 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1598 pnv_pci_dump_phb_diag_data((*pe)->phb, 1599 (*pe)->data); 1600 } 1601 1602 /* 1603 * We probably have the frozen parent PE out there and 1604 * we need have to handle frozen parent PE firstly. 1605 */ 1606 if (ret == EEH_NEXT_ERR_FROZEN_PE) { 1607 parent_pe = (*pe)->parent; 1608 while (parent_pe) { 1609 /* Hit the ceiling ? */ 1610 if (parent_pe->type & EEH_PE_PHB) 1611 break; 1612 1613 /* Frozen parent PE ? */ 1614 state = eeh_ops->get_state(parent_pe, NULL); 1615 if (state > 0 && !eeh_state_active(state)) 1616 *pe = parent_pe; 1617 1618 /* Next parent level */ 1619 parent_pe = parent_pe->parent; 1620 } 1621 1622 /* We possibly migrate to another PE */ 1623 eeh_pe_mark_isolated(*pe); 1624 } 1625 1626 /* 1627 * If we have no errors on the specific PHB or only 1628 * informative error there, we continue poking it. 1629 * Otherwise, we need actions to be taken by upper 1630 * layer. 1631 */ 1632 if (ret > EEH_NEXT_ERR_INF) 1633 break; 1634 } 1635 1636 /* Unmask the event */ 1637 if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 1638 enable_irq(eeh_event_irq); 1639 1640 return ret; 1641 } 1642 1643 static int pnv_eeh_restore_config(struct pci_dn *pdn) 1644 { 1645 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1646 struct pnv_phb *phb; 1647 s64 ret = 0; 1648 int config_addr = (pdn->busno << 8) | (pdn->devfn); 1649 1650 if (!edev) 1651 return -EEXIST; 1652 1653 /* 1654 * We have to restore the PCI config space after reset since the 1655 * firmware can't see SRIOV VFs. 1656 * 1657 * FIXME: The MPS, error routing rules, timeout setting are worthy 1658 * to be exported by firmware in extendible way. 1659 */ 1660 if (edev->physfn) { 1661 ret = eeh_restore_vf_config(pdn); 1662 } else { 1663 phb = pdn->phb->private_data; 1664 ret = opal_pci_reinit(phb->opal_id, 1665 OPAL_REINIT_PCI_DEV, config_addr); 1666 } 1667 1668 if (ret) { 1669 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 1670 __func__, config_addr, ret); 1671 return -EIO; 1672 } 1673 1674 return ret; 1675 } 1676 1677 static struct eeh_ops pnv_eeh_ops = { 1678 .name = "powernv", 1679 .init = pnv_eeh_init, 1680 .probe = pnv_eeh_probe, 1681 .set_option = pnv_eeh_set_option, 1682 .get_pe_addr = pnv_eeh_get_pe_addr, 1683 .get_state = pnv_eeh_get_state, 1684 .reset = pnv_eeh_reset, 1685 .get_log = pnv_eeh_get_log, 1686 .configure_bridge = pnv_eeh_configure_bridge, 1687 .err_inject = pnv_eeh_err_inject, 1688 .read_config = pnv_eeh_read_config, 1689 .write_config = pnv_eeh_write_config, 1690 .next_error = pnv_eeh_next_error, 1691 .restore_config = pnv_eeh_restore_config, 1692 .notify_resume = NULL 1693 }; 1694 1695 #ifdef CONFIG_PCI_IOV 1696 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 1697 { 1698 struct pci_dn *pdn = pci_get_pdn(pdev); 1699 int parent_mps; 1700 1701 if (!pdev->is_virtfn) 1702 return; 1703 1704 /* Synchronize MPS for VF and PF */ 1705 parent_mps = pcie_get_mps(pdev->physfn); 1706 if ((128 << pdev->pcie_mpss) >= parent_mps) 1707 pcie_set_mps(pdev, parent_mps); 1708 pdn->mps = pcie_get_mps(pdev); 1709 } 1710 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 1711 #endif /* CONFIG_PCI_IOV */ 1712 1713 /** 1714 * eeh_powernv_init - Register platform dependent EEH operations 1715 * 1716 * EEH initialization on powernv platform. This function should be 1717 * called before any EEH related functions. 1718 */ 1719 static int __init eeh_powernv_init(void) 1720 { 1721 int ret = -EINVAL; 1722 1723 ret = eeh_ops_register(&pnv_eeh_ops); 1724 if (!ret) 1725 pr_info("EEH: PowerNV platform initialized\n"); 1726 else 1727 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 1728 1729 return ret; 1730 } 1731 machine_early_initcall(powernv, eeh_powernv_init); 1732