1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerNV Platform dependent EEH operations 4 * 5 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 6 */ 7 8 #include <linux/atomic.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/list.h> 15 #include <linux/msi.h> 16 #include <linux/of.h> 17 #include <linux/pci.h> 18 #include <linux/proc_fs.h> 19 #include <linux/rbtree.h> 20 #include <linux/sched.h> 21 #include <linux/seq_file.h> 22 #include <linux/spinlock.h> 23 24 #include <asm/eeh.h> 25 #include <asm/eeh_event.h> 26 #include <asm/firmware.h> 27 #include <asm/io.h> 28 #include <asm/iommu.h> 29 #include <asm/machdep.h> 30 #include <asm/msi_bitmap.h> 31 #include <asm/opal.h> 32 #include <asm/ppc-pci.h> 33 #include <asm/pnv-pci.h> 34 35 #include "powernv.h" 36 #include "pci.h" 37 #include "../../../../drivers/pci/pci.h" 38 39 static int eeh_event_irq = -EINVAL; 40 41 void pnv_pcibios_bus_add_device(struct pci_dev *pdev) 42 { 43 dev_dbg(&pdev->dev, "EEH: Setting up device\n"); 44 eeh_probe_device(pdev); 45 } 46 47 static int pnv_eeh_init(void) 48 { 49 struct pci_controller *hose; 50 struct pnv_phb *phb; 51 int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 52 53 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 54 pr_warn("%s: OPAL is required !\n", 55 __func__); 56 return -EINVAL; 57 } 58 59 /* Set probe mode */ 60 eeh_add_flag(EEH_PROBE_MODE_DEV); 61 62 /* 63 * P7IOC blocks PCI config access to frozen PE, but PHB3 64 * doesn't do that. So we have to selectively enable I/O 65 * prior to collecting error log. 66 */ 67 list_for_each_entry(hose, &hose_list, list_node) { 68 phb = hose->private_data; 69 70 if (phb->model == PNV_PHB_MODEL_P7IOC) 71 eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 72 73 if (phb->diag_data_size > max_diag_size) 74 max_diag_size = phb->diag_data_size; 75 76 /* 77 * PE#0 should be regarded as valid by EEH core 78 * if it's not the reserved one. Currently, we 79 * have the reserved PE#255 and PE#127 for PHB3 80 * and P7IOC separately. So we should regard 81 * PE#0 as valid for PHB3 and P7IOC. 82 */ 83 if (phb->ioda.reserved_pe_idx != 0) 84 eeh_add_flag(EEH_VALID_PE_ZERO); 85 86 break; 87 } 88 89 eeh_set_pe_aux_size(max_diag_size); 90 ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device; 91 92 return 0; 93 } 94 95 static irqreturn_t pnv_eeh_event(int irq, void *data) 96 { 97 /* 98 * We simply send a special EEH event if EEH has been 99 * enabled. We don't care about EEH events until we've 100 * finished processing the outstanding ones. Event processing 101 * gets unmasked in next_error() if EEH is enabled. 102 */ 103 disable_irq_nosync(irq); 104 105 if (eeh_enabled()) 106 eeh_send_failure_event(NULL); 107 108 return IRQ_HANDLED; 109 } 110 111 #ifdef CONFIG_DEBUG_FS 112 static ssize_t pnv_eeh_ei_write(struct file *filp, 113 const char __user *user_buf, 114 size_t count, loff_t *ppos) 115 { 116 struct pci_controller *hose = filp->private_data; 117 struct eeh_pe *pe; 118 int pe_no, type, func; 119 unsigned long addr, mask; 120 char buf[50]; 121 int ret; 122 123 if (!eeh_ops || !eeh_ops->err_inject) 124 return -ENXIO; 125 126 /* Copy over argument buffer */ 127 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 128 if (!ret) 129 return -EFAULT; 130 131 /* Retrieve parameters */ 132 ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 133 &pe_no, &type, &func, &addr, &mask); 134 if (ret != 5) 135 return -EINVAL; 136 137 /* Retrieve PE */ 138 pe = eeh_pe_get(hose, pe_no, 0); 139 if (!pe) 140 return -ENODEV; 141 142 /* Do error injection */ 143 ret = eeh_ops->err_inject(pe, type, func, addr, mask); 144 return ret < 0 ? ret : count; 145 } 146 147 static const struct file_operations pnv_eeh_ei_fops = { 148 .open = simple_open, 149 .llseek = no_llseek, 150 .write = pnv_eeh_ei_write, 151 }; 152 153 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 154 { 155 struct pci_controller *hose = data; 156 struct pnv_phb *phb = hose->private_data; 157 158 out_be64(phb->regs + offset, val); 159 return 0; 160 } 161 162 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 163 { 164 struct pci_controller *hose = data; 165 struct pnv_phb *phb = hose->private_data; 166 167 *val = in_be64(phb->regs + offset); 168 return 0; 169 } 170 171 #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 172 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 173 { \ 174 return pnv_eeh_dbgfs_set(data, reg, val); \ 175 } \ 176 \ 177 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 178 { \ 179 return pnv_eeh_dbgfs_get(data, reg, val); \ 180 } \ 181 \ 182 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 183 pnv_eeh_dbgfs_get_##name, \ 184 pnv_eeh_dbgfs_set_##name, \ 185 "0x%llx\n") 186 187 PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 188 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 189 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 190 191 #endif /* CONFIG_DEBUG_FS */ 192 193 void pnv_eeh_enable_phbs(void) 194 { 195 struct pci_controller *hose; 196 struct pnv_phb *phb; 197 198 list_for_each_entry(hose, &hose_list, list_node) { 199 phb = hose->private_data; 200 /* 201 * If EEH is enabled, we're going to rely on that. 202 * Otherwise, we restore to conventional mechanism 203 * to clear frozen PE during PCI config access. 204 */ 205 if (eeh_enabled()) 206 phb->flags |= PNV_PHB_FLAG_EEH; 207 else 208 phb->flags &= ~PNV_PHB_FLAG_EEH; 209 } 210 } 211 212 /** 213 * pnv_eeh_post_init - EEH platform dependent post initialization 214 * 215 * EEH platform dependent post initialization on powernv. When 216 * the function is called, the EEH PEs and devices should have 217 * been built. If the I/O cache staff has been built, EEH is 218 * ready to supply service. 219 */ 220 int pnv_eeh_post_init(void) 221 { 222 struct pci_controller *hose; 223 struct pnv_phb *phb; 224 int ret = 0; 225 226 eeh_show_enabled(); 227 228 /* Register OPAL event notifier */ 229 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 230 if (eeh_event_irq < 0) { 231 pr_err("%s: Can't register OPAL event interrupt (%d)\n", 232 __func__, eeh_event_irq); 233 return eeh_event_irq; 234 } 235 236 ret = request_irq(eeh_event_irq, pnv_eeh_event, 237 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 238 if (ret < 0) { 239 irq_dispose_mapping(eeh_event_irq); 240 pr_err("%s: Can't request OPAL event interrupt (%d)\n", 241 __func__, eeh_event_irq); 242 return ret; 243 } 244 245 if (!eeh_enabled()) 246 disable_irq(eeh_event_irq); 247 248 pnv_eeh_enable_phbs(); 249 250 list_for_each_entry(hose, &hose_list, list_node) { 251 phb = hose->private_data; 252 253 /* Create debugfs entries */ 254 #ifdef CONFIG_DEBUG_FS 255 if (phb->has_dbgfs || !phb->dbgfs) 256 continue; 257 258 phb->has_dbgfs = 1; 259 debugfs_create_file("err_injct", 0200, 260 phb->dbgfs, hose, 261 &pnv_eeh_ei_fops); 262 263 debugfs_create_file("err_injct_outbound", 0600, 264 phb->dbgfs, hose, 265 &pnv_eeh_dbgfs_ops_outb); 266 debugfs_create_file("err_injct_inboundA", 0600, 267 phb->dbgfs, hose, 268 &pnv_eeh_dbgfs_ops_inbA); 269 debugfs_create_file("err_injct_inboundB", 0600, 270 phb->dbgfs, hose, 271 &pnv_eeh_dbgfs_ops_inbB); 272 #endif /* CONFIG_DEBUG_FS */ 273 } 274 275 return ret; 276 } 277 278 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 279 { 280 int pos = PCI_CAPABILITY_LIST; 281 int cnt = 48; /* Maximal number of capabilities */ 282 u32 status, id; 283 284 if (!pdn) 285 return 0; 286 287 /* Check if the device supports capabilities */ 288 pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 289 if (!(status & PCI_STATUS_CAP_LIST)) 290 return 0; 291 292 while (cnt--) { 293 pnv_pci_cfg_read(pdn, pos, 1, &pos); 294 if (pos < 0x40) 295 break; 296 297 pos &= ~3; 298 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 299 if (id == 0xff) 300 break; 301 302 /* Found */ 303 if (id == cap) 304 return pos; 305 306 /* Next one */ 307 pos += PCI_CAP_LIST_NEXT; 308 } 309 310 return 0; 311 } 312 313 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 314 { 315 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 316 u32 header; 317 int pos = 256, ttl = (4096 - 256) / 8; 318 319 if (!edev || !edev->pcie_cap) 320 return 0; 321 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 322 return 0; 323 else if (!header) 324 return 0; 325 326 while (ttl-- > 0) { 327 if (PCI_EXT_CAP_ID(header) == cap && pos) 328 return pos; 329 330 pos = PCI_EXT_CAP_NEXT(header); 331 if (pos < 256) 332 break; 333 334 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 335 break; 336 } 337 338 return 0; 339 } 340 341 /** 342 * pnv_eeh_probe - Do probe on PCI device 343 * @pdev: pci_dev to probe 344 * 345 * Create, or find the existing, eeh_dev for this pci_dev. 346 */ 347 static struct eeh_dev *pnv_eeh_probe(struct pci_dev *pdev) 348 { 349 struct pci_dn *pdn = pci_get_pdn(pdev); 350 struct pci_controller *hose = pdn->phb; 351 struct pnv_phb *phb = hose->private_data; 352 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 353 uint32_t pcie_flags; 354 int ret; 355 int config_addr = (pdn->busno << 8) | (pdn->devfn); 356 357 /* 358 * When probing the root bridge, which doesn't have any 359 * subordinate PCI devices. We don't have OF node for 360 * the root bridge. So it's not reasonable to continue 361 * the probing. 362 */ 363 if (!edev || edev->pe) 364 return NULL; 365 366 /* already configured? */ 367 if (edev->pdev) { 368 pr_debug("%s: found existing edev for %04x:%02x:%02x.%01x\n", 369 __func__, hose->global_number, config_addr >> 8, 370 PCI_SLOT(config_addr), PCI_FUNC(config_addr)); 371 return edev; 372 } 373 374 /* Skip for PCI-ISA bridge */ 375 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 376 return NULL; 377 378 eeh_edev_dbg(edev, "Probing device\n"); 379 380 /* Initialize eeh device */ 381 edev->class_code = pdn->class_code; 382 edev->mode &= 0xFFFFFF00; 383 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 384 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 385 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 386 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 387 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 388 edev->mode |= EEH_DEV_BRIDGE; 389 if (edev->pcie_cap) { 390 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 391 2, &pcie_flags); 392 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 393 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 394 edev->mode |= EEH_DEV_ROOT_PORT; 395 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 396 edev->mode |= EEH_DEV_DS_PORT; 397 } 398 } 399 400 edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; 401 402 /* Create PE */ 403 ret = eeh_add_to_parent_pe(edev); 404 if (ret) { 405 eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n", ret); 406 return NULL; 407 } 408 409 /* 410 * If the PE contains any one of following adapters, the 411 * PCI config space can't be accessed when dumping EEH log. 412 * Otherwise, we will run into fenced PHB caused by shortage 413 * of outbound credits in the adapter. The PCI config access 414 * should be blocked until PE reset. MMIO access is dropped 415 * by hardware certainly. In order to drop PCI config requests, 416 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 417 * will be checked in the backend for PE state retrival. If 418 * the PE becomes frozen for the first time and the flag has 419 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 420 * that PE to block its config space. 421 * 422 * Broadcom BCM5718 2-ports NICs (14e4:1656) 423 * Broadcom Austin 4-ports NICs (14e4:1657) 424 * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 425 * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 426 */ 427 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 428 pdn->device_id == 0x1656) || 429 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 430 pdn->device_id == 0x1657) || 431 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 432 pdn->device_id == 0x168a) || 433 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 434 pdn->device_id == 0x168e)) 435 edev->pe->state |= EEH_PE_CFG_RESTRICTED; 436 437 /* 438 * Cache the PE primary bus, which can't be fetched when 439 * full hotplug is in progress. In that case, all child 440 * PCI devices of the PE are expected to be removed prior 441 * to PE reset. 442 */ 443 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 444 edev->pe->bus = pci_find_bus(hose->global_number, 445 pdn->busno); 446 if (edev->pe->bus) 447 edev->pe->state |= EEH_PE_PRI_BUS; 448 } 449 450 /* 451 * Enable EEH explicitly so that we will do EEH check 452 * while accessing I/O stuff 453 */ 454 if (!eeh_has_flag(EEH_ENABLED)) { 455 enable_irq(eeh_event_irq); 456 pnv_eeh_enable_phbs(); 457 eeh_add_flag(EEH_ENABLED); 458 } 459 460 /* Save memory bars */ 461 eeh_save_bars(edev); 462 463 eeh_edev_dbg(edev, "EEH enabled on device\n"); 464 465 return edev; 466 } 467 468 /** 469 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 470 * @pe: EEH PE 471 * @option: operation to be issued 472 * 473 * The function is used to control the EEH functionality globally. 474 * Currently, following options are support according to PAPR: 475 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 476 */ 477 static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 478 { 479 struct pci_controller *hose = pe->phb; 480 struct pnv_phb *phb = hose->private_data; 481 bool freeze_pe = false; 482 int opt; 483 s64 rc; 484 485 switch (option) { 486 case EEH_OPT_DISABLE: 487 return -EPERM; 488 case EEH_OPT_ENABLE: 489 return 0; 490 case EEH_OPT_THAW_MMIO: 491 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 492 break; 493 case EEH_OPT_THAW_DMA: 494 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 495 break; 496 case EEH_OPT_FREEZE_PE: 497 freeze_pe = true; 498 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 499 break; 500 default: 501 pr_warn("%s: Invalid option %d\n", __func__, option); 502 return -EINVAL; 503 } 504 505 /* Freeze master and slave PEs if PHB supports compound PEs */ 506 if (freeze_pe) { 507 if (phb->freeze_pe) { 508 phb->freeze_pe(phb, pe->addr); 509 return 0; 510 } 511 512 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 513 if (rc != OPAL_SUCCESS) { 514 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 515 __func__, rc, phb->hose->global_number, 516 pe->addr); 517 return -EIO; 518 } 519 520 return 0; 521 } 522 523 /* Unfreeze master and slave PEs if PHB supports */ 524 if (phb->unfreeze_pe) 525 return phb->unfreeze_pe(phb, pe->addr, opt); 526 527 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 528 if (rc != OPAL_SUCCESS) { 529 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 530 __func__, rc, option, phb->hose->global_number, 531 pe->addr); 532 return -EIO; 533 } 534 535 return 0; 536 } 537 538 /** 539 * pnv_eeh_get_pe_addr - Retrieve PE address 540 * @pe: EEH PE 541 * 542 * Retrieve the PE address according to the given tranditional 543 * PCI BDF (Bus/Device/Function) address. 544 */ 545 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 546 { 547 return pe->addr; 548 } 549 550 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 551 { 552 struct pnv_phb *phb = pe->phb->private_data; 553 s64 rc; 554 555 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 556 phb->diag_data_size); 557 if (rc != OPAL_SUCCESS) 558 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 559 __func__, rc, pe->phb->global_number); 560 } 561 562 static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 563 { 564 struct pnv_phb *phb = pe->phb->private_data; 565 u8 fstate = 0; 566 __be16 pcierr = 0; 567 s64 rc; 568 int result = 0; 569 570 rc = opal_pci_eeh_freeze_status(phb->opal_id, 571 pe->addr, 572 &fstate, 573 &pcierr, 574 NULL); 575 if (rc != OPAL_SUCCESS) { 576 pr_warn("%s: Failure %lld getting PHB#%x state\n", 577 __func__, rc, phb->hose->global_number); 578 return EEH_STATE_NOT_SUPPORT; 579 } 580 581 /* 582 * Check PHB state. If the PHB is frozen for the 583 * first time, to dump the PHB diag-data. 584 */ 585 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 586 result = (EEH_STATE_MMIO_ACTIVE | 587 EEH_STATE_DMA_ACTIVE | 588 EEH_STATE_MMIO_ENABLED | 589 EEH_STATE_DMA_ENABLED); 590 } else if (!(pe->state & EEH_PE_ISOLATED)) { 591 eeh_pe_mark_isolated(pe); 592 pnv_eeh_get_phb_diag(pe); 593 594 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 595 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 596 } 597 598 return result; 599 } 600 601 static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 602 { 603 struct pnv_phb *phb = pe->phb->private_data; 604 u8 fstate = 0; 605 __be16 pcierr = 0; 606 s64 rc; 607 int result; 608 609 /* 610 * We don't clobber hardware frozen state until PE 611 * reset is completed. In order to keep EEH core 612 * moving forward, we have to return operational 613 * state during PE reset. 614 */ 615 if (pe->state & EEH_PE_RESET) { 616 result = (EEH_STATE_MMIO_ACTIVE | 617 EEH_STATE_DMA_ACTIVE | 618 EEH_STATE_MMIO_ENABLED | 619 EEH_STATE_DMA_ENABLED); 620 return result; 621 } 622 623 /* 624 * Fetch PE state from hardware. If the PHB 625 * supports compound PE, let it handle that. 626 */ 627 if (phb->get_pe_state) { 628 fstate = phb->get_pe_state(phb, pe->addr); 629 } else { 630 rc = opal_pci_eeh_freeze_status(phb->opal_id, 631 pe->addr, 632 &fstate, 633 &pcierr, 634 NULL); 635 if (rc != OPAL_SUCCESS) { 636 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 637 __func__, rc, phb->hose->global_number, 638 pe->addr); 639 return EEH_STATE_NOT_SUPPORT; 640 } 641 } 642 643 /* Figure out state */ 644 switch (fstate) { 645 case OPAL_EEH_STOPPED_NOT_FROZEN: 646 result = (EEH_STATE_MMIO_ACTIVE | 647 EEH_STATE_DMA_ACTIVE | 648 EEH_STATE_MMIO_ENABLED | 649 EEH_STATE_DMA_ENABLED); 650 break; 651 case OPAL_EEH_STOPPED_MMIO_FREEZE: 652 result = (EEH_STATE_DMA_ACTIVE | 653 EEH_STATE_DMA_ENABLED); 654 break; 655 case OPAL_EEH_STOPPED_DMA_FREEZE: 656 result = (EEH_STATE_MMIO_ACTIVE | 657 EEH_STATE_MMIO_ENABLED); 658 break; 659 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 660 result = 0; 661 break; 662 case OPAL_EEH_STOPPED_RESET: 663 result = EEH_STATE_RESET_ACTIVE; 664 break; 665 case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 666 result = EEH_STATE_UNAVAILABLE; 667 break; 668 case OPAL_EEH_STOPPED_PERM_UNAVAIL: 669 result = EEH_STATE_NOT_SUPPORT; 670 break; 671 default: 672 result = EEH_STATE_NOT_SUPPORT; 673 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 674 __func__, phb->hose->global_number, 675 pe->addr, fstate); 676 } 677 678 /* 679 * If PHB supports compound PE, to freeze all 680 * slave PEs for consistency. 681 * 682 * If the PE is switching to frozen state for the 683 * first time, to dump the PHB diag-data. 684 */ 685 if (!(result & EEH_STATE_NOT_SUPPORT) && 686 !(result & EEH_STATE_UNAVAILABLE) && 687 !(result & EEH_STATE_MMIO_ACTIVE) && 688 !(result & EEH_STATE_DMA_ACTIVE) && 689 !(pe->state & EEH_PE_ISOLATED)) { 690 if (phb->freeze_pe) 691 phb->freeze_pe(phb, pe->addr); 692 693 eeh_pe_mark_isolated(pe); 694 pnv_eeh_get_phb_diag(pe); 695 696 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 697 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 698 } 699 700 return result; 701 } 702 703 /** 704 * pnv_eeh_get_state - Retrieve PE state 705 * @pe: EEH PE 706 * @delay: delay while PE state is temporarily unavailable 707 * 708 * Retrieve the state of the specified PE. For IODA-compitable 709 * platform, it should be retrieved from IODA table. Therefore, 710 * we prefer passing down to hardware implementation to handle 711 * it. 712 */ 713 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 714 { 715 int ret; 716 717 if (pe->type & EEH_PE_PHB) 718 ret = pnv_eeh_get_phb_state(pe); 719 else 720 ret = pnv_eeh_get_pe_state(pe); 721 722 if (!delay) 723 return ret; 724 725 /* 726 * If the PE state is temporarily unavailable, 727 * to inform the EEH core delay for default 728 * period (1 second) 729 */ 730 *delay = 0; 731 if (ret & EEH_STATE_UNAVAILABLE) 732 *delay = 1000; 733 734 return ret; 735 } 736 737 static s64 pnv_eeh_poll(unsigned long id) 738 { 739 s64 rc = OPAL_HARDWARE; 740 741 while (1) { 742 rc = opal_pci_poll(id); 743 if (rc <= 0) 744 break; 745 746 if (system_state < SYSTEM_RUNNING) 747 udelay(1000 * rc); 748 else 749 msleep(rc); 750 } 751 752 return rc; 753 } 754 755 int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 756 { 757 struct pnv_phb *phb = hose->private_data; 758 s64 rc = OPAL_HARDWARE; 759 760 pr_debug("%s: Reset PHB#%x, option=%d\n", 761 __func__, hose->global_number, option); 762 763 /* Issue PHB complete reset request */ 764 if (option == EEH_RESET_FUNDAMENTAL || 765 option == EEH_RESET_HOT) 766 rc = opal_pci_reset(phb->opal_id, 767 OPAL_RESET_PHB_COMPLETE, 768 OPAL_ASSERT_RESET); 769 else if (option == EEH_RESET_DEACTIVATE) 770 rc = opal_pci_reset(phb->opal_id, 771 OPAL_RESET_PHB_COMPLETE, 772 OPAL_DEASSERT_RESET); 773 if (rc < 0) 774 goto out; 775 776 /* 777 * Poll state of the PHB until the request is done 778 * successfully. The PHB reset is usually PHB complete 779 * reset followed by hot reset on root bus. So we also 780 * need the PCI bus settlement delay. 781 */ 782 if (rc > 0) 783 rc = pnv_eeh_poll(phb->opal_id); 784 if (option == EEH_RESET_DEACTIVATE) { 785 if (system_state < SYSTEM_RUNNING) 786 udelay(1000 * EEH_PE_RST_SETTLE_TIME); 787 else 788 msleep(EEH_PE_RST_SETTLE_TIME); 789 } 790 out: 791 if (rc != OPAL_SUCCESS) 792 return -EIO; 793 794 return 0; 795 } 796 797 static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 798 { 799 struct pnv_phb *phb = hose->private_data; 800 s64 rc = OPAL_HARDWARE; 801 802 pr_debug("%s: Reset PHB#%x, option=%d\n", 803 __func__, hose->global_number, option); 804 805 /* 806 * During the reset deassert time, we needn't care 807 * the reset scope because the firmware does nothing 808 * for fundamental or hot reset during deassert phase. 809 */ 810 if (option == EEH_RESET_FUNDAMENTAL) 811 rc = opal_pci_reset(phb->opal_id, 812 OPAL_RESET_PCI_FUNDAMENTAL, 813 OPAL_ASSERT_RESET); 814 else if (option == EEH_RESET_HOT) 815 rc = opal_pci_reset(phb->opal_id, 816 OPAL_RESET_PCI_HOT, 817 OPAL_ASSERT_RESET); 818 else if (option == EEH_RESET_DEACTIVATE) 819 rc = opal_pci_reset(phb->opal_id, 820 OPAL_RESET_PCI_HOT, 821 OPAL_DEASSERT_RESET); 822 if (rc < 0) 823 goto out; 824 825 /* Poll state of the PHB until the request is done */ 826 if (rc > 0) 827 rc = pnv_eeh_poll(phb->opal_id); 828 if (option == EEH_RESET_DEACTIVATE) 829 msleep(EEH_PE_RST_SETTLE_TIME); 830 out: 831 if (rc != OPAL_SUCCESS) 832 return -EIO; 833 834 return 0; 835 } 836 837 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 838 { 839 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 840 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 841 int aer = edev ? edev->aer_cap : 0; 842 u32 ctrl; 843 844 pr_debug("%s: Secondary Reset PCI bus %04x:%02x with option %d\n", 845 __func__, pci_domain_nr(dev->bus), 846 dev->bus->number, option); 847 848 switch (option) { 849 case EEH_RESET_FUNDAMENTAL: 850 case EEH_RESET_HOT: 851 /* Don't report linkDown event */ 852 if (aer) { 853 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 854 4, &ctrl); 855 ctrl |= PCI_ERR_UNC_SURPDN; 856 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 857 4, ctrl); 858 } 859 860 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 861 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 862 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 863 864 msleep(EEH_PE_RST_HOLD_TIME); 865 break; 866 case EEH_RESET_DEACTIVATE: 867 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 868 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 869 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 870 871 msleep(EEH_PE_RST_SETTLE_TIME); 872 873 /* Continue reporting linkDown event */ 874 if (aer) { 875 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 876 4, &ctrl); 877 ctrl &= ~PCI_ERR_UNC_SURPDN; 878 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 879 4, ctrl); 880 } 881 882 break; 883 } 884 885 return 0; 886 } 887 888 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 889 { 890 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 891 struct pnv_phb *phb = hose->private_data; 892 struct device_node *dn = pci_device_to_OF_node(pdev); 893 uint64_t id = PCI_SLOT_ID(phb->opal_id, 894 (pdev->bus->number << 8) | pdev->devfn); 895 uint8_t scope; 896 int64_t rc; 897 898 /* Hot reset to the bus if firmware cannot handle */ 899 if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 900 return __pnv_eeh_bridge_reset(pdev, option); 901 902 pr_debug("%s: FW reset PCI bus %04x:%02x with option %d\n", 903 __func__, pci_domain_nr(pdev->bus), 904 pdev->bus->number, option); 905 906 switch (option) { 907 case EEH_RESET_FUNDAMENTAL: 908 scope = OPAL_RESET_PCI_FUNDAMENTAL; 909 break; 910 case EEH_RESET_HOT: 911 scope = OPAL_RESET_PCI_HOT; 912 break; 913 case EEH_RESET_DEACTIVATE: 914 return 0; 915 default: 916 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 917 __func__, option); 918 return -EINVAL; 919 } 920 921 rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 922 if (rc <= OPAL_SUCCESS) 923 goto out; 924 925 rc = pnv_eeh_poll(id); 926 out: 927 return (rc == OPAL_SUCCESS) ? 0 : -EIO; 928 } 929 930 void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 931 { 932 struct pci_controller *hose; 933 934 if (pci_is_root_bus(dev->bus)) { 935 hose = pci_bus_to_host(dev->bus); 936 pnv_eeh_root_reset(hose, EEH_RESET_HOT); 937 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 938 } else { 939 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 940 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 941 } 942 } 943 944 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 945 int pos, u16 mask) 946 { 947 int i, status = 0; 948 949 /* Wait for Transaction Pending bit to be cleared */ 950 for (i = 0; i < 4; i++) { 951 eeh_ops->read_config(pdn, pos, 2, &status); 952 if (!(status & mask)) 953 return; 954 955 msleep((1 << i) * 100); 956 } 957 958 pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 959 __func__, type, 960 pdn->phb->global_number, pdn->busno, 961 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 962 } 963 964 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 965 { 966 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 967 u32 reg = 0; 968 969 if (WARN_ON(!edev->pcie_cap)) 970 return -ENOTTY; 971 972 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 973 if (!(reg & PCI_EXP_DEVCAP_FLR)) 974 return -ENOTTY; 975 976 switch (option) { 977 case EEH_RESET_HOT: 978 case EEH_RESET_FUNDAMENTAL: 979 pnv_eeh_wait_for_pending(pdn, "", 980 edev->pcie_cap + PCI_EXP_DEVSTA, 981 PCI_EXP_DEVSTA_TRPND); 982 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 983 4, ®); 984 reg |= PCI_EXP_DEVCTL_BCR_FLR; 985 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 986 4, reg); 987 msleep(EEH_PE_RST_HOLD_TIME); 988 break; 989 case EEH_RESET_DEACTIVATE: 990 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 991 4, ®); 992 reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 993 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 994 4, reg); 995 msleep(EEH_PE_RST_SETTLE_TIME); 996 break; 997 } 998 999 return 0; 1000 } 1001 1002 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 1003 { 1004 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1005 u32 cap = 0; 1006 1007 if (WARN_ON(!edev->af_cap)) 1008 return -ENOTTY; 1009 1010 eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 1011 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 1012 return -ENOTTY; 1013 1014 switch (option) { 1015 case EEH_RESET_HOT: 1016 case EEH_RESET_FUNDAMENTAL: 1017 /* 1018 * Wait for Transaction Pending bit to clear. A word-aligned 1019 * test is used, so we use the conrol offset rather than status 1020 * and shift the test bit to match. 1021 */ 1022 pnv_eeh_wait_for_pending(pdn, "AF", 1023 edev->af_cap + PCI_AF_CTRL, 1024 PCI_AF_STATUS_TP << 8); 1025 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1026 1, PCI_AF_CTRL_FLR); 1027 msleep(EEH_PE_RST_HOLD_TIME); 1028 break; 1029 case EEH_RESET_DEACTIVATE: 1030 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 1031 msleep(EEH_PE_RST_SETTLE_TIME); 1032 break; 1033 } 1034 1035 return 0; 1036 } 1037 1038 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 1039 { 1040 struct eeh_dev *edev; 1041 struct pci_dn *pdn; 1042 int ret; 1043 1044 /* The VF PE should have only one child device */ 1045 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); 1046 pdn = eeh_dev_to_pdn(edev); 1047 if (!pdn) 1048 return -ENXIO; 1049 1050 ret = pnv_eeh_do_flr(pdn, option); 1051 if (!ret) 1052 return ret; 1053 1054 return pnv_eeh_do_af_flr(pdn, option); 1055 } 1056 1057 /** 1058 * pnv_eeh_reset - Reset the specified PE 1059 * @pe: EEH PE 1060 * @option: reset option 1061 * 1062 * Do reset on the indicated PE. For PCI bus sensitive PE, 1063 * we need to reset the parent p2p bridge. The PHB has to 1064 * be reinitialized if the p2p bridge is root bridge. For 1065 * PCI device sensitive PE, we will try to reset the device 1066 * through FLR. For now, we don't have OPAL APIs to do HARD 1067 * reset yet, so all reset would be SOFT (HOT) reset. 1068 */ 1069 static int pnv_eeh_reset(struct eeh_pe *pe, int option) 1070 { 1071 struct pci_controller *hose = pe->phb; 1072 struct pnv_phb *phb; 1073 struct pci_bus *bus; 1074 int64_t rc; 1075 1076 /* 1077 * For PHB reset, we always have complete reset. For those PEs whose 1078 * primary bus derived from root complex (root bus) or root port 1079 * (usually bus#1), we apply hot or fundamental reset on the root port. 1080 * For other PEs, we always have hot reset on the PE primary bus. 1081 * 1082 * Here, we have different design to pHyp, which always clear the 1083 * frozen state during PE reset. However, the good idea here from 1084 * benh is to keep frozen state before we get PE reset done completely 1085 * (until BAR restore). With the frozen state, HW drops illegal IO 1086 * or MMIO access, which can incur recrusive frozen PE during PE 1087 * reset. The side effect is that EEH core has to clear the frozen 1088 * state explicitly after BAR restore. 1089 */ 1090 if (pe->type & EEH_PE_PHB) 1091 return pnv_eeh_phb_reset(hose, option); 1092 1093 /* 1094 * The frozen PE might be caused by PAPR error injection 1095 * registers, which are expected to be cleared after hitting 1096 * frozen PE as stated in the hardware spec. Unfortunately, 1097 * that's not true on P7IOC. So we have to clear it manually 1098 * to avoid recursive EEH errors during recovery. 1099 */ 1100 phb = hose->private_data; 1101 if (phb->model == PNV_PHB_MODEL_P7IOC && 1102 (option == EEH_RESET_HOT || 1103 option == EEH_RESET_FUNDAMENTAL)) { 1104 rc = opal_pci_reset(phb->opal_id, 1105 OPAL_RESET_PHB_ERROR, 1106 OPAL_ASSERT_RESET); 1107 if (rc != OPAL_SUCCESS) { 1108 pr_warn("%s: Failure %lld clearing error injection registers\n", 1109 __func__, rc); 1110 return -EIO; 1111 } 1112 } 1113 1114 if (pe->type & EEH_PE_VF) 1115 return pnv_eeh_reset_vf_pe(pe, option); 1116 1117 bus = eeh_pe_bus_get(pe); 1118 if (!bus) { 1119 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 1120 __func__, pe->phb->global_number, pe->addr); 1121 return -EIO; 1122 } 1123 1124 if (pci_is_root_bus(bus)) 1125 return pnv_eeh_root_reset(hose, option); 1126 1127 /* 1128 * For hot resets try use the generic PCI error recovery reset 1129 * functions. These correctly handles the case where the secondary 1130 * bus is behind a hotplug slot and it will use the slot provided 1131 * reset methods to prevent spurious hotplug events during the reset. 1132 * 1133 * Fundemental resets need to be handled internally to EEH since the 1134 * PCI core doesn't really have a concept of a fundemental reset, 1135 * mainly because there's no standard way to generate one. Only a 1136 * few devices require an FRESET so it should be fine. 1137 */ 1138 if (option != EEH_RESET_FUNDAMENTAL) { 1139 /* 1140 * NB: Skiboot and pnv_eeh_bridge_reset() also no-op the 1141 * de-assert step. It's like the OPAL reset API was 1142 * poorly designed or something... 1143 */ 1144 if (option == EEH_RESET_DEACTIVATE) 1145 return 0; 1146 1147 rc = pci_bus_error_reset(bus->self); 1148 if (!rc) 1149 return 0; 1150 } 1151 1152 /* otherwise, use the generic bridge reset. this might call into FW */ 1153 if (pci_is_root_bus(bus->parent)) 1154 return pnv_eeh_root_reset(hose, option); 1155 return pnv_eeh_bridge_reset(bus->self, option); 1156 } 1157 1158 /** 1159 * pnv_eeh_get_log - Retrieve error log 1160 * @pe: EEH PE 1161 * @severity: temporary or permanent error log 1162 * @drv_log: driver log to be combined with retrieved error log 1163 * @len: length of driver log 1164 * 1165 * Retrieve the temporary or permanent error from the PE. 1166 */ 1167 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 1168 char *drv_log, unsigned long len) 1169 { 1170 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1171 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 1172 1173 return 0; 1174 } 1175 1176 /** 1177 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 1178 * @pe: EEH PE 1179 * 1180 * The function will be called to reconfigure the bridges included 1181 * in the specified PE so that the mulfunctional PE would be recovered 1182 * again. 1183 */ 1184 static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 1185 { 1186 return 0; 1187 } 1188 1189 /** 1190 * pnv_pe_err_inject - Inject specified error to the indicated PE 1191 * @pe: the indicated PE 1192 * @type: error type 1193 * @func: specific error type 1194 * @addr: address 1195 * @mask: address mask 1196 * 1197 * The routine is called to inject specified error, which is 1198 * determined by @type and @func, to the indicated PE for 1199 * testing purpose. 1200 */ 1201 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1202 unsigned long addr, unsigned long mask) 1203 { 1204 struct pci_controller *hose = pe->phb; 1205 struct pnv_phb *phb = hose->private_data; 1206 s64 rc; 1207 1208 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1209 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1210 pr_warn("%s: Invalid error type %d\n", 1211 __func__, type); 1212 return -ERANGE; 1213 } 1214 1215 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1216 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1217 pr_warn("%s: Invalid error function %d\n", 1218 __func__, func); 1219 return -ERANGE; 1220 } 1221 1222 /* Firmware supports error injection ? */ 1223 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1224 pr_warn("%s: Firmware doesn't support error injection\n", 1225 __func__); 1226 return -ENXIO; 1227 } 1228 1229 /* Do error injection */ 1230 rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1231 type, func, addr, mask); 1232 if (rc != OPAL_SUCCESS) { 1233 pr_warn("%s: Failure %lld injecting error " 1234 "%d-%d to PHB#%x-PE#%x\n", 1235 __func__, rc, type, func, 1236 hose->global_number, pe->addr); 1237 return -EIO; 1238 } 1239 1240 return 0; 1241 } 1242 1243 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1244 { 1245 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1246 1247 if (!edev || !edev->pe) 1248 return false; 1249 1250 /* 1251 * We will issue FLR or AF FLR to all VFs, which are contained 1252 * in VF PE. It relies on the EEH PCI config accessors. So we 1253 * can't block them during the window. 1254 */ 1255 if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 1256 return false; 1257 1258 if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1259 return true; 1260 1261 return false; 1262 } 1263 1264 static int pnv_eeh_read_config(struct pci_dn *pdn, 1265 int where, int size, u32 *val) 1266 { 1267 if (!pdn) 1268 return PCIBIOS_DEVICE_NOT_FOUND; 1269 1270 if (pnv_eeh_cfg_blocked(pdn)) { 1271 *val = 0xFFFFFFFF; 1272 return PCIBIOS_SET_FAILED; 1273 } 1274 1275 return pnv_pci_cfg_read(pdn, where, size, val); 1276 } 1277 1278 static int pnv_eeh_write_config(struct pci_dn *pdn, 1279 int where, int size, u32 val) 1280 { 1281 if (!pdn) 1282 return PCIBIOS_DEVICE_NOT_FOUND; 1283 1284 if (pnv_eeh_cfg_blocked(pdn)) 1285 return PCIBIOS_SET_FAILED; 1286 1287 return pnv_pci_cfg_write(pdn, where, size, val); 1288 } 1289 1290 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 1291 { 1292 /* GEM */ 1293 if (data->gemXfir || data->gemRfir || 1294 data->gemRirqfir || data->gemMask || data->gemRwof) 1295 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 1296 be64_to_cpu(data->gemXfir), 1297 be64_to_cpu(data->gemRfir), 1298 be64_to_cpu(data->gemRirqfir), 1299 be64_to_cpu(data->gemMask), 1300 be64_to_cpu(data->gemRwof)); 1301 1302 /* LEM */ 1303 if (data->lemFir || data->lemErrMask || 1304 data->lemAction0 || data->lemAction1 || data->lemWof) 1305 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 1306 be64_to_cpu(data->lemFir), 1307 be64_to_cpu(data->lemErrMask), 1308 be64_to_cpu(data->lemAction0), 1309 be64_to_cpu(data->lemAction1), 1310 be64_to_cpu(data->lemWof)); 1311 } 1312 1313 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 1314 { 1315 struct pnv_phb *phb = hose->private_data; 1316 struct OpalIoP7IOCErrorData *data = 1317 (struct OpalIoP7IOCErrorData*)phb->diag_data; 1318 long rc; 1319 1320 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 1321 if (rc != OPAL_SUCCESS) { 1322 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 1323 __func__, phb->hub_id, rc); 1324 return; 1325 } 1326 1327 switch (be16_to_cpu(data->type)) { 1328 case OPAL_P7IOC_DIAG_TYPE_RGC: 1329 pr_info("P7IOC diag-data for RGC\n\n"); 1330 pnv_eeh_dump_hub_diag_common(data); 1331 if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 1332 pr_info(" RGC: %016llx %016llx\n", 1333 be64_to_cpu(data->rgc.rgcStatus), 1334 be64_to_cpu(data->rgc.rgcLdcp)); 1335 break; 1336 case OPAL_P7IOC_DIAG_TYPE_BI: 1337 pr_info("P7IOC diag-data for BI %s\n\n", 1338 data->bi.biDownbound ? "Downbound" : "Upbound"); 1339 pnv_eeh_dump_hub_diag_common(data); 1340 if (data->bi.biLdcp0 || data->bi.biLdcp1 || 1341 data->bi.biLdcp2 || data->bi.biFenceStatus) 1342 pr_info(" BI: %016llx %016llx %016llx %016llx\n", 1343 be64_to_cpu(data->bi.biLdcp0), 1344 be64_to_cpu(data->bi.biLdcp1), 1345 be64_to_cpu(data->bi.biLdcp2), 1346 be64_to_cpu(data->bi.biFenceStatus)); 1347 break; 1348 case OPAL_P7IOC_DIAG_TYPE_CI: 1349 pr_info("P7IOC diag-data for CI Port %d\n\n", 1350 data->ci.ciPort); 1351 pnv_eeh_dump_hub_diag_common(data); 1352 if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 1353 pr_info(" CI: %016llx %016llx\n", 1354 be64_to_cpu(data->ci.ciPortStatus), 1355 be64_to_cpu(data->ci.ciPortLdcp)); 1356 break; 1357 case OPAL_P7IOC_DIAG_TYPE_MISC: 1358 pr_info("P7IOC diag-data for MISC\n\n"); 1359 pnv_eeh_dump_hub_diag_common(data); 1360 break; 1361 case OPAL_P7IOC_DIAG_TYPE_I2C: 1362 pr_info("P7IOC diag-data for I2C\n\n"); 1363 pnv_eeh_dump_hub_diag_common(data); 1364 break; 1365 default: 1366 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 1367 __func__, phb->hub_id, data->type); 1368 } 1369 } 1370 1371 static int pnv_eeh_get_pe(struct pci_controller *hose, 1372 u16 pe_no, struct eeh_pe **pe) 1373 { 1374 struct pnv_phb *phb = hose->private_data; 1375 struct pnv_ioda_pe *pnv_pe; 1376 struct eeh_pe *dev_pe; 1377 1378 /* 1379 * If PHB supports compound PE, to fetch 1380 * the master PE because slave PE is invisible 1381 * to EEH core. 1382 */ 1383 pnv_pe = &phb->ioda.pe_array[pe_no]; 1384 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 1385 pnv_pe = pnv_pe->master; 1386 WARN_ON(!pnv_pe || 1387 !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 1388 pe_no = pnv_pe->pe_number; 1389 } 1390 1391 /* Find the PE according to PE# */ 1392 dev_pe = eeh_pe_get(hose, pe_no, 0); 1393 if (!dev_pe) 1394 return -EEXIST; 1395 1396 /* Freeze the (compound) PE */ 1397 *pe = dev_pe; 1398 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1399 phb->freeze_pe(phb, pe_no); 1400 1401 /* 1402 * At this point, we're sure the (compound) PE should 1403 * have been frozen. However, we still need poke until 1404 * hitting the frozen PE on top level. 1405 */ 1406 dev_pe = dev_pe->parent; 1407 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 1408 int ret; 1409 ret = eeh_ops->get_state(dev_pe, NULL); 1410 if (ret <= 0 || eeh_state_active(ret)) { 1411 dev_pe = dev_pe->parent; 1412 continue; 1413 } 1414 1415 /* Frozen parent PE */ 1416 *pe = dev_pe; 1417 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1418 phb->freeze_pe(phb, dev_pe->addr); 1419 1420 /* Next one */ 1421 dev_pe = dev_pe->parent; 1422 } 1423 1424 return 0; 1425 } 1426 1427 /** 1428 * pnv_eeh_next_error - Retrieve next EEH error to handle 1429 * @pe: Affected PE 1430 * 1431 * The function is expected to be called by EEH core while it gets 1432 * special EEH event (without binding PE). The function calls to 1433 * OPAL APIs for next error to handle. The informational error is 1434 * handled internally by platform. However, the dead IOC, dead PHB, 1435 * fenced PHB and frozen PE should be handled by EEH core eventually. 1436 */ 1437 static int pnv_eeh_next_error(struct eeh_pe **pe) 1438 { 1439 struct pci_controller *hose; 1440 struct pnv_phb *phb; 1441 struct eeh_pe *phb_pe, *parent_pe; 1442 __be64 frozen_pe_no; 1443 __be16 err_type, severity; 1444 long rc; 1445 int state, ret = EEH_NEXT_ERR_NONE; 1446 1447 /* 1448 * While running here, it's safe to purge the event queue. The 1449 * event should still be masked. 1450 */ 1451 eeh_remove_event(NULL, false); 1452 1453 list_for_each_entry(hose, &hose_list, list_node) { 1454 /* 1455 * If the subordinate PCI buses of the PHB has been 1456 * removed or is exactly under error recovery, we 1457 * needn't take care of it any more. 1458 */ 1459 phb = hose->private_data; 1460 phb_pe = eeh_phb_pe_get(hose); 1461 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 1462 continue; 1463 1464 rc = opal_pci_next_error(phb->opal_id, 1465 &frozen_pe_no, &err_type, &severity); 1466 if (rc != OPAL_SUCCESS) { 1467 pr_devel("%s: Invalid return value on " 1468 "PHB#%x (0x%lx) from opal_pci_next_error", 1469 __func__, hose->global_number, rc); 1470 continue; 1471 } 1472 1473 /* If the PHB doesn't have error, stop processing */ 1474 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 1475 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 1476 pr_devel("%s: No error found on PHB#%x\n", 1477 __func__, hose->global_number); 1478 continue; 1479 } 1480 1481 /* 1482 * Processing the error. We're expecting the error with 1483 * highest priority reported upon multiple errors on the 1484 * specific PHB. 1485 */ 1486 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 1487 __func__, be16_to_cpu(err_type), 1488 be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 1489 hose->global_number); 1490 switch (be16_to_cpu(err_type)) { 1491 case OPAL_EEH_IOC_ERROR: 1492 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 1493 pr_err("EEH: dead IOC detected\n"); 1494 ret = EEH_NEXT_ERR_DEAD_IOC; 1495 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1496 pr_info("EEH: IOC informative error " 1497 "detected\n"); 1498 pnv_eeh_get_and_dump_hub_diag(hose); 1499 ret = EEH_NEXT_ERR_NONE; 1500 } 1501 1502 break; 1503 case OPAL_EEH_PHB_ERROR: 1504 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 1505 *pe = phb_pe; 1506 pr_err("EEH: dead PHB#%x detected, " 1507 "location: %s\n", 1508 hose->global_number, 1509 eeh_pe_loc_get(phb_pe)); 1510 ret = EEH_NEXT_ERR_DEAD_PHB; 1511 } else if (be16_to_cpu(severity) == 1512 OPAL_EEH_SEV_PHB_FENCED) { 1513 *pe = phb_pe; 1514 pr_err("EEH: Fenced PHB#%x detected, " 1515 "location: %s\n", 1516 hose->global_number, 1517 eeh_pe_loc_get(phb_pe)); 1518 ret = EEH_NEXT_ERR_FENCED_PHB; 1519 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1520 pr_info("EEH: PHB#%x informative error " 1521 "detected, location: %s\n", 1522 hose->global_number, 1523 eeh_pe_loc_get(phb_pe)); 1524 pnv_eeh_get_phb_diag(phb_pe); 1525 pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 1526 ret = EEH_NEXT_ERR_NONE; 1527 } 1528 1529 break; 1530 case OPAL_EEH_PE_ERROR: 1531 /* 1532 * If we can't find the corresponding PE, we 1533 * just try to unfreeze. 1534 */ 1535 if (pnv_eeh_get_pe(hose, 1536 be64_to_cpu(frozen_pe_no), pe)) { 1537 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 1538 hose->global_number, be64_to_cpu(frozen_pe_no)); 1539 pr_info("EEH: PHB location: %s\n", 1540 eeh_pe_loc_get(phb_pe)); 1541 1542 /* Dump PHB diag-data */ 1543 rc = opal_pci_get_phb_diag_data2(phb->opal_id, 1544 phb->diag_data, phb->diag_data_size); 1545 if (rc == OPAL_SUCCESS) 1546 pnv_pci_dump_phb_diag_data(hose, 1547 phb->diag_data); 1548 1549 /* Try best to clear it */ 1550 opal_pci_eeh_freeze_clear(phb->opal_id, 1551 be64_to_cpu(frozen_pe_no), 1552 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 1553 ret = EEH_NEXT_ERR_NONE; 1554 } else if ((*pe)->state & EEH_PE_ISOLATED || 1555 eeh_pe_passed(*pe)) { 1556 ret = EEH_NEXT_ERR_NONE; 1557 } else { 1558 pr_err("EEH: Frozen PE#%x " 1559 "on PHB#%x detected\n", 1560 (*pe)->addr, 1561 (*pe)->phb->global_number); 1562 pr_err("EEH: PE location: %s, " 1563 "PHB location: %s\n", 1564 eeh_pe_loc_get(*pe), 1565 eeh_pe_loc_get(phb_pe)); 1566 ret = EEH_NEXT_ERR_FROZEN_PE; 1567 } 1568 1569 break; 1570 default: 1571 pr_warn("%s: Unexpected error type %d\n", 1572 __func__, be16_to_cpu(err_type)); 1573 } 1574 1575 /* 1576 * EEH core will try recover from fenced PHB or 1577 * frozen PE. In the time for frozen PE, EEH core 1578 * enable IO path for that before collecting logs, 1579 * but it ruins the site. So we have to dump the 1580 * log in advance here. 1581 */ 1582 if ((ret == EEH_NEXT_ERR_FROZEN_PE || 1583 ret == EEH_NEXT_ERR_FENCED_PHB) && 1584 !((*pe)->state & EEH_PE_ISOLATED)) { 1585 eeh_pe_mark_isolated(*pe); 1586 pnv_eeh_get_phb_diag(*pe); 1587 1588 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1589 pnv_pci_dump_phb_diag_data((*pe)->phb, 1590 (*pe)->data); 1591 } 1592 1593 /* 1594 * We probably have the frozen parent PE out there and 1595 * we need have to handle frozen parent PE firstly. 1596 */ 1597 if (ret == EEH_NEXT_ERR_FROZEN_PE) { 1598 parent_pe = (*pe)->parent; 1599 while (parent_pe) { 1600 /* Hit the ceiling ? */ 1601 if (parent_pe->type & EEH_PE_PHB) 1602 break; 1603 1604 /* Frozen parent PE ? */ 1605 state = eeh_ops->get_state(parent_pe, NULL); 1606 if (state > 0 && !eeh_state_active(state)) 1607 *pe = parent_pe; 1608 1609 /* Next parent level */ 1610 parent_pe = parent_pe->parent; 1611 } 1612 1613 /* We possibly migrate to another PE */ 1614 eeh_pe_mark_isolated(*pe); 1615 } 1616 1617 /* 1618 * If we have no errors on the specific PHB or only 1619 * informative error there, we continue poking it. 1620 * Otherwise, we need actions to be taken by upper 1621 * layer. 1622 */ 1623 if (ret > EEH_NEXT_ERR_INF) 1624 break; 1625 } 1626 1627 /* Unmask the event */ 1628 if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 1629 enable_irq(eeh_event_irq); 1630 1631 return ret; 1632 } 1633 1634 static int pnv_eeh_restore_config(struct pci_dn *pdn) 1635 { 1636 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1637 struct pnv_phb *phb; 1638 s64 ret = 0; 1639 int config_addr = (pdn->busno << 8) | (pdn->devfn); 1640 1641 if (!edev) 1642 return -EEXIST; 1643 1644 /* 1645 * We have to restore the PCI config space after reset since the 1646 * firmware can't see SRIOV VFs. 1647 * 1648 * FIXME: The MPS, error routing rules, timeout setting are worthy 1649 * to be exported by firmware in extendible way. 1650 */ 1651 if (edev->physfn) { 1652 ret = eeh_restore_vf_config(pdn); 1653 } else { 1654 phb = pdn->phb->private_data; 1655 ret = opal_pci_reinit(phb->opal_id, 1656 OPAL_REINIT_PCI_DEV, config_addr); 1657 } 1658 1659 if (ret) { 1660 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 1661 __func__, config_addr, ret); 1662 return -EIO; 1663 } 1664 1665 return ret; 1666 } 1667 1668 static struct eeh_ops pnv_eeh_ops = { 1669 .name = "powernv", 1670 .init = pnv_eeh_init, 1671 .probe = pnv_eeh_probe, 1672 .set_option = pnv_eeh_set_option, 1673 .get_pe_addr = pnv_eeh_get_pe_addr, 1674 .get_state = pnv_eeh_get_state, 1675 .reset = pnv_eeh_reset, 1676 .get_log = pnv_eeh_get_log, 1677 .configure_bridge = pnv_eeh_configure_bridge, 1678 .err_inject = pnv_eeh_err_inject, 1679 .read_config = pnv_eeh_read_config, 1680 .write_config = pnv_eeh_write_config, 1681 .next_error = pnv_eeh_next_error, 1682 .restore_config = pnv_eeh_restore_config, 1683 .notify_resume = NULL 1684 }; 1685 1686 #ifdef CONFIG_PCI_IOV 1687 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 1688 { 1689 struct pci_dn *pdn = pci_get_pdn(pdev); 1690 int parent_mps; 1691 1692 if (!pdev->is_virtfn) 1693 return; 1694 1695 /* Synchronize MPS for VF and PF */ 1696 parent_mps = pcie_get_mps(pdev->physfn); 1697 if ((128 << pdev->pcie_mpss) >= parent_mps) 1698 pcie_set_mps(pdev, parent_mps); 1699 pdn->mps = pcie_get_mps(pdev); 1700 } 1701 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 1702 #endif /* CONFIG_PCI_IOV */ 1703 1704 /** 1705 * eeh_powernv_init - Register platform dependent EEH operations 1706 * 1707 * EEH initialization on powernv platform. This function should be 1708 * called before any EEH related functions. 1709 */ 1710 static int __init eeh_powernv_init(void) 1711 { 1712 int ret = -EINVAL; 1713 1714 ret = eeh_ops_register(&pnv_eeh_ops); 1715 if (!ret) 1716 pr_info("EEH: PowerNV platform initialized\n"); 1717 else 1718 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 1719 1720 return ret; 1721 } 1722 machine_early_initcall(powernv, eeh_powernv_init); 1723