1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * PowerNV Platform dependent EEH operations 4 * 5 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 6 */ 7 8 #include <linux/atomic.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/list.h> 15 #include <linux/msi.h> 16 #include <linux/of.h> 17 #include <linux/pci.h> 18 #include <linux/proc_fs.h> 19 #include <linux/rbtree.h> 20 #include <linux/sched.h> 21 #include <linux/seq_file.h> 22 #include <linux/spinlock.h> 23 24 #include <asm/eeh.h> 25 #include <asm/eeh_event.h> 26 #include <asm/firmware.h> 27 #include <asm/io.h> 28 #include <asm/iommu.h> 29 #include <asm/machdep.h> 30 #include <asm/msi_bitmap.h> 31 #include <asm/opal.h> 32 #include <asm/ppc-pci.h> 33 #include <asm/pnv-pci.h> 34 35 #include "powernv.h" 36 #include "pci.h" 37 #include "../../../../drivers/pci/pci.h" 38 39 static int eeh_event_irq = -EINVAL; 40 41 void pnv_pcibios_bus_add_device(struct pci_dev *pdev) 42 { 43 dev_dbg(&pdev->dev, "EEH: Setting up device\n"); 44 eeh_probe_device(pdev); 45 } 46 47 static int pnv_eeh_init(void) 48 { 49 struct pci_controller *hose; 50 struct pnv_phb *phb; 51 int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 52 53 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 54 pr_warn("%s: OPAL is required !\n", 55 __func__); 56 return -EINVAL; 57 } 58 59 /* Set probe mode */ 60 eeh_add_flag(EEH_PROBE_MODE_DEV); 61 62 /* 63 * P7IOC blocks PCI config access to frozen PE, but PHB3 64 * doesn't do that. So we have to selectively enable I/O 65 * prior to collecting error log. 66 */ 67 list_for_each_entry(hose, &hose_list, list_node) { 68 phb = hose->private_data; 69 70 if (phb->model == PNV_PHB_MODEL_P7IOC) 71 eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 72 73 if (phb->diag_data_size > max_diag_size) 74 max_diag_size = phb->diag_data_size; 75 76 /* 77 * PE#0 should be regarded as valid by EEH core 78 * if it's not the reserved one. Currently, we 79 * have the reserved PE#255 and PE#127 for PHB3 80 * and P7IOC separately. So we should regard 81 * PE#0 as valid for PHB3 and P7IOC. 82 */ 83 if (phb->ioda.reserved_pe_idx != 0) 84 eeh_add_flag(EEH_VALID_PE_ZERO); 85 86 break; 87 } 88 89 eeh_set_pe_aux_size(max_diag_size); 90 ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device; 91 92 return 0; 93 } 94 95 static irqreturn_t pnv_eeh_event(int irq, void *data) 96 { 97 /* 98 * We simply send a special EEH event if EEH has been 99 * enabled. We don't care about EEH events until we've 100 * finished processing the outstanding ones. Event processing 101 * gets unmasked in next_error() if EEH is enabled. 102 */ 103 disable_irq_nosync(irq); 104 105 if (eeh_enabled()) 106 eeh_send_failure_event(NULL); 107 108 return IRQ_HANDLED; 109 } 110 111 #ifdef CONFIG_DEBUG_FS 112 static ssize_t pnv_eeh_ei_write(struct file *filp, 113 const char __user *user_buf, 114 size_t count, loff_t *ppos) 115 { 116 struct pci_controller *hose = filp->private_data; 117 struct eeh_pe *pe; 118 int pe_no, type, func; 119 unsigned long addr, mask; 120 char buf[50]; 121 int ret; 122 123 if (!eeh_ops || !eeh_ops->err_inject) 124 return -ENXIO; 125 126 /* Copy over argument buffer */ 127 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 128 if (!ret) 129 return -EFAULT; 130 131 /* Retrieve parameters */ 132 ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 133 &pe_no, &type, &func, &addr, &mask); 134 if (ret != 5) 135 return -EINVAL; 136 137 /* Retrieve PE */ 138 pe = eeh_pe_get(hose, pe_no, 0); 139 if (!pe) 140 return -ENODEV; 141 142 /* Do error injection */ 143 ret = eeh_ops->err_inject(pe, type, func, addr, mask); 144 return ret < 0 ? ret : count; 145 } 146 147 static const struct file_operations pnv_eeh_ei_fops = { 148 .open = simple_open, 149 .llseek = no_llseek, 150 .write = pnv_eeh_ei_write, 151 }; 152 153 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 154 { 155 struct pci_controller *hose = data; 156 struct pnv_phb *phb = hose->private_data; 157 158 out_be64(phb->regs + offset, val); 159 return 0; 160 } 161 162 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 163 { 164 struct pci_controller *hose = data; 165 struct pnv_phb *phb = hose->private_data; 166 167 *val = in_be64(phb->regs + offset); 168 return 0; 169 } 170 171 #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 172 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 173 { \ 174 return pnv_eeh_dbgfs_set(data, reg, val); \ 175 } \ 176 \ 177 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 178 { \ 179 return pnv_eeh_dbgfs_get(data, reg, val); \ 180 } \ 181 \ 182 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 183 pnv_eeh_dbgfs_get_##name, \ 184 pnv_eeh_dbgfs_set_##name, \ 185 "0x%llx\n") 186 187 PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 188 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 189 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 190 191 #endif /* CONFIG_DEBUG_FS */ 192 193 void pnv_eeh_enable_phbs(void) 194 { 195 struct pci_controller *hose; 196 struct pnv_phb *phb; 197 198 list_for_each_entry(hose, &hose_list, list_node) { 199 phb = hose->private_data; 200 /* 201 * If EEH is enabled, we're going to rely on that. 202 * Otherwise, we restore to conventional mechanism 203 * to clear frozen PE during PCI config access. 204 */ 205 if (eeh_enabled()) 206 phb->flags |= PNV_PHB_FLAG_EEH; 207 else 208 phb->flags &= ~PNV_PHB_FLAG_EEH; 209 } 210 } 211 212 /** 213 * pnv_eeh_post_init - EEH platform dependent post initialization 214 * 215 * EEH platform dependent post initialization on powernv. When 216 * the function is called, the EEH PEs and devices should have 217 * been built. If the I/O cache staff has been built, EEH is 218 * ready to supply service. 219 */ 220 int pnv_eeh_post_init(void) 221 { 222 struct pci_controller *hose; 223 struct pnv_phb *phb; 224 int ret = 0; 225 226 eeh_show_enabled(); 227 228 /* Register OPAL event notifier */ 229 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 230 if (eeh_event_irq < 0) { 231 pr_err("%s: Can't register OPAL event interrupt (%d)\n", 232 __func__, eeh_event_irq); 233 return eeh_event_irq; 234 } 235 236 ret = request_irq(eeh_event_irq, pnv_eeh_event, 237 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 238 if (ret < 0) { 239 irq_dispose_mapping(eeh_event_irq); 240 pr_err("%s: Can't request OPAL event interrupt (%d)\n", 241 __func__, eeh_event_irq); 242 return ret; 243 } 244 245 if (!eeh_enabled()) 246 disable_irq(eeh_event_irq); 247 248 pnv_eeh_enable_phbs(); 249 250 list_for_each_entry(hose, &hose_list, list_node) { 251 phb = hose->private_data; 252 253 /* Create debugfs entries */ 254 #ifdef CONFIG_DEBUG_FS 255 if (phb->has_dbgfs || !phb->dbgfs) 256 continue; 257 258 phb->has_dbgfs = 1; 259 debugfs_create_file("err_injct", 0200, 260 phb->dbgfs, hose, 261 &pnv_eeh_ei_fops); 262 263 debugfs_create_file("err_injct_outbound", 0600, 264 phb->dbgfs, hose, 265 &pnv_eeh_dbgfs_ops_outb); 266 debugfs_create_file("err_injct_inboundA", 0600, 267 phb->dbgfs, hose, 268 &pnv_eeh_dbgfs_ops_inbA); 269 debugfs_create_file("err_injct_inboundB", 0600, 270 phb->dbgfs, hose, 271 &pnv_eeh_dbgfs_ops_inbB); 272 #endif /* CONFIG_DEBUG_FS */ 273 } 274 275 return ret; 276 } 277 278 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 279 { 280 int pos = PCI_CAPABILITY_LIST; 281 int cnt = 48; /* Maximal number of capabilities */ 282 u32 status, id; 283 284 if (!pdn) 285 return 0; 286 287 /* Check if the device supports capabilities */ 288 pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 289 if (!(status & PCI_STATUS_CAP_LIST)) 290 return 0; 291 292 while (cnt--) { 293 pnv_pci_cfg_read(pdn, pos, 1, &pos); 294 if (pos < 0x40) 295 break; 296 297 pos &= ~3; 298 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 299 if (id == 0xff) 300 break; 301 302 /* Found */ 303 if (id == cap) 304 return pos; 305 306 /* Next one */ 307 pos += PCI_CAP_LIST_NEXT; 308 } 309 310 return 0; 311 } 312 313 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 314 { 315 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 316 u32 header; 317 int pos = 256, ttl = (4096 - 256) / 8; 318 319 if (!edev || !edev->pcie_cap) 320 return 0; 321 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 322 return 0; 323 else if (!header) 324 return 0; 325 326 while (ttl-- > 0) { 327 if (PCI_EXT_CAP_ID(header) == cap && pos) 328 return pos; 329 330 pos = PCI_EXT_CAP_NEXT(header); 331 if (pos < 256) 332 break; 333 334 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 335 break; 336 } 337 338 return 0; 339 } 340 341 static struct eeh_pe *pnv_eeh_get_upstream_pe(struct pci_dev *pdev) 342 { 343 struct pci_controller *hose = pdev->bus->sysdata; 344 struct pnv_phb *phb = hose->private_data; 345 struct pci_dev *parent = pdev->bus->self; 346 347 #ifdef CONFIG_PCI_IOV 348 /* for VFs we use the PF's PE as the upstream PE */ 349 if (pdev->is_virtfn) 350 parent = pdev->physfn; 351 #endif 352 353 /* otherwise use the PE of our parent bridge */ 354 if (parent) { 355 struct pnv_ioda_pe *ioda_pe = pnv_ioda_get_pe(parent); 356 357 return eeh_pe_get(phb->hose, ioda_pe->pe_number, 0); 358 } 359 360 return NULL; 361 } 362 363 /** 364 * pnv_eeh_probe - Do probe on PCI device 365 * @pdev: pci_dev to probe 366 * 367 * Create, or find the existing, eeh_dev for this pci_dev. 368 */ 369 static struct eeh_dev *pnv_eeh_probe(struct pci_dev *pdev) 370 { 371 struct pci_dn *pdn = pci_get_pdn(pdev); 372 struct pci_controller *hose = pdn->phb; 373 struct pnv_phb *phb = hose->private_data; 374 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 375 struct eeh_pe *upstream_pe; 376 uint32_t pcie_flags; 377 int ret; 378 int config_addr = (pdn->busno << 8) | (pdn->devfn); 379 380 /* 381 * When probing the root bridge, which doesn't have any 382 * subordinate PCI devices. We don't have OF node for 383 * the root bridge. So it's not reasonable to continue 384 * the probing. 385 */ 386 if (!edev || edev->pe) 387 return NULL; 388 389 /* already configured? */ 390 if (edev->pdev) { 391 pr_debug("%s: found existing edev for %04x:%02x:%02x.%01x\n", 392 __func__, hose->global_number, config_addr >> 8, 393 PCI_SLOT(config_addr), PCI_FUNC(config_addr)); 394 return edev; 395 } 396 397 /* Skip for PCI-ISA bridge */ 398 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) 399 return NULL; 400 401 eeh_edev_dbg(edev, "Probing device\n"); 402 403 /* Initialize eeh device */ 404 edev->mode &= 0xFFFFFF00; 405 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 406 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 407 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 408 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 409 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 410 edev->mode |= EEH_DEV_BRIDGE; 411 if (edev->pcie_cap) { 412 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 413 2, &pcie_flags); 414 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 415 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 416 edev->mode |= EEH_DEV_ROOT_PORT; 417 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 418 edev->mode |= EEH_DEV_DS_PORT; 419 } 420 } 421 422 edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; 423 424 upstream_pe = pnv_eeh_get_upstream_pe(pdev); 425 426 /* Create PE */ 427 ret = eeh_pe_tree_insert(edev, upstream_pe); 428 if (ret) { 429 eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n", ret); 430 return NULL; 431 } 432 433 /* 434 * If the PE contains any one of following adapters, the 435 * PCI config space can't be accessed when dumping EEH log. 436 * Otherwise, we will run into fenced PHB caused by shortage 437 * of outbound credits in the adapter. The PCI config access 438 * should be blocked until PE reset. MMIO access is dropped 439 * by hardware certainly. In order to drop PCI config requests, 440 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 441 * will be checked in the backend for PE state retrival. If 442 * the PE becomes frozen for the first time and the flag has 443 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 444 * that PE to block its config space. 445 * 446 * Broadcom BCM5718 2-ports NICs (14e4:1656) 447 * Broadcom Austin 4-ports NICs (14e4:1657) 448 * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 449 * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 450 */ 451 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 452 pdn->device_id == 0x1656) || 453 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 454 pdn->device_id == 0x1657) || 455 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 456 pdn->device_id == 0x168a) || 457 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 458 pdn->device_id == 0x168e)) 459 edev->pe->state |= EEH_PE_CFG_RESTRICTED; 460 461 /* 462 * Cache the PE primary bus, which can't be fetched when 463 * full hotplug is in progress. In that case, all child 464 * PCI devices of the PE are expected to be removed prior 465 * to PE reset. 466 */ 467 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 468 edev->pe->bus = pci_find_bus(hose->global_number, 469 pdn->busno); 470 if (edev->pe->bus) 471 edev->pe->state |= EEH_PE_PRI_BUS; 472 } 473 474 /* 475 * Enable EEH explicitly so that we will do EEH check 476 * while accessing I/O stuff 477 */ 478 if (!eeh_has_flag(EEH_ENABLED)) { 479 enable_irq(eeh_event_irq); 480 pnv_eeh_enable_phbs(); 481 eeh_add_flag(EEH_ENABLED); 482 } 483 484 /* Save memory bars */ 485 eeh_save_bars(edev); 486 487 eeh_edev_dbg(edev, "EEH enabled on device\n"); 488 489 return edev; 490 } 491 492 /** 493 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 494 * @pe: EEH PE 495 * @option: operation to be issued 496 * 497 * The function is used to control the EEH functionality globally. 498 * Currently, following options are support according to PAPR: 499 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 500 */ 501 static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 502 { 503 struct pci_controller *hose = pe->phb; 504 struct pnv_phb *phb = hose->private_data; 505 bool freeze_pe = false; 506 int opt; 507 s64 rc; 508 509 switch (option) { 510 case EEH_OPT_DISABLE: 511 return -EPERM; 512 case EEH_OPT_ENABLE: 513 return 0; 514 case EEH_OPT_THAW_MMIO: 515 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 516 break; 517 case EEH_OPT_THAW_DMA: 518 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 519 break; 520 case EEH_OPT_FREEZE_PE: 521 freeze_pe = true; 522 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 523 break; 524 default: 525 pr_warn("%s: Invalid option %d\n", __func__, option); 526 return -EINVAL; 527 } 528 529 /* Freeze master and slave PEs if PHB supports compound PEs */ 530 if (freeze_pe) { 531 if (phb->freeze_pe) { 532 phb->freeze_pe(phb, pe->addr); 533 return 0; 534 } 535 536 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 537 if (rc != OPAL_SUCCESS) { 538 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 539 __func__, rc, phb->hose->global_number, 540 pe->addr); 541 return -EIO; 542 } 543 544 return 0; 545 } 546 547 /* Unfreeze master and slave PEs if PHB supports */ 548 if (phb->unfreeze_pe) 549 return phb->unfreeze_pe(phb, pe->addr, opt); 550 551 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 552 if (rc != OPAL_SUCCESS) { 553 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 554 __func__, rc, option, phb->hose->global_number, 555 pe->addr); 556 return -EIO; 557 } 558 559 return 0; 560 } 561 562 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 563 { 564 struct pnv_phb *phb = pe->phb->private_data; 565 s64 rc; 566 567 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 568 phb->diag_data_size); 569 if (rc != OPAL_SUCCESS) 570 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 571 __func__, rc, pe->phb->global_number); 572 } 573 574 static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 575 { 576 struct pnv_phb *phb = pe->phb->private_data; 577 u8 fstate = 0; 578 __be16 pcierr = 0; 579 s64 rc; 580 int result = 0; 581 582 rc = opal_pci_eeh_freeze_status(phb->opal_id, 583 pe->addr, 584 &fstate, 585 &pcierr, 586 NULL); 587 if (rc != OPAL_SUCCESS) { 588 pr_warn("%s: Failure %lld getting PHB#%x state\n", 589 __func__, rc, phb->hose->global_number); 590 return EEH_STATE_NOT_SUPPORT; 591 } 592 593 /* 594 * Check PHB state. If the PHB is frozen for the 595 * first time, to dump the PHB diag-data. 596 */ 597 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 598 result = (EEH_STATE_MMIO_ACTIVE | 599 EEH_STATE_DMA_ACTIVE | 600 EEH_STATE_MMIO_ENABLED | 601 EEH_STATE_DMA_ENABLED); 602 } else if (!(pe->state & EEH_PE_ISOLATED)) { 603 eeh_pe_mark_isolated(pe); 604 pnv_eeh_get_phb_diag(pe); 605 606 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 607 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 608 } 609 610 return result; 611 } 612 613 static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 614 { 615 struct pnv_phb *phb = pe->phb->private_data; 616 u8 fstate = 0; 617 __be16 pcierr = 0; 618 s64 rc; 619 int result; 620 621 /* 622 * We don't clobber hardware frozen state until PE 623 * reset is completed. In order to keep EEH core 624 * moving forward, we have to return operational 625 * state during PE reset. 626 */ 627 if (pe->state & EEH_PE_RESET) { 628 result = (EEH_STATE_MMIO_ACTIVE | 629 EEH_STATE_DMA_ACTIVE | 630 EEH_STATE_MMIO_ENABLED | 631 EEH_STATE_DMA_ENABLED); 632 return result; 633 } 634 635 /* 636 * Fetch PE state from hardware. If the PHB 637 * supports compound PE, let it handle that. 638 */ 639 if (phb->get_pe_state) { 640 fstate = phb->get_pe_state(phb, pe->addr); 641 } else { 642 rc = opal_pci_eeh_freeze_status(phb->opal_id, 643 pe->addr, 644 &fstate, 645 &pcierr, 646 NULL); 647 if (rc != OPAL_SUCCESS) { 648 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 649 __func__, rc, phb->hose->global_number, 650 pe->addr); 651 return EEH_STATE_NOT_SUPPORT; 652 } 653 } 654 655 /* Figure out state */ 656 switch (fstate) { 657 case OPAL_EEH_STOPPED_NOT_FROZEN: 658 result = (EEH_STATE_MMIO_ACTIVE | 659 EEH_STATE_DMA_ACTIVE | 660 EEH_STATE_MMIO_ENABLED | 661 EEH_STATE_DMA_ENABLED); 662 break; 663 case OPAL_EEH_STOPPED_MMIO_FREEZE: 664 result = (EEH_STATE_DMA_ACTIVE | 665 EEH_STATE_DMA_ENABLED); 666 break; 667 case OPAL_EEH_STOPPED_DMA_FREEZE: 668 result = (EEH_STATE_MMIO_ACTIVE | 669 EEH_STATE_MMIO_ENABLED); 670 break; 671 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 672 result = 0; 673 break; 674 case OPAL_EEH_STOPPED_RESET: 675 result = EEH_STATE_RESET_ACTIVE; 676 break; 677 case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 678 result = EEH_STATE_UNAVAILABLE; 679 break; 680 case OPAL_EEH_STOPPED_PERM_UNAVAIL: 681 result = EEH_STATE_NOT_SUPPORT; 682 break; 683 default: 684 result = EEH_STATE_NOT_SUPPORT; 685 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 686 __func__, phb->hose->global_number, 687 pe->addr, fstate); 688 } 689 690 /* 691 * If PHB supports compound PE, to freeze all 692 * slave PEs for consistency. 693 * 694 * If the PE is switching to frozen state for the 695 * first time, to dump the PHB diag-data. 696 */ 697 if (!(result & EEH_STATE_NOT_SUPPORT) && 698 !(result & EEH_STATE_UNAVAILABLE) && 699 !(result & EEH_STATE_MMIO_ACTIVE) && 700 !(result & EEH_STATE_DMA_ACTIVE) && 701 !(pe->state & EEH_PE_ISOLATED)) { 702 if (phb->freeze_pe) 703 phb->freeze_pe(phb, pe->addr); 704 705 eeh_pe_mark_isolated(pe); 706 pnv_eeh_get_phb_diag(pe); 707 708 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 709 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 710 } 711 712 return result; 713 } 714 715 /** 716 * pnv_eeh_get_state - Retrieve PE state 717 * @pe: EEH PE 718 * @delay: delay while PE state is temporarily unavailable 719 * 720 * Retrieve the state of the specified PE. For IODA-compitable 721 * platform, it should be retrieved from IODA table. Therefore, 722 * we prefer passing down to hardware implementation to handle 723 * it. 724 */ 725 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 726 { 727 int ret; 728 729 if (pe->type & EEH_PE_PHB) 730 ret = pnv_eeh_get_phb_state(pe); 731 else 732 ret = pnv_eeh_get_pe_state(pe); 733 734 if (!delay) 735 return ret; 736 737 /* 738 * If the PE state is temporarily unavailable, 739 * to inform the EEH core delay for default 740 * period (1 second) 741 */ 742 *delay = 0; 743 if (ret & EEH_STATE_UNAVAILABLE) 744 *delay = 1000; 745 746 return ret; 747 } 748 749 static s64 pnv_eeh_poll(unsigned long id) 750 { 751 s64 rc = OPAL_HARDWARE; 752 753 while (1) { 754 rc = opal_pci_poll(id); 755 if (rc <= 0) 756 break; 757 758 if (system_state < SYSTEM_RUNNING) 759 udelay(1000 * rc); 760 else 761 msleep(rc); 762 } 763 764 return rc; 765 } 766 767 int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 768 { 769 struct pnv_phb *phb = hose->private_data; 770 s64 rc = OPAL_HARDWARE; 771 772 pr_debug("%s: Reset PHB#%x, option=%d\n", 773 __func__, hose->global_number, option); 774 775 /* Issue PHB complete reset request */ 776 if (option == EEH_RESET_FUNDAMENTAL || 777 option == EEH_RESET_HOT) 778 rc = opal_pci_reset(phb->opal_id, 779 OPAL_RESET_PHB_COMPLETE, 780 OPAL_ASSERT_RESET); 781 else if (option == EEH_RESET_DEACTIVATE) 782 rc = opal_pci_reset(phb->opal_id, 783 OPAL_RESET_PHB_COMPLETE, 784 OPAL_DEASSERT_RESET); 785 if (rc < 0) 786 goto out; 787 788 /* 789 * Poll state of the PHB until the request is done 790 * successfully. The PHB reset is usually PHB complete 791 * reset followed by hot reset on root bus. So we also 792 * need the PCI bus settlement delay. 793 */ 794 if (rc > 0) 795 rc = pnv_eeh_poll(phb->opal_id); 796 if (option == EEH_RESET_DEACTIVATE) { 797 if (system_state < SYSTEM_RUNNING) 798 udelay(1000 * EEH_PE_RST_SETTLE_TIME); 799 else 800 msleep(EEH_PE_RST_SETTLE_TIME); 801 } 802 out: 803 if (rc != OPAL_SUCCESS) 804 return -EIO; 805 806 return 0; 807 } 808 809 static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 810 { 811 struct pnv_phb *phb = hose->private_data; 812 s64 rc = OPAL_HARDWARE; 813 814 pr_debug("%s: Reset PHB#%x, option=%d\n", 815 __func__, hose->global_number, option); 816 817 /* 818 * During the reset deassert time, we needn't care 819 * the reset scope because the firmware does nothing 820 * for fundamental or hot reset during deassert phase. 821 */ 822 if (option == EEH_RESET_FUNDAMENTAL) 823 rc = opal_pci_reset(phb->opal_id, 824 OPAL_RESET_PCI_FUNDAMENTAL, 825 OPAL_ASSERT_RESET); 826 else if (option == EEH_RESET_HOT) 827 rc = opal_pci_reset(phb->opal_id, 828 OPAL_RESET_PCI_HOT, 829 OPAL_ASSERT_RESET); 830 else if (option == EEH_RESET_DEACTIVATE) 831 rc = opal_pci_reset(phb->opal_id, 832 OPAL_RESET_PCI_HOT, 833 OPAL_DEASSERT_RESET); 834 if (rc < 0) 835 goto out; 836 837 /* Poll state of the PHB until the request is done */ 838 if (rc > 0) 839 rc = pnv_eeh_poll(phb->opal_id); 840 if (option == EEH_RESET_DEACTIVATE) 841 msleep(EEH_PE_RST_SETTLE_TIME); 842 out: 843 if (rc != OPAL_SUCCESS) 844 return -EIO; 845 846 return 0; 847 } 848 849 static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 850 { 851 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 852 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 853 int aer = edev ? edev->aer_cap : 0; 854 u32 ctrl; 855 856 pr_debug("%s: Secondary Reset PCI bus %04x:%02x with option %d\n", 857 __func__, pci_domain_nr(dev->bus), 858 dev->bus->number, option); 859 860 switch (option) { 861 case EEH_RESET_FUNDAMENTAL: 862 case EEH_RESET_HOT: 863 /* Don't report linkDown event */ 864 if (aer) { 865 eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK, 866 4, &ctrl); 867 ctrl |= PCI_ERR_UNC_SURPDN; 868 eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK, 869 4, ctrl); 870 } 871 872 eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl); 873 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 874 eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl); 875 876 msleep(EEH_PE_RST_HOLD_TIME); 877 break; 878 case EEH_RESET_DEACTIVATE: 879 eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl); 880 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 881 eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl); 882 883 msleep(EEH_PE_RST_SETTLE_TIME); 884 885 /* Continue reporting linkDown event */ 886 if (aer) { 887 eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK, 888 4, &ctrl); 889 ctrl &= ~PCI_ERR_UNC_SURPDN; 890 eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK, 891 4, ctrl); 892 } 893 894 break; 895 } 896 897 return 0; 898 } 899 900 static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 901 { 902 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 903 struct pnv_phb *phb = hose->private_data; 904 struct device_node *dn = pci_device_to_OF_node(pdev); 905 uint64_t id = PCI_SLOT_ID(phb->opal_id, 906 (pdev->bus->number << 8) | pdev->devfn); 907 uint8_t scope; 908 int64_t rc; 909 910 /* Hot reset to the bus if firmware cannot handle */ 911 if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 912 return __pnv_eeh_bridge_reset(pdev, option); 913 914 pr_debug("%s: FW reset PCI bus %04x:%02x with option %d\n", 915 __func__, pci_domain_nr(pdev->bus), 916 pdev->bus->number, option); 917 918 switch (option) { 919 case EEH_RESET_FUNDAMENTAL: 920 scope = OPAL_RESET_PCI_FUNDAMENTAL; 921 break; 922 case EEH_RESET_HOT: 923 scope = OPAL_RESET_PCI_HOT; 924 break; 925 case EEH_RESET_DEACTIVATE: 926 return 0; 927 default: 928 dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 929 __func__, option); 930 return -EINVAL; 931 } 932 933 rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 934 if (rc <= OPAL_SUCCESS) 935 goto out; 936 937 rc = pnv_eeh_poll(id); 938 out: 939 return (rc == OPAL_SUCCESS) ? 0 : -EIO; 940 } 941 942 void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 943 { 944 struct pci_controller *hose; 945 946 if (pci_is_root_bus(dev->bus)) { 947 hose = pci_bus_to_host(dev->bus); 948 pnv_eeh_root_reset(hose, EEH_RESET_HOT); 949 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 950 } else { 951 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 952 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 953 } 954 } 955 956 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 957 int pos, u16 mask) 958 { 959 struct eeh_dev *edev = pdn->edev; 960 int i, status = 0; 961 962 /* Wait for Transaction Pending bit to be cleared */ 963 for (i = 0; i < 4; i++) { 964 eeh_ops->read_config(edev, pos, 2, &status); 965 if (!(status & mask)) 966 return; 967 968 msleep((1 << i) * 100); 969 } 970 971 pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 972 __func__, type, 973 pdn->phb->global_number, pdn->busno, 974 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 975 } 976 977 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 978 { 979 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 980 u32 reg = 0; 981 982 if (WARN_ON(!edev->pcie_cap)) 983 return -ENOTTY; 984 985 eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 986 if (!(reg & PCI_EXP_DEVCAP_FLR)) 987 return -ENOTTY; 988 989 switch (option) { 990 case EEH_RESET_HOT: 991 case EEH_RESET_FUNDAMENTAL: 992 pnv_eeh_wait_for_pending(pdn, "", 993 edev->pcie_cap + PCI_EXP_DEVSTA, 994 PCI_EXP_DEVSTA_TRPND); 995 eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, 996 4, ®); 997 reg |= PCI_EXP_DEVCTL_BCR_FLR; 998 eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, 999 4, reg); 1000 msleep(EEH_PE_RST_HOLD_TIME); 1001 break; 1002 case EEH_RESET_DEACTIVATE: 1003 eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, 1004 4, ®); 1005 reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 1006 eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, 1007 4, reg); 1008 msleep(EEH_PE_RST_SETTLE_TIME); 1009 break; 1010 } 1011 1012 return 0; 1013 } 1014 1015 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 1016 { 1017 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1018 u32 cap = 0; 1019 1020 if (WARN_ON(!edev->af_cap)) 1021 return -ENOTTY; 1022 1023 eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap); 1024 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 1025 return -ENOTTY; 1026 1027 switch (option) { 1028 case EEH_RESET_HOT: 1029 case EEH_RESET_FUNDAMENTAL: 1030 /* 1031 * Wait for Transaction Pending bit to clear. A word-aligned 1032 * test is used, so we use the conrol offset rather than status 1033 * and shift the test bit to match. 1034 */ 1035 pnv_eeh_wait_for_pending(pdn, "AF", 1036 edev->af_cap + PCI_AF_CTRL, 1037 PCI_AF_STATUS_TP << 8); 1038 eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1039 1, PCI_AF_CTRL_FLR); 1040 msleep(EEH_PE_RST_HOLD_TIME); 1041 break; 1042 case EEH_RESET_DEACTIVATE: 1043 eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0); 1044 msleep(EEH_PE_RST_SETTLE_TIME); 1045 break; 1046 } 1047 1048 return 0; 1049 } 1050 1051 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 1052 { 1053 struct eeh_dev *edev; 1054 struct pci_dn *pdn; 1055 int ret; 1056 1057 /* The VF PE should have only one child device */ 1058 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); 1059 pdn = eeh_dev_to_pdn(edev); 1060 if (!pdn) 1061 return -ENXIO; 1062 1063 ret = pnv_eeh_do_flr(pdn, option); 1064 if (!ret) 1065 return ret; 1066 1067 return pnv_eeh_do_af_flr(pdn, option); 1068 } 1069 1070 /** 1071 * pnv_eeh_reset - Reset the specified PE 1072 * @pe: EEH PE 1073 * @option: reset option 1074 * 1075 * Do reset on the indicated PE. For PCI bus sensitive PE, 1076 * we need to reset the parent p2p bridge. The PHB has to 1077 * be reinitialized if the p2p bridge is root bridge. For 1078 * PCI device sensitive PE, we will try to reset the device 1079 * through FLR. For now, we don't have OPAL APIs to do HARD 1080 * reset yet, so all reset would be SOFT (HOT) reset. 1081 */ 1082 static int pnv_eeh_reset(struct eeh_pe *pe, int option) 1083 { 1084 struct pci_controller *hose = pe->phb; 1085 struct pnv_phb *phb; 1086 struct pci_bus *bus; 1087 int64_t rc; 1088 1089 /* 1090 * For PHB reset, we always have complete reset. For those PEs whose 1091 * primary bus derived from root complex (root bus) or root port 1092 * (usually bus#1), we apply hot or fundamental reset on the root port. 1093 * For other PEs, we always have hot reset on the PE primary bus. 1094 * 1095 * Here, we have different design to pHyp, which always clear the 1096 * frozen state during PE reset. However, the good idea here from 1097 * benh is to keep frozen state before we get PE reset done completely 1098 * (until BAR restore). With the frozen state, HW drops illegal IO 1099 * or MMIO access, which can incur recrusive frozen PE during PE 1100 * reset. The side effect is that EEH core has to clear the frozen 1101 * state explicitly after BAR restore. 1102 */ 1103 if (pe->type & EEH_PE_PHB) 1104 return pnv_eeh_phb_reset(hose, option); 1105 1106 /* 1107 * The frozen PE might be caused by PAPR error injection 1108 * registers, which are expected to be cleared after hitting 1109 * frozen PE as stated in the hardware spec. Unfortunately, 1110 * that's not true on P7IOC. So we have to clear it manually 1111 * to avoid recursive EEH errors during recovery. 1112 */ 1113 phb = hose->private_data; 1114 if (phb->model == PNV_PHB_MODEL_P7IOC && 1115 (option == EEH_RESET_HOT || 1116 option == EEH_RESET_FUNDAMENTAL)) { 1117 rc = opal_pci_reset(phb->opal_id, 1118 OPAL_RESET_PHB_ERROR, 1119 OPAL_ASSERT_RESET); 1120 if (rc != OPAL_SUCCESS) { 1121 pr_warn("%s: Failure %lld clearing error injection registers\n", 1122 __func__, rc); 1123 return -EIO; 1124 } 1125 } 1126 1127 if (pe->type & EEH_PE_VF) 1128 return pnv_eeh_reset_vf_pe(pe, option); 1129 1130 bus = eeh_pe_bus_get(pe); 1131 if (!bus) { 1132 pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 1133 __func__, pe->phb->global_number, pe->addr); 1134 return -EIO; 1135 } 1136 1137 if (pci_is_root_bus(bus)) 1138 return pnv_eeh_root_reset(hose, option); 1139 1140 /* 1141 * For hot resets try use the generic PCI error recovery reset 1142 * functions. These correctly handles the case where the secondary 1143 * bus is behind a hotplug slot and it will use the slot provided 1144 * reset methods to prevent spurious hotplug events during the reset. 1145 * 1146 * Fundemental resets need to be handled internally to EEH since the 1147 * PCI core doesn't really have a concept of a fundemental reset, 1148 * mainly because there's no standard way to generate one. Only a 1149 * few devices require an FRESET so it should be fine. 1150 */ 1151 if (option != EEH_RESET_FUNDAMENTAL) { 1152 /* 1153 * NB: Skiboot and pnv_eeh_bridge_reset() also no-op the 1154 * de-assert step. It's like the OPAL reset API was 1155 * poorly designed or something... 1156 */ 1157 if (option == EEH_RESET_DEACTIVATE) 1158 return 0; 1159 1160 rc = pci_bus_error_reset(bus->self); 1161 if (!rc) 1162 return 0; 1163 } 1164 1165 /* otherwise, use the generic bridge reset. this might call into FW */ 1166 if (pci_is_root_bus(bus->parent)) 1167 return pnv_eeh_root_reset(hose, option); 1168 return pnv_eeh_bridge_reset(bus->self, option); 1169 } 1170 1171 /** 1172 * pnv_eeh_get_log - Retrieve error log 1173 * @pe: EEH PE 1174 * @severity: temporary or permanent error log 1175 * @drv_log: driver log to be combined with retrieved error log 1176 * @len: length of driver log 1177 * 1178 * Retrieve the temporary or permanent error from the PE. 1179 */ 1180 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 1181 char *drv_log, unsigned long len) 1182 { 1183 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1184 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 1185 1186 return 0; 1187 } 1188 1189 /** 1190 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 1191 * @pe: EEH PE 1192 * 1193 * The function will be called to reconfigure the bridges included 1194 * in the specified PE so that the mulfunctional PE would be recovered 1195 * again. 1196 */ 1197 static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 1198 { 1199 return 0; 1200 } 1201 1202 /** 1203 * pnv_pe_err_inject - Inject specified error to the indicated PE 1204 * @pe: the indicated PE 1205 * @type: error type 1206 * @func: specific error type 1207 * @addr: address 1208 * @mask: address mask 1209 * 1210 * The routine is called to inject specified error, which is 1211 * determined by @type and @func, to the indicated PE for 1212 * testing purpose. 1213 */ 1214 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1215 unsigned long addr, unsigned long mask) 1216 { 1217 struct pci_controller *hose = pe->phb; 1218 struct pnv_phb *phb = hose->private_data; 1219 s64 rc; 1220 1221 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1222 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1223 pr_warn("%s: Invalid error type %d\n", 1224 __func__, type); 1225 return -ERANGE; 1226 } 1227 1228 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1229 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1230 pr_warn("%s: Invalid error function %d\n", 1231 __func__, func); 1232 return -ERANGE; 1233 } 1234 1235 /* Firmware supports error injection ? */ 1236 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1237 pr_warn("%s: Firmware doesn't support error injection\n", 1238 __func__); 1239 return -ENXIO; 1240 } 1241 1242 /* Do error injection */ 1243 rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1244 type, func, addr, mask); 1245 if (rc != OPAL_SUCCESS) { 1246 pr_warn("%s: Failure %lld injecting error " 1247 "%d-%d to PHB#%x-PE#%x\n", 1248 __func__, rc, type, func, 1249 hose->global_number, pe->addr); 1250 return -EIO; 1251 } 1252 1253 return 0; 1254 } 1255 1256 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1257 { 1258 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1259 1260 if (!edev || !edev->pe) 1261 return false; 1262 1263 /* 1264 * We will issue FLR or AF FLR to all VFs, which are contained 1265 * in VF PE. It relies on the EEH PCI config accessors. So we 1266 * can't block them during the window. 1267 */ 1268 if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 1269 return false; 1270 1271 if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1272 return true; 1273 1274 return false; 1275 } 1276 1277 static int pnv_eeh_read_config(struct eeh_dev *edev, 1278 int where, int size, u32 *val) 1279 { 1280 struct pci_dn *pdn = eeh_dev_to_pdn(edev); 1281 1282 if (!pdn) 1283 return PCIBIOS_DEVICE_NOT_FOUND; 1284 1285 if (pnv_eeh_cfg_blocked(pdn)) { 1286 *val = 0xFFFFFFFF; 1287 return PCIBIOS_SET_FAILED; 1288 } 1289 1290 return pnv_pci_cfg_read(pdn, where, size, val); 1291 } 1292 1293 static int pnv_eeh_write_config(struct eeh_dev *edev, 1294 int where, int size, u32 val) 1295 { 1296 struct pci_dn *pdn = eeh_dev_to_pdn(edev); 1297 1298 if (!pdn) 1299 return PCIBIOS_DEVICE_NOT_FOUND; 1300 1301 if (pnv_eeh_cfg_blocked(pdn)) 1302 return PCIBIOS_SET_FAILED; 1303 1304 return pnv_pci_cfg_write(pdn, where, size, val); 1305 } 1306 1307 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 1308 { 1309 /* GEM */ 1310 if (data->gemXfir || data->gemRfir || 1311 data->gemRirqfir || data->gemMask || data->gemRwof) 1312 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 1313 be64_to_cpu(data->gemXfir), 1314 be64_to_cpu(data->gemRfir), 1315 be64_to_cpu(data->gemRirqfir), 1316 be64_to_cpu(data->gemMask), 1317 be64_to_cpu(data->gemRwof)); 1318 1319 /* LEM */ 1320 if (data->lemFir || data->lemErrMask || 1321 data->lemAction0 || data->lemAction1 || data->lemWof) 1322 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 1323 be64_to_cpu(data->lemFir), 1324 be64_to_cpu(data->lemErrMask), 1325 be64_to_cpu(data->lemAction0), 1326 be64_to_cpu(data->lemAction1), 1327 be64_to_cpu(data->lemWof)); 1328 } 1329 1330 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 1331 { 1332 struct pnv_phb *phb = hose->private_data; 1333 struct OpalIoP7IOCErrorData *data = 1334 (struct OpalIoP7IOCErrorData*)phb->diag_data; 1335 long rc; 1336 1337 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 1338 if (rc != OPAL_SUCCESS) { 1339 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 1340 __func__, phb->hub_id, rc); 1341 return; 1342 } 1343 1344 switch (be16_to_cpu(data->type)) { 1345 case OPAL_P7IOC_DIAG_TYPE_RGC: 1346 pr_info("P7IOC diag-data for RGC\n\n"); 1347 pnv_eeh_dump_hub_diag_common(data); 1348 if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 1349 pr_info(" RGC: %016llx %016llx\n", 1350 be64_to_cpu(data->rgc.rgcStatus), 1351 be64_to_cpu(data->rgc.rgcLdcp)); 1352 break; 1353 case OPAL_P7IOC_DIAG_TYPE_BI: 1354 pr_info("P7IOC diag-data for BI %s\n\n", 1355 data->bi.biDownbound ? "Downbound" : "Upbound"); 1356 pnv_eeh_dump_hub_diag_common(data); 1357 if (data->bi.biLdcp0 || data->bi.biLdcp1 || 1358 data->bi.biLdcp2 || data->bi.biFenceStatus) 1359 pr_info(" BI: %016llx %016llx %016llx %016llx\n", 1360 be64_to_cpu(data->bi.biLdcp0), 1361 be64_to_cpu(data->bi.biLdcp1), 1362 be64_to_cpu(data->bi.biLdcp2), 1363 be64_to_cpu(data->bi.biFenceStatus)); 1364 break; 1365 case OPAL_P7IOC_DIAG_TYPE_CI: 1366 pr_info("P7IOC diag-data for CI Port %d\n\n", 1367 data->ci.ciPort); 1368 pnv_eeh_dump_hub_diag_common(data); 1369 if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 1370 pr_info(" CI: %016llx %016llx\n", 1371 be64_to_cpu(data->ci.ciPortStatus), 1372 be64_to_cpu(data->ci.ciPortLdcp)); 1373 break; 1374 case OPAL_P7IOC_DIAG_TYPE_MISC: 1375 pr_info("P7IOC diag-data for MISC\n\n"); 1376 pnv_eeh_dump_hub_diag_common(data); 1377 break; 1378 case OPAL_P7IOC_DIAG_TYPE_I2C: 1379 pr_info("P7IOC diag-data for I2C\n\n"); 1380 pnv_eeh_dump_hub_diag_common(data); 1381 break; 1382 default: 1383 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 1384 __func__, phb->hub_id, data->type); 1385 } 1386 } 1387 1388 static int pnv_eeh_get_pe(struct pci_controller *hose, 1389 u16 pe_no, struct eeh_pe **pe) 1390 { 1391 struct pnv_phb *phb = hose->private_data; 1392 struct pnv_ioda_pe *pnv_pe; 1393 struct eeh_pe *dev_pe; 1394 1395 /* 1396 * If PHB supports compound PE, to fetch 1397 * the master PE because slave PE is invisible 1398 * to EEH core. 1399 */ 1400 pnv_pe = &phb->ioda.pe_array[pe_no]; 1401 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 1402 pnv_pe = pnv_pe->master; 1403 WARN_ON(!pnv_pe || 1404 !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 1405 pe_no = pnv_pe->pe_number; 1406 } 1407 1408 /* Find the PE according to PE# */ 1409 dev_pe = eeh_pe_get(hose, pe_no, 0); 1410 if (!dev_pe) 1411 return -EEXIST; 1412 1413 /* Freeze the (compound) PE */ 1414 *pe = dev_pe; 1415 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1416 phb->freeze_pe(phb, pe_no); 1417 1418 /* 1419 * At this point, we're sure the (compound) PE should 1420 * have been frozen. However, we still need poke until 1421 * hitting the frozen PE on top level. 1422 */ 1423 dev_pe = dev_pe->parent; 1424 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 1425 int ret; 1426 ret = eeh_ops->get_state(dev_pe, NULL); 1427 if (ret <= 0 || eeh_state_active(ret)) { 1428 dev_pe = dev_pe->parent; 1429 continue; 1430 } 1431 1432 /* Frozen parent PE */ 1433 *pe = dev_pe; 1434 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1435 phb->freeze_pe(phb, dev_pe->addr); 1436 1437 /* Next one */ 1438 dev_pe = dev_pe->parent; 1439 } 1440 1441 return 0; 1442 } 1443 1444 /** 1445 * pnv_eeh_next_error - Retrieve next EEH error to handle 1446 * @pe: Affected PE 1447 * 1448 * The function is expected to be called by EEH core while it gets 1449 * special EEH event (without binding PE). The function calls to 1450 * OPAL APIs for next error to handle. The informational error is 1451 * handled internally by platform. However, the dead IOC, dead PHB, 1452 * fenced PHB and frozen PE should be handled by EEH core eventually. 1453 */ 1454 static int pnv_eeh_next_error(struct eeh_pe **pe) 1455 { 1456 struct pci_controller *hose; 1457 struct pnv_phb *phb; 1458 struct eeh_pe *phb_pe, *parent_pe; 1459 __be64 frozen_pe_no; 1460 __be16 err_type, severity; 1461 long rc; 1462 int state, ret = EEH_NEXT_ERR_NONE; 1463 1464 /* 1465 * While running here, it's safe to purge the event queue. The 1466 * event should still be masked. 1467 */ 1468 eeh_remove_event(NULL, false); 1469 1470 list_for_each_entry(hose, &hose_list, list_node) { 1471 /* 1472 * If the subordinate PCI buses of the PHB has been 1473 * removed or is exactly under error recovery, we 1474 * needn't take care of it any more. 1475 */ 1476 phb = hose->private_data; 1477 phb_pe = eeh_phb_pe_get(hose); 1478 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 1479 continue; 1480 1481 rc = opal_pci_next_error(phb->opal_id, 1482 &frozen_pe_no, &err_type, &severity); 1483 if (rc != OPAL_SUCCESS) { 1484 pr_devel("%s: Invalid return value on " 1485 "PHB#%x (0x%lx) from opal_pci_next_error", 1486 __func__, hose->global_number, rc); 1487 continue; 1488 } 1489 1490 /* If the PHB doesn't have error, stop processing */ 1491 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 1492 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 1493 pr_devel("%s: No error found on PHB#%x\n", 1494 __func__, hose->global_number); 1495 continue; 1496 } 1497 1498 /* 1499 * Processing the error. We're expecting the error with 1500 * highest priority reported upon multiple errors on the 1501 * specific PHB. 1502 */ 1503 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 1504 __func__, be16_to_cpu(err_type), 1505 be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 1506 hose->global_number); 1507 switch (be16_to_cpu(err_type)) { 1508 case OPAL_EEH_IOC_ERROR: 1509 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 1510 pr_err("EEH: dead IOC detected\n"); 1511 ret = EEH_NEXT_ERR_DEAD_IOC; 1512 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1513 pr_info("EEH: IOC informative error " 1514 "detected\n"); 1515 pnv_eeh_get_and_dump_hub_diag(hose); 1516 ret = EEH_NEXT_ERR_NONE; 1517 } 1518 1519 break; 1520 case OPAL_EEH_PHB_ERROR: 1521 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 1522 *pe = phb_pe; 1523 pr_err("EEH: dead PHB#%x detected, " 1524 "location: %s\n", 1525 hose->global_number, 1526 eeh_pe_loc_get(phb_pe)); 1527 ret = EEH_NEXT_ERR_DEAD_PHB; 1528 } else if (be16_to_cpu(severity) == 1529 OPAL_EEH_SEV_PHB_FENCED) { 1530 *pe = phb_pe; 1531 pr_err("EEH: Fenced PHB#%x detected, " 1532 "location: %s\n", 1533 hose->global_number, 1534 eeh_pe_loc_get(phb_pe)); 1535 ret = EEH_NEXT_ERR_FENCED_PHB; 1536 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1537 pr_info("EEH: PHB#%x informative error " 1538 "detected, location: %s\n", 1539 hose->global_number, 1540 eeh_pe_loc_get(phb_pe)); 1541 pnv_eeh_get_phb_diag(phb_pe); 1542 pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 1543 ret = EEH_NEXT_ERR_NONE; 1544 } 1545 1546 break; 1547 case OPAL_EEH_PE_ERROR: 1548 /* 1549 * If we can't find the corresponding PE, we 1550 * just try to unfreeze. 1551 */ 1552 if (pnv_eeh_get_pe(hose, 1553 be64_to_cpu(frozen_pe_no), pe)) { 1554 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 1555 hose->global_number, be64_to_cpu(frozen_pe_no)); 1556 pr_info("EEH: PHB location: %s\n", 1557 eeh_pe_loc_get(phb_pe)); 1558 1559 /* Dump PHB diag-data */ 1560 rc = opal_pci_get_phb_diag_data2(phb->opal_id, 1561 phb->diag_data, phb->diag_data_size); 1562 if (rc == OPAL_SUCCESS) 1563 pnv_pci_dump_phb_diag_data(hose, 1564 phb->diag_data); 1565 1566 /* Try best to clear it */ 1567 opal_pci_eeh_freeze_clear(phb->opal_id, 1568 be64_to_cpu(frozen_pe_no), 1569 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 1570 ret = EEH_NEXT_ERR_NONE; 1571 } else if ((*pe)->state & EEH_PE_ISOLATED || 1572 eeh_pe_passed(*pe)) { 1573 ret = EEH_NEXT_ERR_NONE; 1574 } else { 1575 pr_err("EEH: Frozen PE#%x " 1576 "on PHB#%x detected\n", 1577 (*pe)->addr, 1578 (*pe)->phb->global_number); 1579 pr_err("EEH: PE location: %s, " 1580 "PHB location: %s\n", 1581 eeh_pe_loc_get(*pe), 1582 eeh_pe_loc_get(phb_pe)); 1583 ret = EEH_NEXT_ERR_FROZEN_PE; 1584 } 1585 1586 break; 1587 default: 1588 pr_warn("%s: Unexpected error type %d\n", 1589 __func__, be16_to_cpu(err_type)); 1590 } 1591 1592 /* 1593 * EEH core will try recover from fenced PHB or 1594 * frozen PE. In the time for frozen PE, EEH core 1595 * enable IO path for that before collecting logs, 1596 * but it ruins the site. So we have to dump the 1597 * log in advance here. 1598 */ 1599 if ((ret == EEH_NEXT_ERR_FROZEN_PE || 1600 ret == EEH_NEXT_ERR_FENCED_PHB) && 1601 !((*pe)->state & EEH_PE_ISOLATED)) { 1602 eeh_pe_mark_isolated(*pe); 1603 pnv_eeh_get_phb_diag(*pe); 1604 1605 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1606 pnv_pci_dump_phb_diag_data((*pe)->phb, 1607 (*pe)->data); 1608 } 1609 1610 /* 1611 * We probably have the frozen parent PE out there and 1612 * we need have to handle frozen parent PE firstly. 1613 */ 1614 if (ret == EEH_NEXT_ERR_FROZEN_PE) { 1615 parent_pe = (*pe)->parent; 1616 while (parent_pe) { 1617 /* Hit the ceiling ? */ 1618 if (parent_pe->type & EEH_PE_PHB) 1619 break; 1620 1621 /* Frozen parent PE ? */ 1622 state = eeh_ops->get_state(parent_pe, NULL); 1623 if (state > 0 && !eeh_state_active(state)) 1624 *pe = parent_pe; 1625 1626 /* Next parent level */ 1627 parent_pe = parent_pe->parent; 1628 } 1629 1630 /* We possibly migrate to another PE */ 1631 eeh_pe_mark_isolated(*pe); 1632 } 1633 1634 /* 1635 * If we have no errors on the specific PHB or only 1636 * informative error there, we continue poking it. 1637 * Otherwise, we need actions to be taken by upper 1638 * layer. 1639 */ 1640 if (ret > EEH_NEXT_ERR_INF) 1641 break; 1642 } 1643 1644 /* Unmask the event */ 1645 if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 1646 enable_irq(eeh_event_irq); 1647 1648 return ret; 1649 } 1650 1651 static int pnv_eeh_restore_config(struct eeh_dev *edev) 1652 { 1653 struct pnv_phb *phb; 1654 s64 ret = 0; 1655 1656 if (!edev) 1657 return -EEXIST; 1658 1659 if (edev->physfn) 1660 return 0; 1661 1662 phb = edev->controller->private_data; 1663 ret = opal_pci_reinit(phb->opal_id, 1664 OPAL_REINIT_PCI_DEV, edev->bdfn); 1665 1666 if (ret) { 1667 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 1668 __func__, edev->bdfn, ret); 1669 return -EIO; 1670 } 1671 1672 return ret; 1673 } 1674 1675 static struct eeh_ops pnv_eeh_ops = { 1676 .name = "powernv", 1677 .init = pnv_eeh_init, 1678 .probe = pnv_eeh_probe, 1679 .set_option = pnv_eeh_set_option, 1680 .get_state = pnv_eeh_get_state, 1681 .reset = pnv_eeh_reset, 1682 .get_log = pnv_eeh_get_log, 1683 .configure_bridge = pnv_eeh_configure_bridge, 1684 .err_inject = pnv_eeh_err_inject, 1685 .read_config = pnv_eeh_read_config, 1686 .write_config = pnv_eeh_write_config, 1687 .next_error = pnv_eeh_next_error, 1688 .restore_config = pnv_eeh_restore_config, 1689 .notify_resume = NULL 1690 }; 1691 1692 #ifdef CONFIG_PCI_IOV 1693 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 1694 { 1695 struct pci_dn *pdn = pci_get_pdn(pdev); 1696 int parent_mps; 1697 1698 if (!pdev->is_virtfn) 1699 return; 1700 1701 /* Synchronize MPS for VF and PF */ 1702 parent_mps = pcie_get_mps(pdev->physfn); 1703 if ((128 << pdev->pcie_mpss) >= parent_mps) 1704 pcie_set_mps(pdev, parent_mps); 1705 pdn->mps = pcie_get_mps(pdev); 1706 } 1707 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 1708 #endif /* CONFIG_PCI_IOV */ 1709 1710 /** 1711 * eeh_powernv_init - Register platform dependent EEH operations 1712 * 1713 * EEH initialization on powernv platform. This function should be 1714 * called before any EEH related functions. 1715 */ 1716 static int __init eeh_powernv_init(void) 1717 { 1718 int ret = -EINVAL; 1719 1720 ret = eeh_ops_register(&pnv_eeh_ops); 1721 if (!ret) 1722 pr_info("EEH: PowerNV platform initialized\n"); 1723 else 1724 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 1725 1726 return ret; 1727 } 1728 machine_early_initcall(powernv, eeh_powernv_init); 1729