1 /* 2 * The file intends to implement the platform dependent EEH operations on 3 * powernv platform. Actually, the powernv was created in order to fully 4 * hypervisor support. 5 * 6 * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/atomic.h> 15 #include <linux/debugfs.h> 16 #include <linux/delay.h> 17 #include <linux/export.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/list.h> 21 #include <linux/msi.h> 22 #include <linux/of.h> 23 #include <linux/pci.h> 24 #include <linux/proc_fs.h> 25 #include <linux/rbtree.h> 26 #include <linux/sched.h> 27 #include <linux/seq_file.h> 28 #include <linux/spinlock.h> 29 30 #include <asm/eeh.h> 31 #include <asm/eeh_event.h> 32 #include <asm/firmware.h> 33 #include <asm/io.h> 34 #include <asm/iommu.h> 35 #include <asm/machdep.h> 36 #include <asm/msi_bitmap.h> 37 #include <asm/opal.h> 38 #include <asm/ppc-pci.h> 39 40 #include "powernv.h" 41 #include "pci.h" 42 43 static bool pnv_eeh_nb_init = false; 44 static int eeh_event_irq = -EINVAL; 45 46 static int pnv_eeh_init(void) 47 { 48 struct pci_controller *hose; 49 struct pnv_phb *phb; 50 51 if (!firmware_has_feature(FW_FEATURE_OPAL)) { 52 pr_warn("%s: OPAL is required !\n", 53 __func__); 54 return -EINVAL; 55 } 56 57 /* Set probe mode */ 58 eeh_add_flag(EEH_PROBE_MODE_DEV); 59 60 /* 61 * P7IOC blocks PCI config access to frozen PE, but PHB3 62 * doesn't do that. So we have to selectively enable I/O 63 * prior to collecting error log. 64 */ 65 list_for_each_entry(hose, &hose_list, list_node) { 66 phb = hose->private_data; 67 68 if (phb->model == PNV_PHB_MODEL_P7IOC) 69 eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 70 71 /* 72 * PE#0 should be regarded as valid by EEH core 73 * if it's not the reserved one. Currently, we 74 * have the reserved PE#255 and PE#127 for PHB3 75 * and P7IOC separately. So we should regard 76 * PE#0 as valid for PHB3 and P7IOC. 77 */ 78 if (phb->ioda.reserved_pe != 0) 79 eeh_add_flag(EEH_VALID_PE_ZERO); 80 81 break; 82 } 83 84 return 0; 85 } 86 87 static irqreturn_t pnv_eeh_event(int irq, void *data) 88 { 89 /* 90 * We simply send a special EEH event if EEH has been 91 * enabled. We don't care about EEH events until we've 92 * finished processing the outstanding ones. Event processing 93 * gets unmasked in next_error() if EEH is enabled. 94 */ 95 disable_irq_nosync(irq); 96 97 if (eeh_enabled()) 98 eeh_send_failure_event(NULL); 99 100 return IRQ_HANDLED; 101 } 102 103 #ifdef CONFIG_DEBUG_FS 104 static ssize_t pnv_eeh_ei_write(struct file *filp, 105 const char __user *user_buf, 106 size_t count, loff_t *ppos) 107 { 108 struct pci_controller *hose = filp->private_data; 109 struct eeh_dev *edev; 110 struct eeh_pe *pe; 111 int pe_no, type, func; 112 unsigned long addr, mask; 113 char buf[50]; 114 int ret; 115 116 if (!eeh_ops || !eeh_ops->err_inject) 117 return -ENXIO; 118 119 /* Copy over argument buffer */ 120 ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 121 if (!ret) 122 return -EFAULT; 123 124 /* Retrieve parameters */ 125 ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 126 &pe_no, &type, &func, &addr, &mask); 127 if (ret != 5) 128 return -EINVAL; 129 130 /* Retrieve PE */ 131 edev = kzalloc(sizeof(*edev), GFP_KERNEL); 132 if (!edev) 133 return -ENOMEM; 134 edev->phb = hose; 135 edev->pe_config_addr = pe_no; 136 pe = eeh_pe_get(edev); 137 kfree(edev); 138 if (!pe) 139 return -ENODEV; 140 141 /* Do error injection */ 142 ret = eeh_ops->err_inject(pe, type, func, addr, mask); 143 return ret < 0 ? ret : count; 144 } 145 146 static const struct file_operations pnv_eeh_ei_fops = { 147 .open = simple_open, 148 .llseek = no_llseek, 149 .write = pnv_eeh_ei_write, 150 }; 151 152 static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 153 { 154 struct pci_controller *hose = data; 155 struct pnv_phb *phb = hose->private_data; 156 157 out_be64(phb->regs + offset, val); 158 return 0; 159 } 160 161 static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 162 { 163 struct pci_controller *hose = data; 164 struct pnv_phb *phb = hose->private_data; 165 166 *val = in_be64(phb->regs + offset); 167 return 0; 168 } 169 170 #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 171 static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 172 { \ 173 return pnv_eeh_dbgfs_set(data, reg, val); \ 174 } \ 175 \ 176 static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 177 { \ 178 return pnv_eeh_dbgfs_get(data, reg, val); \ 179 } \ 180 \ 181 DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 182 pnv_eeh_dbgfs_get_##name, \ 183 pnv_eeh_dbgfs_set_##name, \ 184 "0x%llx\n") 185 186 PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 187 PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 188 PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 189 190 #endif /* CONFIG_DEBUG_FS */ 191 192 /** 193 * pnv_eeh_post_init - EEH platform dependent post initialization 194 * 195 * EEH platform dependent post initialization on powernv. When 196 * the function is called, the EEH PEs and devices should have 197 * been built. If the I/O cache staff has been built, EEH is 198 * ready to supply service. 199 */ 200 static int pnv_eeh_post_init(void) 201 { 202 struct pci_controller *hose; 203 struct pnv_phb *phb; 204 int ret = 0; 205 206 /* Register OPAL event notifier */ 207 if (!pnv_eeh_nb_init) { 208 eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 209 if (eeh_event_irq < 0) { 210 pr_err("%s: Can't register OPAL event interrupt (%d)\n", 211 __func__, eeh_event_irq); 212 return eeh_event_irq; 213 } 214 215 ret = request_irq(eeh_event_irq, pnv_eeh_event, 216 IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 217 if (ret < 0) { 218 irq_dispose_mapping(eeh_event_irq); 219 pr_err("%s: Can't request OPAL event interrupt (%d)\n", 220 __func__, eeh_event_irq); 221 return ret; 222 } 223 224 pnv_eeh_nb_init = true; 225 } 226 227 if (!eeh_enabled()) 228 disable_irq(eeh_event_irq); 229 230 list_for_each_entry(hose, &hose_list, list_node) { 231 phb = hose->private_data; 232 233 /* 234 * If EEH is enabled, we're going to rely on that. 235 * Otherwise, we restore to conventional mechanism 236 * to clear frozen PE during PCI config access. 237 */ 238 if (eeh_enabled()) 239 phb->flags |= PNV_PHB_FLAG_EEH; 240 else 241 phb->flags &= ~PNV_PHB_FLAG_EEH; 242 243 /* Create debugfs entries */ 244 #ifdef CONFIG_DEBUG_FS 245 if (phb->has_dbgfs || !phb->dbgfs) 246 continue; 247 248 phb->has_dbgfs = 1; 249 debugfs_create_file("err_injct", 0200, 250 phb->dbgfs, hose, 251 &pnv_eeh_ei_fops); 252 253 debugfs_create_file("err_injct_outbound", 0600, 254 phb->dbgfs, hose, 255 &pnv_eeh_dbgfs_ops_outb); 256 debugfs_create_file("err_injct_inboundA", 0600, 257 phb->dbgfs, hose, 258 &pnv_eeh_dbgfs_ops_inbA); 259 debugfs_create_file("err_injct_inboundB", 0600, 260 phb->dbgfs, hose, 261 &pnv_eeh_dbgfs_ops_inbB); 262 #endif /* CONFIG_DEBUG_FS */ 263 } 264 265 return ret; 266 } 267 268 static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 269 { 270 int pos = PCI_CAPABILITY_LIST; 271 int cnt = 48; /* Maximal number of capabilities */ 272 u32 status, id; 273 274 if (!pdn) 275 return 0; 276 277 /* Check if the device supports capabilities */ 278 pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 279 if (!(status & PCI_STATUS_CAP_LIST)) 280 return 0; 281 282 while (cnt--) { 283 pnv_pci_cfg_read(pdn, pos, 1, &pos); 284 if (pos < 0x40) 285 break; 286 287 pos &= ~3; 288 pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 289 if (id == 0xff) 290 break; 291 292 /* Found */ 293 if (id == cap) 294 return pos; 295 296 /* Next one */ 297 pos += PCI_CAP_LIST_NEXT; 298 } 299 300 return 0; 301 } 302 303 static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 304 { 305 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 306 u32 header; 307 int pos = 256, ttl = (4096 - 256) / 8; 308 309 if (!edev || !edev->pcie_cap) 310 return 0; 311 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 312 return 0; 313 else if (!header) 314 return 0; 315 316 while (ttl-- > 0) { 317 if (PCI_EXT_CAP_ID(header) == cap && pos) 318 return pos; 319 320 pos = PCI_EXT_CAP_NEXT(header); 321 if (pos < 256) 322 break; 323 324 if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 325 break; 326 } 327 328 return 0; 329 } 330 331 /** 332 * pnv_eeh_probe - Do probe on PCI device 333 * @pdn: PCI device node 334 * @data: unused 335 * 336 * When EEH module is installed during system boot, all PCI devices 337 * are checked one by one to see if it supports EEH. The function 338 * is introduced for the purpose. By default, EEH has been enabled 339 * on all PCI devices. That's to say, we only need do necessary 340 * initialization on the corresponding eeh device and create PE 341 * accordingly. 342 * 343 * It's notable that's unsafe to retrieve the EEH device through 344 * the corresponding PCI device. During the PCI device hotplug, which 345 * was possiblly triggered by EEH core, the binding between EEH device 346 * and the PCI device isn't built yet. 347 */ 348 static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 349 { 350 struct pci_controller *hose = pdn->phb; 351 struct pnv_phb *phb = hose->private_data; 352 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 353 uint32_t pcie_flags; 354 int ret; 355 356 /* 357 * When probing the root bridge, which doesn't have any 358 * subordinate PCI devices. We don't have OF node for 359 * the root bridge. So it's not reasonable to continue 360 * the probing. 361 */ 362 if (!edev || edev->pe) 363 return NULL; 364 365 /* Skip for PCI-ISA bridge */ 366 if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 367 return NULL; 368 369 /* Initialize eeh device */ 370 edev->class_code = pdn->class_code; 371 edev->mode &= 0xFFFFFF00; 372 edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 373 edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 374 edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 375 edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 376 if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 377 edev->mode |= EEH_DEV_BRIDGE; 378 if (edev->pcie_cap) { 379 pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 380 2, &pcie_flags); 381 pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 382 if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 383 edev->mode |= EEH_DEV_ROOT_PORT; 384 else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 385 edev->mode |= EEH_DEV_DS_PORT; 386 } 387 } 388 389 edev->config_addr = (pdn->busno << 8) | (pdn->devfn); 390 edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr]; 391 392 /* Create PE */ 393 ret = eeh_add_to_parent_pe(edev); 394 if (ret) { 395 pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%d)\n", 396 __func__, hose->global_number, pdn->busno, 397 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 398 return NULL; 399 } 400 401 /* 402 * If the PE contains any one of following adapters, the 403 * PCI config space can't be accessed when dumping EEH log. 404 * Otherwise, we will run into fenced PHB caused by shortage 405 * of outbound credits in the adapter. The PCI config access 406 * should be blocked until PE reset. MMIO access is dropped 407 * by hardware certainly. In order to drop PCI config requests, 408 * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 409 * will be checked in the backend for PE state retrival. If 410 * the PE becomes frozen for the first time and the flag has 411 * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 412 * that PE to block its config space. 413 * 414 * Broadcom Austin 4-ports NICs (14e4:1657) 415 * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 416 * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 417 */ 418 if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 419 pdn->device_id == 0x1657) || 420 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 421 pdn->device_id == 0x168a) || 422 (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 423 pdn->device_id == 0x168e)) 424 edev->pe->state |= EEH_PE_CFG_RESTRICTED; 425 426 /* 427 * Cache the PE primary bus, which can't be fetched when 428 * full hotplug is in progress. In that case, all child 429 * PCI devices of the PE are expected to be removed prior 430 * to PE reset. 431 */ 432 if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 433 edev->pe->bus = pci_find_bus(hose->global_number, 434 pdn->busno); 435 if (edev->pe->bus) 436 edev->pe->state |= EEH_PE_PRI_BUS; 437 } 438 439 /* 440 * Enable EEH explicitly so that we will do EEH check 441 * while accessing I/O stuff 442 */ 443 eeh_add_flag(EEH_ENABLED); 444 445 /* Save memory bars */ 446 eeh_save_bars(edev); 447 448 return NULL; 449 } 450 451 /** 452 * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 453 * @pe: EEH PE 454 * @option: operation to be issued 455 * 456 * The function is used to control the EEH functionality globally. 457 * Currently, following options are support according to PAPR: 458 * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 459 */ 460 static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 461 { 462 struct pci_controller *hose = pe->phb; 463 struct pnv_phb *phb = hose->private_data; 464 bool freeze_pe = false; 465 int opt; 466 s64 rc; 467 468 switch (option) { 469 case EEH_OPT_DISABLE: 470 return -EPERM; 471 case EEH_OPT_ENABLE: 472 return 0; 473 case EEH_OPT_THAW_MMIO: 474 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 475 break; 476 case EEH_OPT_THAW_DMA: 477 opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 478 break; 479 case EEH_OPT_FREEZE_PE: 480 freeze_pe = true; 481 opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 482 break; 483 default: 484 pr_warn("%s: Invalid option %d\n", __func__, option); 485 return -EINVAL; 486 } 487 488 /* Freeze master and slave PEs if PHB supports compound PEs */ 489 if (freeze_pe) { 490 if (phb->freeze_pe) { 491 phb->freeze_pe(phb, pe->addr); 492 return 0; 493 } 494 495 rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 496 if (rc != OPAL_SUCCESS) { 497 pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 498 __func__, rc, phb->hose->global_number, 499 pe->addr); 500 return -EIO; 501 } 502 503 return 0; 504 } 505 506 /* Unfreeze master and slave PEs if PHB supports */ 507 if (phb->unfreeze_pe) 508 return phb->unfreeze_pe(phb, pe->addr, opt); 509 510 rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 511 if (rc != OPAL_SUCCESS) { 512 pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 513 __func__, rc, option, phb->hose->global_number, 514 pe->addr); 515 return -EIO; 516 } 517 518 return 0; 519 } 520 521 /** 522 * pnv_eeh_get_pe_addr - Retrieve PE address 523 * @pe: EEH PE 524 * 525 * Retrieve the PE address according to the given tranditional 526 * PCI BDF (Bus/Device/Function) address. 527 */ 528 static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 529 { 530 return pe->addr; 531 } 532 533 static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 534 { 535 struct pnv_phb *phb = pe->phb->private_data; 536 s64 rc; 537 538 rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 539 PNV_PCI_DIAG_BUF_SIZE); 540 if (rc != OPAL_SUCCESS) 541 pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 542 __func__, rc, pe->phb->global_number); 543 } 544 545 static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 546 { 547 struct pnv_phb *phb = pe->phb->private_data; 548 u8 fstate; 549 __be16 pcierr; 550 s64 rc; 551 int result = 0; 552 553 rc = opal_pci_eeh_freeze_status(phb->opal_id, 554 pe->addr, 555 &fstate, 556 &pcierr, 557 NULL); 558 if (rc != OPAL_SUCCESS) { 559 pr_warn("%s: Failure %lld getting PHB#%x state\n", 560 __func__, rc, phb->hose->global_number); 561 return EEH_STATE_NOT_SUPPORT; 562 } 563 564 /* 565 * Check PHB state. If the PHB is frozen for the 566 * first time, to dump the PHB diag-data. 567 */ 568 if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 569 result = (EEH_STATE_MMIO_ACTIVE | 570 EEH_STATE_DMA_ACTIVE | 571 EEH_STATE_MMIO_ENABLED | 572 EEH_STATE_DMA_ENABLED); 573 } else if (!(pe->state & EEH_PE_ISOLATED)) { 574 eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 575 pnv_eeh_get_phb_diag(pe); 576 577 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 578 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 579 } 580 581 return result; 582 } 583 584 static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 585 { 586 struct pnv_phb *phb = pe->phb->private_data; 587 u8 fstate; 588 __be16 pcierr; 589 s64 rc; 590 int result; 591 592 /* 593 * We don't clobber hardware frozen state until PE 594 * reset is completed. In order to keep EEH core 595 * moving forward, we have to return operational 596 * state during PE reset. 597 */ 598 if (pe->state & EEH_PE_RESET) { 599 result = (EEH_STATE_MMIO_ACTIVE | 600 EEH_STATE_DMA_ACTIVE | 601 EEH_STATE_MMIO_ENABLED | 602 EEH_STATE_DMA_ENABLED); 603 return result; 604 } 605 606 /* 607 * Fetch PE state from hardware. If the PHB 608 * supports compound PE, let it handle that. 609 */ 610 if (phb->get_pe_state) { 611 fstate = phb->get_pe_state(phb, pe->addr); 612 } else { 613 rc = opal_pci_eeh_freeze_status(phb->opal_id, 614 pe->addr, 615 &fstate, 616 &pcierr, 617 NULL); 618 if (rc != OPAL_SUCCESS) { 619 pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 620 __func__, rc, phb->hose->global_number, 621 pe->addr); 622 return EEH_STATE_NOT_SUPPORT; 623 } 624 } 625 626 /* Figure out state */ 627 switch (fstate) { 628 case OPAL_EEH_STOPPED_NOT_FROZEN: 629 result = (EEH_STATE_MMIO_ACTIVE | 630 EEH_STATE_DMA_ACTIVE | 631 EEH_STATE_MMIO_ENABLED | 632 EEH_STATE_DMA_ENABLED); 633 break; 634 case OPAL_EEH_STOPPED_MMIO_FREEZE: 635 result = (EEH_STATE_DMA_ACTIVE | 636 EEH_STATE_DMA_ENABLED); 637 break; 638 case OPAL_EEH_STOPPED_DMA_FREEZE: 639 result = (EEH_STATE_MMIO_ACTIVE | 640 EEH_STATE_MMIO_ENABLED); 641 break; 642 case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 643 result = 0; 644 break; 645 case OPAL_EEH_STOPPED_RESET: 646 result = EEH_STATE_RESET_ACTIVE; 647 break; 648 case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 649 result = EEH_STATE_UNAVAILABLE; 650 break; 651 case OPAL_EEH_STOPPED_PERM_UNAVAIL: 652 result = EEH_STATE_NOT_SUPPORT; 653 break; 654 default: 655 result = EEH_STATE_NOT_SUPPORT; 656 pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 657 __func__, phb->hose->global_number, 658 pe->addr, fstate); 659 } 660 661 /* 662 * If PHB supports compound PE, to freeze all 663 * slave PEs for consistency. 664 * 665 * If the PE is switching to frozen state for the 666 * first time, to dump the PHB diag-data. 667 */ 668 if (!(result & EEH_STATE_NOT_SUPPORT) && 669 !(result & EEH_STATE_UNAVAILABLE) && 670 !(result & EEH_STATE_MMIO_ACTIVE) && 671 !(result & EEH_STATE_DMA_ACTIVE) && 672 !(pe->state & EEH_PE_ISOLATED)) { 673 if (phb->freeze_pe) 674 phb->freeze_pe(phb, pe->addr); 675 676 eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 677 pnv_eeh_get_phb_diag(pe); 678 679 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 680 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 681 } 682 683 return result; 684 } 685 686 /** 687 * pnv_eeh_get_state - Retrieve PE state 688 * @pe: EEH PE 689 * @delay: delay while PE state is temporarily unavailable 690 * 691 * Retrieve the state of the specified PE. For IODA-compitable 692 * platform, it should be retrieved from IODA table. Therefore, 693 * we prefer passing down to hardware implementation to handle 694 * it. 695 */ 696 static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 697 { 698 int ret; 699 700 if (pe->type & EEH_PE_PHB) 701 ret = pnv_eeh_get_phb_state(pe); 702 else 703 ret = pnv_eeh_get_pe_state(pe); 704 705 if (!delay) 706 return ret; 707 708 /* 709 * If the PE state is temporarily unavailable, 710 * to inform the EEH core delay for default 711 * period (1 second) 712 */ 713 *delay = 0; 714 if (ret & EEH_STATE_UNAVAILABLE) 715 *delay = 1000; 716 717 return ret; 718 } 719 720 static s64 pnv_eeh_phb_poll(struct pnv_phb *phb) 721 { 722 s64 rc = OPAL_HARDWARE; 723 724 while (1) { 725 rc = opal_pci_poll(phb->opal_id); 726 if (rc <= 0) 727 break; 728 729 if (system_state < SYSTEM_RUNNING) 730 udelay(1000 * rc); 731 else 732 msleep(rc); 733 } 734 735 return rc; 736 } 737 738 int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 739 { 740 struct pnv_phb *phb = hose->private_data; 741 s64 rc = OPAL_HARDWARE; 742 743 pr_debug("%s: Reset PHB#%x, option=%d\n", 744 __func__, hose->global_number, option); 745 746 /* Issue PHB complete reset request */ 747 if (option == EEH_RESET_FUNDAMENTAL || 748 option == EEH_RESET_HOT) 749 rc = opal_pci_reset(phb->opal_id, 750 OPAL_RESET_PHB_COMPLETE, 751 OPAL_ASSERT_RESET); 752 else if (option == EEH_RESET_DEACTIVATE) 753 rc = opal_pci_reset(phb->opal_id, 754 OPAL_RESET_PHB_COMPLETE, 755 OPAL_DEASSERT_RESET); 756 if (rc < 0) 757 goto out; 758 759 /* 760 * Poll state of the PHB until the request is done 761 * successfully. The PHB reset is usually PHB complete 762 * reset followed by hot reset on root bus. So we also 763 * need the PCI bus settlement delay. 764 */ 765 rc = pnv_eeh_phb_poll(phb); 766 if (option == EEH_RESET_DEACTIVATE) { 767 if (system_state < SYSTEM_RUNNING) 768 udelay(1000 * EEH_PE_RST_SETTLE_TIME); 769 else 770 msleep(EEH_PE_RST_SETTLE_TIME); 771 } 772 out: 773 if (rc != OPAL_SUCCESS) 774 return -EIO; 775 776 return 0; 777 } 778 779 static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 780 { 781 struct pnv_phb *phb = hose->private_data; 782 s64 rc = OPAL_HARDWARE; 783 784 pr_debug("%s: Reset PHB#%x, option=%d\n", 785 __func__, hose->global_number, option); 786 787 /* 788 * During the reset deassert time, we needn't care 789 * the reset scope because the firmware does nothing 790 * for fundamental or hot reset during deassert phase. 791 */ 792 if (option == EEH_RESET_FUNDAMENTAL) 793 rc = opal_pci_reset(phb->opal_id, 794 OPAL_RESET_PCI_FUNDAMENTAL, 795 OPAL_ASSERT_RESET); 796 else if (option == EEH_RESET_HOT) 797 rc = opal_pci_reset(phb->opal_id, 798 OPAL_RESET_PCI_HOT, 799 OPAL_ASSERT_RESET); 800 else if (option == EEH_RESET_DEACTIVATE) 801 rc = opal_pci_reset(phb->opal_id, 802 OPAL_RESET_PCI_HOT, 803 OPAL_DEASSERT_RESET); 804 if (rc < 0) 805 goto out; 806 807 /* Poll state of the PHB until the request is done */ 808 rc = pnv_eeh_phb_poll(phb); 809 if (option == EEH_RESET_DEACTIVATE) 810 msleep(EEH_PE_RST_SETTLE_TIME); 811 out: 812 if (rc != OPAL_SUCCESS) 813 return -EIO; 814 815 return 0; 816 } 817 818 static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 819 { 820 struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 821 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 822 int aer = edev ? edev->aer_cap : 0; 823 u32 ctrl; 824 825 pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 826 __func__, pci_domain_nr(dev->bus), 827 dev->bus->number, option); 828 829 switch (option) { 830 case EEH_RESET_FUNDAMENTAL: 831 case EEH_RESET_HOT: 832 /* Don't report linkDown event */ 833 if (aer) { 834 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 835 4, &ctrl); 836 ctrl |= PCI_ERR_UNC_SURPDN; 837 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 838 4, ctrl); 839 } 840 841 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 842 ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 843 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 844 845 msleep(EEH_PE_RST_HOLD_TIME); 846 break; 847 case EEH_RESET_DEACTIVATE: 848 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 849 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 850 eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 851 852 msleep(EEH_PE_RST_SETTLE_TIME); 853 854 /* Continue reporting linkDown event */ 855 if (aer) { 856 eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 857 4, &ctrl); 858 ctrl &= ~PCI_ERR_UNC_SURPDN; 859 eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 860 4, ctrl); 861 } 862 863 break; 864 } 865 866 return 0; 867 } 868 869 void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 870 { 871 struct pci_controller *hose; 872 873 if (pci_is_root_bus(dev->bus)) { 874 hose = pci_bus_to_host(dev->bus); 875 pnv_eeh_root_reset(hose, EEH_RESET_HOT); 876 pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 877 } else { 878 pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 879 pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 880 } 881 } 882 883 static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 884 int pos, u16 mask) 885 { 886 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 887 int i, status = 0; 888 889 /* Wait for Transaction Pending bit to be cleared */ 890 for (i = 0; i < 4; i++) { 891 eeh_ops->read_config(pdn, pos, 2, &status); 892 if (!(status & mask)) 893 return; 894 895 msleep((1 << i) * 100); 896 } 897 898 pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 899 __func__, type, 900 edev->phb->global_number, pdn->busno, 901 PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 902 } 903 904 static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 905 { 906 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 907 u32 reg = 0; 908 909 if (WARN_ON(!edev->pcie_cap)) 910 return -ENOTTY; 911 912 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 913 if (!(reg & PCI_EXP_DEVCAP_FLR)) 914 return -ENOTTY; 915 916 switch (option) { 917 case EEH_RESET_HOT: 918 case EEH_RESET_FUNDAMENTAL: 919 pnv_eeh_wait_for_pending(pdn, "", 920 edev->pcie_cap + PCI_EXP_DEVSTA, 921 PCI_EXP_DEVSTA_TRPND); 922 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 923 4, ®); 924 reg |= PCI_EXP_DEVCTL_BCR_FLR; 925 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 926 4, reg); 927 msleep(EEH_PE_RST_HOLD_TIME); 928 break; 929 case EEH_RESET_DEACTIVATE: 930 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 931 4, ®); 932 reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 933 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 934 4, reg); 935 msleep(EEH_PE_RST_SETTLE_TIME); 936 break; 937 } 938 939 return 0; 940 } 941 942 static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 943 { 944 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 945 u32 cap = 0; 946 947 if (WARN_ON(!edev->af_cap)) 948 return -ENOTTY; 949 950 eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 951 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 952 return -ENOTTY; 953 954 switch (option) { 955 case EEH_RESET_HOT: 956 case EEH_RESET_FUNDAMENTAL: 957 /* 958 * Wait for Transaction Pending bit to clear. A word-aligned 959 * test is used, so we use the conrol offset rather than status 960 * and shift the test bit to match. 961 */ 962 pnv_eeh_wait_for_pending(pdn, "AF", 963 edev->af_cap + PCI_AF_CTRL, 964 PCI_AF_STATUS_TP << 8); 965 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 966 1, PCI_AF_CTRL_FLR); 967 msleep(EEH_PE_RST_HOLD_TIME); 968 break; 969 case EEH_RESET_DEACTIVATE: 970 eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 971 msleep(EEH_PE_RST_SETTLE_TIME); 972 break; 973 } 974 975 return 0; 976 } 977 978 static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 979 { 980 struct eeh_dev *edev; 981 struct pci_dn *pdn; 982 int ret; 983 984 /* The VF PE should have only one child device */ 985 edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list); 986 pdn = eeh_dev_to_pdn(edev); 987 if (!pdn) 988 return -ENXIO; 989 990 ret = pnv_eeh_do_flr(pdn, option); 991 if (!ret) 992 return ret; 993 994 return pnv_eeh_do_af_flr(pdn, option); 995 } 996 997 /** 998 * pnv_eeh_reset - Reset the specified PE 999 * @pe: EEH PE 1000 * @option: reset option 1001 * 1002 * Do reset on the indicated PE. For PCI bus sensitive PE, 1003 * we need to reset the parent p2p bridge. The PHB has to 1004 * be reinitialized if the p2p bridge is root bridge. For 1005 * PCI device sensitive PE, we will try to reset the device 1006 * through FLR. For now, we don't have OPAL APIs to do HARD 1007 * reset yet, so all reset would be SOFT (HOT) reset. 1008 */ 1009 static int pnv_eeh_reset(struct eeh_pe *pe, int option) 1010 { 1011 struct pci_controller *hose = pe->phb; 1012 struct pci_bus *bus; 1013 int ret; 1014 1015 /* 1016 * For PHB reset, we always have complete reset. For those PEs whose 1017 * primary bus derived from root complex (root bus) or root port 1018 * (usually bus#1), we apply hot or fundamental reset on the root port. 1019 * For other PEs, we always have hot reset on the PE primary bus. 1020 * 1021 * Here, we have different design to pHyp, which always clear the 1022 * frozen state during PE reset. However, the good idea here from 1023 * benh is to keep frozen state before we get PE reset done completely 1024 * (until BAR restore). With the frozen state, HW drops illegal IO 1025 * or MMIO access, which can incur recrusive frozen PE during PE 1026 * reset. The side effect is that EEH core has to clear the frozen 1027 * state explicitly after BAR restore. 1028 */ 1029 if (pe->type & EEH_PE_PHB) { 1030 ret = pnv_eeh_phb_reset(hose, option); 1031 } else { 1032 struct pnv_phb *phb; 1033 s64 rc; 1034 1035 /* 1036 * The frozen PE might be caused by PAPR error injection 1037 * registers, which are expected to be cleared after hitting 1038 * frozen PE as stated in the hardware spec. Unfortunately, 1039 * that's not true on P7IOC. So we have to clear it manually 1040 * to avoid recursive EEH errors during recovery. 1041 */ 1042 phb = hose->private_data; 1043 if (phb->model == PNV_PHB_MODEL_P7IOC && 1044 (option == EEH_RESET_HOT || 1045 option == EEH_RESET_FUNDAMENTAL)) { 1046 rc = opal_pci_reset(phb->opal_id, 1047 OPAL_RESET_PHB_ERROR, 1048 OPAL_ASSERT_RESET); 1049 if (rc != OPAL_SUCCESS) { 1050 pr_warn("%s: Failure %lld clearing " 1051 "error injection registers\n", 1052 __func__, rc); 1053 return -EIO; 1054 } 1055 } 1056 1057 bus = eeh_pe_bus_get(pe); 1058 if (pe->type & EEH_PE_VF) 1059 ret = pnv_eeh_reset_vf_pe(pe, option); 1060 else if (pci_is_root_bus(bus) || 1061 pci_is_root_bus(bus->parent)) 1062 ret = pnv_eeh_root_reset(hose, option); 1063 else 1064 ret = pnv_eeh_bridge_reset(bus->self, option); 1065 } 1066 1067 return ret; 1068 } 1069 1070 /** 1071 * pnv_eeh_wait_state - Wait for PE state 1072 * @pe: EEH PE 1073 * @max_wait: maximal period in millisecond 1074 * 1075 * Wait for the state of associated PE. It might take some time 1076 * to retrieve the PE's state. 1077 */ 1078 static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) 1079 { 1080 int ret; 1081 int mwait; 1082 1083 while (1) { 1084 ret = pnv_eeh_get_state(pe, &mwait); 1085 1086 /* 1087 * If the PE's state is temporarily unavailable, 1088 * we have to wait for the specified time. Otherwise, 1089 * the PE's state will be returned immediately. 1090 */ 1091 if (ret != EEH_STATE_UNAVAILABLE) 1092 return ret; 1093 1094 if (max_wait <= 0) { 1095 pr_warn("%s: Timeout getting PE#%x's state (%d)\n", 1096 __func__, pe->addr, max_wait); 1097 return EEH_STATE_NOT_SUPPORT; 1098 } 1099 1100 max_wait -= mwait; 1101 msleep(mwait); 1102 } 1103 1104 return EEH_STATE_NOT_SUPPORT; 1105 } 1106 1107 /** 1108 * pnv_eeh_get_log - Retrieve error log 1109 * @pe: EEH PE 1110 * @severity: temporary or permanent error log 1111 * @drv_log: driver log to be combined with retrieved error log 1112 * @len: length of driver log 1113 * 1114 * Retrieve the temporary or permanent error from the PE. 1115 */ 1116 static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 1117 char *drv_log, unsigned long len) 1118 { 1119 if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1120 pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 1121 1122 return 0; 1123 } 1124 1125 /** 1126 * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 1127 * @pe: EEH PE 1128 * 1129 * The function will be called to reconfigure the bridges included 1130 * in the specified PE so that the mulfunctional PE would be recovered 1131 * again. 1132 */ 1133 static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 1134 { 1135 return 0; 1136 } 1137 1138 /** 1139 * pnv_pe_err_inject - Inject specified error to the indicated PE 1140 * @pe: the indicated PE 1141 * @type: error type 1142 * @func: specific error type 1143 * @addr: address 1144 * @mask: address mask 1145 * 1146 * The routine is called to inject specified error, which is 1147 * determined by @type and @func, to the indicated PE for 1148 * testing purpose. 1149 */ 1150 static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1151 unsigned long addr, unsigned long mask) 1152 { 1153 struct pci_controller *hose = pe->phb; 1154 struct pnv_phb *phb = hose->private_data; 1155 s64 rc; 1156 1157 if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1158 type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1159 pr_warn("%s: Invalid error type %d\n", 1160 __func__, type); 1161 return -ERANGE; 1162 } 1163 1164 if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1165 func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1166 pr_warn("%s: Invalid error function %d\n", 1167 __func__, func); 1168 return -ERANGE; 1169 } 1170 1171 /* Firmware supports error injection ? */ 1172 if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1173 pr_warn("%s: Firmware doesn't support error injection\n", 1174 __func__); 1175 return -ENXIO; 1176 } 1177 1178 /* Do error injection */ 1179 rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1180 type, func, addr, mask); 1181 if (rc != OPAL_SUCCESS) { 1182 pr_warn("%s: Failure %lld injecting error " 1183 "%d-%d to PHB#%x-PE#%x\n", 1184 __func__, rc, type, func, 1185 hose->global_number, pe->addr); 1186 return -EIO; 1187 } 1188 1189 return 0; 1190 } 1191 1192 static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1193 { 1194 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1195 1196 if (!edev || !edev->pe) 1197 return false; 1198 1199 /* 1200 * We will issue FLR or AF FLR to all VFs, which are contained 1201 * in VF PE. It relies on the EEH PCI config accessors. So we 1202 * can't block them during the window. 1203 */ 1204 if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 1205 return false; 1206 1207 if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1208 return true; 1209 1210 return false; 1211 } 1212 1213 static int pnv_eeh_read_config(struct pci_dn *pdn, 1214 int where, int size, u32 *val) 1215 { 1216 if (!pdn) 1217 return PCIBIOS_DEVICE_NOT_FOUND; 1218 1219 if (pnv_eeh_cfg_blocked(pdn)) { 1220 *val = 0xFFFFFFFF; 1221 return PCIBIOS_SET_FAILED; 1222 } 1223 1224 return pnv_pci_cfg_read(pdn, where, size, val); 1225 } 1226 1227 static int pnv_eeh_write_config(struct pci_dn *pdn, 1228 int where, int size, u32 val) 1229 { 1230 if (!pdn) 1231 return PCIBIOS_DEVICE_NOT_FOUND; 1232 1233 if (pnv_eeh_cfg_blocked(pdn)) 1234 return PCIBIOS_SET_FAILED; 1235 1236 return pnv_pci_cfg_write(pdn, where, size, val); 1237 } 1238 1239 static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 1240 { 1241 /* GEM */ 1242 if (data->gemXfir || data->gemRfir || 1243 data->gemRirqfir || data->gemMask || data->gemRwof) 1244 pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 1245 be64_to_cpu(data->gemXfir), 1246 be64_to_cpu(data->gemRfir), 1247 be64_to_cpu(data->gemRirqfir), 1248 be64_to_cpu(data->gemMask), 1249 be64_to_cpu(data->gemRwof)); 1250 1251 /* LEM */ 1252 if (data->lemFir || data->lemErrMask || 1253 data->lemAction0 || data->lemAction1 || data->lemWof) 1254 pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 1255 be64_to_cpu(data->lemFir), 1256 be64_to_cpu(data->lemErrMask), 1257 be64_to_cpu(data->lemAction0), 1258 be64_to_cpu(data->lemAction1), 1259 be64_to_cpu(data->lemWof)); 1260 } 1261 1262 static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 1263 { 1264 struct pnv_phb *phb = hose->private_data; 1265 struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag; 1266 long rc; 1267 1268 rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 1269 if (rc != OPAL_SUCCESS) { 1270 pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 1271 __func__, phb->hub_id, rc); 1272 return; 1273 } 1274 1275 switch (data->type) { 1276 case OPAL_P7IOC_DIAG_TYPE_RGC: 1277 pr_info("P7IOC diag-data for RGC\n\n"); 1278 pnv_eeh_dump_hub_diag_common(data); 1279 if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 1280 pr_info(" RGC: %016llx %016llx\n", 1281 be64_to_cpu(data->rgc.rgcStatus), 1282 be64_to_cpu(data->rgc.rgcLdcp)); 1283 break; 1284 case OPAL_P7IOC_DIAG_TYPE_BI: 1285 pr_info("P7IOC diag-data for BI %s\n\n", 1286 data->bi.biDownbound ? "Downbound" : "Upbound"); 1287 pnv_eeh_dump_hub_diag_common(data); 1288 if (data->bi.biLdcp0 || data->bi.biLdcp1 || 1289 data->bi.biLdcp2 || data->bi.biFenceStatus) 1290 pr_info(" BI: %016llx %016llx %016llx %016llx\n", 1291 be64_to_cpu(data->bi.biLdcp0), 1292 be64_to_cpu(data->bi.biLdcp1), 1293 be64_to_cpu(data->bi.biLdcp2), 1294 be64_to_cpu(data->bi.biFenceStatus)); 1295 break; 1296 case OPAL_P7IOC_DIAG_TYPE_CI: 1297 pr_info("P7IOC diag-data for CI Port %d\n\n", 1298 data->ci.ciPort); 1299 pnv_eeh_dump_hub_diag_common(data); 1300 if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 1301 pr_info(" CI: %016llx %016llx\n", 1302 be64_to_cpu(data->ci.ciPortStatus), 1303 be64_to_cpu(data->ci.ciPortLdcp)); 1304 break; 1305 case OPAL_P7IOC_DIAG_TYPE_MISC: 1306 pr_info("P7IOC diag-data for MISC\n\n"); 1307 pnv_eeh_dump_hub_diag_common(data); 1308 break; 1309 case OPAL_P7IOC_DIAG_TYPE_I2C: 1310 pr_info("P7IOC diag-data for I2C\n\n"); 1311 pnv_eeh_dump_hub_diag_common(data); 1312 break; 1313 default: 1314 pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 1315 __func__, phb->hub_id, data->type); 1316 } 1317 } 1318 1319 static int pnv_eeh_get_pe(struct pci_controller *hose, 1320 u16 pe_no, struct eeh_pe **pe) 1321 { 1322 struct pnv_phb *phb = hose->private_data; 1323 struct pnv_ioda_pe *pnv_pe; 1324 struct eeh_pe *dev_pe; 1325 struct eeh_dev edev; 1326 1327 /* 1328 * If PHB supports compound PE, to fetch 1329 * the master PE because slave PE is invisible 1330 * to EEH core. 1331 */ 1332 pnv_pe = &phb->ioda.pe_array[pe_no]; 1333 if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 1334 pnv_pe = pnv_pe->master; 1335 WARN_ON(!pnv_pe || 1336 !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 1337 pe_no = pnv_pe->pe_number; 1338 } 1339 1340 /* Find the PE according to PE# */ 1341 memset(&edev, 0, sizeof(struct eeh_dev)); 1342 edev.phb = hose; 1343 edev.pe_config_addr = pe_no; 1344 dev_pe = eeh_pe_get(&edev); 1345 if (!dev_pe) 1346 return -EEXIST; 1347 1348 /* Freeze the (compound) PE */ 1349 *pe = dev_pe; 1350 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1351 phb->freeze_pe(phb, pe_no); 1352 1353 /* 1354 * At this point, we're sure the (compound) PE should 1355 * have been frozen. However, we still need poke until 1356 * hitting the frozen PE on top level. 1357 */ 1358 dev_pe = dev_pe->parent; 1359 while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 1360 int ret; 1361 int active_flags = (EEH_STATE_MMIO_ACTIVE | 1362 EEH_STATE_DMA_ACTIVE); 1363 1364 ret = eeh_ops->get_state(dev_pe, NULL); 1365 if (ret <= 0 || (ret & active_flags) == active_flags) { 1366 dev_pe = dev_pe->parent; 1367 continue; 1368 } 1369 1370 /* Frozen parent PE */ 1371 *pe = dev_pe; 1372 if (!(dev_pe->state & EEH_PE_ISOLATED)) 1373 phb->freeze_pe(phb, dev_pe->addr); 1374 1375 /* Next one */ 1376 dev_pe = dev_pe->parent; 1377 } 1378 1379 return 0; 1380 } 1381 1382 /** 1383 * pnv_eeh_next_error - Retrieve next EEH error to handle 1384 * @pe: Affected PE 1385 * 1386 * The function is expected to be called by EEH core while it gets 1387 * special EEH event (without binding PE). The function calls to 1388 * OPAL APIs for next error to handle. The informational error is 1389 * handled internally by platform. However, the dead IOC, dead PHB, 1390 * fenced PHB and frozen PE should be handled by EEH core eventually. 1391 */ 1392 static int pnv_eeh_next_error(struct eeh_pe **pe) 1393 { 1394 struct pci_controller *hose; 1395 struct pnv_phb *phb; 1396 struct eeh_pe *phb_pe, *parent_pe; 1397 __be64 frozen_pe_no; 1398 __be16 err_type, severity; 1399 int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 1400 long rc; 1401 int state, ret = EEH_NEXT_ERR_NONE; 1402 1403 /* 1404 * While running here, it's safe to purge the event queue. The 1405 * event should still be masked. 1406 */ 1407 eeh_remove_event(NULL, false); 1408 1409 list_for_each_entry(hose, &hose_list, list_node) { 1410 /* 1411 * If the subordinate PCI buses of the PHB has been 1412 * removed or is exactly under error recovery, we 1413 * needn't take care of it any more. 1414 */ 1415 phb = hose->private_data; 1416 phb_pe = eeh_phb_pe_get(hose); 1417 if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 1418 continue; 1419 1420 rc = opal_pci_next_error(phb->opal_id, 1421 &frozen_pe_no, &err_type, &severity); 1422 if (rc != OPAL_SUCCESS) { 1423 pr_devel("%s: Invalid return value on " 1424 "PHB#%x (0x%lx) from opal_pci_next_error", 1425 __func__, hose->global_number, rc); 1426 continue; 1427 } 1428 1429 /* If the PHB doesn't have error, stop processing */ 1430 if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 1431 be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 1432 pr_devel("%s: No error found on PHB#%x\n", 1433 __func__, hose->global_number); 1434 continue; 1435 } 1436 1437 /* 1438 * Processing the error. We're expecting the error with 1439 * highest priority reported upon multiple errors on the 1440 * specific PHB. 1441 */ 1442 pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 1443 __func__, be16_to_cpu(err_type), 1444 be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 1445 hose->global_number); 1446 switch (be16_to_cpu(err_type)) { 1447 case OPAL_EEH_IOC_ERROR: 1448 if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 1449 pr_err("EEH: dead IOC detected\n"); 1450 ret = EEH_NEXT_ERR_DEAD_IOC; 1451 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1452 pr_info("EEH: IOC informative error " 1453 "detected\n"); 1454 pnv_eeh_get_and_dump_hub_diag(hose); 1455 ret = EEH_NEXT_ERR_NONE; 1456 } 1457 1458 break; 1459 case OPAL_EEH_PHB_ERROR: 1460 if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 1461 *pe = phb_pe; 1462 pr_err("EEH: dead PHB#%x detected, " 1463 "location: %s\n", 1464 hose->global_number, 1465 eeh_pe_loc_get(phb_pe)); 1466 ret = EEH_NEXT_ERR_DEAD_PHB; 1467 } else if (be16_to_cpu(severity) == 1468 OPAL_EEH_SEV_PHB_FENCED) { 1469 *pe = phb_pe; 1470 pr_err("EEH: Fenced PHB#%x detected, " 1471 "location: %s\n", 1472 hose->global_number, 1473 eeh_pe_loc_get(phb_pe)); 1474 ret = EEH_NEXT_ERR_FENCED_PHB; 1475 } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 1476 pr_info("EEH: PHB#%x informative error " 1477 "detected, location: %s\n", 1478 hose->global_number, 1479 eeh_pe_loc_get(phb_pe)); 1480 pnv_eeh_get_phb_diag(phb_pe); 1481 pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 1482 ret = EEH_NEXT_ERR_NONE; 1483 } 1484 1485 break; 1486 case OPAL_EEH_PE_ERROR: 1487 /* 1488 * If we can't find the corresponding PE, we 1489 * just try to unfreeze. 1490 */ 1491 if (pnv_eeh_get_pe(hose, 1492 be64_to_cpu(frozen_pe_no), pe)) { 1493 pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 1494 hose->global_number, be64_to_cpu(frozen_pe_no)); 1495 pr_info("EEH: PHB location: %s\n", 1496 eeh_pe_loc_get(phb_pe)); 1497 1498 /* Dump PHB diag-data */ 1499 rc = opal_pci_get_phb_diag_data2(phb->opal_id, 1500 phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE); 1501 if (rc == OPAL_SUCCESS) 1502 pnv_pci_dump_phb_diag_data(hose, 1503 phb->diag.blob); 1504 1505 /* Try best to clear it */ 1506 opal_pci_eeh_freeze_clear(phb->opal_id, 1507 frozen_pe_no, 1508 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 1509 ret = EEH_NEXT_ERR_NONE; 1510 } else if ((*pe)->state & EEH_PE_ISOLATED || 1511 eeh_pe_passed(*pe)) { 1512 ret = EEH_NEXT_ERR_NONE; 1513 } else { 1514 pr_err("EEH: Frozen PE#%x " 1515 "on PHB#%x detected\n", 1516 (*pe)->addr, 1517 (*pe)->phb->global_number); 1518 pr_err("EEH: PE location: %s, " 1519 "PHB location: %s\n", 1520 eeh_pe_loc_get(*pe), 1521 eeh_pe_loc_get(phb_pe)); 1522 ret = EEH_NEXT_ERR_FROZEN_PE; 1523 } 1524 1525 break; 1526 default: 1527 pr_warn("%s: Unexpected error type %d\n", 1528 __func__, be16_to_cpu(err_type)); 1529 } 1530 1531 /* 1532 * EEH core will try recover from fenced PHB or 1533 * frozen PE. In the time for frozen PE, EEH core 1534 * enable IO path for that before collecting logs, 1535 * but it ruins the site. So we have to dump the 1536 * log in advance here. 1537 */ 1538 if ((ret == EEH_NEXT_ERR_FROZEN_PE || 1539 ret == EEH_NEXT_ERR_FENCED_PHB) && 1540 !((*pe)->state & EEH_PE_ISOLATED)) { 1541 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 1542 pnv_eeh_get_phb_diag(*pe); 1543 1544 if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 1545 pnv_pci_dump_phb_diag_data((*pe)->phb, 1546 (*pe)->data); 1547 } 1548 1549 /* 1550 * We probably have the frozen parent PE out there and 1551 * we need have to handle frozen parent PE firstly. 1552 */ 1553 if (ret == EEH_NEXT_ERR_FROZEN_PE) { 1554 parent_pe = (*pe)->parent; 1555 while (parent_pe) { 1556 /* Hit the ceiling ? */ 1557 if (parent_pe->type & EEH_PE_PHB) 1558 break; 1559 1560 /* Frozen parent PE ? */ 1561 state = eeh_ops->get_state(parent_pe, NULL); 1562 if (state > 0 && 1563 (state & active_flags) != active_flags) 1564 *pe = parent_pe; 1565 1566 /* Next parent level */ 1567 parent_pe = parent_pe->parent; 1568 } 1569 1570 /* We possibly migrate to another PE */ 1571 eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 1572 } 1573 1574 /* 1575 * If we have no errors on the specific PHB or only 1576 * informative error there, we continue poking it. 1577 * Otherwise, we need actions to be taken by upper 1578 * layer. 1579 */ 1580 if (ret > EEH_NEXT_ERR_INF) 1581 break; 1582 } 1583 1584 /* Unmask the event */ 1585 if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 1586 enable_irq(eeh_event_irq); 1587 1588 return ret; 1589 } 1590 1591 static int pnv_eeh_restore_vf_config(struct pci_dn *pdn) 1592 { 1593 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1594 u32 devctl, cmd, cap2, aer_capctl; 1595 int old_mps; 1596 1597 if (edev->pcie_cap) { 1598 /* Restore MPS */ 1599 old_mps = (ffs(pdn->mps) - 8) << 5; 1600 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1601 2, &devctl); 1602 devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; 1603 devctl |= old_mps; 1604 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1605 2, devctl); 1606 1607 /* Disable Completion Timeout */ 1608 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2, 1609 4, &cap2); 1610 if (cap2 & 0x10) { 1611 eeh_ops->read_config(pdn, 1612 edev->pcie_cap + PCI_EXP_DEVCTL2, 1613 4, &cap2); 1614 cap2 |= 0x10; 1615 eeh_ops->write_config(pdn, 1616 edev->pcie_cap + PCI_EXP_DEVCTL2, 1617 4, cap2); 1618 } 1619 } 1620 1621 /* Enable SERR and parity checking */ 1622 eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd); 1623 cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 1624 eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd); 1625 1626 /* Enable report various errors */ 1627 if (edev->pcie_cap) { 1628 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1629 2, &devctl); 1630 devctl &= ~PCI_EXP_DEVCTL_CERE; 1631 devctl |= (PCI_EXP_DEVCTL_NFERE | 1632 PCI_EXP_DEVCTL_FERE | 1633 PCI_EXP_DEVCTL_URRE); 1634 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 1635 2, devctl); 1636 } 1637 1638 /* Enable ECRC generation and check */ 1639 if (edev->pcie_cap && edev->aer_cap) { 1640 eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP, 1641 4, &aer_capctl); 1642 aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 1643 eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP, 1644 4, aer_capctl); 1645 } 1646 1647 return 0; 1648 } 1649 1650 static int pnv_eeh_restore_config(struct pci_dn *pdn) 1651 { 1652 struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1653 struct pnv_phb *phb; 1654 s64 ret; 1655 1656 if (!edev) 1657 return -EEXIST; 1658 1659 /* 1660 * We have to restore the PCI config space after reset since the 1661 * firmware can't see SRIOV VFs. 1662 * 1663 * FIXME: The MPS, error routing rules, timeout setting are worthy 1664 * to be exported by firmware in extendible way. 1665 */ 1666 if (edev->physfn) { 1667 ret = pnv_eeh_restore_vf_config(pdn); 1668 } else { 1669 phb = edev->phb->private_data; 1670 ret = opal_pci_reinit(phb->opal_id, 1671 OPAL_REINIT_PCI_DEV, edev->config_addr); 1672 } 1673 1674 if (ret) { 1675 pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 1676 __func__, edev->config_addr, ret); 1677 return -EIO; 1678 } 1679 1680 return 0; 1681 } 1682 1683 static struct eeh_ops pnv_eeh_ops = { 1684 .name = "powernv", 1685 .init = pnv_eeh_init, 1686 .post_init = pnv_eeh_post_init, 1687 .probe = pnv_eeh_probe, 1688 .set_option = pnv_eeh_set_option, 1689 .get_pe_addr = pnv_eeh_get_pe_addr, 1690 .get_state = pnv_eeh_get_state, 1691 .reset = pnv_eeh_reset, 1692 .wait_state = pnv_eeh_wait_state, 1693 .get_log = pnv_eeh_get_log, 1694 .configure_bridge = pnv_eeh_configure_bridge, 1695 .err_inject = pnv_eeh_err_inject, 1696 .read_config = pnv_eeh_read_config, 1697 .write_config = pnv_eeh_write_config, 1698 .next_error = pnv_eeh_next_error, 1699 .restore_config = pnv_eeh_restore_config 1700 }; 1701 1702 void pcibios_bus_add_device(struct pci_dev *pdev) 1703 { 1704 struct pci_dn *pdn = pci_get_pdn(pdev); 1705 1706 if (!pdev->is_virtfn) 1707 return; 1708 1709 /* 1710 * The following operations will fail if VF's sysfs files 1711 * aren't created or its resources aren't finalized. 1712 */ 1713 eeh_add_device_early(pdn); 1714 eeh_add_device_late(pdev); 1715 eeh_sysfs_add_device(pdev); 1716 } 1717 1718 #ifdef CONFIG_PCI_IOV 1719 static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 1720 { 1721 struct pci_dn *pdn = pci_get_pdn(pdev); 1722 int parent_mps; 1723 1724 if (!pdev->is_virtfn) 1725 return; 1726 1727 /* Synchronize MPS for VF and PF */ 1728 parent_mps = pcie_get_mps(pdev->physfn); 1729 if ((128 << pdev->pcie_mpss) >= parent_mps) 1730 pcie_set_mps(pdev, parent_mps); 1731 pdn->mps = pcie_get_mps(pdev); 1732 } 1733 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 1734 #endif /* CONFIG_PCI_IOV */ 1735 1736 /** 1737 * eeh_powernv_init - Register platform dependent EEH operations 1738 * 1739 * EEH initialization on powernv platform. This function should be 1740 * called before any EEH related functions. 1741 */ 1742 static int __init eeh_powernv_init(void) 1743 { 1744 int ret = -EINVAL; 1745 1746 eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE); 1747 ret = eeh_ops_register(&pnv_eeh_ops); 1748 if (!ret) 1749 pr_info("EEH: PowerNV platform initialized\n"); 1750 else 1751 pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 1752 1753 return ret; 1754 } 1755 machine_early_initcall(powernv, eeh_powernv_init); 1756