129310e5eSGavin Shan /* 229310e5eSGavin Shan * The file intends to implement the platform dependent EEH operations on 329310e5eSGavin Shan * powernv platform. Actually, the powernv was created in order to fully 429310e5eSGavin Shan * hypervisor support. 529310e5eSGavin Shan * 629310e5eSGavin Shan * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 729310e5eSGavin Shan * 829310e5eSGavin Shan * This program is free software; you can redistribute it and/or modify 929310e5eSGavin Shan * it under the terms of the GNU General Public License as published by 1029310e5eSGavin Shan * the Free Software Foundation; either version 2 of the License, or 1129310e5eSGavin Shan * (at your option) any later version. 1229310e5eSGavin Shan */ 1329310e5eSGavin Shan 1429310e5eSGavin Shan #include <linux/atomic.h> 154cf17445SGavin Shan #include <linux/debugfs.h> 1629310e5eSGavin Shan #include <linux/delay.h> 1729310e5eSGavin Shan #include <linux/export.h> 1829310e5eSGavin Shan #include <linux/init.h> 1979231448SAlistair Popple #include <linux/interrupt.h> 2029310e5eSGavin Shan #include <linux/list.h> 2129310e5eSGavin Shan #include <linux/msi.h> 2229310e5eSGavin Shan #include <linux/of.h> 2329310e5eSGavin Shan #include <linux/pci.h> 2429310e5eSGavin Shan #include <linux/proc_fs.h> 2529310e5eSGavin Shan #include <linux/rbtree.h> 2629310e5eSGavin Shan #include <linux/sched.h> 2729310e5eSGavin Shan #include <linux/seq_file.h> 2829310e5eSGavin Shan #include <linux/spinlock.h> 2929310e5eSGavin Shan 3029310e5eSGavin Shan #include <asm/eeh.h> 3129310e5eSGavin Shan #include <asm/eeh_event.h> 3229310e5eSGavin Shan #include <asm/firmware.h> 3329310e5eSGavin Shan #include <asm/io.h> 3429310e5eSGavin Shan #include <asm/iommu.h> 3529310e5eSGavin Shan #include <asm/machdep.h> 3629310e5eSGavin Shan #include <asm/msi_bitmap.h> 3729310e5eSGavin Shan #include <asm/opal.h> 3829310e5eSGavin Shan #include <asm/ppc-pci.h> 3929310e5eSGavin Shan 4029310e5eSGavin Shan #include "powernv.h" 4129310e5eSGavin Shan #include "pci.h" 4229310e5eSGavin Shan 434cf17445SGavin Shan static bool pnv_eeh_nb_init = false; 4479231448SAlistair Popple static int eeh_event_irq = -EINVAL; 454cf17445SGavin Shan 4601f3bfb7SGavin Shan static int pnv_eeh_init(void) 4729310e5eSGavin Shan { 48dc561fb9SGavin Shan struct pci_controller *hose; 49dc561fb9SGavin Shan struct pnv_phb *phb; 50dc561fb9SGavin Shan 51e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 52e4d54f71SStewart Smith pr_warn("%s: OPAL is required !\n", 530dae2743SGavin Shan __func__); 5429310e5eSGavin Shan return -EINVAL; 5529310e5eSGavin Shan } 5629310e5eSGavin Shan 5705b1721dSGavin Shan /* Set probe mode */ 5805b1721dSGavin Shan eeh_add_flag(EEH_PROBE_MODE_DEV); 5929310e5eSGavin Shan 60dc561fb9SGavin Shan /* 61dc561fb9SGavin Shan * P7IOC blocks PCI config access to frozen PE, but PHB3 62dc561fb9SGavin Shan * doesn't do that. So we have to selectively enable I/O 63dc561fb9SGavin Shan * prior to collecting error log. 64dc561fb9SGavin Shan */ 65dc561fb9SGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 66dc561fb9SGavin Shan phb = hose->private_data; 67dc561fb9SGavin Shan 68dc561fb9SGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC) 69dc561fb9SGavin Shan eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 702aa5cf9eSGavin Shan 712aa5cf9eSGavin Shan /* 722aa5cf9eSGavin Shan * PE#0 should be regarded as valid by EEH core 732aa5cf9eSGavin Shan * if it's not the reserved one. Currently, we 74608fb9c2SGavin Shan * have the reserved PE#255 and PE#127 for PHB3 752aa5cf9eSGavin Shan * and P7IOC separately. So we should regard 76608fb9c2SGavin Shan * PE#0 as valid for PHB3 and P7IOC. 772aa5cf9eSGavin Shan */ 7892b8f137SGavin Shan if (phb->ioda.reserved_pe_idx != 0) 792aa5cf9eSGavin Shan eeh_add_flag(EEH_VALID_PE_ZERO); 802aa5cf9eSGavin Shan 81dc561fb9SGavin Shan break; 82dc561fb9SGavin Shan } 83dc561fb9SGavin Shan 8429310e5eSGavin Shan return 0; 8529310e5eSGavin Shan } 8629310e5eSGavin Shan 8779231448SAlistair Popple static irqreturn_t pnv_eeh_event(int irq, void *data) 884cf17445SGavin Shan { 894cf17445SGavin Shan /* 9079231448SAlistair Popple * We simply send a special EEH event if EEH has been 9179231448SAlistair Popple * enabled. We don't care about EEH events until we've 9279231448SAlistair Popple * finished processing the outstanding ones. Event processing 9379231448SAlistair Popple * gets unmasked in next_error() if EEH is enabled. 944cf17445SGavin Shan */ 9579231448SAlistair Popple disable_irq_nosync(irq); 964cf17445SGavin Shan 974cf17445SGavin Shan if (eeh_enabled()) 984cf17445SGavin Shan eeh_send_failure_event(NULL); 994cf17445SGavin Shan 10079231448SAlistair Popple return IRQ_HANDLED; 1014cf17445SGavin Shan } 1024cf17445SGavin Shan 1034cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 1044cf17445SGavin Shan static ssize_t pnv_eeh_ei_write(struct file *filp, 1054cf17445SGavin Shan const char __user *user_buf, 1064cf17445SGavin Shan size_t count, loff_t *ppos) 1074cf17445SGavin Shan { 1084cf17445SGavin Shan struct pci_controller *hose = filp->private_data; 1094cf17445SGavin Shan struct eeh_dev *edev; 1104cf17445SGavin Shan struct eeh_pe *pe; 1114cf17445SGavin Shan int pe_no, type, func; 1124cf17445SGavin Shan unsigned long addr, mask; 1134cf17445SGavin Shan char buf[50]; 1144cf17445SGavin Shan int ret; 1154cf17445SGavin Shan 1164cf17445SGavin Shan if (!eeh_ops || !eeh_ops->err_inject) 1174cf17445SGavin Shan return -ENXIO; 1184cf17445SGavin Shan 1194cf17445SGavin Shan /* Copy over argument buffer */ 1204cf17445SGavin Shan ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 1214cf17445SGavin Shan if (!ret) 1224cf17445SGavin Shan return -EFAULT; 1234cf17445SGavin Shan 1244cf17445SGavin Shan /* Retrieve parameters */ 1254cf17445SGavin Shan ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 1264cf17445SGavin Shan &pe_no, &type, &func, &addr, &mask); 1274cf17445SGavin Shan if (ret != 5) 1284cf17445SGavin Shan return -EINVAL; 1294cf17445SGavin Shan 1304cf17445SGavin Shan /* Retrieve PE */ 1314cf17445SGavin Shan edev = kzalloc(sizeof(*edev), GFP_KERNEL); 1324cf17445SGavin Shan if (!edev) 1334cf17445SGavin Shan return -ENOMEM; 1344cf17445SGavin Shan edev->phb = hose; 1354cf17445SGavin Shan edev->pe_config_addr = pe_no; 1364cf17445SGavin Shan pe = eeh_pe_get(edev); 1374cf17445SGavin Shan kfree(edev); 1384cf17445SGavin Shan if (!pe) 1394cf17445SGavin Shan return -ENODEV; 1404cf17445SGavin Shan 1414cf17445SGavin Shan /* Do error injection */ 1424cf17445SGavin Shan ret = eeh_ops->err_inject(pe, type, func, addr, mask); 1434cf17445SGavin Shan return ret < 0 ? ret : count; 1444cf17445SGavin Shan } 1454cf17445SGavin Shan 1464cf17445SGavin Shan static const struct file_operations pnv_eeh_ei_fops = { 1474cf17445SGavin Shan .open = simple_open, 1484cf17445SGavin Shan .llseek = no_llseek, 1494cf17445SGavin Shan .write = pnv_eeh_ei_write, 1504cf17445SGavin Shan }; 1514cf17445SGavin Shan 1524cf17445SGavin Shan static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 1534cf17445SGavin Shan { 1544cf17445SGavin Shan struct pci_controller *hose = data; 1554cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1564cf17445SGavin Shan 1574cf17445SGavin Shan out_be64(phb->regs + offset, val); 1584cf17445SGavin Shan return 0; 1594cf17445SGavin Shan } 1604cf17445SGavin Shan 1614cf17445SGavin Shan static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 1624cf17445SGavin Shan { 1634cf17445SGavin Shan struct pci_controller *hose = data; 1644cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1654cf17445SGavin Shan 1664cf17445SGavin Shan *val = in_be64(phb->regs + offset); 1674cf17445SGavin Shan return 0; 1684cf17445SGavin Shan } 1694cf17445SGavin Shan 170ccc9662dSGavin Shan #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 171ccc9662dSGavin Shan static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 172ccc9662dSGavin Shan { \ 173ccc9662dSGavin Shan return pnv_eeh_dbgfs_set(data, reg, val); \ 174ccc9662dSGavin Shan } \ 175ccc9662dSGavin Shan \ 176ccc9662dSGavin Shan static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 177ccc9662dSGavin Shan { \ 178ccc9662dSGavin Shan return pnv_eeh_dbgfs_get(data, reg, val); \ 179ccc9662dSGavin Shan } \ 180ccc9662dSGavin Shan \ 181ccc9662dSGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 182ccc9662dSGavin Shan pnv_eeh_dbgfs_get_##name, \ 183ccc9662dSGavin Shan pnv_eeh_dbgfs_set_##name, \ 184ccc9662dSGavin Shan "0x%llx\n") 1854cf17445SGavin Shan 186ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 187ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 188ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 1894cf17445SGavin Shan 1904cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 1914cf17445SGavin Shan 19229310e5eSGavin Shan /** 19301f3bfb7SGavin Shan * pnv_eeh_post_init - EEH platform dependent post initialization 19429310e5eSGavin Shan * 19529310e5eSGavin Shan * EEH platform dependent post initialization on powernv. When 19629310e5eSGavin Shan * the function is called, the EEH PEs and devices should have 19729310e5eSGavin Shan * been built. If the I/O cache staff has been built, EEH is 19829310e5eSGavin Shan * ready to supply service. 19929310e5eSGavin Shan */ 20001f3bfb7SGavin Shan static int pnv_eeh_post_init(void) 20129310e5eSGavin Shan { 20229310e5eSGavin Shan struct pci_controller *hose; 20329310e5eSGavin Shan struct pnv_phb *phb; 20429310e5eSGavin Shan int ret = 0; 20529310e5eSGavin Shan 2064cf17445SGavin Shan /* Register OPAL event notifier */ 2074cf17445SGavin Shan if (!pnv_eeh_nb_init) { 20879231448SAlistair Popple eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 20979231448SAlistair Popple if (eeh_event_irq < 0) { 21079231448SAlistair Popple pr_err("%s: Can't register OPAL event interrupt (%d)\n", 21179231448SAlistair Popple __func__, eeh_event_irq); 21279231448SAlistair Popple return eeh_event_irq; 21379231448SAlistair Popple } 21479231448SAlistair Popple 21579231448SAlistair Popple ret = request_irq(eeh_event_irq, pnv_eeh_event, 21679231448SAlistair Popple IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 21779231448SAlistair Popple if (ret < 0) { 21879231448SAlistair Popple irq_dispose_mapping(eeh_event_irq); 21979231448SAlistair Popple pr_err("%s: Can't request OPAL event interrupt (%d)\n", 22079231448SAlistair Popple __func__, eeh_event_irq); 2214cf17445SGavin Shan return ret; 2224cf17445SGavin Shan } 2234cf17445SGavin Shan 2244cf17445SGavin Shan pnv_eeh_nb_init = true; 2254cf17445SGavin Shan } 2264cf17445SGavin Shan 22779231448SAlistair Popple if (!eeh_enabled()) 22879231448SAlistair Popple disable_irq(eeh_event_irq); 22979231448SAlistair Popple 23029310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 23129310e5eSGavin Shan phb = hose->private_data; 23229310e5eSGavin Shan 2334cf17445SGavin Shan /* 2344cf17445SGavin Shan * If EEH is enabled, we're going to rely on that. 2354cf17445SGavin Shan * Otherwise, we restore to conventional mechanism 2364cf17445SGavin Shan * to clear frozen PE during PCI config access. 2374cf17445SGavin Shan */ 2384cf17445SGavin Shan if (eeh_enabled()) 2394cf17445SGavin Shan phb->flags |= PNV_PHB_FLAG_EEH; 2404cf17445SGavin Shan else 2414cf17445SGavin Shan phb->flags &= ~PNV_PHB_FLAG_EEH; 2424cf17445SGavin Shan 2434cf17445SGavin Shan /* Create debugfs entries */ 2444cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 2454cf17445SGavin Shan if (phb->has_dbgfs || !phb->dbgfs) 2464cf17445SGavin Shan continue; 2474cf17445SGavin Shan 2484cf17445SGavin Shan phb->has_dbgfs = 1; 2494cf17445SGavin Shan debugfs_create_file("err_injct", 0200, 2504cf17445SGavin Shan phb->dbgfs, hose, 2514cf17445SGavin Shan &pnv_eeh_ei_fops); 2524cf17445SGavin Shan 2534cf17445SGavin Shan debugfs_create_file("err_injct_outbound", 0600, 2544cf17445SGavin Shan phb->dbgfs, hose, 255ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_outb); 2564cf17445SGavin Shan debugfs_create_file("err_injct_inboundA", 0600, 2574cf17445SGavin Shan phb->dbgfs, hose, 258ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbA); 2594cf17445SGavin Shan debugfs_create_file("err_injct_inboundB", 0600, 2604cf17445SGavin Shan phb->dbgfs, hose, 261ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbB); 2624cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 26329310e5eSGavin Shan } 2644cf17445SGavin Shan 26529310e5eSGavin Shan return ret; 26629310e5eSGavin Shan } 26729310e5eSGavin Shan 2684d6186caSGavin Shan static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 269ff57b454SGavin Shan { 2704d6186caSGavin Shan int pos = PCI_CAPABILITY_LIST; 2714d6186caSGavin Shan int cnt = 48; /* Maximal number of capabilities */ 2724d6186caSGavin Shan u32 status, id; 273ff57b454SGavin Shan 274ff57b454SGavin Shan if (!pdn) 275ff57b454SGavin Shan return 0; 276ff57b454SGavin Shan 2774d6186caSGavin Shan /* Check if the device supports capabilities */ 278ff57b454SGavin Shan pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 279ff57b454SGavin Shan if (!(status & PCI_STATUS_CAP_LIST)) 280ff57b454SGavin Shan return 0; 281ff57b454SGavin Shan 282ff57b454SGavin Shan while (cnt--) { 283ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos, 1, &pos); 284ff57b454SGavin Shan if (pos < 0x40) 285ff57b454SGavin Shan break; 286ff57b454SGavin Shan 287ff57b454SGavin Shan pos &= ~3; 288ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 289ff57b454SGavin Shan if (id == 0xff) 290ff57b454SGavin Shan break; 291ff57b454SGavin Shan 292ff57b454SGavin Shan /* Found */ 293ff57b454SGavin Shan if (id == cap) 294ff57b454SGavin Shan return pos; 295ff57b454SGavin Shan 296ff57b454SGavin Shan /* Next one */ 297ff57b454SGavin Shan pos += PCI_CAP_LIST_NEXT; 298ff57b454SGavin Shan } 299ff57b454SGavin Shan 300ff57b454SGavin Shan return 0; 301ff57b454SGavin Shan } 302ff57b454SGavin Shan 303ff57b454SGavin Shan static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 304ff57b454SGavin Shan { 305ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 306ff57b454SGavin Shan u32 header; 307ff57b454SGavin Shan int pos = 256, ttl = (4096 - 256) / 8; 308ff57b454SGavin Shan 309ff57b454SGavin Shan if (!edev || !edev->pcie_cap) 310ff57b454SGavin Shan return 0; 311ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 312ff57b454SGavin Shan return 0; 313ff57b454SGavin Shan else if (!header) 314ff57b454SGavin Shan return 0; 315ff57b454SGavin Shan 316ff57b454SGavin Shan while (ttl-- > 0) { 317ff57b454SGavin Shan if (PCI_EXT_CAP_ID(header) == cap && pos) 318ff57b454SGavin Shan return pos; 319ff57b454SGavin Shan 320ff57b454SGavin Shan pos = PCI_EXT_CAP_NEXT(header); 321ff57b454SGavin Shan if (pos < 256) 322ff57b454SGavin Shan break; 323ff57b454SGavin Shan 324ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 325ff57b454SGavin Shan break; 326ff57b454SGavin Shan } 327ff57b454SGavin Shan 328ff57b454SGavin Shan return 0; 329ff57b454SGavin Shan } 330ff57b454SGavin Shan 33129310e5eSGavin Shan /** 332ff57b454SGavin Shan * pnv_eeh_probe - Do probe on PCI device 333ff57b454SGavin Shan * @pdn: PCI device node 334ff57b454SGavin Shan * @data: unused 33529310e5eSGavin Shan * 33629310e5eSGavin Shan * When EEH module is installed during system boot, all PCI devices 33729310e5eSGavin Shan * are checked one by one to see if it supports EEH. The function 33829310e5eSGavin Shan * is introduced for the purpose. By default, EEH has been enabled 33929310e5eSGavin Shan * on all PCI devices. That's to say, we only need do necessary 34029310e5eSGavin Shan * initialization on the corresponding eeh device and create PE 34129310e5eSGavin Shan * accordingly. 34229310e5eSGavin Shan * 34329310e5eSGavin Shan * It's notable that's unsafe to retrieve the EEH device through 34429310e5eSGavin Shan * the corresponding PCI device. During the PCI device hotplug, which 34529310e5eSGavin Shan * was possiblly triggered by EEH core, the binding between EEH device 34629310e5eSGavin Shan * and the PCI device isn't built yet. 34729310e5eSGavin Shan */ 348ff57b454SGavin Shan static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 34929310e5eSGavin Shan { 350ff57b454SGavin Shan struct pci_controller *hose = pdn->phb; 35129310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 352ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 353ff57b454SGavin Shan uint32_t pcie_flags; 354dadcd6d6SMike Qiu int ret; 35529310e5eSGavin Shan 35629310e5eSGavin Shan /* 35729310e5eSGavin Shan * When probing the root bridge, which doesn't have any 35829310e5eSGavin Shan * subordinate PCI devices. We don't have OF node for 35929310e5eSGavin Shan * the root bridge. So it's not reasonable to continue 36029310e5eSGavin Shan * the probing. 36129310e5eSGavin Shan */ 362ff57b454SGavin Shan if (!edev || edev->pe) 363ff57b454SGavin Shan return NULL; 36429310e5eSGavin Shan 36529310e5eSGavin Shan /* Skip for PCI-ISA bridge */ 366ff57b454SGavin Shan if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 367ff57b454SGavin Shan return NULL; 36829310e5eSGavin Shan 36929310e5eSGavin Shan /* Initialize eeh device */ 370ff57b454SGavin Shan edev->class_code = pdn->class_code; 371ab55d218SGavin Shan edev->mode &= 0xFFFFFF00; 372ff57b454SGavin Shan edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 373ff57b454SGavin Shan edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 3749312bc5bSWei Yang edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 375ff57b454SGavin Shan edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 376ff57b454SGavin Shan if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 3774b83bd45SGavin Shan edev->mode |= EEH_DEV_BRIDGE; 378ff57b454SGavin Shan if (edev->pcie_cap) { 379ff57b454SGavin Shan pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 380ff57b454SGavin Shan 2, &pcie_flags); 381ff57b454SGavin Shan pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 382ff57b454SGavin Shan if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 3834b83bd45SGavin Shan edev->mode |= EEH_DEV_ROOT_PORT; 384ff57b454SGavin Shan else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 3854b83bd45SGavin Shan edev->mode |= EEH_DEV_DS_PORT; 386ff57b454SGavin Shan } 3874b83bd45SGavin Shan } 3884b83bd45SGavin Shan 389ff57b454SGavin Shan edev->config_addr = (pdn->busno << 8) | (pdn->devfn); 390ff57b454SGavin Shan edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr]; 39129310e5eSGavin Shan 39229310e5eSGavin Shan /* Create PE */ 393dadcd6d6SMike Qiu ret = eeh_add_to_parent_pe(edev); 394dadcd6d6SMike Qiu if (ret) { 395ff57b454SGavin Shan pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%d)\n", 396ff57b454SGavin Shan __func__, hose->global_number, pdn->busno, 397ff57b454SGavin Shan PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 398ff57b454SGavin Shan return NULL; 399dadcd6d6SMike Qiu } 400dadcd6d6SMike Qiu 401dadcd6d6SMike Qiu /* 402b6541db1SGavin Shan * If the PE contains any one of following adapters, the 403b6541db1SGavin Shan * PCI config space can't be accessed when dumping EEH log. 404b6541db1SGavin Shan * Otherwise, we will run into fenced PHB caused by shortage 405b6541db1SGavin Shan * of outbound credits in the adapter. The PCI config access 406b6541db1SGavin Shan * should be blocked until PE reset. MMIO access is dropped 407b6541db1SGavin Shan * by hardware certainly. In order to drop PCI config requests, 408b6541db1SGavin Shan * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 409b6541db1SGavin Shan * will be checked in the backend for PE state retrival. If 410b6541db1SGavin Shan * the PE becomes frozen for the first time and the flag has 411b6541db1SGavin Shan * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 412b6541db1SGavin Shan * that PE to block its config space. 413b6541db1SGavin Shan * 414b6541db1SGavin Shan * Broadcom Austin 4-ports NICs (14e4:1657) 415353169acSGavin Shan * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 416179ea48bSGavin Shan * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 417b6541db1SGavin Shan */ 418ff57b454SGavin Shan if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 419ff57b454SGavin Shan pdn->device_id == 0x1657) || 420ff57b454SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 421353169acSGavin Shan pdn->device_id == 0x168a) || 422353169acSGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 423ff57b454SGavin Shan pdn->device_id == 0x168e)) 424b6541db1SGavin Shan edev->pe->state |= EEH_PE_CFG_RESTRICTED; 425b6541db1SGavin Shan 426b6541db1SGavin Shan /* 427dadcd6d6SMike Qiu * Cache the PE primary bus, which can't be fetched when 428dadcd6d6SMike Qiu * full hotplug is in progress. In that case, all child 429dadcd6d6SMike Qiu * PCI devices of the PE are expected to be removed prior 430dadcd6d6SMike Qiu * to PE reset. 431dadcd6d6SMike Qiu */ 43205ba75f8SGavin Shan if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 433ff57b454SGavin Shan edev->pe->bus = pci_find_bus(hose->global_number, 434ff57b454SGavin Shan pdn->busno); 43505ba75f8SGavin Shan if (edev->pe->bus) 43605ba75f8SGavin Shan edev->pe->state |= EEH_PE_PRI_BUS; 43705ba75f8SGavin Shan } 43829310e5eSGavin Shan 43929310e5eSGavin Shan /* 44029310e5eSGavin Shan * Enable EEH explicitly so that we will do EEH check 44129310e5eSGavin Shan * while accessing I/O stuff 44229310e5eSGavin Shan */ 44305b1721dSGavin Shan eeh_add_flag(EEH_ENABLED); 44429310e5eSGavin Shan 44529310e5eSGavin Shan /* Save memory bars */ 44629310e5eSGavin Shan eeh_save_bars(edev); 44729310e5eSGavin Shan 448ff57b454SGavin Shan return NULL; 44929310e5eSGavin Shan } 45029310e5eSGavin Shan 45129310e5eSGavin Shan /** 45201f3bfb7SGavin Shan * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 45329310e5eSGavin Shan * @pe: EEH PE 45429310e5eSGavin Shan * @option: operation to be issued 45529310e5eSGavin Shan * 45629310e5eSGavin Shan * The function is used to control the EEH functionality globally. 45729310e5eSGavin Shan * Currently, following options are support according to PAPR: 45829310e5eSGavin Shan * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 45929310e5eSGavin Shan */ 46001f3bfb7SGavin Shan static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 46129310e5eSGavin Shan { 46229310e5eSGavin Shan struct pci_controller *hose = pe->phb; 46329310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 4647e3e4f8dSGavin Shan bool freeze_pe = false; 465f9433718SGavin Shan int opt; 4667e3e4f8dSGavin Shan s64 rc; 46729310e5eSGavin Shan 4687e3e4f8dSGavin Shan switch (option) { 4697e3e4f8dSGavin Shan case EEH_OPT_DISABLE: 4707e3e4f8dSGavin Shan return -EPERM; 4717e3e4f8dSGavin Shan case EEH_OPT_ENABLE: 4727e3e4f8dSGavin Shan return 0; 4737e3e4f8dSGavin Shan case EEH_OPT_THAW_MMIO: 4747e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 4757e3e4f8dSGavin Shan break; 4767e3e4f8dSGavin Shan case EEH_OPT_THAW_DMA: 4777e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 4787e3e4f8dSGavin Shan break; 4797e3e4f8dSGavin Shan case EEH_OPT_FREEZE_PE: 4807e3e4f8dSGavin Shan freeze_pe = true; 4817e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 4827e3e4f8dSGavin Shan break; 4837e3e4f8dSGavin Shan default: 4847e3e4f8dSGavin Shan pr_warn("%s: Invalid option %d\n", __func__, option); 4857e3e4f8dSGavin Shan return -EINVAL; 4867e3e4f8dSGavin Shan } 4877e3e4f8dSGavin Shan 488f9433718SGavin Shan /* Freeze master and slave PEs if PHB supports compound PEs */ 4897e3e4f8dSGavin Shan if (freeze_pe) { 4907e3e4f8dSGavin Shan if (phb->freeze_pe) { 4917e3e4f8dSGavin Shan phb->freeze_pe(phb, pe->addr); 492f9433718SGavin Shan return 0; 4937e3e4f8dSGavin Shan } 49429310e5eSGavin Shan 495f9433718SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 496f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 497f9433718SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 498f9433718SGavin Shan __func__, rc, phb->hose->global_number, 499f9433718SGavin Shan pe->addr); 500f9433718SGavin Shan return -EIO; 501f9433718SGavin Shan } 502f9433718SGavin Shan 503f9433718SGavin Shan return 0; 504f9433718SGavin Shan } 505f9433718SGavin Shan 506f9433718SGavin Shan /* Unfreeze master and slave PEs if PHB supports */ 507f9433718SGavin Shan if (phb->unfreeze_pe) 508f9433718SGavin Shan return phb->unfreeze_pe(phb, pe->addr, opt); 509f9433718SGavin Shan 510f9433718SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 511f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 512f9433718SGavin Shan pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 513f9433718SGavin Shan __func__, rc, option, phb->hose->global_number, 514f9433718SGavin Shan pe->addr); 515f9433718SGavin Shan return -EIO; 516f9433718SGavin Shan } 517f9433718SGavin Shan 518f9433718SGavin Shan return 0; 51929310e5eSGavin Shan } 52029310e5eSGavin Shan 52129310e5eSGavin Shan /** 52201f3bfb7SGavin Shan * pnv_eeh_get_pe_addr - Retrieve PE address 52329310e5eSGavin Shan * @pe: EEH PE 52429310e5eSGavin Shan * 52529310e5eSGavin Shan * Retrieve the PE address according to the given tranditional 52629310e5eSGavin Shan * PCI BDF (Bus/Device/Function) address. 52729310e5eSGavin Shan */ 52801f3bfb7SGavin Shan static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 52929310e5eSGavin Shan { 53029310e5eSGavin Shan return pe->addr; 53129310e5eSGavin Shan } 53229310e5eSGavin Shan 53340ae5f69SGavin Shan static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 53440ae5f69SGavin Shan { 53540ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 53640ae5f69SGavin Shan s64 rc; 53740ae5f69SGavin Shan 53840ae5f69SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 53940ae5f69SGavin Shan PNV_PCI_DIAG_BUF_SIZE); 54040ae5f69SGavin Shan if (rc != OPAL_SUCCESS) 54140ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 54240ae5f69SGavin Shan __func__, rc, pe->phb->global_number); 54340ae5f69SGavin Shan } 54440ae5f69SGavin Shan 54540ae5f69SGavin Shan static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 54640ae5f69SGavin Shan { 54740ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 54840ae5f69SGavin Shan u8 fstate; 54940ae5f69SGavin Shan __be16 pcierr; 55040ae5f69SGavin Shan s64 rc; 55140ae5f69SGavin Shan int result = 0; 55240ae5f69SGavin Shan 55340ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 55440ae5f69SGavin Shan pe->addr, 55540ae5f69SGavin Shan &fstate, 55640ae5f69SGavin Shan &pcierr, 55740ae5f69SGavin Shan NULL); 55840ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 55940ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x state\n", 56040ae5f69SGavin Shan __func__, rc, phb->hose->global_number); 56140ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 56240ae5f69SGavin Shan } 56340ae5f69SGavin Shan 56440ae5f69SGavin Shan /* 56540ae5f69SGavin Shan * Check PHB state. If the PHB is frozen for the 56640ae5f69SGavin Shan * first time, to dump the PHB diag-data. 56740ae5f69SGavin Shan */ 56840ae5f69SGavin Shan if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 56940ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 57040ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 57140ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 57240ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 57340ae5f69SGavin Shan } else if (!(pe->state & EEH_PE_ISOLATED)) { 57440ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 57540ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 57640ae5f69SGavin Shan 57740ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 57840ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 57940ae5f69SGavin Shan } 58040ae5f69SGavin Shan 58140ae5f69SGavin Shan return result; 58240ae5f69SGavin Shan } 58340ae5f69SGavin Shan 58440ae5f69SGavin Shan static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 58540ae5f69SGavin Shan { 58640ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 58740ae5f69SGavin Shan u8 fstate; 58840ae5f69SGavin Shan __be16 pcierr; 58940ae5f69SGavin Shan s64 rc; 59040ae5f69SGavin Shan int result; 59140ae5f69SGavin Shan 59240ae5f69SGavin Shan /* 59340ae5f69SGavin Shan * We don't clobber hardware frozen state until PE 59440ae5f69SGavin Shan * reset is completed. In order to keep EEH core 59540ae5f69SGavin Shan * moving forward, we have to return operational 59640ae5f69SGavin Shan * state during PE reset. 59740ae5f69SGavin Shan */ 59840ae5f69SGavin Shan if (pe->state & EEH_PE_RESET) { 59940ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 60040ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 60140ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 60240ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 60340ae5f69SGavin Shan return result; 60440ae5f69SGavin Shan } 60540ae5f69SGavin Shan 60640ae5f69SGavin Shan /* 60740ae5f69SGavin Shan * Fetch PE state from hardware. If the PHB 60840ae5f69SGavin Shan * supports compound PE, let it handle that. 60940ae5f69SGavin Shan */ 61040ae5f69SGavin Shan if (phb->get_pe_state) { 61140ae5f69SGavin Shan fstate = phb->get_pe_state(phb, pe->addr); 61240ae5f69SGavin Shan } else { 61340ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 61440ae5f69SGavin Shan pe->addr, 61540ae5f69SGavin Shan &fstate, 61640ae5f69SGavin Shan &pcierr, 61740ae5f69SGavin Shan NULL); 61840ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 61940ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 62040ae5f69SGavin Shan __func__, rc, phb->hose->global_number, 62140ae5f69SGavin Shan pe->addr); 62240ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 62340ae5f69SGavin Shan } 62440ae5f69SGavin Shan } 62540ae5f69SGavin Shan 62640ae5f69SGavin Shan /* Figure out state */ 62740ae5f69SGavin Shan switch (fstate) { 62840ae5f69SGavin Shan case OPAL_EEH_STOPPED_NOT_FROZEN: 62940ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 63040ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 63140ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 63240ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 63340ae5f69SGavin Shan break; 63440ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_FREEZE: 63540ae5f69SGavin Shan result = (EEH_STATE_DMA_ACTIVE | 63640ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 63740ae5f69SGavin Shan break; 63840ae5f69SGavin Shan case OPAL_EEH_STOPPED_DMA_FREEZE: 63940ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 64040ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED); 64140ae5f69SGavin Shan break; 64240ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 64340ae5f69SGavin Shan result = 0; 64440ae5f69SGavin Shan break; 64540ae5f69SGavin Shan case OPAL_EEH_STOPPED_RESET: 64640ae5f69SGavin Shan result = EEH_STATE_RESET_ACTIVE; 64740ae5f69SGavin Shan break; 64840ae5f69SGavin Shan case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 64940ae5f69SGavin Shan result = EEH_STATE_UNAVAILABLE; 65040ae5f69SGavin Shan break; 65140ae5f69SGavin Shan case OPAL_EEH_STOPPED_PERM_UNAVAIL: 65240ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 65340ae5f69SGavin Shan break; 65440ae5f69SGavin Shan default: 65540ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 65640ae5f69SGavin Shan pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 65740ae5f69SGavin Shan __func__, phb->hose->global_number, 65840ae5f69SGavin Shan pe->addr, fstate); 65940ae5f69SGavin Shan } 66040ae5f69SGavin Shan 66140ae5f69SGavin Shan /* 66240ae5f69SGavin Shan * If PHB supports compound PE, to freeze all 66340ae5f69SGavin Shan * slave PEs for consistency. 66440ae5f69SGavin Shan * 66540ae5f69SGavin Shan * If the PE is switching to frozen state for the 66640ae5f69SGavin Shan * first time, to dump the PHB diag-data. 66740ae5f69SGavin Shan */ 66840ae5f69SGavin Shan if (!(result & EEH_STATE_NOT_SUPPORT) && 66940ae5f69SGavin Shan !(result & EEH_STATE_UNAVAILABLE) && 67040ae5f69SGavin Shan !(result & EEH_STATE_MMIO_ACTIVE) && 67140ae5f69SGavin Shan !(result & EEH_STATE_DMA_ACTIVE) && 67240ae5f69SGavin Shan !(pe->state & EEH_PE_ISOLATED)) { 67340ae5f69SGavin Shan if (phb->freeze_pe) 67440ae5f69SGavin Shan phb->freeze_pe(phb, pe->addr); 67540ae5f69SGavin Shan 67640ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 67740ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 67840ae5f69SGavin Shan 67940ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 68040ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 68140ae5f69SGavin Shan } 68240ae5f69SGavin Shan 68340ae5f69SGavin Shan return result; 68440ae5f69SGavin Shan } 68540ae5f69SGavin Shan 68629310e5eSGavin Shan /** 68701f3bfb7SGavin Shan * pnv_eeh_get_state - Retrieve PE state 68829310e5eSGavin Shan * @pe: EEH PE 68929310e5eSGavin Shan * @delay: delay while PE state is temporarily unavailable 69029310e5eSGavin Shan * 69129310e5eSGavin Shan * Retrieve the state of the specified PE. For IODA-compitable 69229310e5eSGavin Shan * platform, it should be retrieved from IODA table. Therefore, 69329310e5eSGavin Shan * we prefer passing down to hardware implementation to handle 69429310e5eSGavin Shan * it. 69529310e5eSGavin Shan */ 69601f3bfb7SGavin Shan static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 69729310e5eSGavin Shan { 69840ae5f69SGavin Shan int ret; 69929310e5eSGavin Shan 70040ae5f69SGavin Shan if (pe->type & EEH_PE_PHB) 70140ae5f69SGavin Shan ret = pnv_eeh_get_phb_state(pe); 70240ae5f69SGavin Shan else 70340ae5f69SGavin Shan ret = pnv_eeh_get_pe_state(pe); 70440ae5f69SGavin Shan 70540ae5f69SGavin Shan if (!delay) 70640ae5f69SGavin Shan return ret; 70729310e5eSGavin Shan 70829310e5eSGavin Shan /* 70929310e5eSGavin Shan * If the PE state is temporarily unavailable, 71029310e5eSGavin Shan * to inform the EEH core delay for default 71129310e5eSGavin Shan * period (1 second) 71229310e5eSGavin Shan */ 71329310e5eSGavin Shan *delay = 0; 71429310e5eSGavin Shan if (ret & EEH_STATE_UNAVAILABLE) 71529310e5eSGavin Shan *delay = 1000; 71629310e5eSGavin Shan 71729310e5eSGavin Shan return ret; 71829310e5eSGavin Shan } 71929310e5eSGavin Shan 720ebe22531SGavin Shan static s64 pnv_eeh_poll(unsigned long id) 721cadf364dSGavin Shan { 722cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 723cadf364dSGavin Shan 724cadf364dSGavin Shan while (1) { 725ebe22531SGavin Shan rc = opal_pci_poll(id); 726cadf364dSGavin Shan if (rc <= 0) 727cadf364dSGavin Shan break; 728cadf364dSGavin Shan 729cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 730cadf364dSGavin Shan udelay(1000 * rc); 731cadf364dSGavin Shan else 732cadf364dSGavin Shan msleep(rc); 733cadf364dSGavin Shan } 734cadf364dSGavin Shan 735cadf364dSGavin Shan return rc; 736cadf364dSGavin Shan } 737cadf364dSGavin Shan 738cadf364dSGavin Shan int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 739cadf364dSGavin Shan { 740cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 741cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 742cadf364dSGavin Shan 743cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 744cadf364dSGavin Shan __func__, hose->global_number, option); 745cadf364dSGavin Shan 746cadf364dSGavin Shan /* Issue PHB complete reset request */ 747cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL || 748cadf364dSGavin Shan option == EEH_RESET_HOT) 749cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 750cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 751cadf364dSGavin Shan OPAL_ASSERT_RESET); 752cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 753cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 754cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 755cadf364dSGavin Shan OPAL_DEASSERT_RESET); 756cadf364dSGavin Shan if (rc < 0) 757cadf364dSGavin Shan goto out; 758cadf364dSGavin Shan 759cadf364dSGavin Shan /* 760cadf364dSGavin Shan * Poll state of the PHB until the request is done 761cadf364dSGavin Shan * successfully. The PHB reset is usually PHB complete 762cadf364dSGavin Shan * reset followed by hot reset on root bus. So we also 763cadf364dSGavin Shan * need the PCI bus settlement delay. 764cadf364dSGavin Shan */ 765ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 766cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) { 767cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 768cadf364dSGavin Shan udelay(1000 * EEH_PE_RST_SETTLE_TIME); 769cadf364dSGavin Shan else 770cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 771cadf364dSGavin Shan } 772cadf364dSGavin Shan out: 773cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 774cadf364dSGavin Shan return -EIO; 775cadf364dSGavin Shan 776cadf364dSGavin Shan return 0; 777cadf364dSGavin Shan } 778cadf364dSGavin Shan 779cadf364dSGavin Shan static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 780cadf364dSGavin Shan { 781cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 782cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 783cadf364dSGavin Shan 784cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 785cadf364dSGavin Shan __func__, hose->global_number, option); 786cadf364dSGavin Shan 787cadf364dSGavin Shan /* 788cadf364dSGavin Shan * During the reset deassert time, we needn't care 789cadf364dSGavin Shan * the reset scope because the firmware does nothing 790cadf364dSGavin Shan * for fundamental or hot reset during deassert phase. 791cadf364dSGavin Shan */ 792cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL) 793cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 794cadf364dSGavin Shan OPAL_RESET_PCI_FUNDAMENTAL, 795cadf364dSGavin Shan OPAL_ASSERT_RESET); 796cadf364dSGavin Shan else if (option == EEH_RESET_HOT) 797cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 798cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 799cadf364dSGavin Shan OPAL_ASSERT_RESET); 800cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 801cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 802cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 803cadf364dSGavin Shan OPAL_DEASSERT_RESET); 804cadf364dSGavin Shan if (rc < 0) 805cadf364dSGavin Shan goto out; 806cadf364dSGavin Shan 807cadf364dSGavin Shan /* Poll state of the PHB until the request is done */ 808ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 809cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) 810cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 811cadf364dSGavin Shan out: 812cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 813cadf364dSGavin Shan return -EIO; 814cadf364dSGavin Shan 815cadf364dSGavin Shan return 0; 816cadf364dSGavin Shan } 817cadf364dSGavin Shan 818cadf364dSGavin Shan static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 819cadf364dSGavin Shan { 8200bd78587SGavin Shan struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 8210bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 822cadf364dSGavin Shan int aer = edev ? edev->aer_cap : 0; 823cadf364dSGavin Shan u32 ctrl; 824cadf364dSGavin Shan 825cadf364dSGavin Shan pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 826cadf364dSGavin Shan __func__, pci_domain_nr(dev->bus), 827cadf364dSGavin Shan dev->bus->number, option); 828cadf364dSGavin Shan 829cadf364dSGavin Shan switch (option) { 830cadf364dSGavin Shan case EEH_RESET_FUNDAMENTAL: 831cadf364dSGavin Shan case EEH_RESET_HOT: 832cadf364dSGavin Shan /* Don't report linkDown event */ 833cadf364dSGavin Shan if (aer) { 8340bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 835cadf364dSGavin Shan 4, &ctrl); 836cadf364dSGavin Shan ctrl |= PCI_ERR_UNC_SURPDN; 8370bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 838cadf364dSGavin Shan 4, ctrl); 839cadf364dSGavin Shan } 840cadf364dSGavin Shan 8410bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 842cadf364dSGavin Shan ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 8430bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 844cadf364dSGavin Shan 845cadf364dSGavin Shan msleep(EEH_PE_RST_HOLD_TIME); 846cadf364dSGavin Shan break; 847cadf364dSGavin Shan case EEH_RESET_DEACTIVATE: 8480bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 849cadf364dSGavin Shan ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 8500bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 851cadf364dSGavin Shan 852cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 853cadf364dSGavin Shan 854cadf364dSGavin Shan /* Continue reporting linkDown event */ 855cadf364dSGavin Shan if (aer) { 8560bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 857cadf364dSGavin Shan 4, &ctrl); 858cadf364dSGavin Shan ctrl &= ~PCI_ERR_UNC_SURPDN; 8590bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 860cadf364dSGavin Shan 4, ctrl); 861cadf364dSGavin Shan } 862cadf364dSGavin Shan 863cadf364dSGavin Shan break; 864cadf364dSGavin Shan } 865cadf364dSGavin Shan 866cadf364dSGavin Shan return 0; 867cadf364dSGavin Shan } 868cadf364dSGavin Shan 869cadf364dSGavin Shan void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 870cadf364dSGavin Shan { 871848912e5SMichael Ellerman struct pci_controller *hose; 872848912e5SMichael Ellerman 873848912e5SMichael Ellerman if (pci_is_root_bus(dev->bus)) { 874848912e5SMichael Ellerman hose = pci_bus_to_host(dev->bus); 875848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_HOT); 876848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 877848912e5SMichael Ellerman } else { 878cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 879cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 880cadf364dSGavin Shan } 881848912e5SMichael Ellerman } 882cadf364dSGavin Shan 8839312bc5bSWei Yang static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 8849312bc5bSWei Yang int pos, u16 mask) 8859312bc5bSWei Yang { 8869312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 8879312bc5bSWei Yang int i, status = 0; 8889312bc5bSWei Yang 8899312bc5bSWei Yang /* Wait for Transaction Pending bit to be cleared */ 8909312bc5bSWei Yang for (i = 0; i < 4; i++) { 8919312bc5bSWei Yang eeh_ops->read_config(pdn, pos, 2, &status); 8929312bc5bSWei Yang if (!(status & mask)) 8939312bc5bSWei Yang return; 8949312bc5bSWei Yang 8959312bc5bSWei Yang msleep((1 << i) * 100); 8969312bc5bSWei Yang } 8979312bc5bSWei Yang 8989312bc5bSWei Yang pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 8999312bc5bSWei Yang __func__, type, 9009312bc5bSWei Yang edev->phb->global_number, pdn->busno, 9019312bc5bSWei Yang PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 9029312bc5bSWei Yang } 9039312bc5bSWei Yang 9049312bc5bSWei Yang static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 9059312bc5bSWei Yang { 9069312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9079312bc5bSWei Yang u32 reg = 0; 9089312bc5bSWei Yang 9099312bc5bSWei Yang if (WARN_ON(!edev->pcie_cap)) 9109312bc5bSWei Yang return -ENOTTY; 9119312bc5bSWei Yang 9129312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 9139312bc5bSWei Yang if (!(reg & PCI_EXP_DEVCAP_FLR)) 9149312bc5bSWei Yang return -ENOTTY; 9159312bc5bSWei Yang 9169312bc5bSWei Yang switch (option) { 9179312bc5bSWei Yang case EEH_RESET_HOT: 9189312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 9199312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "", 9209312bc5bSWei Yang edev->pcie_cap + PCI_EXP_DEVSTA, 9219312bc5bSWei Yang PCI_EXP_DEVSTA_TRPND); 9229312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9239312bc5bSWei Yang 4, ®); 9249312bc5bSWei Yang reg |= PCI_EXP_DEVCTL_BCR_FLR; 9259312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9269312bc5bSWei Yang 4, reg); 9279312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 9289312bc5bSWei Yang break; 9299312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 9309312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9319312bc5bSWei Yang 4, ®); 9329312bc5bSWei Yang reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 9339312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9349312bc5bSWei Yang 4, reg); 9359312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 9369312bc5bSWei Yang break; 9379312bc5bSWei Yang } 9389312bc5bSWei Yang 9399312bc5bSWei Yang return 0; 9409312bc5bSWei Yang } 9419312bc5bSWei Yang 9429312bc5bSWei Yang static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 9439312bc5bSWei Yang { 9449312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9459312bc5bSWei Yang u32 cap = 0; 9469312bc5bSWei Yang 9479312bc5bSWei Yang if (WARN_ON(!edev->af_cap)) 9489312bc5bSWei Yang return -ENOTTY; 9499312bc5bSWei Yang 9509312bc5bSWei Yang eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 9519312bc5bSWei Yang if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 9529312bc5bSWei Yang return -ENOTTY; 9539312bc5bSWei Yang 9549312bc5bSWei Yang switch (option) { 9559312bc5bSWei Yang case EEH_RESET_HOT: 9569312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 9579312bc5bSWei Yang /* 9589312bc5bSWei Yang * Wait for Transaction Pending bit to clear. A word-aligned 9599312bc5bSWei Yang * test is used, so we use the conrol offset rather than status 9609312bc5bSWei Yang * and shift the test bit to match. 9619312bc5bSWei Yang */ 9629312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "AF", 9639312bc5bSWei Yang edev->af_cap + PCI_AF_CTRL, 9649312bc5bSWei Yang PCI_AF_STATUS_TP << 8); 9659312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 9669312bc5bSWei Yang 1, PCI_AF_CTRL_FLR); 9679312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 9689312bc5bSWei Yang break; 9699312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 9709312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 9719312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 9729312bc5bSWei Yang break; 9739312bc5bSWei Yang } 9749312bc5bSWei Yang 9759312bc5bSWei Yang return 0; 9769312bc5bSWei Yang } 9779312bc5bSWei Yang 9789312bc5bSWei Yang static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 9799312bc5bSWei Yang { 9809312bc5bSWei Yang struct eeh_dev *edev; 9819312bc5bSWei Yang struct pci_dn *pdn; 9829312bc5bSWei Yang int ret; 9839312bc5bSWei Yang 9849312bc5bSWei Yang /* The VF PE should have only one child device */ 9859312bc5bSWei Yang edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list); 9869312bc5bSWei Yang pdn = eeh_dev_to_pdn(edev); 9879312bc5bSWei Yang if (!pdn) 9889312bc5bSWei Yang return -ENXIO; 9899312bc5bSWei Yang 9909312bc5bSWei Yang ret = pnv_eeh_do_flr(pdn, option); 9919312bc5bSWei Yang if (!ret) 9929312bc5bSWei Yang return ret; 9939312bc5bSWei Yang 9949312bc5bSWei Yang return pnv_eeh_do_af_flr(pdn, option); 9959312bc5bSWei Yang } 9969312bc5bSWei Yang 99729310e5eSGavin Shan /** 99801f3bfb7SGavin Shan * pnv_eeh_reset - Reset the specified PE 99929310e5eSGavin Shan * @pe: EEH PE 100029310e5eSGavin Shan * @option: reset option 100129310e5eSGavin Shan * 1002cadf364dSGavin Shan * Do reset on the indicated PE. For PCI bus sensitive PE, 1003cadf364dSGavin Shan * we need to reset the parent p2p bridge. The PHB has to 1004cadf364dSGavin Shan * be reinitialized if the p2p bridge is root bridge. For 1005cadf364dSGavin Shan * PCI device sensitive PE, we will try to reset the device 1006cadf364dSGavin Shan * through FLR. For now, we don't have OPAL APIs to do HARD 1007cadf364dSGavin Shan * reset yet, so all reset would be SOFT (HOT) reset. 100829310e5eSGavin Shan */ 100901f3bfb7SGavin Shan static int pnv_eeh_reset(struct eeh_pe *pe, int option) 101029310e5eSGavin Shan { 101129310e5eSGavin Shan struct pci_controller *hose = pe->phb; 10124fad4943SGavin Shan struct pnv_phb *phb; 1013cadf364dSGavin Shan struct pci_bus *bus; 10144fad4943SGavin Shan int64_t rc; 101529310e5eSGavin Shan 1016cadf364dSGavin Shan /* 1017cadf364dSGavin Shan * For PHB reset, we always have complete reset. For those PEs whose 1018cadf364dSGavin Shan * primary bus derived from root complex (root bus) or root port 1019cadf364dSGavin Shan * (usually bus#1), we apply hot or fundamental reset on the root port. 1020cadf364dSGavin Shan * For other PEs, we always have hot reset on the PE primary bus. 1021cadf364dSGavin Shan * 1022cadf364dSGavin Shan * Here, we have different design to pHyp, which always clear the 1023cadf364dSGavin Shan * frozen state during PE reset. However, the good idea here from 1024cadf364dSGavin Shan * benh is to keep frozen state before we get PE reset done completely 1025cadf364dSGavin Shan * (until BAR restore). With the frozen state, HW drops illegal IO 1026cadf364dSGavin Shan * or MMIO access, which can incur recrusive frozen PE during PE 1027cadf364dSGavin Shan * reset. The side effect is that EEH core has to clear the frozen 1028cadf364dSGavin Shan * state explicitly after BAR restore. 1029cadf364dSGavin Shan */ 10304fad4943SGavin Shan if (pe->type & EEH_PE_PHB) 10314fad4943SGavin Shan return pnv_eeh_phb_reset(hose, option); 1032cadf364dSGavin Shan 1033cadf364dSGavin Shan /* 1034cadf364dSGavin Shan * The frozen PE might be caused by PAPR error injection 1035cadf364dSGavin Shan * registers, which are expected to be cleared after hitting 1036cadf364dSGavin Shan * frozen PE as stated in the hardware spec. Unfortunately, 1037cadf364dSGavin Shan * that's not true on P7IOC. So we have to clear it manually 1038cadf364dSGavin Shan * to avoid recursive EEH errors during recovery. 1039cadf364dSGavin Shan */ 1040cadf364dSGavin Shan phb = hose->private_data; 1041cadf364dSGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC && 1042cadf364dSGavin Shan (option == EEH_RESET_HOT || 1043cadf364dSGavin Shan option == EEH_RESET_FUNDAMENTAL)) { 1044cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 1045cadf364dSGavin Shan OPAL_RESET_PHB_ERROR, 1046cadf364dSGavin Shan OPAL_ASSERT_RESET); 1047cadf364dSGavin Shan if (rc != OPAL_SUCCESS) { 10484fad4943SGavin Shan pr_warn("%s: Failure %lld clearing error injection registers\n", 1049cadf364dSGavin Shan __func__, rc); 1050cadf364dSGavin Shan return -EIO; 1051cadf364dSGavin Shan } 1052cadf364dSGavin Shan } 1053cadf364dSGavin Shan 1054cadf364dSGavin Shan bus = eeh_pe_bus_get(pe); 10559312bc5bSWei Yang if (pe->type & EEH_PE_VF) 10564fad4943SGavin Shan return pnv_eeh_reset_vf_pe(pe, option); 105729310e5eSGavin Shan 10584fad4943SGavin Shan if (pci_is_root_bus(bus) || 10594fad4943SGavin Shan pci_is_root_bus(bus->parent)) 10604fad4943SGavin Shan return pnv_eeh_root_reset(hose, option); 10614fad4943SGavin Shan 10624fad4943SGavin Shan return pnv_eeh_bridge_reset(bus->self, option); 106329310e5eSGavin Shan } 106429310e5eSGavin Shan 106529310e5eSGavin Shan /** 106601f3bfb7SGavin Shan * pnv_eeh_wait_state - Wait for PE state 106729310e5eSGavin Shan * @pe: EEH PE 10682ac3990cSWei Yang * @max_wait: maximal period in millisecond 106929310e5eSGavin Shan * 107029310e5eSGavin Shan * Wait for the state of associated PE. It might take some time 107129310e5eSGavin Shan * to retrieve the PE's state. 107229310e5eSGavin Shan */ 107301f3bfb7SGavin Shan static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) 107429310e5eSGavin Shan { 107529310e5eSGavin Shan int ret; 107629310e5eSGavin Shan int mwait; 107729310e5eSGavin Shan 107829310e5eSGavin Shan while (1) { 107901f3bfb7SGavin Shan ret = pnv_eeh_get_state(pe, &mwait); 108029310e5eSGavin Shan 108129310e5eSGavin Shan /* 108229310e5eSGavin Shan * If the PE's state is temporarily unavailable, 108329310e5eSGavin Shan * we have to wait for the specified time. Otherwise, 108429310e5eSGavin Shan * the PE's state will be returned immediately. 108529310e5eSGavin Shan */ 108629310e5eSGavin Shan if (ret != EEH_STATE_UNAVAILABLE) 108729310e5eSGavin Shan return ret; 108829310e5eSGavin Shan 108929310e5eSGavin Shan if (max_wait <= 0) { 10900dae2743SGavin Shan pr_warn("%s: Timeout getting PE#%x's state (%d)\n", 109129310e5eSGavin Shan __func__, pe->addr, max_wait); 109229310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 109329310e5eSGavin Shan } 109429310e5eSGavin Shan 1095e17866d5SWei Yang max_wait -= mwait; 109629310e5eSGavin Shan msleep(mwait); 109729310e5eSGavin Shan } 109829310e5eSGavin Shan 109929310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 110029310e5eSGavin Shan } 110129310e5eSGavin Shan 110229310e5eSGavin Shan /** 110301f3bfb7SGavin Shan * pnv_eeh_get_log - Retrieve error log 110429310e5eSGavin Shan * @pe: EEH PE 110529310e5eSGavin Shan * @severity: temporary or permanent error log 110629310e5eSGavin Shan * @drv_log: driver log to be combined with retrieved error log 110729310e5eSGavin Shan * @len: length of driver log 110829310e5eSGavin Shan * 110929310e5eSGavin Shan * Retrieve the temporary or permanent error from the PE. 111029310e5eSGavin Shan */ 111101f3bfb7SGavin Shan static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 111229310e5eSGavin Shan char *drv_log, unsigned long len) 111329310e5eSGavin Shan { 111495edcdeaSGavin Shan if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 111595edcdeaSGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 111629310e5eSGavin Shan 111795edcdeaSGavin Shan return 0; 111829310e5eSGavin Shan } 111929310e5eSGavin Shan 112029310e5eSGavin Shan /** 112101f3bfb7SGavin Shan * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 112229310e5eSGavin Shan * @pe: EEH PE 112329310e5eSGavin Shan * 112429310e5eSGavin Shan * The function will be called to reconfigure the bridges included 112529310e5eSGavin Shan * in the specified PE so that the mulfunctional PE would be recovered 112629310e5eSGavin Shan * again. 112729310e5eSGavin Shan */ 112801f3bfb7SGavin Shan static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 112929310e5eSGavin Shan { 1130bbe170edSGavin Shan return 0; 113129310e5eSGavin Shan } 113229310e5eSGavin Shan 113329310e5eSGavin Shan /** 113401f3bfb7SGavin Shan * pnv_pe_err_inject - Inject specified error to the indicated PE 1135131c123aSGavin Shan * @pe: the indicated PE 1136131c123aSGavin Shan * @type: error type 1137131c123aSGavin Shan * @func: specific error type 1138131c123aSGavin Shan * @addr: address 1139131c123aSGavin Shan * @mask: address mask 1140131c123aSGavin Shan * 1141131c123aSGavin Shan * The routine is called to inject specified error, which is 1142131c123aSGavin Shan * determined by @type and @func, to the indicated PE for 1143131c123aSGavin Shan * testing purpose. 1144131c123aSGavin Shan */ 114501f3bfb7SGavin Shan static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1146131c123aSGavin Shan unsigned long addr, unsigned long mask) 1147131c123aSGavin Shan { 1148131c123aSGavin Shan struct pci_controller *hose = pe->phb; 1149131c123aSGavin Shan struct pnv_phb *phb = hose->private_data; 1150fa646c3cSGavin Shan s64 rc; 1151131c123aSGavin Shan 1152fa646c3cSGavin Shan if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1153fa646c3cSGavin Shan type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1154fa646c3cSGavin Shan pr_warn("%s: Invalid error type %d\n", 1155fa646c3cSGavin Shan __func__, type); 1156fa646c3cSGavin Shan return -ERANGE; 1157fa646c3cSGavin Shan } 1158131c123aSGavin Shan 1159fa646c3cSGavin Shan if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1160fa646c3cSGavin Shan func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1161fa646c3cSGavin Shan pr_warn("%s: Invalid error function %d\n", 1162fa646c3cSGavin Shan __func__, func); 1163fa646c3cSGavin Shan return -ERANGE; 1164fa646c3cSGavin Shan } 1165fa646c3cSGavin Shan 1166fa646c3cSGavin Shan /* Firmware supports error injection ? */ 1167fa646c3cSGavin Shan if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1168fa646c3cSGavin Shan pr_warn("%s: Firmware doesn't support error injection\n", 1169fa646c3cSGavin Shan __func__); 1170fa646c3cSGavin Shan return -ENXIO; 1171fa646c3cSGavin Shan } 1172fa646c3cSGavin Shan 1173fa646c3cSGavin Shan /* Do error injection */ 1174fa646c3cSGavin Shan rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1175fa646c3cSGavin Shan type, func, addr, mask); 1176fa646c3cSGavin Shan if (rc != OPAL_SUCCESS) { 1177fa646c3cSGavin Shan pr_warn("%s: Failure %lld injecting error " 1178fa646c3cSGavin Shan "%d-%d to PHB#%x-PE#%x\n", 1179fa646c3cSGavin Shan __func__, rc, type, func, 1180fa646c3cSGavin Shan hose->global_number, pe->addr); 1181fa646c3cSGavin Shan return -EIO; 1182fa646c3cSGavin Shan } 1183fa646c3cSGavin Shan 1184fa646c3cSGavin Shan return 0; 1185131c123aSGavin Shan } 1186131c123aSGavin Shan 11870bd78587SGavin Shan static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1188d2cfbcd7SGavin Shan { 11890bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1190d2cfbcd7SGavin Shan 1191d2cfbcd7SGavin Shan if (!edev || !edev->pe) 1192d2cfbcd7SGavin Shan return false; 1193d2cfbcd7SGavin Shan 11949312bc5bSWei Yang /* 11959312bc5bSWei Yang * We will issue FLR or AF FLR to all VFs, which are contained 11969312bc5bSWei Yang * in VF PE. It relies on the EEH PCI config accessors. So we 11979312bc5bSWei Yang * can't block them during the window. 11989312bc5bSWei Yang */ 11999312bc5bSWei Yang if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 12009312bc5bSWei Yang return false; 12019312bc5bSWei Yang 1202d2cfbcd7SGavin Shan if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1203d2cfbcd7SGavin Shan return true; 1204d2cfbcd7SGavin Shan 1205d2cfbcd7SGavin Shan return false; 1206d2cfbcd7SGavin Shan } 1207d2cfbcd7SGavin Shan 12080bd78587SGavin Shan static int pnv_eeh_read_config(struct pci_dn *pdn, 1209d2cfbcd7SGavin Shan int where, int size, u32 *val) 1210d2cfbcd7SGavin Shan { 12113532a741SGavin Shan if (!pdn) 12123532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12133532a741SGavin Shan 12140bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) { 1215d2cfbcd7SGavin Shan *val = 0xFFFFFFFF; 1216d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1217d2cfbcd7SGavin Shan } 1218d2cfbcd7SGavin Shan 12193532a741SGavin Shan return pnv_pci_cfg_read(pdn, where, size, val); 1220d2cfbcd7SGavin Shan } 1221d2cfbcd7SGavin Shan 12220bd78587SGavin Shan static int pnv_eeh_write_config(struct pci_dn *pdn, 1223d2cfbcd7SGavin Shan int where, int size, u32 val) 1224d2cfbcd7SGavin Shan { 12253532a741SGavin Shan if (!pdn) 12263532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12273532a741SGavin Shan 12280bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) 1229d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1230d2cfbcd7SGavin Shan 12313532a741SGavin Shan return pnv_pci_cfg_write(pdn, where, size, val); 1232d2cfbcd7SGavin Shan } 1233d2cfbcd7SGavin Shan 12342a485ad7SGavin Shan static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 12352a485ad7SGavin Shan { 12362a485ad7SGavin Shan /* GEM */ 12372a485ad7SGavin Shan if (data->gemXfir || data->gemRfir || 12382a485ad7SGavin Shan data->gemRirqfir || data->gemMask || data->gemRwof) 12392a485ad7SGavin Shan pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 12402a485ad7SGavin Shan be64_to_cpu(data->gemXfir), 12412a485ad7SGavin Shan be64_to_cpu(data->gemRfir), 12422a485ad7SGavin Shan be64_to_cpu(data->gemRirqfir), 12432a485ad7SGavin Shan be64_to_cpu(data->gemMask), 12442a485ad7SGavin Shan be64_to_cpu(data->gemRwof)); 12452a485ad7SGavin Shan 12462a485ad7SGavin Shan /* LEM */ 12472a485ad7SGavin Shan if (data->lemFir || data->lemErrMask || 12482a485ad7SGavin Shan data->lemAction0 || data->lemAction1 || data->lemWof) 12492a485ad7SGavin Shan pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 12502a485ad7SGavin Shan be64_to_cpu(data->lemFir), 12512a485ad7SGavin Shan be64_to_cpu(data->lemErrMask), 12522a485ad7SGavin Shan be64_to_cpu(data->lemAction0), 12532a485ad7SGavin Shan be64_to_cpu(data->lemAction1), 12542a485ad7SGavin Shan be64_to_cpu(data->lemWof)); 12552a485ad7SGavin Shan } 12562a485ad7SGavin Shan 12572a485ad7SGavin Shan static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 12582a485ad7SGavin Shan { 12592a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 12602a485ad7SGavin Shan struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag; 12612a485ad7SGavin Shan long rc; 12622a485ad7SGavin Shan 12632a485ad7SGavin Shan rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 12642a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 12652a485ad7SGavin Shan pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 12662a485ad7SGavin Shan __func__, phb->hub_id, rc); 12672a485ad7SGavin Shan return; 12682a485ad7SGavin Shan } 12692a485ad7SGavin Shan 12702a485ad7SGavin Shan switch (data->type) { 12712a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_RGC: 12722a485ad7SGavin Shan pr_info("P7IOC diag-data for RGC\n\n"); 12732a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 12742a485ad7SGavin Shan if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 12752a485ad7SGavin Shan pr_info(" RGC: %016llx %016llx\n", 12762a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcStatus), 12772a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcLdcp)); 12782a485ad7SGavin Shan break; 12792a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_BI: 12802a485ad7SGavin Shan pr_info("P7IOC diag-data for BI %s\n\n", 12812a485ad7SGavin Shan data->bi.biDownbound ? "Downbound" : "Upbound"); 12822a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 12832a485ad7SGavin Shan if (data->bi.biLdcp0 || data->bi.biLdcp1 || 12842a485ad7SGavin Shan data->bi.biLdcp2 || data->bi.biFenceStatus) 12852a485ad7SGavin Shan pr_info(" BI: %016llx %016llx %016llx %016llx\n", 12862a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp0), 12872a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp1), 12882a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp2), 12892a485ad7SGavin Shan be64_to_cpu(data->bi.biFenceStatus)); 12902a485ad7SGavin Shan break; 12912a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_CI: 12922a485ad7SGavin Shan pr_info("P7IOC diag-data for CI Port %d\n\n", 12932a485ad7SGavin Shan data->ci.ciPort); 12942a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 12952a485ad7SGavin Shan if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 12962a485ad7SGavin Shan pr_info(" CI: %016llx %016llx\n", 12972a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortStatus), 12982a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortLdcp)); 12992a485ad7SGavin Shan break; 13002a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_MISC: 13012a485ad7SGavin Shan pr_info("P7IOC diag-data for MISC\n\n"); 13022a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13032a485ad7SGavin Shan break; 13042a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_I2C: 13052a485ad7SGavin Shan pr_info("P7IOC diag-data for I2C\n\n"); 13062a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13072a485ad7SGavin Shan break; 13082a485ad7SGavin Shan default: 13092a485ad7SGavin Shan pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 13102a485ad7SGavin Shan __func__, phb->hub_id, data->type); 13112a485ad7SGavin Shan } 13122a485ad7SGavin Shan } 13132a485ad7SGavin Shan 13142a485ad7SGavin Shan static int pnv_eeh_get_pe(struct pci_controller *hose, 13152a485ad7SGavin Shan u16 pe_no, struct eeh_pe **pe) 13162a485ad7SGavin Shan { 13172a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 13182a485ad7SGavin Shan struct pnv_ioda_pe *pnv_pe; 13192a485ad7SGavin Shan struct eeh_pe *dev_pe; 13202a485ad7SGavin Shan struct eeh_dev edev; 13212a485ad7SGavin Shan 13222a485ad7SGavin Shan /* 13232a485ad7SGavin Shan * If PHB supports compound PE, to fetch 13242a485ad7SGavin Shan * the master PE because slave PE is invisible 13252a485ad7SGavin Shan * to EEH core. 13262a485ad7SGavin Shan */ 13272a485ad7SGavin Shan pnv_pe = &phb->ioda.pe_array[pe_no]; 13282a485ad7SGavin Shan if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 13292a485ad7SGavin Shan pnv_pe = pnv_pe->master; 13302a485ad7SGavin Shan WARN_ON(!pnv_pe || 13312a485ad7SGavin Shan !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 13322a485ad7SGavin Shan pe_no = pnv_pe->pe_number; 13332a485ad7SGavin Shan } 13342a485ad7SGavin Shan 13352a485ad7SGavin Shan /* Find the PE according to PE# */ 13362a485ad7SGavin Shan memset(&edev, 0, sizeof(struct eeh_dev)); 13372a485ad7SGavin Shan edev.phb = hose; 13382a485ad7SGavin Shan edev.pe_config_addr = pe_no; 13392a485ad7SGavin Shan dev_pe = eeh_pe_get(&edev); 13402a485ad7SGavin Shan if (!dev_pe) 13412a485ad7SGavin Shan return -EEXIST; 13422a485ad7SGavin Shan 13432a485ad7SGavin Shan /* Freeze the (compound) PE */ 13442a485ad7SGavin Shan *pe = dev_pe; 13452a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 13462a485ad7SGavin Shan phb->freeze_pe(phb, pe_no); 13472a485ad7SGavin Shan 13482a485ad7SGavin Shan /* 13492a485ad7SGavin Shan * At this point, we're sure the (compound) PE should 13502a485ad7SGavin Shan * have been frozen. However, we still need poke until 13512a485ad7SGavin Shan * hitting the frozen PE on top level. 13522a485ad7SGavin Shan */ 13532a485ad7SGavin Shan dev_pe = dev_pe->parent; 13542a485ad7SGavin Shan while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 13552a485ad7SGavin Shan int ret; 13562a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | 13572a485ad7SGavin Shan EEH_STATE_DMA_ACTIVE); 13582a485ad7SGavin Shan 13592a485ad7SGavin Shan ret = eeh_ops->get_state(dev_pe, NULL); 13602a485ad7SGavin Shan if (ret <= 0 || (ret & active_flags) == active_flags) { 13612a485ad7SGavin Shan dev_pe = dev_pe->parent; 13622a485ad7SGavin Shan continue; 13632a485ad7SGavin Shan } 13642a485ad7SGavin Shan 13652a485ad7SGavin Shan /* Frozen parent PE */ 13662a485ad7SGavin Shan *pe = dev_pe; 13672a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 13682a485ad7SGavin Shan phb->freeze_pe(phb, dev_pe->addr); 13692a485ad7SGavin Shan 13702a485ad7SGavin Shan /* Next one */ 13712a485ad7SGavin Shan dev_pe = dev_pe->parent; 13722a485ad7SGavin Shan } 13732a485ad7SGavin Shan 13742a485ad7SGavin Shan return 0; 13752a485ad7SGavin Shan } 13762a485ad7SGavin Shan 1377131c123aSGavin Shan /** 137801f3bfb7SGavin Shan * pnv_eeh_next_error - Retrieve next EEH error to handle 137929310e5eSGavin Shan * @pe: Affected PE 138029310e5eSGavin Shan * 13812a485ad7SGavin Shan * The function is expected to be called by EEH core while it gets 13822a485ad7SGavin Shan * special EEH event (without binding PE). The function calls to 13832a485ad7SGavin Shan * OPAL APIs for next error to handle. The informational error is 13842a485ad7SGavin Shan * handled internally by platform. However, the dead IOC, dead PHB, 13852a485ad7SGavin Shan * fenced PHB and frozen PE should be handled by EEH core eventually. 138629310e5eSGavin Shan */ 138701f3bfb7SGavin Shan static int pnv_eeh_next_error(struct eeh_pe **pe) 138829310e5eSGavin Shan { 138929310e5eSGavin Shan struct pci_controller *hose; 13902a485ad7SGavin Shan struct pnv_phb *phb; 13912a485ad7SGavin Shan struct eeh_pe *phb_pe, *parent_pe; 13922a485ad7SGavin Shan __be64 frozen_pe_no; 13932a485ad7SGavin Shan __be16 err_type, severity; 13942a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 13952a485ad7SGavin Shan long rc; 13962a485ad7SGavin Shan int state, ret = EEH_NEXT_ERR_NONE; 13972a485ad7SGavin Shan 13982a485ad7SGavin Shan /* 139979231448SAlistair Popple * While running here, it's safe to purge the event queue. The 140079231448SAlistair Popple * event should still be masked. 14012a485ad7SGavin Shan */ 14022a485ad7SGavin Shan eeh_remove_event(NULL, false); 140329310e5eSGavin Shan 140429310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 14052a485ad7SGavin Shan /* 14062a485ad7SGavin Shan * If the subordinate PCI buses of the PHB has been 14072a485ad7SGavin Shan * removed or is exactly under error recovery, we 14082a485ad7SGavin Shan * needn't take care of it any more. 14092a485ad7SGavin Shan */ 141029310e5eSGavin Shan phb = hose->private_data; 14112a485ad7SGavin Shan phb_pe = eeh_phb_pe_get(hose); 14122a485ad7SGavin Shan if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 14132a485ad7SGavin Shan continue; 14142a485ad7SGavin Shan 14152a485ad7SGavin Shan rc = opal_pci_next_error(phb->opal_id, 14162a485ad7SGavin Shan &frozen_pe_no, &err_type, &severity); 14172a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 14182a485ad7SGavin Shan pr_devel("%s: Invalid return value on " 14192a485ad7SGavin Shan "PHB#%x (0x%lx) from opal_pci_next_error", 14202a485ad7SGavin Shan __func__, hose->global_number, rc); 14212a485ad7SGavin Shan continue; 14222a485ad7SGavin Shan } 14232a485ad7SGavin Shan 14242a485ad7SGavin Shan /* If the PHB doesn't have error, stop processing */ 14252a485ad7SGavin Shan if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 14262a485ad7SGavin Shan be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 14272a485ad7SGavin Shan pr_devel("%s: No error found on PHB#%x\n", 14282a485ad7SGavin Shan __func__, hose->global_number); 14292a485ad7SGavin Shan continue; 14302a485ad7SGavin Shan } 14312a485ad7SGavin Shan 14322a485ad7SGavin Shan /* 14332a485ad7SGavin Shan * Processing the error. We're expecting the error with 14342a485ad7SGavin Shan * highest priority reported upon multiple errors on the 14352a485ad7SGavin Shan * specific PHB. 14362a485ad7SGavin Shan */ 14372a485ad7SGavin Shan pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 14382a485ad7SGavin Shan __func__, be16_to_cpu(err_type), 14392a485ad7SGavin Shan be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 14402a485ad7SGavin Shan hose->global_number); 14412a485ad7SGavin Shan switch (be16_to_cpu(err_type)) { 14422a485ad7SGavin Shan case OPAL_EEH_IOC_ERROR: 14432a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 14442a485ad7SGavin Shan pr_err("EEH: dead IOC detected\n"); 14452a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_IOC; 14462a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 14472a485ad7SGavin Shan pr_info("EEH: IOC informative error " 14482a485ad7SGavin Shan "detected\n"); 14492a485ad7SGavin Shan pnv_eeh_get_and_dump_hub_diag(hose); 14502a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 14512a485ad7SGavin Shan } 14522a485ad7SGavin Shan 14532a485ad7SGavin Shan break; 14542a485ad7SGavin Shan case OPAL_EEH_PHB_ERROR: 14552a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 14562a485ad7SGavin Shan *pe = phb_pe; 14572a485ad7SGavin Shan pr_err("EEH: dead PHB#%x detected, " 14582a485ad7SGavin Shan "location: %s\n", 14592a485ad7SGavin Shan hose->global_number, 14602a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14612a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_PHB; 14622a485ad7SGavin Shan } else if (be16_to_cpu(severity) == 14632a485ad7SGavin Shan OPAL_EEH_SEV_PHB_FENCED) { 14642a485ad7SGavin Shan *pe = phb_pe; 14652a485ad7SGavin Shan pr_err("EEH: Fenced PHB#%x detected, " 14662a485ad7SGavin Shan "location: %s\n", 14672a485ad7SGavin Shan hose->global_number, 14682a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14692a485ad7SGavin Shan ret = EEH_NEXT_ERR_FENCED_PHB; 14702a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 14712a485ad7SGavin Shan pr_info("EEH: PHB#%x informative error " 14722a485ad7SGavin Shan "detected, location: %s\n", 14732a485ad7SGavin Shan hose->global_number, 14742a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14752a485ad7SGavin Shan pnv_eeh_get_phb_diag(phb_pe); 14762a485ad7SGavin Shan pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 14772a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 14782a485ad7SGavin Shan } 14792a485ad7SGavin Shan 14802a485ad7SGavin Shan break; 14812a485ad7SGavin Shan case OPAL_EEH_PE_ERROR: 14822a485ad7SGavin Shan /* 14832a485ad7SGavin Shan * If we can't find the corresponding PE, we 14842a485ad7SGavin Shan * just try to unfreeze. 14852a485ad7SGavin Shan */ 14862a485ad7SGavin Shan if (pnv_eeh_get_pe(hose, 14872a485ad7SGavin Shan be64_to_cpu(frozen_pe_no), pe)) { 14882a485ad7SGavin Shan pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 14890f36db77SGavin Shan hose->global_number, be64_to_cpu(frozen_pe_no)); 14902a485ad7SGavin Shan pr_info("EEH: PHB location: %s\n", 14912a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 149279cd9520SGavin Shan 149379cd9520SGavin Shan /* Dump PHB diag-data */ 149479cd9520SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, 149579cd9520SGavin Shan phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE); 149679cd9520SGavin Shan if (rc == OPAL_SUCCESS) 149779cd9520SGavin Shan pnv_pci_dump_phb_diag_data(hose, 149879cd9520SGavin Shan phb->diag.blob); 149979cd9520SGavin Shan 150079cd9520SGavin Shan /* Try best to clear it */ 15012a485ad7SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 15022a485ad7SGavin Shan frozen_pe_no, 15032a485ad7SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 15042a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15052a485ad7SGavin Shan } else if ((*pe)->state & EEH_PE_ISOLATED || 15062a485ad7SGavin Shan eeh_pe_passed(*pe)) { 15072a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15082a485ad7SGavin Shan } else { 15092a485ad7SGavin Shan pr_err("EEH: Frozen PE#%x " 15102a485ad7SGavin Shan "on PHB#%x detected\n", 15112a485ad7SGavin Shan (*pe)->addr, 15122a485ad7SGavin Shan (*pe)->phb->global_number); 15132a485ad7SGavin Shan pr_err("EEH: PE location: %s, " 15142a485ad7SGavin Shan "PHB location: %s\n", 15152a485ad7SGavin Shan eeh_pe_loc_get(*pe), 15162a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15172a485ad7SGavin Shan ret = EEH_NEXT_ERR_FROZEN_PE; 15182a485ad7SGavin Shan } 15192a485ad7SGavin Shan 15202a485ad7SGavin Shan break; 15212a485ad7SGavin Shan default: 15222a485ad7SGavin Shan pr_warn("%s: Unexpected error type %d\n", 15232a485ad7SGavin Shan __func__, be16_to_cpu(err_type)); 15242a485ad7SGavin Shan } 15252a485ad7SGavin Shan 15262a485ad7SGavin Shan /* 15272a485ad7SGavin Shan * EEH core will try recover from fenced PHB or 15282a485ad7SGavin Shan * frozen PE. In the time for frozen PE, EEH core 15292a485ad7SGavin Shan * enable IO path for that before collecting logs, 15302a485ad7SGavin Shan * but it ruins the site. So we have to dump the 15312a485ad7SGavin Shan * log in advance here. 15322a485ad7SGavin Shan */ 15332a485ad7SGavin Shan if ((ret == EEH_NEXT_ERR_FROZEN_PE || 15342a485ad7SGavin Shan ret == EEH_NEXT_ERR_FENCED_PHB) && 15352a485ad7SGavin Shan !((*pe)->state & EEH_PE_ISOLATED)) { 15362a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 15372a485ad7SGavin Shan pnv_eeh_get_phb_diag(*pe); 15382a485ad7SGavin Shan 15392a485ad7SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 15402a485ad7SGavin Shan pnv_pci_dump_phb_diag_data((*pe)->phb, 15412a485ad7SGavin Shan (*pe)->data); 15422a485ad7SGavin Shan } 15432a485ad7SGavin Shan 15442a485ad7SGavin Shan /* 15452a485ad7SGavin Shan * We probably have the frozen parent PE out there and 15462a485ad7SGavin Shan * we need have to handle frozen parent PE firstly. 15472a485ad7SGavin Shan */ 15482a485ad7SGavin Shan if (ret == EEH_NEXT_ERR_FROZEN_PE) { 15492a485ad7SGavin Shan parent_pe = (*pe)->parent; 15502a485ad7SGavin Shan while (parent_pe) { 15512a485ad7SGavin Shan /* Hit the ceiling ? */ 15522a485ad7SGavin Shan if (parent_pe->type & EEH_PE_PHB) 15532a485ad7SGavin Shan break; 15542a485ad7SGavin Shan 15552a485ad7SGavin Shan /* Frozen parent PE ? */ 15562a485ad7SGavin Shan state = eeh_ops->get_state(parent_pe, NULL); 15572a485ad7SGavin Shan if (state > 0 && 15582a485ad7SGavin Shan (state & active_flags) != active_flags) 15592a485ad7SGavin Shan *pe = parent_pe; 15602a485ad7SGavin Shan 15612a485ad7SGavin Shan /* Next parent level */ 15622a485ad7SGavin Shan parent_pe = parent_pe->parent; 15632a485ad7SGavin Shan } 15642a485ad7SGavin Shan 15652a485ad7SGavin Shan /* We possibly migrate to another PE */ 15662a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 15672a485ad7SGavin Shan } 15682a485ad7SGavin Shan 15692a485ad7SGavin Shan /* 15702a485ad7SGavin Shan * If we have no errors on the specific PHB or only 15712a485ad7SGavin Shan * informative error there, we continue poking it. 15722a485ad7SGavin Shan * Otherwise, we need actions to be taken by upper 15732a485ad7SGavin Shan * layer. 15742a485ad7SGavin Shan */ 15752a485ad7SGavin Shan if (ret > EEH_NEXT_ERR_INF) 157629310e5eSGavin Shan break; 157729310e5eSGavin Shan } 157829310e5eSGavin Shan 157979231448SAlistair Popple /* Unmask the event */ 1580b8d65e96SAlistair Popple if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 158179231448SAlistair Popple enable_irq(eeh_event_irq); 158279231448SAlistair Popple 15832a485ad7SGavin Shan return ret; 158429310e5eSGavin Shan } 158529310e5eSGavin Shan 15860dc2830eSWei Yang static int pnv_eeh_restore_vf_config(struct pci_dn *pdn) 15870dc2830eSWei Yang { 15880dc2830eSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 15890dc2830eSWei Yang u32 devctl, cmd, cap2, aer_capctl; 15900dc2830eSWei Yang int old_mps; 15910dc2830eSWei Yang 15920dc2830eSWei Yang if (edev->pcie_cap) { 15930dc2830eSWei Yang /* Restore MPS */ 15940dc2830eSWei Yang old_mps = (ffs(pdn->mps) - 8) << 5; 15950dc2830eSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 15960dc2830eSWei Yang 2, &devctl); 15970dc2830eSWei Yang devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; 15980dc2830eSWei Yang devctl |= old_mps; 15990dc2830eSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 16000dc2830eSWei Yang 2, devctl); 16010dc2830eSWei Yang 16020dc2830eSWei Yang /* Disable Completion Timeout */ 16030dc2830eSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2, 16040dc2830eSWei Yang 4, &cap2); 16050dc2830eSWei Yang if (cap2 & 0x10) { 16060dc2830eSWei Yang eeh_ops->read_config(pdn, 16070dc2830eSWei Yang edev->pcie_cap + PCI_EXP_DEVCTL2, 16080dc2830eSWei Yang 4, &cap2); 16090dc2830eSWei Yang cap2 |= 0x10; 16100dc2830eSWei Yang eeh_ops->write_config(pdn, 16110dc2830eSWei Yang edev->pcie_cap + PCI_EXP_DEVCTL2, 16120dc2830eSWei Yang 4, cap2); 16130dc2830eSWei Yang } 16140dc2830eSWei Yang } 16150dc2830eSWei Yang 16160dc2830eSWei Yang /* Enable SERR and parity checking */ 16170dc2830eSWei Yang eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd); 16180dc2830eSWei Yang cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 16190dc2830eSWei Yang eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd); 16200dc2830eSWei Yang 16210dc2830eSWei Yang /* Enable report various errors */ 16220dc2830eSWei Yang if (edev->pcie_cap) { 16230dc2830eSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 16240dc2830eSWei Yang 2, &devctl); 16250dc2830eSWei Yang devctl &= ~PCI_EXP_DEVCTL_CERE; 16260dc2830eSWei Yang devctl |= (PCI_EXP_DEVCTL_NFERE | 16270dc2830eSWei Yang PCI_EXP_DEVCTL_FERE | 16280dc2830eSWei Yang PCI_EXP_DEVCTL_URRE); 16290dc2830eSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 16300dc2830eSWei Yang 2, devctl); 16310dc2830eSWei Yang } 16320dc2830eSWei Yang 16330dc2830eSWei Yang /* Enable ECRC generation and check */ 16340dc2830eSWei Yang if (edev->pcie_cap && edev->aer_cap) { 16350dc2830eSWei Yang eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP, 16360dc2830eSWei Yang 4, &aer_capctl); 16370dc2830eSWei Yang aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 16380dc2830eSWei Yang eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP, 16390dc2830eSWei Yang 4, aer_capctl); 16400dc2830eSWei Yang } 16410dc2830eSWei Yang 16420dc2830eSWei Yang return 0; 16430dc2830eSWei Yang } 16440dc2830eSWei Yang 16450bd78587SGavin Shan static int pnv_eeh_restore_config(struct pci_dn *pdn) 16469be3beccSGavin Shan { 16470bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 16489be3beccSGavin Shan struct pnv_phb *phb; 16499be3beccSGavin Shan s64 ret; 16509be3beccSGavin Shan 16519be3beccSGavin Shan if (!edev) 16529be3beccSGavin Shan return -EEXIST; 16539be3beccSGavin Shan 16540dc2830eSWei Yang /* 16550dc2830eSWei Yang * We have to restore the PCI config space after reset since the 16560dc2830eSWei Yang * firmware can't see SRIOV VFs. 16570dc2830eSWei Yang * 16580dc2830eSWei Yang * FIXME: The MPS, error routing rules, timeout setting are worthy 16590dc2830eSWei Yang * to be exported by firmware in extendible way. 16600dc2830eSWei Yang */ 16610dc2830eSWei Yang if (edev->physfn) { 16620dc2830eSWei Yang ret = pnv_eeh_restore_vf_config(pdn); 16630dc2830eSWei Yang } else { 16649be3beccSGavin Shan phb = edev->phb->private_data; 16659be3beccSGavin Shan ret = opal_pci_reinit(phb->opal_id, 16669be3beccSGavin Shan OPAL_REINIT_PCI_DEV, edev->config_addr); 16670dc2830eSWei Yang } 16680dc2830eSWei Yang 16699be3beccSGavin Shan if (ret) { 16709be3beccSGavin Shan pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 16719be3beccSGavin Shan __func__, edev->config_addr, ret); 16729be3beccSGavin Shan return -EIO; 16739be3beccSGavin Shan } 16749be3beccSGavin Shan 16759be3beccSGavin Shan return 0; 16769be3beccSGavin Shan } 16779be3beccSGavin Shan 167801f3bfb7SGavin Shan static struct eeh_ops pnv_eeh_ops = { 167929310e5eSGavin Shan .name = "powernv", 168001f3bfb7SGavin Shan .init = pnv_eeh_init, 168101f3bfb7SGavin Shan .post_init = pnv_eeh_post_init, 1682ff57b454SGavin Shan .probe = pnv_eeh_probe, 168301f3bfb7SGavin Shan .set_option = pnv_eeh_set_option, 168401f3bfb7SGavin Shan .get_pe_addr = pnv_eeh_get_pe_addr, 168501f3bfb7SGavin Shan .get_state = pnv_eeh_get_state, 168601f3bfb7SGavin Shan .reset = pnv_eeh_reset, 168701f3bfb7SGavin Shan .wait_state = pnv_eeh_wait_state, 168801f3bfb7SGavin Shan .get_log = pnv_eeh_get_log, 168901f3bfb7SGavin Shan .configure_bridge = pnv_eeh_configure_bridge, 169001f3bfb7SGavin Shan .err_inject = pnv_eeh_err_inject, 169101f3bfb7SGavin Shan .read_config = pnv_eeh_read_config, 169201f3bfb7SGavin Shan .write_config = pnv_eeh_write_config, 169301f3bfb7SGavin Shan .next_error = pnv_eeh_next_error, 169401f3bfb7SGavin Shan .restore_config = pnv_eeh_restore_config 169529310e5eSGavin Shan }; 169629310e5eSGavin Shan 1697c29fa27dSWei Yang void pcibios_bus_add_device(struct pci_dev *pdev) 1698c29fa27dSWei Yang { 1699c29fa27dSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 1700c29fa27dSWei Yang 1701c29fa27dSWei Yang if (!pdev->is_virtfn) 1702c29fa27dSWei Yang return; 1703c29fa27dSWei Yang 1704c29fa27dSWei Yang /* 1705c29fa27dSWei Yang * The following operations will fail if VF's sysfs files 1706c29fa27dSWei Yang * aren't created or its resources aren't finalized. 1707c29fa27dSWei Yang */ 1708c29fa27dSWei Yang eeh_add_device_early(pdn); 1709c29fa27dSWei Yang eeh_add_device_late(pdev); 1710c29fa27dSWei Yang eeh_sysfs_add_device(pdev); 1711c29fa27dSWei Yang } 1712c29fa27dSWei Yang 17130dc2830eSWei Yang #ifdef CONFIG_PCI_IOV 17140dc2830eSWei Yang static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 17150dc2830eSWei Yang { 17160dc2830eSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 17170dc2830eSWei Yang int parent_mps; 17180dc2830eSWei Yang 17190dc2830eSWei Yang if (!pdev->is_virtfn) 17200dc2830eSWei Yang return; 17210dc2830eSWei Yang 17220dc2830eSWei Yang /* Synchronize MPS for VF and PF */ 17230dc2830eSWei Yang parent_mps = pcie_get_mps(pdev->physfn); 17240dc2830eSWei Yang if ((128 << pdev->pcie_mpss) >= parent_mps) 17250dc2830eSWei Yang pcie_set_mps(pdev, parent_mps); 17260dc2830eSWei Yang pdn->mps = pcie_get_mps(pdev); 17270dc2830eSWei Yang } 17280dc2830eSWei Yang DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 17290dc2830eSWei Yang #endif /* CONFIG_PCI_IOV */ 17300dc2830eSWei Yang 173129310e5eSGavin Shan /** 173229310e5eSGavin Shan * eeh_powernv_init - Register platform dependent EEH operations 173329310e5eSGavin Shan * 173429310e5eSGavin Shan * EEH initialization on powernv platform. This function should be 173529310e5eSGavin Shan * called before any EEH related functions. 173629310e5eSGavin Shan */ 173729310e5eSGavin Shan static int __init eeh_powernv_init(void) 173829310e5eSGavin Shan { 173929310e5eSGavin Shan int ret = -EINVAL; 174029310e5eSGavin Shan 1741bb593c00SGavin Shan eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE); 174201f3bfb7SGavin Shan ret = eeh_ops_register(&pnv_eeh_ops); 174329310e5eSGavin Shan if (!ret) 174429310e5eSGavin Shan pr_info("EEH: PowerNV platform initialized\n"); 174529310e5eSGavin Shan else 174629310e5eSGavin Shan pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 174729310e5eSGavin Shan 174829310e5eSGavin Shan return ret; 174929310e5eSGavin Shan } 1750b14726c5SMichael Ellerman machine_early_initcall(powernv, eeh_powernv_init); 1751