12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 229310e5eSGavin Shan /* 341732bdcSStewart Smith * PowerNV Platform dependent EEH operations 429310e5eSGavin Shan * 529310e5eSGavin Shan * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 629310e5eSGavin Shan */ 729310e5eSGavin Shan 829310e5eSGavin Shan #include <linux/atomic.h> 94cf17445SGavin Shan #include <linux/debugfs.h> 1029310e5eSGavin Shan #include <linux/delay.h> 1129310e5eSGavin Shan #include <linux/export.h> 1229310e5eSGavin Shan #include <linux/init.h> 1379231448SAlistair Popple #include <linux/interrupt.h> 14*e6f6390aSChristophe Leroy #include <linux/irqdomain.h> 1529310e5eSGavin Shan #include <linux/list.h> 1629310e5eSGavin Shan #include <linux/msi.h> 1729310e5eSGavin Shan #include <linux/of.h> 1829310e5eSGavin Shan #include <linux/pci.h> 1929310e5eSGavin Shan #include <linux/proc_fs.h> 2029310e5eSGavin Shan #include <linux/rbtree.h> 2129310e5eSGavin Shan #include <linux/sched.h> 2229310e5eSGavin Shan #include <linux/seq_file.h> 2329310e5eSGavin Shan #include <linux/spinlock.h> 2429310e5eSGavin Shan 2529310e5eSGavin Shan #include <asm/eeh.h> 2629310e5eSGavin Shan #include <asm/eeh_event.h> 2729310e5eSGavin Shan #include <asm/firmware.h> 2829310e5eSGavin Shan #include <asm/io.h> 2929310e5eSGavin Shan #include <asm/iommu.h> 3029310e5eSGavin Shan #include <asm/machdep.h> 3129310e5eSGavin Shan #include <asm/msi_bitmap.h> 3229310e5eSGavin Shan #include <asm/opal.h> 3329310e5eSGavin Shan #include <asm/ppc-pci.h> 349c0e1ecbSGavin Shan #include <asm/pnv-pci.h> 3529310e5eSGavin Shan 3629310e5eSGavin Shan #include "powernv.h" 3729310e5eSGavin Shan #include "pci.h" 3898fd32cdSOliver O'Halloran #include "../../../../drivers/pci/pci.h" 3929310e5eSGavin Shan 4079231448SAlistair Popple static int eeh_event_irq = -EINVAL; 414cf17445SGavin Shan 423b70464aSOliver O'Halloran static void pnv_pcibios_bus_add_device(struct pci_dev *pdev) 43988fc3baSBryant G. Ly { 441ff8f36fSSam Bobroff dev_dbg(&pdev->dev, "EEH: Setting up device\n"); 45e86350f7SOliver O'Halloran eeh_probe_device(pdev); 46988fc3baSBryant G. Ly } 47988fc3baSBryant G. Ly 4879231448SAlistair Popple static irqreturn_t pnv_eeh_event(int irq, void *data) 494cf17445SGavin Shan { 504cf17445SGavin Shan /* 5179231448SAlistair Popple * We simply send a special EEH event if EEH has been 5279231448SAlistair Popple * enabled. We don't care about EEH events until we've 5379231448SAlistair Popple * finished processing the outstanding ones. Event processing 5479231448SAlistair Popple * gets unmasked in next_error() if EEH is enabled. 554cf17445SGavin Shan */ 5679231448SAlistair Popple disable_irq_nosync(irq); 574cf17445SGavin Shan 584cf17445SGavin Shan if (eeh_enabled()) 594cf17445SGavin Shan eeh_send_failure_event(NULL); 604cf17445SGavin Shan 6179231448SAlistair Popple return IRQ_HANDLED; 624cf17445SGavin Shan } 634cf17445SGavin Shan 644cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 654cf17445SGavin Shan static ssize_t pnv_eeh_ei_write(struct file *filp, 664cf17445SGavin Shan const char __user *user_buf, 674cf17445SGavin Shan size_t count, loff_t *ppos) 684cf17445SGavin Shan { 694cf17445SGavin Shan struct pci_controller *hose = filp->private_data; 704cf17445SGavin Shan struct eeh_pe *pe; 714cf17445SGavin Shan int pe_no, type, func; 724cf17445SGavin Shan unsigned long addr, mask; 734cf17445SGavin Shan char buf[50]; 744cf17445SGavin Shan int ret; 754cf17445SGavin Shan 764cf17445SGavin Shan if (!eeh_ops || !eeh_ops->err_inject) 774cf17445SGavin Shan return -ENXIO; 784cf17445SGavin Shan 794cf17445SGavin Shan /* Copy over argument buffer */ 804cf17445SGavin Shan ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 814cf17445SGavin Shan if (!ret) 824cf17445SGavin Shan return -EFAULT; 834cf17445SGavin Shan 844cf17445SGavin Shan /* Retrieve parameters */ 854cf17445SGavin Shan ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 864cf17445SGavin Shan &pe_no, &type, &func, &addr, &mask); 874cf17445SGavin Shan if (ret != 5) 884cf17445SGavin Shan return -EINVAL; 894cf17445SGavin Shan 904cf17445SGavin Shan /* Retrieve PE */ 9135d64734SOliver O'Halloran pe = eeh_pe_get(hose, pe_no); 924cf17445SGavin Shan if (!pe) 934cf17445SGavin Shan return -ENODEV; 944cf17445SGavin Shan 954cf17445SGavin Shan /* Do error injection */ 964cf17445SGavin Shan ret = eeh_ops->err_inject(pe, type, func, addr, mask); 974cf17445SGavin Shan return ret < 0 ? ret : count; 984cf17445SGavin Shan } 994cf17445SGavin Shan 1004cf17445SGavin Shan static const struct file_operations pnv_eeh_ei_fops = { 1014cf17445SGavin Shan .open = simple_open, 1024cf17445SGavin Shan .llseek = no_llseek, 1034cf17445SGavin Shan .write = pnv_eeh_ei_write, 1044cf17445SGavin Shan }; 1054cf17445SGavin Shan 1064cf17445SGavin Shan static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 1074cf17445SGavin Shan { 1084cf17445SGavin Shan struct pci_controller *hose = data; 1094cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1104cf17445SGavin Shan 1114cf17445SGavin Shan out_be64(phb->regs + offset, val); 1124cf17445SGavin Shan return 0; 1134cf17445SGavin Shan } 1144cf17445SGavin Shan 1154cf17445SGavin Shan static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 1164cf17445SGavin Shan { 1174cf17445SGavin Shan struct pci_controller *hose = data; 1184cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1194cf17445SGavin Shan 1204cf17445SGavin Shan *val = in_be64(phb->regs + offset); 1214cf17445SGavin Shan return 0; 1224cf17445SGavin Shan } 1234cf17445SGavin Shan 124ccc9662dSGavin Shan #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 125ccc9662dSGavin Shan static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 126ccc9662dSGavin Shan { \ 127ccc9662dSGavin Shan return pnv_eeh_dbgfs_set(data, reg, val); \ 128ccc9662dSGavin Shan } \ 129ccc9662dSGavin Shan \ 130ccc9662dSGavin Shan static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 131ccc9662dSGavin Shan { \ 132ccc9662dSGavin Shan return pnv_eeh_dbgfs_get(data, reg, val); \ 133ccc9662dSGavin Shan } \ 134ccc9662dSGavin Shan \ 135ccc9662dSGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 136ccc9662dSGavin Shan pnv_eeh_dbgfs_get_##name, \ 137ccc9662dSGavin Shan pnv_eeh_dbgfs_set_##name, \ 138ccc9662dSGavin Shan "0x%llx\n") 1394cf17445SGavin Shan 140ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 141ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 142ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 1434cf17445SGavin Shan 1444cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 1454cf17445SGavin Shan 1463b70464aSOliver O'Halloran static void pnv_eeh_enable_phbs(void) 147b905f8cdSSam Bobroff { 148b905f8cdSSam Bobroff struct pci_controller *hose; 149b905f8cdSSam Bobroff struct pnv_phb *phb; 150b905f8cdSSam Bobroff 151b905f8cdSSam Bobroff list_for_each_entry(hose, &hose_list, list_node) { 152b905f8cdSSam Bobroff phb = hose->private_data; 153b905f8cdSSam Bobroff /* 154b905f8cdSSam Bobroff * If EEH is enabled, we're going to rely on that. 155b905f8cdSSam Bobroff * Otherwise, we restore to conventional mechanism 156b905f8cdSSam Bobroff * to clear frozen PE during PCI config access. 157b905f8cdSSam Bobroff */ 158b905f8cdSSam Bobroff if (eeh_enabled()) 159b905f8cdSSam Bobroff phb->flags |= PNV_PHB_FLAG_EEH; 160b905f8cdSSam Bobroff else 161b905f8cdSSam Bobroff phb->flags &= ~PNV_PHB_FLAG_EEH; 162b905f8cdSSam Bobroff } 163b905f8cdSSam Bobroff } 164b905f8cdSSam Bobroff 16529310e5eSGavin Shan /** 16601f3bfb7SGavin Shan * pnv_eeh_post_init - EEH platform dependent post initialization 16729310e5eSGavin Shan * 16829310e5eSGavin Shan * EEH platform dependent post initialization on powernv. When 16929310e5eSGavin Shan * the function is called, the EEH PEs and devices should have 17029310e5eSGavin Shan * been built. If the I/O cache staff has been built, EEH is 17129310e5eSGavin Shan * ready to supply service. 17229310e5eSGavin Shan */ 173b9fde58dSBenjamin Herrenschmidt int pnv_eeh_post_init(void) 17429310e5eSGavin Shan { 17529310e5eSGavin Shan struct pci_controller *hose; 17629310e5eSGavin Shan struct pnv_phb *phb; 17729310e5eSGavin Shan int ret = 0; 17829310e5eSGavin Shan 179c44e4ccaSSam Bobroff eeh_show_enabled(); 180b9fde58dSBenjamin Herrenschmidt 1814cf17445SGavin Shan /* Register OPAL event notifier */ 18279231448SAlistair Popple eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 18379231448SAlistair Popple if (eeh_event_irq < 0) { 18479231448SAlistair Popple pr_err("%s: Can't register OPAL event interrupt (%d)\n", 18579231448SAlistair Popple __func__, eeh_event_irq); 18679231448SAlistair Popple return eeh_event_irq; 18779231448SAlistair Popple } 18879231448SAlistair Popple 18979231448SAlistair Popple ret = request_irq(eeh_event_irq, pnv_eeh_event, 19079231448SAlistair Popple IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 19179231448SAlistair Popple if (ret < 0) { 19279231448SAlistair Popple irq_dispose_mapping(eeh_event_irq); 19379231448SAlistair Popple pr_err("%s: Can't request OPAL event interrupt (%d)\n", 19479231448SAlistair Popple __func__, eeh_event_irq); 1954cf17445SGavin Shan return ret; 1964cf17445SGavin Shan } 1974cf17445SGavin Shan 19879231448SAlistair Popple if (!eeh_enabled()) 19979231448SAlistair Popple disable_irq(eeh_event_irq); 20079231448SAlistair Popple 201b905f8cdSSam Bobroff pnv_eeh_enable_phbs(); 202b905f8cdSSam Bobroff 20329310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 20429310e5eSGavin Shan phb = hose->private_data; 20529310e5eSGavin Shan 2064cf17445SGavin Shan /* Create debugfs entries */ 2074cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 2084cf17445SGavin Shan if (phb->has_dbgfs || !phb->dbgfs) 2094cf17445SGavin Shan continue; 2104cf17445SGavin Shan 2114cf17445SGavin Shan phb->has_dbgfs = 1; 2124cf17445SGavin Shan debugfs_create_file("err_injct", 0200, 2134cf17445SGavin Shan phb->dbgfs, hose, 2144cf17445SGavin Shan &pnv_eeh_ei_fops); 2154cf17445SGavin Shan 2164cf17445SGavin Shan debugfs_create_file("err_injct_outbound", 0600, 2174cf17445SGavin Shan phb->dbgfs, hose, 218ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_outb); 2194cf17445SGavin Shan debugfs_create_file("err_injct_inboundA", 0600, 2204cf17445SGavin Shan phb->dbgfs, hose, 221ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbA); 2224cf17445SGavin Shan debugfs_create_file("err_injct_inboundB", 0600, 2234cf17445SGavin Shan phb->dbgfs, hose, 224ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbB); 2254cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 22629310e5eSGavin Shan } 2274cf17445SGavin Shan 22829310e5eSGavin Shan return ret; 22929310e5eSGavin Shan } 23029310e5eSGavin Shan 2314d6186caSGavin Shan static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 232ff57b454SGavin Shan { 2334d6186caSGavin Shan int pos = PCI_CAPABILITY_LIST; 2344d6186caSGavin Shan int cnt = 48; /* Maximal number of capabilities */ 2354d6186caSGavin Shan u32 status, id; 236ff57b454SGavin Shan 237ff57b454SGavin Shan if (!pdn) 238ff57b454SGavin Shan return 0; 239ff57b454SGavin Shan 2404d6186caSGavin Shan /* Check if the device supports capabilities */ 241ff57b454SGavin Shan pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 242ff57b454SGavin Shan if (!(status & PCI_STATUS_CAP_LIST)) 243ff57b454SGavin Shan return 0; 244ff57b454SGavin Shan 245ff57b454SGavin Shan while (cnt--) { 246ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos, 1, &pos); 247ff57b454SGavin Shan if (pos < 0x40) 248ff57b454SGavin Shan break; 249ff57b454SGavin Shan 250ff57b454SGavin Shan pos &= ~3; 251ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 252ff57b454SGavin Shan if (id == 0xff) 253ff57b454SGavin Shan break; 254ff57b454SGavin Shan 255ff57b454SGavin Shan /* Found */ 256ff57b454SGavin Shan if (id == cap) 257ff57b454SGavin Shan return pos; 258ff57b454SGavin Shan 259ff57b454SGavin Shan /* Next one */ 260ff57b454SGavin Shan pos += PCI_CAP_LIST_NEXT; 261ff57b454SGavin Shan } 262ff57b454SGavin Shan 263ff57b454SGavin Shan return 0; 264ff57b454SGavin Shan } 265ff57b454SGavin Shan 266ff57b454SGavin Shan static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 267ff57b454SGavin Shan { 268ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 269ff57b454SGavin Shan u32 header; 270ff57b454SGavin Shan int pos = 256, ttl = (4096 - 256) / 8; 271ff57b454SGavin Shan 272ff57b454SGavin Shan if (!edev || !edev->pcie_cap) 273ff57b454SGavin Shan return 0; 274ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 275ff57b454SGavin Shan return 0; 276ff57b454SGavin Shan else if (!header) 277ff57b454SGavin Shan return 0; 278ff57b454SGavin Shan 279ff57b454SGavin Shan while (ttl-- > 0) { 280ff57b454SGavin Shan if (PCI_EXT_CAP_ID(header) == cap && pos) 281ff57b454SGavin Shan return pos; 282ff57b454SGavin Shan 283ff57b454SGavin Shan pos = PCI_EXT_CAP_NEXT(header); 284ff57b454SGavin Shan if (pos < 256) 285ff57b454SGavin Shan break; 286ff57b454SGavin Shan 287ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 288ff57b454SGavin Shan break; 289ff57b454SGavin Shan } 290ff57b454SGavin Shan 291ff57b454SGavin Shan return 0; 292ff57b454SGavin Shan } 293ff57b454SGavin Shan 294a131bfc6SOliver O'Halloran static struct eeh_pe *pnv_eeh_get_upstream_pe(struct pci_dev *pdev) 295a131bfc6SOliver O'Halloran { 296a131bfc6SOliver O'Halloran struct pci_controller *hose = pdev->bus->sysdata; 297a131bfc6SOliver O'Halloran struct pnv_phb *phb = hose->private_data; 298a131bfc6SOliver O'Halloran struct pci_dev *parent = pdev->bus->self; 299a131bfc6SOliver O'Halloran 300a131bfc6SOliver O'Halloran #ifdef CONFIG_PCI_IOV 301a131bfc6SOliver O'Halloran /* for VFs we use the PF's PE as the upstream PE */ 302a131bfc6SOliver O'Halloran if (pdev->is_virtfn) 303a131bfc6SOliver O'Halloran parent = pdev->physfn; 304a131bfc6SOliver O'Halloran #endif 305a131bfc6SOliver O'Halloran 306a131bfc6SOliver O'Halloran /* otherwise use the PE of our parent bridge */ 307a131bfc6SOliver O'Halloran if (parent) { 308a131bfc6SOliver O'Halloran struct pnv_ioda_pe *ioda_pe = pnv_ioda_get_pe(parent); 309a131bfc6SOliver O'Halloran 31035d64734SOliver O'Halloran return eeh_pe_get(phb->hose, ioda_pe->pe_number); 311a131bfc6SOliver O'Halloran } 312a131bfc6SOliver O'Halloran 313a131bfc6SOliver O'Halloran return NULL; 314a131bfc6SOliver O'Halloran } 315a131bfc6SOliver O'Halloran 31629310e5eSGavin Shan /** 317ff57b454SGavin Shan * pnv_eeh_probe - Do probe on PCI device 318e86350f7SOliver O'Halloran * @pdev: pci_dev to probe 31929310e5eSGavin Shan * 320e86350f7SOliver O'Halloran * Create, or find the existing, eeh_dev for this pci_dev. 32129310e5eSGavin Shan */ 322e86350f7SOliver O'Halloran static struct eeh_dev *pnv_eeh_probe(struct pci_dev *pdev) 32329310e5eSGavin Shan { 324e86350f7SOliver O'Halloran struct pci_dn *pdn = pci_get_pdn(pdev); 325ff57b454SGavin Shan struct pci_controller *hose = pdn->phb; 32629310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 327ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 328a131bfc6SOliver O'Halloran struct eeh_pe *upstream_pe; 329ff57b454SGavin Shan uint32_t pcie_flags; 330dadcd6d6SMike Qiu int ret; 331405b33a7SAlexey Kardashevskiy int config_addr = (pdn->busno << 8) | (pdn->devfn); 33229310e5eSGavin Shan 33329310e5eSGavin Shan /* 33429310e5eSGavin Shan * When probing the root bridge, which doesn't have any 33529310e5eSGavin Shan * subordinate PCI devices. We don't have OF node for 33629310e5eSGavin Shan * the root bridge. So it's not reasonable to continue 33729310e5eSGavin Shan * the probing. 33829310e5eSGavin Shan */ 339ff57b454SGavin Shan if (!edev || edev->pe) 340ff57b454SGavin Shan return NULL; 34129310e5eSGavin Shan 342e86350f7SOliver O'Halloran /* already configured? */ 343e86350f7SOliver O'Halloran if (edev->pdev) { 344e86350f7SOliver O'Halloran pr_debug("%s: found existing edev for %04x:%02x:%02x.%01x\n", 345e86350f7SOliver O'Halloran __func__, hose->global_number, config_addr >> 8, 346e86350f7SOliver O'Halloran PCI_SLOT(config_addr), PCI_FUNC(config_addr)); 347e86350f7SOliver O'Halloran return edev; 348e86350f7SOliver O'Halloran } 349e86350f7SOliver O'Halloran 35029310e5eSGavin Shan /* Skip for PCI-ISA bridge */ 351768a4284SOliver O'Halloran if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) 352ff57b454SGavin Shan return NULL; 35329310e5eSGavin Shan 3541ff8f36fSSam Bobroff eeh_edev_dbg(edev, "Probing device\n"); 3551ff8f36fSSam Bobroff 35629310e5eSGavin Shan /* Initialize eeh device */ 357ab55d218SGavin Shan edev->mode &= 0xFFFFFF00; 358ff57b454SGavin Shan edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 359ff57b454SGavin Shan edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 3609312bc5bSWei Yang edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 361ff57b454SGavin Shan edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 362768a4284SOliver O'Halloran if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_PCI) { 3634b83bd45SGavin Shan edev->mode |= EEH_DEV_BRIDGE; 364ff57b454SGavin Shan if (edev->pcie_cap) { 365ff57b454SGavin Shan pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 366ff57b454SGavin Shan 2, &pcie_flags); 367ff57b454SGavin Shan pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 368ff57b454SGavin Shan if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 3694b83bd45SGavin Shan edev->mode |= EEH_DEV_ROOT_PORT; 370ff57b454SGavin Shan else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 3714b83bd45SGavin Shan edev->mode |= EEH_DEV_DS_PORT; 372ff57b454SGavin Shan } 3734b83bd45SGavin Shan } 3744b83bd45SGavin Shan 375405b33a7SAlexey Kardashevskiy edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; 37629310e5eSGavin Shan 377a131bfc6SOliver O'Halloran upstream_pe = pnv_eeh_get_upstream_pe(pdev); 378a131bfc6SOliver O'Halloran 37929310e5eSGavin Shan /* Create PE */ 380a131bfc6SOliver O'Halloran ret = eeh_pe_tree_insert(edev, upstream_pe); 381dadcd6d6SMike Qiu if (ret) { 3821ff8f36fSSam Bobroff eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n", ret); 383ff57b454SGavin Shan return NULL; 384dadcd6d6SMike Qiu } 385dadcd6d6SMike Qiu 386dadcd6d6SMike Qiu /* 387b6541db1SGavin Shan * If the PE contains any one of following adapters, the 388b6541db1SGavin Shan * PCI config space can't be accessed when dumping EEH log. 389b6541db1SGavin Shan * Otherwise, we will run into fenced PHB caused by shortage 390b6541db1SGavin Shan * of outbound credits in the adapter. The PCI config access 391b6541db1SGavin Shan * should be blocked until PE reset. MMIO access is dropped 392b6541db1SGavin Shan * by hardware certainly. In order to drop PCI config requests, 393b6541db1SGavin Shan * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 3941fd02f66SJulia Lawall * will be checked in the backend for PE state retrieval. If 395b6541db1SGavin Shan * the PE becomes frozen for the first time and the flag has 396b6541db1SGavin Shan * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 397b6541db1SGavin Shan * that PE to block its config space. 398b6541db1SGavin Shan * 399c374ed27SGavin Shan * Broadcom BCM5718 2-ports NICs (14e4:1656) 400b6541db1SGavin Shan * Broadcom Austin 4-ports NICs (14e4:1657) 401353169acSGavin Shan * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 402179ea48bSGavin Shan * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 403b6541db1SGavin Shan */ 404ff57b454SGavin Shan if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 405c374ed27SGavin Shan pdn->device_id == 0x1656) || 406c374ed27SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 407ff57b454SGavin Shan pdn->device_id == 0x1657) || 408ff57b454SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 409353169acSGavin Shan pdn->device_id == 0x168a) || 410353169acSGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 411ff57b454SGavin Shan pdn->device_id == 0x168e)) 412b6541db1SGavin Shan edev->pe->state |= EEH_PE_CFG_RESTRICTED; 413b6541db1SGavin Shan 414b6541db1SGavin Shan /* 415dadcd6d6SMike Qiu * Cache the PE primary bus, which can't be fetched when 416dadcd6d6SMike Qiu * full hotplug is in progress. In that case, all child 417dadcd6d6SMike Qiu * PCI devices of the PE are expected to be removed prior 418dadcd6d6SMike Qiu * to PE reset. 419dadcd6d6SMike Qiu */ 42005ba75f8SGavin Shan if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 421ff57b454SGavin Shan edev->pe->bus = pci_find_bus(hose->global_number, 422ff57b454SGavin Shan pdn->busno); 42305ba75f8SGavin Shan if (edev->pe->bus) 42405ba75f8SGavin Shan edev->pe->state |= EEH_PE_PRI_BUS; 42505ba75f8SGavin Shan } 42629310e5eSGavin Shan 42729310e5eSGavin Shan /* 42829310e5eSGavin Shan * Enable EEH explicitly so that we will do EEH check 42929310e5eSGavin Shan * while accessing I/O stuff 43029310e5eSGavin Shan */ 431b905f8cdSSam Bobroff if (!eeh_has_flag(EEH_ENABLED)) { 432b905f8cdSSam Bobroff enable_irq(eeh_event_irq); 433b905f8cdSSam Bobroff pnv_eeh_enable_phbs(); 43405b1721dSGavin Shan eeh_add_flag(EEH_ENABLED); 435b905f8cdSSam Bobroff } 43629310e5eSGavin Shan 43729310e5eSGavin Shan /* Save memory bars */ 43829310e5eSGavin Shan eeh_save_bars(edev); 43929310e5eSGavin Shan 4401ff8f36fSSam Bobroff eeh_edev_dbg(edev, "EEH enabled on device\n"); 441617082a4SSam Bobroff 442e86350f7SOliver O'Halloran return edev; 44329310e5eSGavin Shan } 44429310e5eSGavin Shan 44529310e5eSGavin Shan /** 44601f3bfb7SGavin Shan * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 44729310e5eSGavin Shan * @pe: EEH PE 44829310e5eSGavin Shan * @option: operation to be issued 44929310e5eSGavin Shan * 45029310e5eSGavin Shan * The function is used to control the EEH functionality globally. 45129310e5eSGavin Shan * Currently, following options are support according to PAPR: 45229310e5eSGavin Shan * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 45329310e5eSGavin Shan */ 45401f3bfb7SGavin Shan static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 45529310e5eSGavin Shan { 45629310e5eSGavin Shan struct pci_controller *hose = pe->phb; 45729310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 4587e3e4f8dSGavin Shan bool freeze_pe = false; 459f9433718SGavin Shan int opt; 4607e3e4f8dSGavin Shan s64 rc; 46129310e5eSGavin Shan 4627e3e4f8dSGavin Shan switch (option) { 4637e3e4f8dSGavin Shan case EEH_OPT_DISABLE: 4647e3e4f8dSGavin Shan return -EPERM; 4657e3e4f8dSGavin Shan case EEH_OPT_ENABLE: 4667e3e4f8dSGavin Shan return 0; 4677e3e4f8dSGavin Shan case EEH_OPT_THAW_MMIO: 4687e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 4697e3e4f8dSGavin Shan break; 4707e3e4f8dSGavin Shan case EEH_OPT_THAW_DMA: 4717e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 4727e3e4f8dSGavin Shan break; 4737e3e4f8dSGavin Shan case EEH_OPT_FREEZE_PE: 4747e3e4f8dSGavin Shan freeze_pe = true; 4757e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 4767e3e4f8dSGavin Shan break; 4777e3e4f8dSGavin Shan default: 4787e3e4f8dSGavin Shan pr_warn("%s: Invalid option %d\n", __func__, option); 4797e3e4f8dSGavin Shan return -EINVAL; 4807e3e4f8dSGavin Shan } 4817e3e4f8dSGavin Shan 482f9433718SGavin Shan /* Freeze master and slave PEs if PHB supports compound PEs */ 4837e3e4f8dSGavin Shan if (freeze_pe) { 4847e3e4f8dSGavin Shan if (phb->freeze_pe) { 4857e3e4f8dSGavin Shan phb->freeze_pe(phb, pe->addr); 486f9433718SGavin Shan return 0; 4877e3e4f8dSGavin Shan } 48829310e5eSGavin Shan 489f9433718SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 490f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 491f9433718SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 492f9433718SGavin Shan __func__, rc, phb->hose->global_number, 493f9433718SGavin Shan pe->addr); 494f9433718SGavin Shan return -EIO; 495f9433718SGavin Shan } 496f9433718SGavin Shan 497f9433718SGavin Shan return 0; 498f9433718SGavin Shan } 499f9433718SGavin Shan 500f9433718SGavin Shan /* Unfreeze master and slave PEs if PHB supports */ 501f9433718SGavin Shan if (phb->unfreeze_pe) 502f9433718SGavin Shan return phb->unfreeze_pe(phb, pe->addr, opt); 503f9433718SGavin Shan 504f9433718SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 505f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 506f9433718SGavin Shan pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 507f9433718SGavin Shan __func__, rc, option, phb->hose->global_number, 508f9433718SGavin Shan pe->addr); 509f9433718SGavin Shan return -EIO; 510f9433718SGavin Shan } 511f9433718SGavin Shan 512f9433718SGavin Shan return 0; 51329310e5eSGavin Shan } 51429310e5eSGavin Shan 51540ae5f69SGavin Shan static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 51640ae5f69SGavin Shan { 51740ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 51840ae5f69SGavin Shan s64 rc; 51940ae5f69SGavin Shan 52040ae5f69SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 5215cb1f8fdSRussell Currey phb->diag_data_size); 52240ae5f69SGavin Shan if (rc != OPAL_SUCCESS) 52340ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 52440ae5f69SGavin Shan __func__, rc, pe->phb->global_number); 52540ae5f69SGavin Shan } 52640ae5f69SGavin Shan 52740ae5f69SGavin Shan static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 52840ae5f69SGavin Shan { 52940ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 530c2057701SAlexey Kardashevskiy u8 fstate = 0; 531c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 53240ae5f69SGavin Shan s64 rc; 53340ae5f69SGavin Shan int result = 0; 53440ae5f69SGavin Shan 53540ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 53640ae5f69SGavin Shan pe->addr, 53740ae5f69SGavin Shan &fstate, 53840ae5f69SGavin Shan &pcierr, 53940ae5f69SGavin Shan NULL); 54040ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 54140ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x state\n", 54240ae5f69SGavin Shan __func__, rc, phb->hose->global_number); 54340ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 54440ae5f69SGavin Shan } 54540ae5f69SGavin Shan 54640ae5f69SGavin Shan /* 54740ae5f69SGavin Shan * Check PHB state. If the PHB is frozen for the 54840ae5f69SGavin Shan * first time, to dump the PHB diag-data. 54940ae5f69SGavin Shan */ 55040ae5f69SGavin Shan if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 55140ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 55240ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 55340ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 55440ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 55540ae5f69SGavin Shan } else if (!(pe->state & EEH_PE_ISOLATED)) { 556e762bb89SSam Bobroff eeh_pe_mark_isolated(pe); 55740ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 55840ae5f69SGavin Shan 55940ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 56040ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 56140ae5f69SGavin Shan } 56240ae5f69SGavin Shan 56340ae5f69SGavin Shan return result; 56440ae5f69SGavin Shan } 56540ae5f69SGavin Shan 56640ae5f69SGavin Shan static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 56740ae5f69SGavin Shan { 56840ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 569c2057701SAlexey Kardashevskiy u8 fstate = 0; 570c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 57140ae5f69SGavin Shan s64 rc; 57240ae5f69SGavin Shan int result; 57340ae5f69SGavin Shan 57440ae5f69SGavin Shan /* 57540ae5f69SGavin Shan * We don't clobber hardware frozen state until PE 57640ae5f69SGavin Shan * reset is completed. In order to keep EEH core 57740ae5f69SGavin Shan * moving forward, we have to return operational 57840ae5f69SGavin Shan * state during PE reset. 57940ae5f69SGavin Shan */ 58040ae5f69SGavin Shan if (pe->state & EEH_PE_RESET) { 58140ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 58240ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 58340ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 58440ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 58540ae5f69SGavin Shan return result; 58640ae5f69SGavin Shan } 58740ae5f69SGavin Shan 58840ae5f69SGavin Shan /* 58940ae5f69SGavin Shan * Fetch PE state from hardware. If the PHB 59040ae5f69SGavin Shan * supports compound PE, let it handle that. 59140ae5f69SGavin Shan */ 59240ae5f69SGavin Shan if (phb->get_pe_state) { 59340ae5f69SGavin Shan fstate = phb->get_pe_state(phb, pe->addr); 59440ae5f69SGavin Shan } else { 59540ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 59640ae5f69SGavin Shan pe->addr, 59740ae5f69SGavin Shan &fstate, 59840ae5f69SGavin Shan &pcierr, 59940ae5f69SGavin Shan NULL); 60040ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 60140ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 60240ae5f69SGavin Shan __func__, rc, phb->hose->global_number, 60340ae5f69SGavin Shan pe->addr); 60440ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 60540ae5f69SGavin Shan } 60640ae5f69SGavin Shan } 60740ae5f69SGavin Shan 60840ae5f69SGavin Shan /* Figure out state */ 60940ae5f69SGavin Shan switch (fstate) { 61040ae5f69SGavin Shan case OPAL_EEH_STOPPED_NOT_FROZEN: 61140ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 61240ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 61340ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 61440ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 61540ae5f69SGavin Shan break; 61640ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_FREEZE: 61740ae5f69SGavin Shan result = (EEH_STATE_DMA_ACTIVE | 61840ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 61940ae5f69SGavin Shan break; 62040ae5f69SGavin Shan case OPAL_EEH_STOPPED_DMA_FREEZE: 62140ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 62240ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED); 62340ae5f69SGavin Shan break; 62440ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 62540ae5f69SGavin Shan result = 0; 62640ae5f69SGavin Shan break; 62740ae5f69SGavin Shan case OPAL_EEH_STOPPED_RESET: 62840ae5f69SGavin Shan result = EEH_STATE_RESET_ACTIVE; 62940ae5f69SGavin Shan break; 63040ae5f69SGavin Shan case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 63140ae5f69SGavin Shan result = EEH_STATE_UNAVAILABLE; 63240ae5f69SGavin Shan break; 63340ae5f69SGavin Shan case OPAL_EEH_STOPPED_PERM_UNAVAIL: 63440ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 63540ae5f69SGavin Shan break; 63640ae5f69SGavin Shan default: 63740ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 63840ae5f69SGavin Shan pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 63940ae5f69SGavin Shan __func__, phb->hose->global_number, 64040ae5f69SGavin Shan pe->addr, fstate); 64140ae5f69SGavin Shan } 64240ae5f69SGavin Shan 64340ae5f69SGavin Shan /* 64440ae5f69SGavin Shan * If PHB supports compound PE, to freeze all 64540ae5f69SGavin Shan * slave PEs for consistency. 64640ae5f69SGavin Shan * 64740ae5f69SGavin Shan * If the PE is switching to frozen state for the 64840ae5f69SGavin Shan * first time, to dump the PHB diag-data. 64940ae5f69SGavin Shan */ 65040ae5f69SGavin Shan if (!(result & EEH_STATE_NOT_SUPPORT) && 65140ae5f69SGavin Shan !(result & EEH_STATE_UNAVAILABLE) && 65240ae5f69SGavin Shan !(result & EEH_STATE_MMIO_ACTIVE) && 65340ae5f69SGavin Shan !(result & EEH_STATE_DMA_ACTIVE) && 65440ae5f69SGavin Shan !(pe->state & EEH_PE_ISOLATED)) { 65540ae5f69SGavin Shan if (phb->freeze_pe) 65640ae5f69SGavin Shan phb->freeze_pe(phb, pe->addr); 65740ae5f69SGavin Shan 658e762bb89SSam Bobroff eeh_pe_mark_isolated(pe); 65940ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 66040ae5f69SGavin Shan 66140ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 66240ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 66340ae5f69SGavin Shan } 66440ae5f69SGavin Shan 66540ae5f69SGavin Shan return result; 66640ae5f69SGavin Shan } 66740ae5f69SGavin Shan 66829310e5eSGavin Shan /** 66901f3bfb7SGavin Shan * pnv_eeh_get_state - Retrieve PE state 67029310e5eSGavin Shan * @pe: EEH PE 67129310e5eSGavin Shan * @delay: delay while PE state is temporarily unavailable 67229310e5eSGavin Shan * 67329310e5eSGavin Shan * Retrieve the state of the specified PE. For IODA-compitable 67429310e5eSGavin Shan * platform, it should be retrieved from IODA table. Therefore, 67529310e5eSGavin Shan * we prefer passing down to hardware implementation to handle 67629310e5eSGavin Shan * it. 67729310e5eSGavin Shan */ 67801f3bfb7SGavin Shan static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 67929310e5eSGavin Shan { 68040ae5f69SGavin Shan int ret; 68129310e5eSGavin Shan 68240ae5f69SGavin Shan if (pe->type & EEH_PE_PHB) 68340ae5f69SGavin Shan ret = pnv_eeh_get_phb_state(pe); 68440ae5f69SGavin Shan else 68540ae5f69SGavin Shan ret = pnv_eeh_get_pe_state(pe); 68640ae5f69SGavin Shan 68740ae5f69SGavin Shan if (!delay) 68840ae5f69SGavin Shan return ret; 68929310e5eSGavin Shan 69029310e5eSGavin Shan /* 69129310e5eSGavin Shan * If the PE state is temporarily unavailable, 69229310e5eSGavin Shan * to inform the EEH core delay for default 69329310e5eSGavin Shan * period (1 second) 69429310e5eSGavin Shan */ 69529310e5eSGavin Shan *delay = 0; 69629310e5eSGavin Shan if (ret & EEH_STATE_UNAVAILABLE) 69729310e5eSGavin Shan *delay = 1000; 69829310e5eSGavin Shan 69929310e5eSGavin Shan return ret; 70029310e5eSGavin Shan } 70129310e5eSGavin Shan 702ebe22531SGavin Shan static s64 pnv_eeh_poll(unsigned long id) 703cadf364dSGavin Shan { 704cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 705cadf364dSGavin Shan 706cadf364dSGavin Shan while (1) { 707ebe22531SGavin Shan rc = opal_pci_poll(id); 708cadf364dSGavin Shan if (rc <= 0) 709cadf364dSGavin Shan break; 710cadf364dSGavin Shan 711cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 712cadf364dSGavin Shan udelay(1000 * rc); 713cadf364dSGavin Shan else 714cadf364dSGavin Shan msleep(rc); 715cadf364dSGavin Shan } 716cadf364dSGavin Shan 717cadf364dSGavin Shan return rc; 718cadf364dSGavin Shan } 719cadf364dSGavin Shan 720cadf364dSGavin Shan int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 721cadf364dSGavin Shan { 722cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 723cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 724cadf364dSGavin Shan 725cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 726cadf364dSGavin Shan __func__, hose->global_number, option); 727cadf364dSGavin Shan 728cadf364dSGavin Shan /* Issue PHB complete reset request */ 729cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL || 730cadf364dSGavin Shan option == EEH_RESET_HOT) 731cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 732cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 733cadf364dSGavin Shan OPAL_ASSERT_RESET); 734cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 735cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 736cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 737cadf364dSGavin Shan OPAL_DEASSERT_RESET); 738cadf364dSGavin Shan if (rc < 0) 739cadf364dSGavin Shan goto out; 740cadf364dSGavin Shan 741cadf364dSGavin Shan /* 742cadf364dSGavin Shan * Poll state of the PHB until the request is done 743cadf364dSGavin Shan * successfully. The PHB reset is usually PHB complete 744cadf364dSGavin Shan * reset followed by hot reset on root bus. So we also 745cadf364dSGavin Shan * need the PCI bus settlement delay. 746cadf364dSGavin Shan */ 747fbce44d0SGavin Shan if (rc > 0) 748ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 749cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) { 750cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 751cadf364dSGavin Shan udelay(1000 * EEH_PE_RST_SETTLE_TIME); 752cadf364dSGavin Shan else 753cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 754cadf364dSGavin Shan } 755cadf364dSGavin Shan out: 756cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 757cadf364dSGavin Shan return -EIO; 758cadf364dSGavin Shan 759cadf364dSGavin Shan return 0; 760cadf364dSGavin Shan } 761cadf364dSGavin Shan 762cadf364dSGavin Shan static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 763cadf364dSGavin Shan { 764cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 765cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 766cadf364dSGavin Shan 767cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 768cadf364dSGavin Shan __func__, hose->global_number, option); 769cadf364dSGavin Shan 770cadf364dSGavin Shan /* 771cadf364dSGavin Shan * During the reset deassert time, we needn't care 772cadf364dSGavin Shan * the reset scope because the firmware does nothing 773cadf364dSGavin Shan * for fundamental or hot reset during deassert phase. 774cadf364dSGavin Shan */ 775cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL) 776cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 777cadf364dSGavin Shan OPAL_RESET_PCI_FUNDAMENTAL, 778cadf364dSGavin Shan OPAL_ASSERT_RESET); 779cadf364dSGavin Shan else if (option == EEH_RESET_HOT) 780cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 781cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 782cadf364dSGavin Shan OPAL_ASSERT_RESET); 783cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 784cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 785cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 786cadf364dSGavin Shan OPAL_DEASSERT_RESET); 787cadf364dSGavin Shan if (rc < 0) 788cadf364dSGavin Shan goto out; 789cadf364dSGavin Shan 790cadf364dSGavin Shan /* Poll state of the PHB until the request is done */ 791fbce44d0SGavin Shan if (rc > 0) 792ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 793cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) 794cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 795cadf364dSGavin Shan out: 796cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 797cadf364dSGavin Shan return -EIO; 798cadf364dSGavin Shan 799cadf364dSGavin Shan return 0; 800cadf364dSGavin Shan } 801cadf364dSGavin Shan 8029c0e1ecbSGavin Shan static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 803cadf364dSGavin Shan { 8040bd78587SGavin Shan struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 8050bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 806cadf364dSGavin Shan int aer = edev ? edev->aer_cap : 0; 807cadf364dSGavin Shan u32 ctrl; 808cadf364dSGavin Shan 80998fd32cdSOliver O'Halloran pr_debug("%s: Secondary Reset PCI bus %04x:%02x with option %d\n", 810cadf364dSGavin Shan __func__, pci_domain_nr(dev->bus), 811cadf364dSGavin Shan dev->bus->number, option); 812cadf364dSGavin Shan 813cadf364dSGavin Shan switch (option) { 814cadf364dSGavin Shan case EEH_RESET_FUNDAMENTAL: 815cadf364dSGavin Shan case EEH_RESET_HOT: 816cadf364dSGavin Shan /* Don't report linkDown event */ 817cadf364dSGavin Shan if (aer) { 81817d2a487SOliver O'Halloran eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK, 819cadf364dSGavin Shan 4, &ctrl); 820cadf364dSGavin Shan ctrl |= PCI_ERR_UNC_SURPDN; 82117d2a487SOliver O'Halloran eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK, 822cadf364dSGavin Shan 4, ctrl); 823cadf364dSGavin Shan } 824cadf364dSGavin Shan 82517d2a487SOliver O'Halloran eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl); 826cadf364dSGavin Shan ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 82717d2a487SOliver O'Halloran eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl); 828cadf364dSGavin Shan 829cadf364dSGavin Shan msleep(EEH_PE_RST_HOLD_TIME); 830cadf364dSGavin Shan break; 831cadf364dSGavin Shan case EEH_RESET_DEACTIVATE: 83217d2a487SOliver O'Halloran eeh_ops->read_config(edev, PCI_BRIDGE_CONTROL, 2, &ctrl); 833cadf364dSGavin Shan ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 83417d2a487SOliver O'Halloran eeh_ops->write_config(edev, PCI_BRIDGE_CONTROL, 2, ctrl); 835cadf364dSGavin Shan 836cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 837cadf364dSGavin Shan 838cadf364dSGavin Shan /* Continue reporting linkDown event */ 839cadf364dSGavin Shan if (aer) { 84017d2a487SOliver O'Halloran eeh_ops->read_config(edev, aer + PCI_ERR_UNCOR_MASK, 841cadf364dSGavin Shan 4, &ctrl); 842cadf364dSGavin Shan ctrl &= ~PCI_ERR_UNC_SURPDN; 84317d2a487SOliver O'Halloran eeh_ops->write_config(edev, aer + PCI_ERR_UNCOR_MASK, 844cadf364dSGavin Shan 4, ctrl); 845cadf364dSGavin Shan } 846cadf364dSGavin Shan 847cadf364dSGavin Shan break; 848cadf364dSGavin Shan } 849cadf364dSGavin Shan 850cadf364dSGavin Shan return 0; 851cadf364dSGavin Shan } 852cadf364dSGavin Shan 8539c0e1ecbSGavin Shan static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 8549c0e1ecbSGavin Shan { 8559c0e1ecbSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 8569c0e1ecbSGavin Shan struct pnv_phb *phb = hose->private_data; 8579c0e1ecbSGavin Shan struct device_node *dn = pci_device_to_OF_node(pdev); 8589c0e1ecbSGavin Shan uint64_t id = PCI_SLOT_ID(phb->opal_id, 8599c0e1ecbSGavin Shan (pdev->bus->number << 8) | pdev->devfn); 8609c0e1ecbSGavin Shan uint8_t scope; 8619c0e1ecbSGavin Shan int64_t rc; 8629c0e1ecbSGavin Shan 8639c0e1ecbSGavin Shan /* Hot reset to the bus if firmware cannot handle */ 8649c0e1ecbSGavin Shan if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 8659c0e1ecbSGavin Shan return __pnv_eeh_bridge_reset(pdev, option); 8669c0e1ecbSGavin Shan 86798fd32cdSOliver O'Halloran pr_debug("%s: FW reset PCI bus %04x:%02x with option %d\n", 86898fd32cdSOliver O'Halloran __func__, pci_domain_nr(pdev->bus), 86998fd32cdSOliver O'Halloran pdev->bus->number, option); 87098fd32cdSOliver O'Halloran 8719c0e1ecbSGavin Shan switch (option) { 8729c0e1ecbSGavin Shan case EEH_RESET_FUNDAMENTAL: 8739c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_FUNDAMENTAL; 8749c0e1ecbSGavin Shan break; 8759c0e1ecbSGavin Shan case EEH_RESET_HOT: 8769c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_HOT; 8779c0e1ecbSGavin Shan break; 8789c0e1ecbSGavin Shan case EEH_RESET_DEACTIVATE: 8799c0e1ecbSGavin Shan return 0; 8809c0e1ecbSGavin Shan default: 8819c0e1ecbSGavin Shan dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 8829c0e1ecbSGavin Shan __func__, option); 8839c0e1ecbSGavin Shan return -EINVAL; 8849c0e1ecbSGavin Shan } 8859c0e1ecbSGavin Shan 8869c0e1ecbSGavin Shan rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 8879c0e1ecbSGavin Shan if (rc <= OPAL_SUCCESS) 8889c0e1ecbSGavin Shan goto out; 8899c0e1ecbSGavin Shan 8909c0e1ecbSGavin Shan rc = pnv_eeh_poll(id); 8919c0e1ecbSGavin Shan out: 8929c0e1ecbSGavin Shan return (rc == OPAL_SUCCESS) ? 0 : -EIO; 8939c0e1ecbSGavin Shan } 8949c0e1ecbSGavin Shan 895cadf364dSGavin Shan void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 896cadf364dSGavin Shan { 897848912e5SMichael Ellerman struct pci_controller *hose; 898848912e5SMichael Ellerman 899848912e5SMichael Ellerman if (pci_is_root_bus(dev->bus)) { 900848912e5SMichael Ellerman hose = pci_bus_to_host(dev->bus); 901848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_HOT); 902848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 903848912e5SMichael Ellerman } else { 904cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 905cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 906cadf364dSGavin Shan } 907848912e5SMichael Ellerman } 908cadf364dSGavin Shan 9099312bc5bSWei Yang static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 9109312bc5bSWei Yang int pos, u16 mask) 9119312bc5bSWei Yang { 91217d2a487SOliver O'Halloran struct eeh_dev *edev = pdn->edev; 9139312bc5bSWei Yang int i, status = 0; 9149312bc5bSWei Yang 9159312bc5bSWei Yang /* Wait for Transaction Pending bit to be cleared */ 9169312bc5bSWei Yang for (i = 0; i < 4; i++) { 91717d2a487SOliver O'Halloran eeh_ops->read_config(edev, pos, 2, &status); 9189312bc5bSWei Yang if (!(status & mask)) 9199312bc5bSWei Yang return; 9209312bc5bSWei Yang 9219312bc5bSWei Yang msleep((1 << i) * 100); 9229312bc5bSWei Yang } 9239312bc5bSWei Yang 9249312bc5bSWei Yang pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 9259312bc5bSWei Yang __func__, type, 92669672bd7SAlexey Kardashevskiy pdn->phb->global_number, pdn->busno, 9279312bc5bSWei Yang PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 9289312bc5bSWei Yang } 9299312bc5bSWei Yang 9309312bc5bSWei Yang static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 9319312bc5bSWei Yang { 9329312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9339312bc5bSWei Yang u32 reg = 0; 9349312bc5bSWei Yang 9359312bc5bSWei Yang if (WARN_ON(!edev->pcie_cap)) 9369312bc5bSWei Yang return -ENOTTY; 9379312bc5bSWei Yang 93817d2a487SOliver O'Halloran eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 9399312bc5bSWei Yang if (!(reg & PCI_EXP_DEVCAP_FLR)) 9409312bc5bSWei Yang return -ENOTTY; 9419312bc5bSWei Yang 9429312bc5bSWei Yang switch (option) { 9439312bc5bSWei Yang case EEH_RESET_HOT: 9449312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 9459312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "", 9469312bc5bSWei Yang edev->pcie_cap + PCI_EXP_DEVSTA, 9479312bc5bSWei Yang PCI_EXP_DEVSTA_TRPND); 94817d2a487SOliver O'Halloran eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, 9499312bc5bSWei Yang 4, ®); 9509312bc5bSWei Yang reg |= PCI_EXP_DEVCTL_BCR_FLR; 95117d2a487SOliver O'Halloran eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, 9529312bc5bSWei Yang 4, reg); 9539312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 9549312bc5bSWei Yang break; 9559312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 95617d2a487SOliver O'Halloran eeh_ops->read_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, 9579312bc5bSWei Yang 4, ®); 9589312bc5bSWei Yang reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 95917d2a487SOliver O'Halloran eeh_ops->write_config(edev, edev->pcie_cap + PCI_EXP_DEVCTL, 9609312bc5bSWei Yang 4, reg); 9619312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 9629312bc5bSWei Yang break; 9639312bc5bSWei Yang } 9649312bc5bSWei Yang 9659312bc5bSWei Yang return 0; 9669312bc5bSWei Yang } 9679312bc5bSWei Yang 9689312bc5bSWei Yang static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 9699312bc5bSWei Yang { 9709312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9719312bc5bSWei Yang u32 cap = 0; 9729312bc5bSWei Yang 9739312bc5bSWei Yang if (WARN_ON(!edev->af_cap)) 9749312bc5bSWei Yang return -ENOTTY; 9759312bc5bSWei Yang 97617d2a487SOliver O'Halloran eeh_ops->read_config(edev, edev->af_cap + PCI_AF_CAP, 1, &cap); 9779312bc5bSWei Yang if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 9789312bc5bSWei Yang return -ENOTTY; 9799312bc5bSWei Yang 9809312bc5bSWei Yang switch (option) { 9819312bc5bSWei Yang case EEH_RESET_HOT: 9829312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 9839312bc5bSWei Yang /* 9849312bc5bSWei Yang * Wait for Transaction Pending bit to clear. A word-aligned 9851fd02f66SJulia Lawall * test is used, so we use the control offset rather than status 9869312bc5bSWei Yang * and shift the test bit to match. 9879312bc5bSWei Yang */ 9889312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "AF", 9899312bc5bSWei Yang edev->af_cap + PCI_AF_CTRL, 9909312bc5bSWei Yang PCI_AF_STATUS_TP << 8); 99117d2a487SOliver O'Halloran eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 9929312bc5bSWei Yang 1, PCI_AF_CTRL_FLR); 9939312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 9949312bc5bSWei Yang break; 9959312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 99617d2a487SOliver O'Halloran eeh_ops->write_config(edev, edev->af_cap + PCI_AF_CTRL, 1, 0); 9979312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 9989312bc5bSWei Yang break; 9999312bc5bSWei Yang } 10009312bc5bSWei Yang 10019312bc5bSWei Yang return 0; 10029312bc5bSWei Yang } 10039312bc5bSWei Yang 10049312bc5bSWei Yang static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 10059312bc5bSWei Yang { 10069312bc5bSWei Yang struct eeh_dev *edev; 10079312bc5bSWei Yang struct pci_dn *pdn; 10089312bc5bSWei Yang int ret; 10099312bc5bSWei Yang 10109312bc5bSWei Yang /* The VF PE should have only one child device */ 101180e65b00SSam Bobroff edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); 10129312bc5bSWei Yang pdn = eeh_dev_to_pdn(edev); 10139312bc5bSWei Yang if (!pdn) 10149312bc5bSWei Yang return -ENXIO; 10159312bc5bSWei Yang 10169312bc5bSWei Yang ret = pnv_eeh_do_flr(pdn, option); 10179312bc5bSWei Yang if (!ret) 10189312bc5bSWei Yang return ret; 10199312bc5bSWei Yang 10209312bc5bSWei Yang return pnv_eeh_do_af_flr(pdn, option); 10219312bc5bSWei Yang } 10229312bc5bSWei Yang 102329310e5eSGavin Shan /** 102401f3bfb7SGavin Shan * pnv_eeh_reset - Reset the specified PE 102529310e5eSGavin Shan * @pe: EEH PE 102629310e5eSGavin Shan * @option: reset option 102729310e5eSGavin Shan * 1028cadf364dSGavin Shan * Do reset on the indicated PE. For PCI bus sensitive PE, 1029cadf364dSGavin Shan * we need to reset the parent p2p bridge. The PHB has to 1030cadf364dSGavin Shan * be reinitialized if the p2p bridge is root bridge. For 1031cadf364dSGavin Shan * PCI device sensitive PE, we will try to reset the device 1032cadf364dSGavin Shan * through FLR. For now, we don't have OPAL APIs to do HARD 1033cadf364dSGavin Shan * reset yet, so all reset would be SOFT (HOT) reset. 103429310e5eSGavin Shan */ 103501f3bfb7SGavin Shan static int pnv_eeh_reset(struct eeh_pe *pe, int option) 103629310e5eSGavin Shan { 103729310e5eSGavin Shan struct pci_controller *hose = pe->phb; 10384fad4943SGavin Shan struct pnv_phb *phb; 1039cadf364dSGavin Shan struct pci_bus *bus; 10404fad4943SGavin Shan int64_t rc; 104129310e5eSGavin Shan 1042cadf364dSGavin Shan /* 1043cadf364dSGavin Shan * For PHB reset, we always have complete reset. For those PEs whose 1044cadf364dSGavin Shan * primary bus derived from root complex (root bus) or root port 1045cadf364dSGavin Shan * (usually bus#1), we apply hot or fundamental reset on the root port. 1046cadf364dSGavin Shan * For other PEs, we always have hot reset on the PE primary bus. 1047cadf364dSGavin Shan * 1048cadf364dSGavin Shan * Here, we have different design to pHyp, which always clear the 1049cadf364dSGavin Shan * frozen state during PE reset. However, the good idea here from 1050cadf364dSGavin Shan * benh is to keep frozen state before we get PE reset done completely 1051cadf364dSGavin Shan * (until BAR restore). With the frozen state, HW drops illegal IO 10521fd02f66SJulia Lawall * or MMIO access, which can incur recursive frozen PE during PE 1053cadf364dSGavin Shan * reset. The side effect is that EEH core has to clear the frozen 1054cadf364dSGavin Shan * state explicitly after BAR restore. 1055cadf364dSGavin Shan */ 10564fad4943SGavin Shan if (pe->type & EEH_PE_PHB) 10574fad4943SGavin Shan return pnv_eeh_phb_reset(hose, option); 1058cadf364dSGavin Shan 1059cadf364dSGavin Shan /* 1060cadf364dSGavin Shan * The frozen PE might be caused by PAPR error injection 1061cadf364dSGavin Shan * registers, which are expected to be cleared after hitting 1062cadf364dSGavin Shan * frozen PE as stated in the hardware spec. Unfortunately, 1063cadf364dSGavin Shan * that's not true on P7IOC. So we have to clear it manually 1064cadf364dSGavin Shan * to avoid recursive EEH errors during recovery. 1065cadf364dSGavin Shan */ 1066cadf364dSGavin Shan phb = hose->private_data; 1067cadf364dSGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC && 1068cadf364dSGavin Shan (option == EEH_RESET_HOT || 1069cadf364dSGavin Shan option == EEH_RESET_FUNDAMENTAL)) { 1070cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 1071cadf364dSGavin Shan OPAL_RESET_PHB_ERROR, 1072cadf364dSGavin Shan OPAL_ASSERT_RESET); 1073cadf364dSGavin Shan if (rc != OPAL_SUCCESS) { 10744fad4943SGavin Shan pr_warn("%s: Failure %lld clearing error injection registers\n", 1075cadf364dSGavin Shan __func__, rc); 1076cadf364dSGavin Shan return -EIO; 1077cadf364dSGavin Shan } 1078cadf364dSGavin Shan } 1079cadf364dSGavin Shan 1080e98ddb77SRussell Currey if (pe->type & EEH_PE_VF) 1081e98ddb77SRussell Currey return pnv_eeh_reset_vf_pe(pe, option); 1082e98ddb77SRussell Currey 1083cadf364dSGavin Shan bus = eeh_pe_bus_get(pe); 108404fec21cSRussell Currey if (!bus) { 10851f52f176SRussell Currey pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 108604fec21cSRussell Currey __func__, pe->phb->global_number, pe->addr); 108704fec21cSRussell Currey return -EIO; 108804fec21cSRussell Currey } 108929310e5eSGavin Shan 109098fd32cdSOliver O'Halloran if (pci_is_root_bus(bus)) 10914fad4943SGavin Shan return pnv_eeh_root_reset(hose, option); 10924fad4943SGavin Shan 109398fd32cdSOliver O'Halloran /* 109498fd32cdSOliver O'Halloran * For hot resets try use the generic PCI error recovery reset 109598fd32cdSOliver O'Halloran * functions. These correctly handles the case where the secondary 109698fd32cdSOliver O'Halloran * bus is behind a hotplug slot and it will use the slot provided 109798fd32cdSOliver O'Halloran * reset methods to prevent spurious hotplug events during the reset. 109898fd32cdSOliver O'Halloran * 10991fd02f66SJulia Lawall * Fundamental resets need to be handled internally to EEH since the 11001fd02f66SJulia Lawall * PCI core doesn't really have a concept of a fundamental reset, 110198fd32cdSOliver O'Halloran * mainly because there's no standard way to generate one. Only a 110298fd32cdSOliver O'Halloran * few devices require an FRESET so it should be fine. 110398fd32cdSOliver O'Halloran */ 110498fd32cdSOliver O'Halloran if (option != EEH_RESET_FUNDAMENTAL) { 110598fd32cdSOliver O'Halloran /* 110698fd32cdSOliver O'Halloran * NB: Skiboot and pnv_eeh_bridge_reset() also no-op the 110798fd32cdSOliver O'Halloran * de-assert step. It's like the OPAL reset API was 110898fd32cdSOliver O'Halloran * poorly designed or something... 110998fd32cdSOliver O'Halloran */ 111098fd32cdSOliver O'Halloran if (option == EEH_RESET_DEACTIVATE) 111198fd32cdSOliver O'Halloran return 0; 111298fd32cdSOliver O'Halloran 111398fd32cdSOliver O'Halloran rc = pci_bus_error_reset(bus->self); 111498fd32cdSOliver O'Halloran if (!rc) 111598fd32cdSOliver O'Halloran return 0; 111698fd32cdSOliver O'Halloran } 111798fd32cdSOliver O'Halloran 111898fd32cdSOliver O'Halloran /* otherwise, use the generic bridge reset. this might call into FW */ 111998fd32cdSOliver O'Halloran if (pci_is_root_bus(bus->parent)) 112098fd32cdSOliver O'Halloran return pnv_eeh_root_reset(hose, option); 11214fad4943SGavin Shan return pnv_eeh_bridge_reset(bus->self, option); 112229310e5eSGavin Shan } 112329310e5eSGavin Shan 112429310e5eSGavin Shan /** 112501f3bfb7SGavin Shan * pnv_eeh_get_log - Retrieve error log 112629310e5eSGavin Shan * @pe: EEH PE 112729310e5eSGavin Shan * @severity: temporary or permanent error log 112829310e5eSGavin Shan * @drv_log: driver log to be combined with retrieved error log 112929310e5eSGavin Shan * @len: length of driver log 113029310e5eSGavin Shan * 113129310e5eSGavin Shan * Retrieve the temporary or permanent error from the PE. 113229310e5eSGavin Shan */ 113301f3bfb7SGavin Shan static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 113429310e5eSGavin Shan char *drv_log, unsigned long len) 113529310e5eSGavin Shan { 113695edcdeaSGavin Shan if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 113795edcdeaSGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 113829310e5eSGavin Shan 113995edcdeaSGavin Shan return 0; 114029310e5eSGavin Shan } 114129310e5eSGavin Shan 114229310e5eSGavin Shan /** 114301f3bfb7SGavin Shan * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 114429310e5eSGavin Shan * @pe: EEH PE 114529310e5eSGavin Shan * 114629310e5eSGavin Shan * The function will be called to reconfigure the bridges included 114729310e5eSGavin Shan * in the specified PE so that the mulfunctional PE would be recovered 114829310e5eSGavin Shan * again. 114929310e5eSGavin Shan */ 115001f3bfb7SGavin Shan static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 115129310e5eSGavin Shan { 1152bbe170edSGavin Shan return 0; 115329310e5eSGavin Shan } 115429310e5eSGavin Shan 115529310e5eSGavin Shan /** 115601f3bfb7SGavin Shan * pnv_pe_err_inject - Inject specified error to the indicated PE 1157131c123aSGavin Shan * @pe: the indicated PE 1158131c123aSGavin Shan * @type: error type 1159131c123aSGavin Shan * @func: specific error type 1160131c123aSGavin Shan * @addr: address 1161131c123aSGavin Shan * @mask: address mask 1162131c123aSGavin Shan * 1163131c123aSGavin Shan * The routine is called to inject specified error, which is 1164131c123aSGavin Shan * determined by @type and @func, to the indicated PE for 1165131c123aSGavin Shan * testing purpose. 1166131c123aSGavin Shan */ 116701f3bfb7SGavin Shan static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1168131c123aSGavin Shan unsigned long addr, unsigned long mask) 1169131c123aSGavin Shan { 1170131c123aSGavin Shan struct pci_controller *hose = pe->phb; 1171131c123aSGavin Shan struct pnv_phb *phb = hose->private_data; 1172fa646c3cSGavin Shan s64 rc; 1173131c123aSGavin Shan 1174fa646c3cSGavin Shan if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1175fa646c3cSGavin Shan type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1176fa646c3cSGavin Shan pr_warn("%s: Invalid error type %d\n", 1177fa646c3cSGavin Shan __func__, type); 1178fa646c3cSGavin Shan return -ERANGE; 1179fa646c3cSGavin Shan } 1180131c123aSGavin Shan 1181fa646c3cSGavin Shan if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1182fa646c3cSGavin Shan func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1183fa646c3cSGavin Shan pr_warn("%s: Invalid error function %d\n", 1184fa646c3cSGavin Shan __func__, func); 1185fa646c3cSGavin Shan return -ERANGE; 1186fa646c3cSGavin Shan } 1187fa646c3cSGavin Shan 1188fa646c3cSGavin Shan /* Firmware supports error injection ? */ 1189fa646c3cSGavin Shan if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1190fa646c3cSGavin Shan pr_warn("%s: Firmware doesn't support error injection\n", 1191fa646c3cSGavin Shan __func__); 1192fa646c3cSGavin Shan return -ENXIO; 1193fa646c3cSGavin Shan } 1194fa646c3cSGavin Shan 1195fa646c3cSGavin Shan /* Do error injection */ 1196fa646c3cSGavin Shan rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1197fa646c3cSGavin Shan type, func, addr, mask); 1198fa646c3cSGavin Shan if (rc != OPAL_SUCCESS) { 1199fa646c3cSGavin Shan pr_warn("%s: Failure %lld injecting error " 1200fa646c3cSGavin Shan "%d-%d to PHB#%x-PE#%x\n", 1201fa646c3cSGavin Shan __func__, rc, type, func, 1202fa646c3cSGavin Shan hose->global_number, pe->addr); 1203fa646c3cSGavin Shan return -EIO; 1204fa646c3cSGavin Shan } 1205fa646c3cSGavin Shan 1206fa646c3cSGavin Shan return 0; 1207131c123aSGavin Shan } 1208131c123aSGavin Shan 12090bd78587SGavin Shan static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1210d2cfbcd7SGavin Shan { 12110bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1212d2cfbcd7SGavin Shan 1213d2cfbcd7SGavin Shan if (!edev || !edev->pe) 1214d2cfbcd7SGavin Shan return false; 1215d2cfbcd7SGavin Shan 12169312bc5bSWei Yang /* 12179312bc5bSWei Yang * We will issue FLR or AF FLR to all VFs, which are contained 12189312bc5bSWei Yang * in VF PE. It relies on the EEH PCI config accessors. So we 12199312bc5bSWei Yang * can't block them during the window. 12209312bc5bSWei Yang */ 12219312bc5bSWei Yang if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 12229312bc5bSWei Yang return false; 12239312bc5bSWei Yang 1224d2cfbcd7SGavin Shan if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1225d2cfbcd7SGavin Shan return true; 1226d2cfbcd7SGavin Shan 1227d2cfbcd7SGavin Shan return false; 1228d2cfbcd7SGavin Shan } 1229d2cfbcd7SGavin Shan 123017d2a487SOliver O'Halloran static int pnv_eeh_read_config(struct eeh_dev *edev, 1231d2cfbcd7SGavin Shan int where, int size, u32 *val) 1232d2cfbcd7SGavin Shan { 123317d2a487SOliver O'Halloran struct pci_dn *pdn = eeh_dev_to_pdn(edev); 123417d2a487SOliver O'Halloran 12353532a741SGavin Shan if (!pdn) 12363532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12373532a741SGavin Shan 12380bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) { 1239d2cfbcd7SGavin Shan *val = 0xFFFFFFFF; 1240d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1241d2cfbcd7SGavin Shan } 1242d2cfbcd7SGavin Shan 12433532a741SGavin Shan return pnv_pci_cfg_read(pdn, where, size, val); 1244d2cfbcd7SGavin Shan } 1245d2cfbcd7SGavin Shan 124617d2a487SOliver O'Halloran static int pnv_eeh_write_config(struct eeh_dev *edev, 1247d2cfbcd7SGavin Shan int where, int size, u32 val) 1248d2cfbcd7SGavin Shan { 124917d2a487SOliver O'Halloran struct pci_dn *pdn = eeh_dev_to_pdn(edev); 125017d2a487SOliver O'Halloran 12513532a741SGavin Shan if (!pdn) 12523532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12533532a741SGavin Shan 12540bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) 1255d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1256d2cfbcd7SGavin Shan 12573532a741SGavin Shan return pnv_pci_cfg_write(pdn, where, size, val); 1258d2cfbcd7SGavin Shan } 1259d2cfbcd7SGavin Shan 12602a485ad7SGavin Shan static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 12612a485ad7SGavin Shan { 12622a485ad7SGavin Shan /* GEM */ 12632a485ad7SGavin Shan if (data->gemXfir || data->gemRfir || 12642a485ad7SGavin Shan data->gemRirqfir || data->gemMask || data->gemRwof) 12652a485ad7SGavin Shan pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 12662a485ad7SGavin Shan be64_to_cpu(data->gemXfir), 12672a485ad7SGavin Shan be64_to_cpu(data->gemRfir), 12682a485ad7SGavin Shan be64_to_cpu(data->gemRirqfir), 12692a485ad7SGavin Shan be64_to_cpu(data->gemMask), 12702a485ad7SGavin Shan be64_to_cpu(data->gemRwof)); 12712a485ad7SGavin Shan 12722a485ad7SGavin Shan /* LEM */ 12732a485ad7SGavin Shan if (data->lemFir || data->lemErrMask || 12742a485ad7SGavin Shan data->lemAction0 || data->lemAction1 || data->lemWof) 12752a485ad7SGavin Shan pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 12762a485ad7SGavin Shan be64_to_cpu(data->lemFir), 12772a485ad7SGavin Shan be64_to_cpu(data->lemErrMask), 12782a485ad7SGavin Shan be64_to_cpu(data->lemAction0), 12792a485ad7SGavin Shan be64_to_cpu(data->lemAction1), 12802a485ad7SGavin Shan be64_to_cpu(data->lemWof)); 12812a485ad7SGavin Shan } 12822a485ad7SGavin Shan 12832a485ad7SGavin Shan static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 12842a485ad7SGavin Shan { 12852a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 12865cb1f8fdSRussell Currey struct OpalIoP7IOCErrorData *data = 12875cb1f8fdSRussell Currey (struct OpalIoP7IOCErrorData*)phb->diag_data; 12882a485ad7SGavin Shan long rc; 12892a485ad7SGavin Shan 12902a485ad7SGavin Shan rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 12912a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 12922a485ad7SGavin Shan pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 12932a485ad7SGavin Shan __func__, phb->hub_id, rc); 12942a485ad7SGavin Shan return; 12952a485ad7SGavin Shan } 12962a485ad7SGavin Shan 1297a7032132SGavin Shan switch (be16_to_cpu(data->type)) { 12982a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_RGC: 12992a485ad7SGavin Shan pr_info("P7IOC diag-data for RGC\n\n"); 13002a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13012a485ad7SGavin Shan if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 13022a485ad7SGavin Shan pr_info(" RGC: %016llx %016llx\n", 13032a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcStatus), 13042a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcLdcp)); 13052a485ad7SGavin Shan break; 13062a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_BI: 13072a485ad7SGavin Shan pr_info("P7IOC diag-data for BI %s\n\n", 13082a485ad7SGavin Shan data->bi.biDownbound ? "Downbound" : "Upbound"); 13092a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13102a485ad7SGavin Shan if (data->bi.biLdcp0 || data->bi.biLdcp1 || 13112a485ad7SGavin Shan data->bi.biLdcp2 || data->bi.biFenceStatus) 13122a485ad7SGavin Shan pr_info(" BI: %016llx %016llx %016llx %016llx\n", 13132a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp0), 13142a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp1), 13152a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp2), 13162a485ad7SGavin Shan be64_to_cpu(data->bi.biFenceStatus)); 13172a485ad7SGavin Shan break; 13182a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_CI: 13192a485ad7SGavin Shan pr_info("P7IOC diag-data for CI Port %d\n\n", 13202a485ad7SGavin Shan data->ci.ciPort); 13212a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13222a485ad7SGavin Shan if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 13232a485ad7SGavin Shan pr_info(" CI: %016llx %016llx\n", 13242a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortStatus), 13252a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortLdcp)); 13262a485ad7SGavin Shan break; 13272a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_MISC: 13282a485ad7SGavin Shan pr_info("P7IOC diag-data for MISC\n\n"); 13292a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13302a485ad7SGavin Shan break; 13312a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_I2C: 13322a485ad7SGavin Shan pr_info("P7IOC diag-data for I2C\n\n"); 13332a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13342a485ad7SGavin Shan break; 13352a485ad7SGavin Shan default: 13362a485ad7SGavin Shan pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 13372a485ad7SGavin Shan __func__, phb->hub_id, data->type); 13382a485ad7SGavin Shan } 13392a485ad7SGavin Shan } 13402a485ad7SGavin Shan 13412a485ad7SGavin Shan static int pnv_eeh_get_pe(struct pci_controller *hose, 13422a485ad7SGavin Shan u16 pe_no, struct eeh_pe **pe) 13432a485ad7SGavin Shan { 13442a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 13452a485ad7SGavin Shan struct pnv_ioda_pe *pnv_pe; 13462a485ad7SGavin Shan struct eeh_pe *dev_pe; 13472a485ad7SGavin Shan 13482a485ad7SGavin Shan /* 13492a485ad7SGavin Shan * If PHB supports compound PE, to fetch 13502a485ad7SGavin Shan * the master PE because slave PE is invisible 13512a485ad7SGavin Shan * to EEH core. 13522a485ad7SGavin Shan */ 13532a485ad7SGavin Shan pnv_pe = &phb->ioda.pe_array[pe_no]; 13542a485ad7SGavin Shan if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 13552a485ad7SGavin Shan pnv_pe = pnv_pe->master; 13562a485ad7SGavin Shan WARN_ON(!pnv_pe || 13572a485ad7SGavin Shan !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 13582a485ad7SGavin Shan pe_no = pnv_pe->pe_number; 13592a485ad7SGavin Shan } 13602a485ad7SGavin Shan 13612a485ad7SGavin Shan /* Find the PE according to PE# */ 136235d64734SOliver O'Halloran dev_pe = eeh_pe_get(hose, pe_no); 13632a485ad7SGavin Shan if (!dev_pe) 13642a485ad7SGavin Shan return -EEXIST; 13652a485ad7SGavin Shan 13662a485ad7SGavin Shan /* Freeze the (compound) PE */ 13672a485ad7SGavin Shan *pe = dev_pe; 13682a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 13692a485ad7SGavin Shan phb->freeze_pe(phb, pe_no); 13702a485ad7SGavin Shan 13712a485ad7SGavin Shan /* 13722a485ad7SGavin Shan * At this point, we're sure the (compound) PE should 13732a485ad7SGavin Shan * have been frozen. However, we still need poke until 13742a485ad7SGavin Shan * hitting the frozen PE on top level. 13752a485ad7SGavin Shan */ 13762a485ad7SGavin Shan dev_pe = dev_pe->parent; 13772a485ad7SGavin Shan while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 13782a485ad7SGavin Shan int ret; 13792a485ad7SGavin Shan ret = eeh_ops->get_state(dev_pe, NULL); 138034a286a4SSam Bobroff if (ret <= 0 || eeh_state_active(ret)) { 13812a485ad7SGavin Shan dev_pe = dev_pe->parent; 13822a485ad7SGavin Shan continue; 13832a485ad7SGavin Shan } 13842a485ad7SGavin Shan 13852a485ad7SGavin Shan /* Frozen parent PE */ 13862a485ad7SGavin Shan *pe = dev_pe; 13872a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 13882a485ad7SGavin Shan phb->freeze_pe(phb, dev_pe->addr); 13892a485ad7SGavin Shan 13902a485ad7SGavin Shan /* Next one */ 13912a485ad7SGavin Shan dev_pe = dev_pe->parent; 13922a485ad7SGavin Shan } 13932a485ad7SGavin Shan 13942a485ad7SGavin Shan return 0; 13952a485ad7SGavin Shan } 13962a485ad7SGavin Shan 1397131c123aSGavin Shan /** 139801f3bfb7SGavin Shan * pnv_eeh_next_error - Retrieve next EEH error to handle 139929310e5eSGavin Shan * @pe: Affected PE 140029310e5eSGavin Shan * 14012a485ad7SGavin Shan * The function is expected to be called by EEH core while it gets 14022a485ad7SGavin Shan * special EEH event (without binding PE). The function calls to 14032a485ad7SGavin Shan * OPAL APIs for next error to handle. The informational error is 14042a485ad7SGavin Shan * handled internally by platform. However, the dead IOC, dead PHB, 14052a485ad7SGavin Shan * fenced PHB and frozen PE should be handled by EEH core eventually. 140629310e5eSGavin Shan */ 140701f3bfb7SGavin Shan static int pnv_eeh_next_error(struct eeh_pe **pe) 140829310e5eSGavin Shan { 140929310e5eSGavin Shan struct pci_controller *hose; 14102a485ad7SGavin Shan struct pnv_phb *phb; 14112a485ad7SGavin Shan struct eeh_pe *phb_pe, *parent_pe; 14122a485ad7SGavin Shan __be64 frozen_pe_no; 14132a485ad7SGavin Shan __be16 err_type, severity; 14142a485ad7SGavin Shan long rc; 14152a485ad7SGavin Shan int state, ret = EEH_NEXT_ERR_NONE; 14162a485ad7SGavin Shan 14172a485ad7SGavin Shan /* 141879231448SAlistair Popple * While running here, it's safe to purge the event queue. The 141979231448SAlistair Popple * event should still be masked. 14202a485ad7SGavin Shan */ 14212a485ad7SGavin Shan eeh_remove_event(NULL, false); 142229310e5eSGavin Shan 142329310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 14242a485ad7SGavin Shan /* 14252a485ad7SGavin Shan * If the subordinate PCI buses of the PHB has been 14262a485ad7SGavin Shan * removed or is exactly under error recovery, we 14272a485ad7SGavin Shan * needn't take care of it any more. 14282a485ad7SGavin Shan */ 142929310e5eSGavin Shan phb = hose->private_data; 14302a485ad7SGavin Shan phb_pe = eeh_phb_pe_get(hose); 14312a485ad7SGavin Shan if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 14322a485ad7SGavin Shan continue; 14332a485ad7SGavin Shan 14342a485ad7SGavin Shan rc = opal_pci_next_error(phb->opal_id, 14352a485ad7SGavin Shan &frozen_pe_no, &err_type, &severity); 14362a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 14372a485ad7SGavin Shan pr_devel("%s: Invalid return value on " 14382a485ad7SGavin Shan "PHB#%x (0x%lx) from opal_pci_next_error", 14392a485ad7SGavin Shan __func__, hose->global_number, rc); 14402a485ad7SGavin Shan continue; 14412a485ad7SGavin Shan } 14422a485ad7SGavin Shan 14432a485ad7SGavin Shan /* If the PHB doesn't have error, stop processing */ 14442a485ad7SGavin Shan if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 14452a485ad7SGavin Shan be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 14462a485ad7SGavin Shan pr_devel("%s: No error found on PHB#%x\n", 14472a485ad7SGavin Shan __func__, hose->global_number); 14482a485ad7SGavin Shan continue; 14492a485ad7SGavin Shan } 14502a485ad7SGavin Shan 14512a485ad7SGavin Shan /* 14522a485ad7SGavin Shan * Processing the error. We're expecting the error with 14532a485ad7SGavin Shan * highest priority reported upon multiple errors on the 14542a485ad7SGavin Shan * specific PHB. 14552a485ad7SGavin Shan */ 14562a485ad7SGavin Shan pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 14572a485ad7SGavin Shan __func__, be16_to_cpu(err_type), 14582a485ad7SGavin Shan be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 14592a485ad7SGavin Shan hose->global_number); 14602a485ad7SGavin Shan switch (be16_to_cpu(err_type)) { 14612a485ad7SGavin Shan case OPAL_EEH_IOC_ERROR: 14622a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 14632a485ad7SGavin Shan pr_err("EEH: dead IOC detected\n"); 14642a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_IOC; 14652a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 14662a485ad7SGavin Shan pr_info("EEH: IOC informative error " 14672a485ad7SGavin Shan "detected\n"); 14682a485ad7SGavin Shan pnv_eeh_get_and_dump_hub_diag(hose); 14692a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 14702a485ad7SGavin Shan } 14712a485ad7SGavin Shan 14722a485ad7SGavin Shan break; 14732a485ad7SGavin Shan case OPAL_EEH_PHB_ERROR: 14742a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 14752a485ad7SGavin Shan *pe = phb_pe; 14762a485ad7SGavin Shan pr_err("EEH: dead PHB#%x detected, " 14772a485ad7SGavin Shan "location: %s\n", 14782a485ad7SGavin Shan hose->global_number, 14792a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14802a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_PHB; 14812a485ad7SGavin Shan } else if (be16_to_cpu(severity) == 14822a485ad7SGavin Shan OPAL_EEH_SEV_PHB_FENCED) { 14832a485ad7SGavin Shan *pe = phb_pe; 14842a485ad7SGavin Shan pr_err("EEH: Fenced PHB#%x detected, " 14852a485ad7SGavin Shan "location: %s\n", 14862a485ad7SGavin Shan hose->global_number, 14872a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14882a485ad7SGavin Shan ret = EEH_NEXT_ERR_FENCED_PHB; 14892a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 14902a485ad7SGavin Shan pr_info("EEH: PHB#%x informative error " 14912a485ad7SGavin Shan "detected, location: %s\n", 14922a485ad7SGavin Shan hose->global_number, 14932a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14942a485ad7SGavin Shan pnv_eeh_get_phb_diag(phb_pe); 14952a485ad7SGavin Shan pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 14962a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 14972a485ad7SGavin Shan } 14982a485ad7SGavin Shan 14992a485ad7SGavin Shan break; 15002a485ad7SGavin Shan case OPAL_EEH_PE_ERROR: 15012a485ad7SGavin Shan /* 15022a485ad7SGavin Shan * If we can't find the corresponding PE, we 15032a485ad7SGavin Shan * just try to unfreeze. 15042a485ad7SGavin Shan */ 15052a485ad7SGavin Shan if (pnv_eeh_get_pe(hose, 15062a485ad7SGavin Shan be64_to_cpu(frozen_pe_no), pe)) { 15072a485ad7SGavin Shan pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 15080f36db77SGavin Shan hose->global_number, be64_to_cpu(frozen_pe_no)); 15092a485ad7SGavin Shan pr_info("EEH: PHB location: %s\n", 15102a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 151179cd9520SGavin Shan 151279cd9520SGavin Shan /* Dump PHB diag-data */ 151379cd9520SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, 15145cb1f8fdSRussell Currey phb->diag_data, phb->diag_data_size); 151579cd9520SGavin Shan if (rc == OPAL_SUCCESS) 151679cd9520SGavin Shan pnv_pci_dump_phb_diag_data(hose, 15175cb1f8fdSRussell Currey phb->diag_data); 151879cd9520SGavin Shan 151979cd9520SGavin Shan /* Try best to clear it */ 15202a485ad7SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 1521d63e51b3SGavin Shan be64_to_cpu(frozen_pe_no), 15222a485ad7SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 15232a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15242a485ad7SGavin Shan } else if ((*pe)->state & EEH_PE_ISOLATED || 15252a485ad7SGavin Shan eeh_pe_passed(*pe)) { 15262a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15272a485ad7SGavin Shan } else { 15282a485ad7SGavin Shan pr_err("EEH: Frozen PE#%x " 15292a485ad7SGavin Shan "on PHB#%x detected\n", 15302a485ad7SGavin Shan (*pe)->addr, 15312a485ad7SGavin Shan (*pe)->phb->global_number); 15322a485ad7SGavin Shan pr_err("EEH: PE location: %s, " 15332a485ad7SGavin Shan "PHB location: %s\n", 15342a485ad7SGavin Shan eeh_pe_loc_get(*pe), 15352a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15362a485ad7SGavin Shan ret = EEH_NEXT_ERR_FROZEN_PE; 15372a485ad7SGavin Shan } 15382a485ad7SGavin Shan 15392a485ad7SGavin Shan break; 15402a485ad7SGavin Shan default: 15412a485ad7SGavin Shan pr_warn("%s: Unexpected error type %d\n", 15422a485ad7SGavin Shan __func__, be16_to_cpu(err_type)); 15432a485ad7SGavin Shan } 15442a485ad7SGavin Shan 15452a485ad7SGavin Shan /* 15462a485ad7SGavin Shan * EEH core will try recover from fenced PHB or 15472a485ad7SGavin Shan * frozen PE. In the time for frozen PE, EEH core 15482a485ad7SGavin Shan * enable IO path for that before collecting logs, 15492a485ad7SGavin Shan * but it ruins the site. So we have to dump the 15502a485ad7SGavin Shan * log in advance here. 15512a485ad7SGavin Shan */ 15522a485ad7SGavin Shan if ((ret == EEH_NEXT_ERR_FROZEN_PE || 15532a485ad7SGavin Shan ret == EEH_NEXT_ERR_FENCED_PHB) && 15542a485ad7SGavin Shan !((*pe)->state & EEH_PE_ISOLATED)) { 1555e762bb89SSam Bobroff eeh_pe_mark_isolated(*pe); 15562a485ad7SGavin Shan pnv_eeh_get_phb_diag(*pe); 15572a485ad7SGavin Shan 15582a485ad7SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 15592a485ad7SGavin Shan pnv_pci_dump_phb_diag_data((*pe)->phb, 15602a485ad7SGavin Shan (*pe)->data); 15612a485ad7SGavin Shan } 15622a485ad7SGavin Shan 15632a485ad7SGavin Shan /* 15642a485ad7SGavin Shan * We probably have the frozen parent PE out there and 15652a485ad7SGavin Shan * we need have to handle frozen parent PE firstly. 15662a485ad7SGavin Shan */ 15672a485ad7SGavin Shan if (ret == EEH_NEXT_ERR_FROZEN_PE) { 15682a485ad7SGavin Shan parent_pe = (*pe)->parent; 15692a485ad7SGavin Shan while (parent_pe) { 15702a485ad7SGavin Shan /* Hit the ceiling ? */ 15712a485ad7SGavin Shan if (parent_pe->type & EEH_PE_PHB) 15722a485ad7SGavin Shan break; 15732a485ad7SGavin Shan 15742a485ad7SGavin Shan /* Frozen parent PE ? */ 15752a485ad7SGavin Shan state = eeh_ops->get_state(parent_pe, NULL); 157634a286a4SSam Bobroff if (state > 0 && !eeh_state_active(state)) 15772a485ad7SGavin Shan *pe = parent_pe; 15782a485ad7SGavin Shan 15792a485ad7SGavin Shan /* Next parent level */ 15802a485ad7SGavin Shan parent_pe = parent_pe->parent; 15812a485ad7SGavin Shan } 15822a485ad7SGavin Shan 15832a485ad7SGavin Shan /* We possibly migrate to another PE */ 1584e762bb89SSam Bobroff eeh_pe_mark_isolated(*pe); 15852a485ad7SGavin Shan } 15862a485ad7SGavin Shan 15872a485ad7SGavin Shan /* 15882a485ad7SGavin Shan * If we have no errors on the specific PHB or only 15892a485ad7SGavin Shan * informative error there, we continue poking it. 15902a485ad7SGavin Shan * Otherwise, we need actions to be taken by upper 15912a485ad7SGavin Shan * layer. 15922a485ad7SGavin Shan */ 15932a485ad7SGavin Shan if (ret > EEH_NEXT_ERR_INF) 159429310e5eSGavin Shan break; 159529310e5eSGavin Shan } 159629310e5eSGavin Shan 159779231448SAlistair Popple /* Unmask the event */ 1598b8d65e96SAlistair Popple if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 159979231448SAlistair Popple enable_irq(eeh_event_irq); 160079231448SAlistair Popple 16012a485ad7SGavin Shan return ret; 160229310e5eSGavin Shan } 160329310e5eSGavin Shan 16040c2c7652SOliver O'Halloran static int pnv_eeh_restore_config(struct eeh_dev *edev) 16059be3beccSGavin Shan { 16069be3beccSGavin Shan struct pnv_phb *phb; 160764ba3dc7SBryant G. Ly s64 ret = 0; 16089be3beccSGavin Shan 16099be3beccSGavin Shan if (!edev) 16109be3beccSGavin Shan return -EEXIST; 16119be3beccSGavin Shan 161221b43bd5SOliver O'Halloran if (edev->physfn) 161321b43bd5SOliver O'Halloran return 0; 161421b43bd5SOliver O'Halloran 161521b43bd5SOliver O'Halloran phb = edev->controller->private_data; 16169be3beccSGavin Shan ret = opal_pci_reinit(phb->opal_id, 161721b43bd5SOliver O'Halloran OPAL_REINIT_PCI_DEV, edev->bdfn); 16180dc2830eSWei Yang 16199be3beccSGavin Shan if (ret) { 16209be3beccSGavin Shan pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 16210c2c7652SOliver O'Halloran __func__, edev->bdfn, ret); 16229be3beccSGavin Shan return -EIO; 16239be3beccSGavin Shan } 16249be3beccSGavin Shan 162564ba3dc7SBryant G. Ly return ret; 16269be3beccSGavin Shan } 16279be3beccSGavin Shan 162801f3bfb7SGavin Shan static struct eeh_ops pnv_eeh_ops = { 162929310e5eSGavin Shan .name = "powernv", 1630ff57b454SGavin Shan .probe = pnv_eeh_probe, 163101f3bfb7SGavin Shan .set_option = pnv_eeh_set_option, 163201f3bfb7SGavin Shan .get_state = pnv_eeh_get_state, 163301f3bfb7SGavin Shan .reset = pnv_eeh_reset, 163401f3bfb7SGavin Shan .get_log = pnv_eeh_get_log, 163501f3bfb7SGavin Shan .configure_bridge = pnv_eeh_configure_bridge, 163601f3bfb7SGavin Shan .err_inject = pnv_eeh_err_inject, 163701f3bfb7SGavin Shan .read_config = pnv_eeh_read_config, 163801f3bfb7SGavin Shan .write_config = pnv_eeh_write_config, 163901f3bfb7SGavin Shan .next_error = pnv_eeh_next_error, 164067923cfcSBryant G. Ly .restore_config = pnv_eeh_restore_config, 164167923cfcSBryant G. Ly .notify_resume = NULL 164229310e5eSGavin Shan }; 164329310e5eSGavin Shan 16440dc2830eSWei Yang #ifdef CONFIG_PCI_IOV 16450dc2830eSWei Yang static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 16460dc2830eSWei Yang { 16470dc2830eSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 16480dc2830eSWei Yang int parent_mps; 16490dc2830eSWei Yang 16500dc2830eSWei Yang if (!pdev->is_virtfn) 16510dc2830eSWei Yang return; 16520dc2830eSWei Yang 16530dc2830eSWei Yang /* Synchronize MPS for VF and PF */ 16540dc2830eSWei Yang parent_mps = pcie_get_mps(pdev->physfn); 16550dc2830eSWei Yang if ((128 << pdev->pcie_mpss) >= parent_mps) 16560dc2830eSWei Yang pcie_set_mps(pdev, parent_mps); 16570dc2830eSWei Yang pdn->mps = pcie_get_mps(pdev); 16580dc2830eSWei Yang } 16590dc2830eSWei Yang DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 16600dc2830eSWei Yang #endif /* CONFIG_PCI_IOV */ 16610dc2830eSWei Yang 166229310e5eSGavin Shan /** 166329310e5eSGavin Shan * eeh_powernv_init - Register platform dependent EEH operations 166429310e5eSGavin Shan * 166529310e5eSGavin Shan * EEH initialization on powernv platform. This function should be 166629310e5eSGavin Shan * called before any EEH related functions. 166729310e5eSGavin Shan */ 166829310e5eSGavin Shan static int __init eeh_powernv_init(void) 166929310e5eSGavin Shan { 167082a1ea21SOliver O'Halloran int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 167182a1ea21SOliver O'Halloran struct pci_controller *hose; 167282a1ea21SOliver O'Halloran struct pnv_phb *phb; 167329310e5eSGavin Shan int ret = -EINVAL; 167429310e5eSGavin Shan 167582a1ea21SOliver O'Halloran if (!firmware_has_feature(FW_FEATURE_OPAL)) { 167682a1ea21SOliver O'Halloran pr_warn("%s: OPAL is required !\n", __func__); 167782a1ea21SOliver O'Halloran return -EINVAL; 167882a1ea21SOliver O'Halloran } 167982a1ea21SOliver O'Halloran 168082a1ea21SOliver O'Halloran /* Set probe mode */ 168182a1ea21SOliver O'Halloran eeh_add_flag(EEH_PROBE_MODE_DEV); 168282a1ea21SOliver O'Halloran 168382a1ea21SOliver O'Halloran /* 168482a1ea21SOliver O'Halloran * P7IOC blocks PCI config access to frozen PE, but PHB3 168582a1ea21SOliver O'Halloran * doesn't do that. So we have to selectively enable I/O 168682a1ea21SOliver O'Halloran * prior to collecting error log. 168782a1ea21SOliver O'Halloran */ 168882a1ea21SOliver O'Halloran list_for_each_entry(hose, &hose_list, list_node) { 168982a1ea21SOliver O'Halloran phb = hose->private_data; 169082a1ea21SOliver O'Halloran 169182a1ea21SOliver O'Halloran if (phb->model == PNV_PHB_MODEL_P7IOC) 169282a1ea21SOliver O'Halloran eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 169382a1ea21SOliver O'Halloran 169482a1ea21SOliver O'Halloran if (phb->diag_data_size > max_diag_size) 169582a1ea21SOliver O'Halloran max_diag_size = phb->diag_data_size; 169682a1ea21SOliver O'Halloran 169782a1ea21SOliver O'Halloran break; 169882a1ea21SOliver O'Halloran } 169982a1ea21SOliver O'Halloran 170082a1ea21SOliver O'Halloran /* 170182a1ea21SOliver O'Halloran * eeh_init() allocates the eeh_pe and its aux data buf so the 170282a1ea21SOliver O'Halloran * size needs to be set before calling eeh_init(). 170382a1ea21SOliver O'Halloran */ 170482a1ea21SOliver O'Halloran eeh_set_pe_aux_size(max_diag_size); 170582a1ea21SOliver O'Halloran ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device; 170682a1ea21SOliver O'Halloran 1707d125aedbSOliver O'Halloran ret = eeh_init(&pnv_eeh_ops); 170829310e5eSGavin Shan if (!ret) 170929310e5eSGavin Shan pr_info("EEH: PowerNV platform initialized\n"); 171029310e5eSGavin Shan else 171129310e5eSGavin Shan pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 171229310e5eSGavin Shan 171329310e5eSGavin Shan return ret; 171429310e5eSGavin Shan } 1715395ee2a2SOliver O'Halloran machine_arch_initcall(powernv, eeh_powernv_init); 1716