129310e5eSGavin Shan /* 229310e5eSGavin Shan * The file intends to implement the platform dependent EEH operations on 329310e5eSGavin Shan * powernv platform. Actually, the powernv was created in order to fully 429310e5eSGavin Shan * hypervisor support. 529310e5eSGavin Shan * 629310e5eSGavin Shan * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 729310e5eSGavin Shan * 829310e5eSGavin Shan * This program is free software; you can redistribute it and/or modify 929310e5eSGavin Shan * it under the terms of the GNU General Public License as published by 1029310e5eSGavin Shan * the Free Software Foundation; either version 2 of the License, or 1129310e5eSGavin Shan * (at your option) any later version. 1229310e5eSGavin Shan */ 1329310e5eSGavin Shan 1429310e5eSGavin Shan #include <linux/atomic.h> 154cf17445SGavin Shan #include <linux/debugfs.h> 1629310e5eSGavin Shan #include <linux/delay.h> 1729310e5eSGavin Shan #include <linux/export.h> 1829310e5eSGavin Shan #include <linux/init.h> 1979231448SAlistair Popple #include <linux/interrupt.h> 2029310e5eSGavin Shan #include <linux/list.h> 2129310e5eSGavin Shan #include <linux/msi.h> 2229310e5eSGavin Shan #include <linux/of.h> 2329310e5eSGavin Shan #include <linux/pci.h> 2429310e5eSGavin Shan #include <linux/proc_fs.h> 2529310e5eSGavin Shan #include <linux/rbtree.h> 2629310e5eSGavin Shan #include <linux/sched.h> 2729310e5eSGavin Shan #include <linux/seq_file.h> 2829310e5eSGavin Shan #include <linux/spinlock.h> 2929310e5eSGavin Shan 3029310e5eSGavin Shan #include <asm/eeh.h> 3129310e5eSGavin Shan #include <asm/eeh_event.h> 3229310e5eSGavin Shan #include <asm/firmware.h> 3329310e5eSGavin Shan #include <asm/io.h> 3429310e5eSGavin Shan #include <asm/iommu.h> 3529310e5eSGavin Shan #include <asm/machdep.h> 3629310e5eSGavin Shan #include <asm/msi_bitmap.h> 3729310e5eSGavin Shan #include <asm/opal.h> 3829310e5eSGavin Shan #include <asm/ppc-pci.h> 399c0e1ecbSGavin Shan #include <asm/pnv-pci.h> 4029310e5eSGavin Shan 4129310e5eSGavin Shan #include "powernv.h" 4229310e5eSGavin Shan #include "pci.h" 4329310e5eSGavin Shan 444cf17445SGavin Shan static bool pnv_eeh_nb_init = false; 4579231448SAlistair Popple static int eeh_event_irq = -EINVAL; 464cf17445SGavin Shan 4701f3bfb7SGavin Shan static int pnv_eeh_init(void) 4829310e5eSGavin Shan { 49dc561fb9SGavin Shan struct pci_controller *hose; 50dc561fb9SGavin Shan struct pnv_phb *phb; 51dc561fb9SGavin Shan 52e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 53e4d54f71SStewart Smith pr_warn("%s: OPAL is required !\n", 540dae2743SGavin Shan __func__); 5529310e5eSGavin Shan return -EINVAL; 5629310e5eSGavin Shan } 5729310e5eSGavin Shan 5805b1721dSGavin Shan /* Set probe mode */ 5905b1721dSGavin Shan eeh_add_flag(EEH_PROBE_MODE_DEV); 6029310e5eSGavin Shan 61dc561fb9SGavin Shan /* 62dc561fb9SGavin Shan * P7IOC blocks PCI config access to frozen PE, but PHB3 63dc561fb9SGavin Shan * doesn't do that. So we have to selectively enable I/O 64dc561fb9SGavin Shan * prior to collecting error log. 65dc561fb9SGavin Shan */ 66dc561fb9SGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 67dc561fb9SGavin Shan phb = hose->private_data; 68dc561fb9SGavin Shan 69dc561fb9SGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC) 70dc561fb9SGavin Shan eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 712aa5cf9eSGavin Shan 722aa5cf9eSGavin Shan /* 732aa5cf9eSGavin Shan * PE#0 should be regarded as valid by EEH core 742aa5cf9eSGavin Shan * if it's not the reserved one. Currently, we 75608fb9c2SGavin Shan * have the reserved PE#255 and PE#127 for PHB3 762aa5cf9eSGavin Shan * and P7IOC separately. So we should regard 77608fb9c2SGavin Shan * PE#0 as valid for PHB3 and P7IOC. 782aa5cf9eSGavin Shan */ 7992b8f137SGavin Shan if (phb->ioda.reserved_pe_idx != 0) 802aa5cf9eSGavin Shan eeh_add_flag(EEH_VALID_PE_ZERO); 812aa5cf9eSGavin Shan 82dc561fb9SGavin Shan break; 83dc561fb9SGavin Shan } 84dc561fb9SGavin Shan 8529310e5eSGavin Shan return 0; 8629310e5eSGavin Shan } 8729310e5eSGavin Shan 8879231448SAlistair Popple static irqreturn_t pnv_eeh_event(int irq, void *data) 894cf17445SGavin Shan { 904cf17445SGavin Shan /* 9179231448SAlistair Popple * We simply send a special EEH event if EEH has been 9279231448SAlistair Popple * enabled. We don't care about EEH events until we've 9379231448SAlistair Popple * finished processing the outstanding ones. Event processing 9479231448SAlistair Popple * gets unmasked in next_error() if EEH is enabled. 954cf17445SGavin Shan */ 9679231448SAlistair Popple disable_irq_nosync(irq); 974cf17445SGavin Shan 984cf17445SGavin Shan if (eeh_enabled()) 994cf17445SGavin Shan eeh_send_failure_event(NULL); 1004cf17445SGavin Shan 10179231448SAlistair Popple return IRQ_HANDLED; 1024cf17445SGavin Shan } 1034cf17445SGavin Shan 1044cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 1054cf17445SGavin Shan static ssize_t pnv_eeh_ei_write(struct file *filp, 1064cf17445SGavin Shan const char __user *user_buf, 1074cf17445SGavin Shan size_t count, loff_t *ppos) 1084cf17445SGavin Shan { 1094cf17445SGavin Shan struct pci_controller *hose = filp->private_data; 1104cf17445SGavin Shan struct eeh_dev *edev; 1114cf17445SGavin Shan struct eeh_pe *pe; 1124cf17445SGavin Shan int pe_no, type, func; 1134cf17445SGavin Shan unsigned long addr, mask; 1144cf17445SGavin Shan char buf[50]; 1154cf17445SGavin Shan int ret; 1164cf17445SGavin Shan 1174cf17445SGavin Shan if (!eeh_ops || !eeh_ops->err_inject) 1184cf17445SGavin Shan return -ENXIO; 1194cf17445SGavin Shan 1204cf17445SGavin Shan /* Copy over argument buffer */ 1214cf17445SGavin Shan ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 1224cf17445SGavin Shan if (!ret) 1234cf17445SGavin Shan return -EFAULT; 1244cf17445SGavin Shan 1254cf17445SGavin Shan /* Retrieve parameters */ 1264cf17445SGavin Shan ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 1274cf17445SGavin Shan &pe_no, &type, &func, &addr, &mask); 1284cf17445SGavin Shan if (ret != 5) 1294cf17445SGavin Shan return -EINVAL; 1304cf17445SGavin Shan 1314cf17445SGavin Shan /* Retrieve PE */ 1324cf17445SGavin Shan edev = kzalloc(sizeof(*edev), GFP_KERNEL); 1334cf17445SGavin Shan if (!edev) 1344cf17445SGavin Shan return -ENOMEM; 1354cf17445SGavin Shan edev->phb = hose; 1364cf17445SGavin Shan edev->pe_config_addr = pe_no; 1374cf17445SGavin Shan pe = eeh_pe_get(edev); 1384cf17445SGavin Shan kfree(edev); 1394cf17445SGavin Shan if (!pe) 1404cf17445SGavin Shan return -ENODEV; 1414cf17445SGavin Shan 1424cf17445SGavin Shan /* Do error injection */ 1434cf17445SGavin Shan ret = eeh_ops->err_inject(pe, type, func, addr, mask); 1444cf17445SGavin Shan return ret < 0 ? ret : count; 1454cf17445SGavin Shan } 1464cf17445SGavin Shan 1474cf17445SGavin Shan static const struct file_operations pnv_eeh_ei_fops = { 1484cf17445SGavin Shan .open = simple_open, 1494cf17445SGavin Shan .llseek = no_llseek, 1504cf17445SGavin Shan .write = pnv_eeh_ei_write, 1514cf17445SGavin Shan }; 1524cf17445SGavin Shan 1534cf17445SGavin Shan static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 1544cf17445SGavin Shan { 1554cf17445SGavin Shan struct pci_controller *hose = data; 1564cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1574cf17445SGavin Shan 1584cf17445SGavin Shan out_be64(phb->regs + offset, val); 1594cf17445SGavin Shan return 0; 1604cf17445SGavin Shan } 1614cf17445SGavin Shan 1624cf17445SGavin Shan static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 1634cf17445SGavin Shan { 1644cf17445SGavin Shan struct pci_controller *hose = data; 1654cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1664cf17445SGavin Shan 1674cf17445SGavin Shan *val = in_be64(phb->regs + offset); 1684cf17445SGavin Shan return 0; 1694cf17445SGavin Shan } 1704cf17445SGavin Shan 171ccc9662dSGavin Shan #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 172ccc9662dSGavin Shan static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 173ccc9662dSGavin Shan { \ 174ccc9662dSGavin Shan return pnv_eeh_dbgfs_set(data, reg, val); \ 175ccc9662dSGavin Shan } \ 176ccc9662dSGavin Shan \ 177ccc9662dSGavin Shan static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 178ccc9662dSGavin Shan { \ 179ccc9662dSGavin Shan return pnv_eeh_dbgfs_get(data, reg, val); \ 180ccc9662dSGavin Shan } \ 181ccc9662dSGavin Shan \ 182ccc9662dSGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 183ccc9662dSGavin Shan pnv_eeh_dbgfs_get_##name, \ 184ccc9662dSGavin Shan pnv_eeh_dbgfs_set_##name, \ 185ccc9662dSGavin Shan "0x%llx\n") 1864cf17445SGavin Shan 187ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 188ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 189ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 1904cf17445SGavin Shan 1914cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 1924cf17445SGavin Shan 19329310e5eSGavin Shan /** 19401f3bfb7SGavin Shan * pnv_eeh_post_init - EEH platform dependent post initialization 19529310e5eSGavin Shan * 19629310e5eSGavin Shan * EEH platform dependent post initialization on powernv. When 19729310e5eSGavin Shan * the function is called, the EEH PEs and devices should have 19829310e5eSGavin Shan * been built. If the I/O cache staff has been built, EEH is 19929310e5eSGavin Shan * ready to supply service. 20029310e5eSGavin Shan */ 20101f3bfb7SGavin Shan static int pnv_eeh_post_init(void) 20229310e5eSGavin Shan { 20329310e5eSGavin Shan struct pci_controller *hose; 20429310e5eSGavin Shan struct pnv_phb *phb; 20529310e5eSGavin Shan int ret = 0; 20629310e5eSGavin Shan 2074cf17445SGavin Shan /* Register OPAL event notifier */ 2084cf17445SGavin Shan if (!pnv_eeh_nb_init) { 20979231448SAlistair Popple eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 21079231448SAlistair Popple if (eeh_event_irq < 0) { 21179231448SAlistair Popple pr_err("%s: Can't register OPAL event interrupt (%d)\n", 21279231448SAlistair Popple __func__, eeh_event_irq); 21379231448SAlistair Popple return eeh_event_irq; 21479231448SAlistair Popple } 21579231448SAlistair Popple 21679231448SAlistair Popple ret = request_irq(eeh_event_irq, pnv_eeh_event, 21779231448SAlistair Popple IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 21879231448SAlistair Popple if (ret < 0) { 21979231448SAlistair Popple irq_dispose_mapping(eeh_event_irq); 22079231448SAlistair Popple pr_err("%s: Can't request OPAL event interrupt (%d)\n", 22179231448SAlistair Popple __func__, eeh_event_irq); 2224cf17445SGavin Shan return ret; 2234cf17445SGavin Shan } 2244cf17445SGavin Shan 2254cf17445SGavin Shan pnv_eeh_nb_init = true; 2264cf17445SGavin Shan } 2274cf17445SGavin Shan 22879231448SAlistair Popple if (!eeh_enabled()) 22979231448SAlistair Popple disable_irq(eeh_event_irq); 23079231448SAlistair Popple 23129310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 23229310e5eSGavin Shan phb = hose->private_data; 23329310e5eSGavin Shan 2344cf17445SGavin Shan /* 2354cf17445SGavin Shan * If EEH is enabled, we're going to rely on that. 2364cf17445SGavin Shan * Otherwise, we restore to conventional mechanism 2374cf17445SGavin Shan * to clear frozen PE during PCI config access. 2384cf17445SGavin Shan */ 2394cf17445SGavin Shan if (eeh_enabled()) 2404cf17445SGavin Shan phb->flags |= PNV_PHB_FLAG_EEH; 2414cf17445SGavin Shan else 2424cf17445SGavin Shan phb->flags &= ~PNV_PHB_FLAG_EEH; 2434cf17445SGavin Shan 2444cf17445SGavin Shan /* Create debugfs entries */ 2454cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 2464cf17445SGavin Shan if (phb->has_dbgfs || !phb->dbgfs) 2474cf17445SGavin Shan continue; 2484cf17445SGavin Shan 2494cf17445SGavin Shan phb->has_dbgfs = 1; 2504cf17445SGavin Shan debugfs_create_file("err_injct", 0200, 2514cf17445SGavin Shan phb->dbgfs, hose, 2524cf17445SGavin Shan &pnv_eeh_ei_fops); 2534cf17445SGavin Shan 2544cf17445SGavin Shan debugfs_create_file("err_injct_outbound", 0600, 2554cf17445SGavin Shan phb->dbgfs, hose, 256ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_outb); 2574cf17445SGavin Shan debugfs_create_file("err_injct_inboundA", 0600, 2584cf17445SGavin Shan phb->dbgfs, hose, 259ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbA); 2604cf17445SGavin Shan debugfs_create_file("err_injct_inboundB", 0600, 2614cf17445SGavin Shan phb->dbgfs, hose, 262ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbB); 2634cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 26429310e5eSGavin Shan } 2654cf17445SGavin Shan 26629310e5eSGavin Shan return ret; 26729310e5eSGavin Shan } 26829310e5eSGavin Shan 2694d6186caSGavin Shan static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 270ff57b454SGavin Shan { 2714d6186caSGavin Shan int pos = PCI_CAPABILITY_LIST; 2724d6186caSGavin Shan int cnt = 48; /* Maximal number of capabilities */ 2734d6186caSGavin Shan u32 status, id; 274ff57b454SGavin Shan 275ff57b454SGavin Shan if (!pdn) 276ff57b454SGavin Shan return 0; 277ff57b454SGavin Shan 2784d6186caSGavin Shan /* Check if the device supports capabilities */ 279ff57b454SGavin Shan pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 280ff57b454SGavin Shan if (!(status & PCI_STATUS_CAP_LIST)) 281ff57b454SGavin Shan return 0; 282ff57b454SGavin Shan 283ff57b454SGavin Shan while (cnt--) { 284ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos, 1, &pos); 285ff57b454SGavin Shan if (pos < 0x40) 286ff57b454SGavin Shan break; 287ff57b454SGavin Shan 288ff57b454SGavin Shan pos &= ~3; 289ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 290ff57b454SGavin Shan if (id == 0xff) 291ff57b454SGavin Shan break; 292ff57b454SGavin Shan 293ff57b454SGavin Shan /* Found */ 294ff57b454SGavin Shan if (id == cap) 295ff57b454SGavin Shan return pos; 296ff57b454SGavin Shan 297ff57b454SGavin Shan /* Next one */ 298ff57b454SGavin Shan pos += PCI_CAP_LIST_NEXT; 299ff57b454SGavin Shan } 300ff57b454SGavin Shan 301ff57b454SGavin Shan return 0; 302ff57b454SGavin Shan } 303ff57b454SGavin Shan 304ff57b454SGavin Shan static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 305ff57b454SGavin Shan { 306ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 307ff57b454SGavin Shan u32 header; 308ff57b454SGavin Shan int pos = 256, ttl = (4096 - 256) / 8; 309ff57b454SGavin Shan 310ff57b454SGavin Shan if (!edev || !edev->pcie_cap) 311ff57b454SGavin Shan return 0; 312ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 313ff57b454SGavin Shan return 0; 314ff57b454SGavin Shan else if (!header) 315ff57b454SGavin Shan return 0; 316ff57b454SGavin Shan 317ff57b454SGavin Shan while (ttl-- > 0) { 318ff57b454SGavin Shan if (PCI_EXT_CAP_ID(header) == cap && pos) 319ff57b454SGavin Shan return pos; 320ff57b454SGavin Shan 321ff57b454SGavin Shan pos = PCI_EXT_CAP_NEXT(header); 322ff57b454SGavin Shan if (pos < 256) 323ff57b454SGavin Shan break; 324ff57b454SGavin Shan 325ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 326ff57b454SGavin Shan break; 327ff57b454SGavin Shan } 328ff57b454SGavin Shan 329ff57b454SGavin Shan return 0; 330ff57b454SGavin Shan } 331ff57b454SGavin Shan 33229310e5eSGavin Shan /** 333ff57b454SGavin Shan * pnv_eeh_probe - Do probe on PCI device 334ff57b454SGavin Shan * @pdn: PCI device node 335ff57b454SGavin Shan * @data: unused 33629310e5eSGavin Shan * 33729310e5eSGavin Shan * When EEH module is installed during system boot, all PCI devices 33829310e5eSGavin Shan * are checked one by one to see if it supports EEH. The function 33929310e5eSGavin Shan * is introduced for the purpose. By default, EEH has been enabled 34029310e5eSGavin Shan * on all PCI devices. That's to say, we only need do necessary 34129310e5eSGavin Shan * initialization on the corresponding eeh device and create PE 34229310e5eSGavin Shan * accordingly. 34329310e5eSGavin Shan * 34429310e5eSGavin Shan * It's notable that's unsafe to retrieve the EEH device through 34529310e5eSGavin Shan * the corresponding PCI device. During the PCI device hotplug, which 34629310e5eSGavin Shan * was possiblly triggered by EEH core, the binding between EEH device 34729310e5eSGavin Shan * and the PCI device isn't built yet. 34829310e5eSGavin Shan */ 349ff57b454SGavin Shan static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 35029310e5eSGavin Shan { 351ff57b454SGavin Shan struct pci_controller *hose = pdn->phb; 35229310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 353ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 354ff57b454SGavin Shan uint32_t pcie_flags; 355dadcd6d6SMike Qiu int ret; 35629310e5eSGavin Shan 35729310e5eSGavin Shan /* 35829310e5eSGavin Shan * When probing the root bridge, which doesn't have any 35929310e5eSGavin Shan * subordinate PCI devices. We don't have OF node for 36029310e5eSGavin Shan * the root bridge. So it's not reasonable to continue 36129310e5eSGavin Shan * the probing. 36229310e5eSGavin Shan */ 363ff57b454SGavin Shan if (!edev || edev->pe) 364ff57b454SGavin Shan return NULL; 36529310e5eSGavin Shan 36629310e5eSGavin Shan /* Skip for PCI-ISA bridge */ 367ff57b454SGavin Shan if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 368ff57b454SGavin Shan return NULL; 36929310e5eSGavin Shan 37029310e5eSGavin Shan /* Initialize eeh device */ 371ff57b454SGavin Shan edev->class_code = pdn->class_code; 372ab55d218SGavin Shan edev->mode &= 0xFFFFFF00; 373ff57b454SGavin Shan edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 374ff57b454SGavin Shan edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 3759312bc5bSWei Yang edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 376ff57b454SGavin Shan edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 377ff57b454SGavin Shan if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 3784b83bd45SGavin Shan edev->mode |= EEH_DEV_BRIDGE; 379ff57b454SGavin Shan if (edev->pcie_cap) { 380ff57b454SGavin Shan pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 381ff57b454SGavin Shan 2, &pcie_flags); 382ff57b454SGavin Shan pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 383ff57b454SGavin Shan if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 3844b83bd45SGavin Shan edev->mode |= EEH_DEV_ROOT_PORT; 385ff57b454SGavin Shan else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 3864b83bd45SGavin Shan edev->mode |= EEH_DEV_DS_PORT; 387ff57b454SGavin Shan } 3884b83bd45SGavin Shan } 3894b83bd45SGavin Shan 390ff57b454SGavin Shan edev->config_addr = (pdn->busno << 8) | (pdn->devfn); 391ff57b454SGavin Shan edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr]; 39229310e5eSGavin Shan 39329310e5eSGavin Shan /* Create PE */ 394dadcd6d6SMike Qiu ret = eeh_add_to_parent_pe(edev); 395dadcd6d6SMike Qiu if (ret) { 3961f52f176SRussell Currey pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n", 397ff57b454SGavin Shan __func__, hose->global_number, pdn->busno, 398ff57b454SGavin Shan PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 399ff57b454SGavin Shan return NULL; 400dadcd6d6SMike Qiu } 401dadcd6d6SMike Qiu 402dadcd6d6SMike Qiu /* 403b6541db1SGavin Shan * If the PE contains any one of following adapters, the 404b6541db1SGavin Shan * PCI config space can't be accessed when dumping EEH log. 405b6541db1SGavin Shan * Otherwise, we will run into fenced PHB caused by shortage 406b6541db1SGavin Shan * of outbound credits in the adapter. The PCI config access 407b6541db1SGavin Shan * should be blocked until PE reset. MMIO access is dropped 408b6541db1SGavin Shan * by hardware certainly. In order to drop PCI config requests, 409b6541db1SGavin Shan * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 410b6541db1SGavin Shan * will be checked in the backend for PE state retrival. If 411b6541db1SGavin Shan * the PE becomes frozen for the first time and the flag has 412b6541db1SGavin Shan * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 413b6541db1SGavin Shan * that PE to block its config space. 414b6541db1SGavin Shan * 415c374ed27SGavin Shan * Broadcom BCM5718 2-ports NICs (14e4:1656) 416b6541db1SGavin Shan * Broadcom Austin 4-ports NICs (14e4:1657) 417353169acSGavin Shan * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 418179ea48bSGavin Shan * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 419b6541db1SGavin Shan */ 420ff57b454SGavin Shan if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 421c374ed27SGavin Shan pdn->device_id == 0x1656) || 422c374ed27SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 423ff57b454SGavin Shan pdn->device_id == 0x1657) || 424ff57b454SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 425353169acSGavin Shan pdn->device_id == 0x168a) || 426353169acSGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 427ff57b454SGavin Shan pdn->device_id == 0x168e)) 428b6541db1SGavin Shan edev->pe->state |= EEH_PE_CFG_RESTRICTED; 429b6541db1SGavin Shan 430b6541db1SGavin Shan /* 431dadcd6d6SMike Qiu * Cache the PE primary bus, which can't be fetched when 432dadcd6d6SMike Qiu * full hotplug is in progress. In that case, all child 433dadcd6d6SMike Qiu * PCI devices of the PE are expected to be removed prior 434dadcd6d6SMike Qiu * to PE reset. 435dadcd6d6SMike Qiu */ 43605ba75f8SGavin Shan if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 437ff57b454SGavin Shan edev->pe->bus = pci_find_bus(hose->global_number, 438ff57b454SGavin Shan pdn->busno); 43905ba75f8SGavin Shan if (edev->pe->bus) 44005ba75f8SGavin Shan edev->pe->state |= EEH_PE_PRI_BUS; 44105ba75f8SGavin Shan } 44229310e5eSGavin Shan 44329310e5eSGavin Shan /* 44429310e5eSGavin Shan * Enable EEH explicitly so that we will do EEH check 44529310e5eSGavin Shan * while accessing I/O stuff 44629310e5eSGavin Shan */ 44705b1721dSGavin Shan eeh_add_flag(EEH_ENABLED); 44829310e5eSGavin Shan 44929310e5eSGavin Shan /* Save memory bars */ 45029310e5eSGavin Shan eeh_save_bars(edev); 45129310e5eSGavin Shan 452ff57b454SGavin Shan return NULL; 45329310e5eSGavin Shan } 45429310e5eSGavin Shan 45529310e5eSGavin Shan /** 45601f3bfb7SGavin Shan * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 45729310e5eSGavin Shan * @pe: EEH PE 45829310e5eSGavin Shan * @option: operation to be issued 45929310e5eSGavin Shan * 46029310e5eSGavin Shan * The function is used to control the EEH functionality globally. 46129310e5eSGavin Shan * Currently, following options are support according to PAPR: 46229310e5eSGavin Shan * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 46329310e5eSGavin Shan */ 46401f3bfb7SGavin Shan static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 46529310e5eSGavin Shan { 46629310e5eSGavin Shan struct pci_controller *hose = pe->phb; 46729310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 4687e3e4f8dSGavin Shan bool freeze_pe = false; 469f9433718SGavin Shan int opt; 4707e3e4f8dSGavin Shan s64 rc; 47129310e5eSGavin Shan 4727e3e4f8dSGavin Shan switch (option) { 4737e3e4f8dSGavin Shan case EEH_OPT_DISABLE: 4747e3e4f8dSGavin Shan return -EPERM; 4757e3e4f8dSGavin Shan case EEH_OPT_ENABLE: 4767e3e4f8dSGavin Shan return 0; 4777e3e4f8dSGavin Shan case EEH_OPT_THAW_MMIO: 4787e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 4797e3e4f8dSGavin Shan break; 4807e3e4f8dSGavin Shan case EEH_OPT_THAW_DMA: 4817e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 4827e3e4f8dSGavin Shan break; 4837e3e4f8dSGavin Shan case EEH_OPT_FREEZE_PE: 4847e3e4f8dSGavin Shan freeze_pe = true; 4857e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 4867e3e4f8dSGavin Shan break; 4877e3e4f8dSGavin Shan default: 4887e3e4f8dSGavin Shan pr_warn("%s: Invalid option %d\n", __func__, option); 4897e3e4f8dSGavin Shan return -EINVAL; 4907e3e4f8dSGavin Shan } 4917e3e4f8dSGavin Shan 492f9433718SGavin Shan /* Freeze master and slave PEs if PHB supports compound PEs */ 4937e3e4f8dSGavin Shan if (freeze_pe) { 4947e3e4f8dSGavin Shan if (phb->freeze_pe) { 4957e3e4f8dSGavin Shan phb->freeze_pe(phb, pe->addr); 496f9433718SGavin Shan return 0; 4977e3e4f8dSGavin Shan } 49829310e5eSGavin Shan 499f9433718SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 500f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 501f9433718SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 502f9433718SGavin Shan __func__, rc, phb->hose->global_number, 503f9433718SGavin Shan pe->addr); 504f9433718SGavin Shan return -EIO; 505f9433718SGavin Shan } 506f9433718SGavin Shan 507f9433718SGavin Shan return 0; 508f9433718SGavin Shan } 509f9433718SGavin Shan 510f9433718SGavin Shan /* Unfreeze master and slave PEs if PHB supports */ 511f9433718SGavin Shan if (phb->unfreeze_pe) 512f9433718SGavin Shan return phb->unfreeze_pe(phb, pe->addr, opt); 513f9433718SGavin Shan 514f9433718SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 515f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 516f9433718SGavin Shan pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 517f9433718SGavin Shan __func__, rc, option, phb->hose->global_number, 518f9433718SGavin Shan pe->addr); 519f9433718SGavin Shan return -EIO; 520f9433718SGavin Shan } 521f9433718SGavin Shan 522f9433718SGavin Shan return 0; 52329310e5eSGavin Shan } 52429310e5eSGavin Shan 52529310e5eSGavin Shan /** 52601f3bfb7SGavin Shan * pnv_eeh_get_pe_addr - Retrieve PE address 52729310e5eSGavin Shan * @pe: EEH PE 52829310e5eSGavin Shan * 52929310e5eSGavin Shan * Retrieve the PE address according to the given tranditional 53029310e5eSGavin Shan * PCI BDF (Bus/Device/Function) address. 53129310e5eSGavin Shan */ 53201f3bfb7SGavin Shan static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 53329310e5eSGavin Shan { 53429310e5eSGavin Shan return pe->addr; 53529310e5eSGavin Shan } 53629310e5eSGavin Shan 53740ae5f69SGavin Shan static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 53840ae5f69SGavin Shan { 53940ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 54040ae5f69SGavin Shan s64 rc; 54140ae5f69SGavin Shan 54240ae5f69SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 54340ae5f69SGavin Shan PNV_PCI_DIAG_BUF_SIZE); 54440ae5f69SGavin Shan if (rc != OPAL_SUCCESS) 54540ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 54640ae5f69SGavin Shan __func__, rc, pe->phb->global_number); 54740ae5f69SGavin Shan } 54840ae5f69SGavin Shan 54940ae5f69SGavin Shan static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 55040ae5f69SGavin Shan { 55140ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 55240ae5f69SGavin Shan u8 fstate; 55340ae5f69SGavin Shan __be16 pcierr; 55440ae5f69SGavin Shan s64 rc; 55540ae5f69SGavin Shan int result = 0; 55640ae5f69SGavin Shan 55740ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 55840ae5f69SGavin Shan pe->addr, 55940ae5f69SGavin Shan &fstate, 56040ae5f69SGavin Shan &pcierr, 56140ae5f69SGavin Shan NULL); 56240ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 56340ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x state\n", 56440ae5f69SGavin Shan __func__, rc, phb->hose->global_number); 56540ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 56640ae5f69SGavin Shan } 56740ae5f69SGavin Shan 56840ae5f69SGavin Shan /* 56940ae5f69SGavin Shan * Check PHB state. If the PHB is frozen for the 57040ae5f69SGavin Shan * first time, to dump the PHB diag-data. 57140ae5f69SGavin Shan */ 57240ae5f69SGavin Shan if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 57340ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 57440ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 57540ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 57640ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 57740ae5f69SGavin Shan } else if (!(pe->state & EEH_PE_ISOLATED)) { 57840ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 57940ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 58040ae5f69SGavin Shan 58140ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 58240ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 58340ae5f69SGavin Shan } 58440ae5f69SGavin Shan 58540ae5f69SGavin Shan return result; 58640ae5f69SGavin Shan } 58740ae5f69SGavin Shan 58840ae5f69SGavin Shan static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 58940ae5f69SGavin Shan { 59040ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 59140ae5f69SGavin Shan u8 fstate; 59240ae5f69SGavin Shan __be16 pcierr; 59340ae5f69SGavin Shan s64 rc; 59440ae5f69SGavin Shan int result; 59540ae5f69SGavin Shan 59640ae5f69SGavin Shan /* 59740ae5f69SGavin Shan * We don't clobber hardware frozen state until PE 59840ae5f69SGavin Shan * reset is completed. In order to keep EEH core 59940ae5f69SGavin Shan * moving forward, we have to return operational 60040ae5f69SGavin Shan * state during PE reset. 60140ae5f69SGavin Shan */ 60240ae5f69SGavin Shan if (pe->state & EEH_PE_RESET) { 60340ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 60440ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 60540ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 60640ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 60740ae5f69SGavin Shan return result; 60840ae5f69SGavin Shan } 60940ae5f69SGavin Shan 61040ae5f69SGavin Shan /* 61140ae5f69SGavin Shan * Fetch PE state from hardware. If the PHB 61240ae5f69SGavin Shan * supports compound PE, let it handle that. 61340ae5f69SGavin Shan */ 61440ae5f69SGavin Shan if (phb->get_pe_state) { 61540ae5f69SGavin Shan fstate = phb->get_pe_state(phb, pe->addr); 61640ae5f69SGavin Shan } else { 61740ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 61840ae5f69SGavin Shan pe->addr, 61940ae5f69SGavin Shan &fstate, 62040ae5f69SGavin Shan &pcierr, 62140ae5f69SGavin Shan NULL); 62240ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 62340ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 62440ae5f69SGavin Shan __func__, rc, phb->hose->global_number, 62540ae5f69SGavin Shan pe->addr); 62640ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 62740ae5f69SGavin Shan } 62840ae5f69SGavin Shan } 62940ae5f69SGavin Shan 63040ae5f69SGavin Shan /* Figure out state */ 63140ae5f69SGavin Shan switch (fstate) { 63240ae5f69SGavin Shan case OPAL_EEH_STOPPED_NOT_FROZEN: 63340ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 63440ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 63540ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 63640ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 63740ae5f69SGavin Shan break; 63840ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_FREEZE: 63940ae5f69SGavin Shan result = (EEH_STATE_DMA_ACTIVE | 64040ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 64140ae5f69SGavin Shan break; 64240ae5f69SGavin Shan case OPAL_EEH_STOPPED_DMA_FREEZE: 64340ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 64440ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED); 64540ae5f69SGavin Shan break; 64640ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 64740ae5f69SGavin Shan result = 0; 64840ae5f69SGavin Shan break; 64940ae5f69SGavin Shan case OPAL_EEH_STOPPED_RESET: 65040ae5f69SGavin Shan result = EEH_STATE_RESET_ACTIVE; 65140ae5f69SGavin Shan break; 65240ae5f69SGavin Shan case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 65340ae5f69SGavin Shan result = EEH_STATE_UNAVAILABLE; 65440ae5f69SGavin Shan break; 65540ae5f69SGavin Shan case OPAL_EEH_STOPPED_PERM_UNAVAIL: 65640ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 65740ae5f69SGavin Shan break; 65840ae5f69SGavin Shan default: 65940ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 66040ae5f69SGavin Shan pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 66140ae5f69SGavin Shan __func__, phb->hose->global_number, 66240ae5f69SGavin Shan pe->addr, fstate); 66340ae5f69SGavin Shan } 66440ae5f69SGavin Shan 66540ae5f69SGavin Shan /* 66640ae5f69SGavin Shan * If PHB supports compound PE, to freeze all 66740ae5f69SGavin Shan * slave PEs for consistency. 66840ae5f69SGavin Shan * 66940ae5f69SGavin Shan * If the PE is switching to frozen state for the 67040ae5f69SGavin Shan * first time, to dump the PHB diag-data. 67140ae5f69SGavin Shan */ 67240ae5f69SGavin Shan if (!(result & EEH_STATE_NOT_SUPPORT) && 67340ae5f69SGavin Shan !(result & EEH_STATE_UNAVAILABLE) && 67440ae5f69SGavin Shan !(result & EEH_STATE_MMIO_ACTIVE) && 67540ae5f69SGavin Shan !(result & EEH_STATE_DMA_ACTIVE) && 67640ae5f69SGavin Shan !(pe->state & EEH_PE_ISOLATED)) { 67740ae5f69SGavin Shan if (phb->freeze_pe) 67840ae5f69SGavin Shan phb->freeze_pe(phb, pe->addr); 67940ae5f69SGavin Shan 68040ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 68140ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 68240ae5f69SGavin Shan 68340ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 68440ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 68540ae5f69SGavin Shan } 68640ae5f69SGavin Shan 68740ae5f69SGavin Shan return result; 68840ae5f69SGavin Shan } 68940ae5f69SGavin Shan 69029310e5eSGavin Shan /** 69101f3bfb7SGavin Shan * pnv_eeh_get_state - Retrieve PE state 69229310e5eSGavin Shan * @pe: EEH PE 69329310e5eSGavin Shan * @delay: delay while PE state is temporarily unavailable 69429310e5eSGavin Shan * 69529310e5eSGavin Shan * Retrieve the state of the specified PE. For IODA-compitable 69629310e5eSGavin Shan * platform, it should be retrieved from IODA table. Therefore, 69729310e5eSGavin Shan * we prefer passing down to hardware implementation to handle 69829310e5eSGavin Shan * it. 69929310e5eSGavin Shan */ 70001f3bfb7SGavin Shan static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 70129310e5eSGavin Shan { 70240ae5f69SGavin Shan int ret; 70329310e5eSGavin Shan 70440ae5f69SGavin Shan if (pe->type & EEH_PE_PHB) 70540ae5f69SGavin Shan ret = pnv_eeh_get_phb_state(pe); 70640ae5f69SGavin Shan else 70740ae5f69SGavin Shan ret = pnv_eeh_get_pe_state(pe); 70840ae5f69SGavin Shan 70940ae5f69SGavin Shan if (!delay) 71040ae5f69SGavin Shan return ret; 71129310e5eSGavin Shan 71229310e5eSGavin Shan /* 71329310e5eSGavin Shan * If the PE state is temporarily unavailable, 71429310e5eSGavin Shan * to inform the EEH core delay for default 71529310e5eSGavin Shan * period (1 second) 71629310e5eSGavin Shan */ 71729310e5eSGavin Shan *delay = 0; 71829310e5eSGavin Shan if (ret & EEH_STATE_UNAVAILABLE) 71929310e5eSGavin Shan *delay = 1000; 72029310e5eSGavin Shan 72129310e5eSGavin Shan return ret; 72229310e5eSGavin Shan } 72329310e5eSGavin Shan 724ebe22531SGavin Shan static s64 pnv_eeh_poll(unsigned long id) 725cadf364dSGavin Shan { 726cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 727cadf364dSGavin Shan 728cadf364dSGavin Shan while (1) { 729ebe22531SGavin Shan rc = opal_pci_poll(id); 730cadf364dSGavin Shan if (rc <= 0) 731cadf364dSGavin Shan break; 732cadf364dSGavin Shan 733cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 734cadf364dSGavin Shan udelay(1000 * rc); 735cadf364dSGavin Shan else 736cadf364dSGavin Shan msleep(rc); 737cadf364dSGavin Shan } 738cadf364dSGavin Shan 739cadf364dSGavin Shan return rc; 740cadf364dSGavin Shan } 741cadf364dSGavin Shan 742cadf364dSGavin Shan int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 743cadf364dSGavin Shan { 744cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 745cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 746cadf364dSGavin Shan 747cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 748cadf364dSGavin Shan __func__, hose->global_number, option); 749cadf364dSGavin Shan 750cadf364dSGavin Shan /* Issue PHB complete reset request */ 751cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL || 752cadf364dSGavin Shan option == EEH_RESET_HOT) 753cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 754cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 755cadf364dSGavin Shan OPAL_ASSERT_RESET); 756cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 757cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 758cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 759cadf364dSGavin Shan OPAL_DEASSERT_RESET); 760cadf364dSGavin Shan if (rc < 0) 761cadf364dSGavin Shan goto out; 762cadf364dSGavin Shan 763cadf364dSGavin Shan /* 764cadf364dSGavin Shan * Poll state of the PHB until the request is done 765cadf364dSGavin Shan * successfully. The PHB reset is usually PHB complete 766cadf364dSGavin Shan * reset followed by hot reset on root bus. So we also 767cadf364dSGavin Shan * need the PCI bus settlement delay. 768cadf364dSGavin Shan */ 769fbce44d0SGavin Shan if (rc > 0) 770ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 771cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) { 772cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 773cadf364dSGavin Shan udelay(1000 * EEH_PE_RST_SETTLE_TIME); 774cadf364dSGavin Shan else 775cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 776cadf364dSGavin Shan } 777cadf364dSGavin Shan out: 778cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 779cadf364dSGavin Shan return -EIO; 780cadf364dSGavin Shan 781cadf364dSGavin Shan return 0; 782cadf364dSGavin Shan } 783cadf364dSGavin Shan 784cadf364dSGavin Shan static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 785cadf364dSGavin Shan { 786cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 787cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 788cadf364dSGavin Shan 789cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 790cadf364dSGavin Shan __func__, hose->global_number, option); 791cadf364dSGavin Shan 792cadf364dSGavin Shan /* 793cadf364dSGavin Shan * During the reset deassert time, we needn't care 794cadf364dSGavin Shan * the reset scope because the firmware does nothing 795cadf364dSGavin Shan * for fundamental or hot reset during deassert phase. 796cadf364dSGavin Shan */ 797cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL) 798cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 799cadf364dSGavin Shan OPAL_RESET_PCI_FUNDAMENTAL, 800cadf364dSGavin Shan OPAL_ASSERT_RESET); 801cadf364dSGavin Shan else if (option == EEH_RESET_HOT) 802cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 803cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 804cadf364dSGavin Shan OPAL_ASSERT_RESET); 805cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 806cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 807cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 808cadf364dSGavin Shan OPAL_DEASSERT_RESET); 809cadf364dSGavin Shan if (rc < 0) 810cadf364dSGavin Shan goto out; 811cadf364dSGavin Shan 812cadf364dSGavin Shan /* Poll state of the PHB until the request is done */ 813fbce44d0SGavin Shan if (rc > 0) 814ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 815cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) 816cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 817cadf364dSGavin Shan out: 818cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 819cadf364dSGavin Shan return -EIO; 820cadf364dSGavin Shan 821cadf364dSGavin Shan return 0; 822cadf364dSGavin Shan } 823cadf364dSGavin Shan 8249c0e1ecbSGavin Shan static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 825cadf364dSGavin Shan { 8260bd78587SGavin Shan struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 8270bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 828cadf364dSGavin Shan int aer = edev ? edev->aer_cap : 0; 829cadf364dSGavin Shan u32 ctrl; 830cadf364dSGavin Shan 831cadf364dSGavin Shan pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 832cadf364dSGavin Shan __func__, pci_domain_nr(dev->bus), 833cadf364dSGavin Shan dev->bus->number, option); 834cadf364dSGavin Shan 835cadf364dSGavin Shan switch (option) { 836cadf364dSGavin Shan case EEH_RESET_FUNDAMENTAL: 837cadf364dSGavin Shan case EEH_RESET_HOT: 838cadf364dSGavin Shan /* Don't report linkDown event */ 839cadf364dSGavin Shan if (aer) { 8400bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 841cadf364dSGavin Shan 4, &ctrl); 842cadf364dSGavin Shan ctrl |= PCI_ERR_UNC_SURPDN; 8430bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 844cadf364dSGavin Shan 4, ctrl); 845cadf364dSGavin Shan } 846cadf364dSGavin Shan 8470bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 848cadf364dSGavin Shan ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 8490bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 850cadf364dSGavin Shan 851cadf364dSGavin Shan msleep(EEH_PE_RST_HOLD_TIME); 852cadf364dSGavin Shan break; 853cadf364dSGavin Shan case EEH_RESET_DEACTIVATE: 8540bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 855cadf364dSGavin Shan ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 8560bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 857cadf364dSGavin Shan 858cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 859cadf364dSGavin Shan 860cadf364dSGavin Shan /* Continue reporting linkDown event */ 861cadf364dSGavin Shan if (aer) { 8620bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 863cadf364dSGavin Shan 4, &ctrl); 864cadf364dSGavin Shan ctrl &= ~PCI_ERR_UNC_SURPDN; 8650bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 866cadf364dSGavin Shan 4, ctrl); 867cadf364dSGavin Shan } 868cadf364dSGavin Shan 869cadf364dSGavin Shan break; 870cadf364dSGavin Shan } 871cadf364dSGavin Shan 872cadf364dSGavin Shan return 0; 873cadf364dSGavin Shan } 874cadf364dSGavin Shan 8759c0e1ecbSGavin Shan static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 8769c0e1ecbSGavin Shan { 8779c0e1ecbSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 8789c0e1ecbSGavin Shan struct pnv_phb *phb = hose->private_data; 8799c0e1ecbSGavin Shan struct device_node *dn = pci_device_to_OF_node(pdev); 8809c0e1ecbSGavin Shan uint64_t id = PCI_SLOT_ID(phb->opal_id, 8819c0e1ecbSGavin Shan (pdev->bus->number << 8) | pdev->devfn); 8829c0e1ecbSGavin Shan uint8_t scope; 8839c0e1ecbSGavin Shan int64_t rc; 8849c0e1ecbSGavin Shan 8859c0e1ecbSGavin Shan /* Hot reset to the bus if firmware cannot handle */ 8869c0e1ecbSGavin Shan if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 8879c0e1ecbSGavin Shan return __pnv_eeh_bridge_reset(pdev, option); 8889c0e1ecbSGavin Shan 8899c0e1ecbSGavin Shan switch (option) { 8909c0e1ecbSGavin Shan case EEH_RESET_FUNDAMENTAL: 8919c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_FUNDAMENTAL; 8929c0e1ecbSGavin Shan break; 8939c0e1ecbSGavin Shan case EEH_RESET_HOT: 8949c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_HOT; 8959c0e1ecbSGavin Shan break; 8969c0e1ecbSGavin Shan case EEH_RESET_DEACTIVATE: 8979c0e1ecbSGavin Shan return 0; 8989c0e1ecbSGavin Shan default: 8999c0e1ecbSGavin Shan dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 9009c0e1ecbSGavin Shan __func__, option); 9019c0e1ecbSGavin Shan return -EINVAL; 9029c0e1ecbSGavin Shan } 9039c0e1ecbSGavin Shan 9049c0e1ecbSGavin Shan rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 9059c0e1ecbSGavin Shan if (rc <= OPAL_SUCCESS) 9069c0e1ecbSGavin Shan goto out; 9079c0e1ecbSGavin Shan 9089c0e1ecbSGavin Shan rc = pnv_eeh_poll(id); 9099c0e1ecbSGavin Shan out: 9109c0e1ecbSGavin Shan return (rc == OPAL_SUCCESS) ? 0 : -EIO; 9119c0e1ecbSGavin Shan } 9129c0e1ecbSGavin Shan 913cadf364dSGavin Shan void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 914cadf364dSGavin Shan { 915848912e5SMichael Ellerman struct pci_controller *hose; 916848912e5SMichael Ellerman 917848912e5SMichael Ellerman if (pci_is_root_bus(dev->bus)) { 918848912e5SMichael Ellerman hose = pci_bus_to_host(dev->bus); 919848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_HOT); 920848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 921848912e5SMichael Ellerman } else { 922cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 923cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 924cadf364dSGavin Shan } 925848912e5SMichael Ellerman } 926cadf364dSGavin Shan 9279312bc5bSWei Yang static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 9289312bc5bSWei Yang int pos, u16 mask) 9299312bc5bSWei Yang { 9309312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9319312bc5bSWei Yang int i, status = 0; 9329312bc5bSWei Yang 9339312bc5bSWei Yang /* Wait for Transaction Pending bit to be cleared */ 9349312bc5bSWei Yang for (i = 0; i < 4; i++) { 9359312bc5bSWei Yang eeh_ops->read_config(pdn, pos, 2, &status); 9369312bc5bSWei Yang if (!(status & mask)) 9379312bc5bSWei Yang return; 9389312bc5bSWei Yang 9399312bc5bSWei Yang msleep((1 << i) * 100); 9409312bc5bSWei Yang } 9419312bc5bSWei Yang 9429312bc5bSWei Yang pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 9439312bc5bSWei Yang __func__, type, 9449312bc5bSWei Yang edev->phb->global_number, pdn->busno, 9459312bc5bSWei Yang PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 9469312bc5bSWei Yang } 9479312bc5bSWei Yang 9489312bc5bSWei Yang static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 9499312bc5bSWei Yang { 9509312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9519312bc5bSWei Yang u32 reg = 0; 9529312bc5bSWei Yang 9539312bc5bSWei Yang if (WARN_ON(!edev->pcie_cap)) 9549312bc5bSWei Yang return -ENOTTY; 9559312bc5bSWei Yang 9569312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 9579312bc5bSWei Yang if (!(reg & PCI_EXP_DEVCAP_FLR)) 9589312bc5bSWei Yang return -ENOTTY; 9599312bc5bSWei Yang 9609312bc5bSWei Yang switch (option) { 9619312bc5bSWei Yang case EEH_RESET_HOT: 9629312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 9639312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "", 9649312bc5bSWei Yang edev->pcie_cap + PCI_EXP_DEVSTA, 9659312bc5bSWei Yang PCI_EXP_DEVSTA_TRPND); 9669312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9679312bc5bSWei Yang 4, ®); 9689312bc5bSWei Yang reg |= PCI_EXP_DEVCTL_BCR_FLR; 9699312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9709312bc5bSWei Yang 4, reg); 9719312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 9729312bc5bSWei Yang break; 9739312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 9749312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9759312bc5bSWei Yang 4, ®); 9769312bc5bSWei Yang reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 9779312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9789312bc5bSWei Yang 4, reg); 9799312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 9809312bc5bSWei Yang break; 9819312bc5bSWei Yang } 9829312bc5bSWei Yang 9839312bc5bSWei Yang return 0; 9849312bc5bSWei Yang } 9859312bc5bSWei Yang 9869312bc5bSWei Yang static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 9879312bc5bSWei Yang { 9889312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9899312bc5bSWei Yang u32 cap = 0; 9909312bc5bSWei Yang 9919312bc5bSWei Yang if (WARN_ON(!edev->af_cap)) 9929312bc5bSWei Yang return -ENOTTY; 9939312bc5bSWei Yang 9949312bc5bSWei Yang eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 9959312bc5bSWei Yang if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 9969312bc5bSWei Yang return -ENOTTY; 9979312bc5bSWei Yang 9989312bc5bSWei Yang switch (option) { 9999312bc5bSWei Yang case EEH_RESET_HOT: 10009312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 10019312bc5bSWei Yang /* 10029312bc5bSWei Yang * Wait for Transaction Pending bit to clear. A word-aligned 10039312bc5bSWei Yang * test is used, so we use the conrol offset rather than status 10049312bc5bSWei Yang * and shift the test bit to match. 10059312bc5bSWei Yang */ 10069312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "AF", 10079312bc5bSWei Yang edev->af_cap + PCI_AF_CTRL, 10089312bc5bSWei Yang PCI_AF_STATUS_TP << 8); 10099312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 10109312bc5bSWei Yang 1, PCI_AF_CTRL_FLR); 10119312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 10129312bc5bSWei Yang break; 10139312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 10149312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 10159312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 10169312bc5bSWei Yang break; 10179312bc5bSWei Yang } 10189312bc5bSWei Yang 10199312bc5bSWei Yang return 0; 10209312bc5bSWei Yang } 10219312bc5bSWei Yang 10229312bc5bSWei Yang static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 10239312bc5bSWei Yang { 10249312bc5bSWei Yang struct eeh_dev *edev; 10259312bc5bSWei Yang struct pci_dn *pdn; 10269312bc5bSWei Yang int ret; 10279312bc5bSWei Yang 10289312bc5bSWei Yang /* The VF PE should have only one child device */ 10299312bc5bSWei Yang edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list); 10309312bc5bSWei Yang pdn = eeh_dev_to_pdn(edev); 10319312bc5bSWei Yang if (!pdn) 10329312bc5bSWei Yang return -ENXIO; 10339312bc5bSWei Yang 10349312bc5bSWei Yang ret = pnv_eeh_do_flr(pdn, option); 10359312bc5bSWei Yang if (!ret) 10369312bc5bSWei Yang return ret; 10379312bc5bSWei Yang 10389312bc5bSWei Yang return pnv_eeh_do_af_flr(pdn, option); 10399312bc5bSWei Yang } 10409312bc5bSWei Yang 104129310e5eSGavin Shan /** 104201f3bfb7SGavin Shan * pnv_eeh_reset - Reset the specified PE 104329310e5eSGavin Shan * @pe: EEH PE 104429310e5eSGavin Shan * @option: reset option 104529310e5eSGavin Shan * 1046cadf364dSGavin Shan * Do reset on the indicated PE. For PCI bus sensitive PE, 1047cadf364dSGavin Shan * we need to reset the parent p2p bridge. The PHB has to 1048cadf364dSGavin Shan * be reinitialized if the p2p bridge is root bridge. For 1049cadf364dSGavin Shan * PCI device sensitive PE, we will try to reset the device 1050cadf364dSGavin Shan * through FLR. For now, we don't have OPAL APIs to do HARD 1051cadf364dSGavin Shan * reset yet, so all reset would be SOFT (HOT) reset. 105229310e5eSGavin Shan */ 105301f3bfb7SGavin Shan static int pnv_eeh_reset(struct eeh_pe *pe, int option) 105429310e5eSGavin Shan { 105529310e5eSGavin Shan struct pci_controller *hose = pe->phb; 10564fad4943SGavin Shan struct pnv_phb *phb; 1057cadf364dSGavin Shan struct pci_bus *bus; 10584fad4943SGavin Shan int64_t rc; 105929310e5eSGavin Shan 1060cadf364dSGavin Shan /* 1061cadf364dSGavin Shan * For PHB reset, we always have complete reset. For those PEs whose 1062cadf364dSGavin Shan * primary bus derived from root complex (root bus) or root port 1063cadf364dSGavin Shan * (usually bus#1), we apply hot or fundamental reset on the root port. 1064cadf364dSGavin Shan * For other PEs, we always have hot reset on the PE primary bus. 1065cadf364dSGavin Shan * 1066cadf364dSGavin Shan * Here, we have different design to pHyp, which always clear the 1067cadf364dSGavin Shan * frozen state during PE reset. However, the good idea here from 1068cadf364dSGavin Shan * benh is to keep frozen state before we get PE reset done completely 1069cadf364dSGavin Shan * (until BAR restore). With the frozen state, HW drops illegal IO 1070cadf364dSGavin Shan * or MMIO access, which can incur recrusive frozen PE during PE 1071cadf364dSGavin Shan * reset. The side effect is that EEH core has to clear the frozen 1072cadf364dSGavin Shan * state explicitly after BAR restore. 1073cadf364dSGavin Shan */ 10744fad4943SGavin Shan if (pe->type & EEH_PE_PHB) 10754fad4943SGavin Shan return pnv_eeh_phb_reset(hose, option); 1076cadf364dSGavin Shan 1077cadf364dSGavin Shan /* 1078cadf364dSGavin Shan * The frozen PE might be caused by PAPR error injection 1079cadf364dSGavin Shan * registers, which are expected to be cleared after hitting 1080cadf364dSGavin Shan * frozen PE as stated in the hardware spec. Unfortunately, 1081cadf364dSGavin Shan * that's not true on P7IOC. So we have to clear it manually 1082cadf364dSGavin Shan * to avoid recursive EEH errors during recovery. 1083cadf364dSGavin Shan */ 1084cadf364dSGavin Shan phb = hose->private_data; 1085cadf364dSGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC && 1086cadf364dSGavin Shan (option == EEH_RESET_HOT || 1087cadf364dSGavin Shan option == EEH_RESET_FUNDAMENTAL)) { 1088cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 1089cadf364dSGavin Shan OPAL_RESET_PHB_ERROR, 1090cadf364dSGavin Shan OPAL_ASSERT_RESET); 1091cadf364dSGavin Shan if (rc != OPAL_SUCCESS) { 10924fad4943SGavin Shan pr_warn("%s: Failure %lld clearing error injection registers\n", 1093cadf364dSGavin Shan __func__, rc); 1094cadf364dSGavin Shan return -EIO; 1095cadf364dSGavin Shan } 1096cadf364dSGavin Shan } 1097cadf364dSGavin Shan 1098e98ddb77SRussell Currey if (pe->type & EEH_PE_VF) 1099e98ddb77SRussell Currey return pnv_eeh_reset_vf_pe(pe, option); 1100e98ddb77SRussell Currey 1101cadf364dSGavin Shan bus = eeh_pe_bus_get(pe); 110204fec21cSRussell Currey if (!bus) { 11031f52f176SRussell Currey pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 110404fec21cSRussell Currey __func__, pe->phb->global_number, pe->addr); 110504fec21cSRussell Currey return -EIO; 110604fec21cSRussell Currey } 110729310e5eSGavin Shan 1108b7da1230SAndrew Donnellan /* 1109b7da1230SAndrew Donnellan * If dealing with the root bus (or the bus underneath the 1110b7da1230SAndrew Donnellan * root port), we reset the bus underneath the root port. 1111b7da1230SAndrew Donnellan * 1112b7da1230SAndrew Donnellan * The cxl driver depends on this behaviour for bi-modal card 1113b7da1230SAndrew Donnellan * switching. 1114b7da1230SAndrew Donnellan */ 11154fad4943SGavin Shan if (pci_is_root_bus(bus) || 11164fad4943SGavin Shan pci_is_root_bus(bus->parent)) 11174fad4943SGavin Shan return pnv_eeh_root_reset(hose, option); 11184fad4943SGavin Shan 11194fad4943SGavin Shan return pnv_eeh_bridge_reset(bus->self, option); 112029310e5eSGavin Shan } 112129310e5eSGavin Shan 112229310e5eSGavin Shan /** 112301f3bfb7SGavin Shan * pnv_eeh_wait_state - Wait for PE state 112429310e5eSGavin Shan * @pe: EEH PE 11252ac3990cSWei Yang * @max_wait: maximal period in millisecond 112629310e5eSGavin Shan * 112729310e5eSGavin Shan * Wait for the state of associated PE. It might take some time 112829310e5eSGavin Shan * to retrieve the PE's state. 112929310e5eSGavin Shan */ 113001f3bfb7SGavin Shan static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) 113129310e5eSGavin Shan { 113229310e5eSGavin Shan int ret; 113329310e5eSGavin Shan int mwait; 113429310e5eSGavin Shan 113529310e5eSGavin Shan while (1) { 113601f3bfb7SGavin Shan ret = pnv_eeh_get_state(pe, &mwait); 113729310e5eSGavin Shan 113829310e5eSGavin Shan /* 113929310e5eSGavin Shan * If the PE's state is temporarily unavailable, 114029310e5eSGavin Shan * we have to wait for the specified time. Otherwise, 114129310e5eSGavin Shan * the PE's state will be returned immediately. 114229310e5eSGavin Shan */ 114329310e5eSGavin Shan if (ret != EEH_STATE_UNAVAILABLE) 114429310e5eSGavin Shan return ret; 114529310e5eSGavin Shan 114629310e5eSGavin Shan if (max_wait <= 0) { 11470dae2743SGavin Shan pr_warn("%s: Timeout getting PE#%x's state (%d)\n", 114829310e5eSGavin Shan __func__, pe->addr, max_wait); 114929310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 115029310e5eSGavin Shan } 115129310e5eSGavin Shan 1152e17866d5SWei Yang max_wait -= mwait; 115329310e5eSGavin Shan msleep(mwait); 115429310e5eSGavin Shan } 115529310e5eSGavin Shan 115629310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 115729310e5eSGavin Shan } 115829310e5eSGavin Shan 115929310e5eSGavin Shan /** 116001f3bfb7SGavin Shan * pnv_eeh_get_log - Retrieve error log 116129310e5eSGavin Shan * @pe: EEH PE 116229310e5eSGavin Shan * @severity: temporary or permanent error log 116329310e5eSGavin Shan * @drv_log: driver log to be combined with retrieved error log 116429310e5eSGavin Shan * @len: length of driver log 116529310e5eSGavin Shan * 116629310e5eSGavin Shan * Retrieve the temporary or permanent error from the PE. 116729310e5eSGavin Shan */ 116801f3bfb7SGavin Shan static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 116929310e5eSGavin Shan char *drv_log, unsigned long len) 117029310e5eSGavin Shan { 117195edcdeaSGavin Shan if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 117295edcdeaSGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 117329310e5eSGavin Shan 117495edcdeaSGavin Shan return 0; 117529310e5eSGavin Shan } 117629310e5eSGavin Shan 117729310e5eSGavin Shan /** 117801f3bfb7SGavin Shan * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 117929310e5eSGavin Shan * @pe: EEH PE 118029310e5eSGavin Shan * 118129310e5eSGavin Shan * The function will be called to reconfigure the bridges included 118229310e5eSGavin Shan * in the specified PE so that the mulfunctional PE would be recovered 118329310e5eSGavin Shan * again. 118429310e5eSGavin Shan */ 118501f3bfb7SGavin Shan static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 118629310e5eSGavin Shan { 1187bbe170edSGavin Shan return 0; 118829310e5eSGavin Shan } 118929310e5eSGavin Shan 119029310e5eSGavin Shan /** 119101f3bfb7SGavin Shan * pnv_pe_err_inject - Inject specified error to the indicated PE 1192131c123aSGavin Shan * @pe: the indicated PE 1193131c123aSGavin Shan * @type: error type 1194131c123aSGavin Shan * @func: specific error type 1195131c123aSGavin Shan * @addr: address 1196131c123aSGavin Shan * @mask: address mask 1197131c123aSGavin Shan * 1198131c123aSGavin Shan * The routine is called to inject specified error, which is 1199131c123aSGavin Shan * determined by @type and @func, to the indicated PE for 1200131c123aSGavin Shan * testing purpose. 1201131c123aSGavin Shan */ 120201f3bfb7SGavin Shan static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1203131c123aSGavin Shan unsigned long addr, unsigned long mask) 1204131c123aSGavin Shan { 1205131c123aSGavin Shan struct pci_controller *hose = pe->phb; 1206131c123aSGavin Shan struct pnv_phb *phb = hose->private_data; 1207fa646c3cSGavin Shan s64 rc; 1208131c123aSGavin Shan 1209fa646c3cSGavin Shan if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1210fa646c3cSGavin Shan type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1211fa646c3cSGavin Shan pr_warn("%s: Invalid error type %d\n", 1212fa646c3cSGavin Shan __func__, type); 1213fa646c3cSGavin Shan return -ERANGE; 1214fa646c3cSGavin Shan } 1215131c123aSGavin Shan 1216fa646c3cSGavin Shan if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1217fa646c3cSGavin Shan func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1218fa646c3cSGavin Shan pr_warn("%s: Invalid error function %d\n", 1219fa646c3cSGavin Shan __func__, func); 1220fa646c3cSGavin Shan return -ERANGE; 1221fa646c3cSGavin Shan } 1222fa646c3cSGavin Shan 1223fa646c3cSGavin Shan /* Firmware supports error injection ? */ 1224fa646c3cSGavin Shan if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1225fa646c3cSGavin Shan pr_warn("%s: Firmware doesn't support error injection\n", 1226fa646c3cSGavin Shan __func__); 1227fa646c3cSGavin Shan return -ENXIO; 1228fa646c3cSGavin Shan } 1229fa646c3cSGavin Shan 1230fa646c3cSGavin Shan /* Do error injection */ 1231fa646c3cSGavin Shan rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1232fa646c3cSGavin Shan type, func, addr, mask); 1233fa646c3cSGavin Shan if (rc != OPAL_SUCCESS) { 1234fa646c3cSGavin Shan pr_warn("%s: Failure %lld injecting error " 1235fa646c3cSGavin Shan "%d-%d to PHB#%x-PE#%x\n", 1236fa646c3cSGavin Shan __func__, rc, type, func, 1237fa646c3cSGavin Shan hose->global_number, pe->addr); 1238fa646c3cSGavin Shan return -EIO; 1239fa646c3cSGavin Shan } 1240fa646c3cSGavin Shan 1241fa646c3cSGavin Shan return 0; 1242131c123aSGavin Shan } 1243131c123aSGavin Shan 12440bd78587SGavin Shan static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1245d2cfbcd7SGavin Shan { 12460bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1247d2cfbcd7SGavin Shan 1248d2cfbcd7SGavin Shan if (!edev || !edev->pe) 1249d2cfbcd7SGavin Shan return false; 1250d2cfbcd7SGavin Shan 12519312bc5bSWei Yang /* 12529312bc5bSWei Yang * We will issue FLR or AF FLR to all VFs, which are contained 12539312bc5bSWei Yang * in VF PE. It relies on the EEH PCI config accessors. So we 12549312bc5bSWei Yang * can't block them during the window. 12559312bc5bSWei Yang */ 12569312bc5bSWei Yang if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 12579312bc5bSWei Yang return false; 12589312bc5bSWei Yang 1259d2cfbcd7SGavin Shan if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1260d2cfbcd7SGavin Shan return true; 1261d2cfbcd7SGavin Shan 1262d2cfbcd7SGavin Shan return false; 1263d2cfbcd7SGavin Shan } 1264d2cfbcd7SGavin Shan 12650bd78587SGavin Shan static int pnv_eeh_read_config(struct pci_dn *pdn, 1266d2cfbcd7SGavin Shan int where, int size, u32 *val) 1267d2cfbcd7SGavin Shan { 12683532a741SGavin Shan if (!pdn) 12693532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12703532a741SGavin Shan 12710bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) { 1272d2cfbcd7SGavin Shan *val = 0xFFFFFFFF; 1273d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1274d2cfbcd7SGavin Shan } 1275d2cfbcd7SGavin Shan 12763532a741SGavin Shan return pnv_pci_cfg_read(pdn, where, size, val); 1277d2cfbcd7SGavin Shan } 1278d2cfbcd7SGavin Shan 12790bd78587SGavin Shan static int pnv_eeh_write_config(struct pci_dn *pdn, 1280d2cfbcd7SGavin Shan int where, int size, u32 val) 1281d2cfbcd7SGavin Shan { 12823532a741SGavin Shan if (!pdn) 12833532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12843532a741SGavin Shan 12850bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) 1286d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1287d2cfbcd7SGavin Shan 12883532a741SGavin Shan return pnv_pci_cfg_write(pdn, where, size, val); 1289d2cfbcd7SGavin Shan } 1290d2cfbcd7SGavin Shan 12912a485ad7SGavin Shan static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 12922a485ad7SGavin Shan { 12932a485ad7SGavin Shan /* GEM */ 12942a485ad7SGavin Shan if (data->gemXfir || data->gemRfir || 12952a485ad7SGavin Shan data->gemRirqfir || data->gemMask || data->gemRwof) 12962a485ad7SGavin Shan pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 12972a485ad7SGavin Shan be64_to_cpu(data->gemXfir), 12982a485ad7SGavin Shan be64_to_cpu(data->gemRfir), 12992a485ad7SGavin Shan be64_to_cpu(data->gemRirqfir), 13002a485ad7SGavin Shan be64_to_cpu(data->gemMask), 13012a485ad7SGavin Shan be64_to_cpu(data->gemRwof)); 13022a485ad7SGavin Shan 13032a485ad7SGavin Shan /* LEM */ 13042a485ad7SGavin Shan if (data->lemFir || data->lemErrMask || 13052a485ad7SGavin Shan data->lemAction0 || data->lemAction1 || data->lemWof) 13062a485ad7SGavin Shan pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 13072a485ad7SGavin Shan be64_to_cpu(data->lemFir), 13082a485ad7SGavin Shan be64_to_cpu(data->lemErrMask), 13092a485ad7SGavin Shan be64_to_cpu(data->lemAction0), 13102a485ad7SGavin Shan be64_to_cpu(data->lemAction1), 13112a485ad7SGavin Shan be64_to_cpu(data->lemWof)); 13122a485ad7SGavin Shan } 13132a485ad7SGavin Shan 13142a485ad7SGavin Shan static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 13152a485ad7SGavin Shan { 13162a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 13172a485ad7SGavin Shan struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag; 13182a485ad7SGavin Shan long rc; 13192a485ad7SGavin Shan 13202a485ad7SGavin Shan rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 13212a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 13222a485ad7SGavin Shan pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 13232a485ad7SGavin Shan __func__, phb->hub_id, rc); 13242a485ad7SGavin Shan return; 13252a485ad7SGavin Shan } 13262a485ad7SGavin Shan 1327a7032132SGavin Shan switch (be16_to_cpu(data->type)) { 13282a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_RGC: 13292a485ad7SGavin Shan pr_info("P7IOC diag-data for RGC\n\n"); 13302a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13312a485ad7SGavin Shan if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 13322a485ad7SGavin Shan pr_info(" RGC: %016llx %016llx\n", 13332a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcStatus), 13342a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcLdcp)); 13352a485ad7SGavin Shan break; 13362a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_BI: 13372a485ad7SGavin Shan pr_info("P7IOC diag-data for BI %s\n\n", 13382a485ad7SGavin Shan data->bi.biDownbound ? "Downbound" : "Upbound"); 13392a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13402a485ad7SGavin Shan if (data->bi.biLdcp0 || data->bi.biLdcp1 || 13412a485ad7SGavin Shan data->bi.biLdcp2 || data->bi.biFenceStatus) 13422a485ad7SGavin Shan pr_info(" BI: %016llx %016llx %016llx %016llx\n", 13432a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp0), 13442a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp1), 13452a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp2), 13462a485ad7SGavin Shan be64_to_cpu(data->bi.biFenceStatus)); 13472a485ad7SGavin Shan break; 13482a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_CI: 13492a485ad7SGavin Shan pr_info("P7IOC diag-data for CI Port %d\n\n", 13502a485ad7SGavin Shan data->ci.ciPort); 13512a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13522a485ad7SGavin Shan if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 13532a485ad7SGavin Shan pr_info(" CI: %016llx %016llx\n", 13542a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortStatus), 13552a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortLdcp)); 13562a485ad7SGavin Shan break; 13572a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_MISC: 13582a485ad7SGavin Shan pr_info("P7IOC diag-data for MISC\n\n"); 13592a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13602a485ad7SGavin Shan break; 13612a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_I2C: 13622a485ad7SGavin Shan pr_info("P7IOC diag-data for I2C\n\n"); 13632a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13642a485ad7SGavin Shan break; 13652a485ad7SGavin Shan default: 13662a485ad7SGavin Shan pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 13672a485ad7SGavin Shan __func__, phb->hub_id, data->type); 13682a485ad7SGavin Shan } 13692a485ad7SGavin Shan } 13702a485ad7SGavin Shan 13712a485ad7SGavin Shan static int pnv_eeh_get_pe(struct pci_controller *hose, 13722a485ad7SGavin Shan u16 pe_no, struct eeh_pe **pe) 13732a485ad7SGavin Shan { 13742a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 13752a485ad7SGavin Shan struct pnv_ioda_pe *pnv_pe; 13762a485ad7SGavin Shan struct eeh_pe *dev_pe; 13772a485ad7SGavin Shan struct eeh_dev edev; 13782a485ad7SGavin Shan 13792a485ad7SGavin Shan /* 13802a485ad7SGavin Shan * If PHB supports compound PE, to fetch 13812a485ad7SGavin Shan * the master PE because slave PE is invisible 13822a485ad7SGavin Shan * to EEH core. 13832a485ad7SGavin Shan */ 13842a485ad7SGavin Shan pnv_pe = &phb->ioda.pe_array[pe_no]; 13852a485ad7SGavin Shan if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 13862a485ad7SGavin Shan pnv_pe = pnv_pe->master; 13872a485ad7SGavin Shan WARN_ON(!pnv_pe || 13882a485ad7SGavin Shan !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 13892a485ad7SGavin Shan pe_no = pnv_pe->pe_number; 13902a485ad7SGavin Shan } 13912a485ad7SGavin Shan 13922a485ad7SGavin Shan /* Find the PE according to PE# */ 13932a485ad7SGavin Shan memset(&edev, 0, sizeof(struct eeh_dev)); 13942a485ad7SGavin Shan edev.phb = hose; 13952a485ad7SGavin Shan edev.pe_config_addr = pe_no; 13962a485ad7SGavin Shan dev_pe = eeh_pe_get(&edev); 13972a485ad7SGavin Shan if (!dev_pe) 13982a485ad7SGavin Shan return -EEXIST; 13992a485ad7SGavin Shan 14002a485ad7SGavin Shan /* Freeze the (compound) PE */ 14012a485ad7SGavin Shan *pe = dev_pe; 14022a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 14032a485ad7SGavin Shan phb->freeze_pe(phb, pe_no); 14042a485ad7SGavin Shan 14052a485ad7SGavin Shan /* 14062a485ad7SGavin Shan * At this point, we're sure the (compound) PE should 14072a485ad7SGavin Shan * have been frozen. However, we still need poke until 14082a485ad7SGavin Shan * hitting the frozen PE on top level. 14092a485ad7SGavin Shan */ 14102a485ad7SGavin Shan dev_pe = dev_pe->parent; 14112a485ad7SGavin Shan while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 14122a485ad7SGavin Shan int ret; 14132a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | 14142a485ad7SGavin Shan EEH_STATE_DMA_ACTIVE); 14152a485ad7SGavin Shan 14162a485ad7SGavin Shan ret = eeh_ops->get_state(dev_pe, NULL); 14172a485ad7SGavin Shan if (ret <= 0 || (ret & active_flags) == active_flags) { 14182a485ad7SGavin Shan dev_pe = dev_pe->parent; 14192a485ad7SGavin Shan continue; 14202a485ad7SGavin Shan } 14212a485ad7SGavin Shan 14222a485ad7SGavin Shan /* Frozen parent PE */ 14232a485ad7SGavin Shan *pe = dev_pe; 14242a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 14252a485ad7SGavin Shan phb->freeze_pe(phb, dev_pe->addr); 14262a485ad7SGavin Shan 14272a485ad7SGavin Shan /* Next one */ 14282a485ad7SGavin Shan dev_pe = dev_pe->parent; 14292a485ad7SGavin Shan } 14302a485ad7SGavin Shan 14312a485ad7SGavin Shan return 0; 14322a485ad7SGavin Shan } 14332a485ad7SGavin Shan 1434131c123aSGavin Shan /** 143501f3bfb7SGavin Shan * pnv_eeh_next_error - Retrieve next EEH error to handle 143629310e5eSGavin Shan * @pe: Affected PE 143729310e5eSGavin Shan * 14382a485ad7SGavin Shan * The function is expected to be called by EEH core while it gets 14392a485ad7SGavin Shan * special EEH event (without binding PE). The function calls to 14402a485ad7SGavin Shan * OPAL APIs for next error to handle. The informational error is 14412a485ad7SGavin Shan * handled internally by platform. However, the dead IOC, dead PHB, 14422a485ad7SGavin Shan * fenced PHB and frozen PE should be handled by EEH core eventually. 144329310e5eSGavin Shan */ 144401f3bfb7SGavin Shan static int pnv_eeh_next_error(struct eeh_pe **pe) 144529310e5eSGavin Shan { 144629310e5eSGavin Shan struct pci_controller *hose; 14472a485ad7SGavin Shan struct pnv_phb *phb; 14482a485ad7SGavin Shan struct eeh_pe *phb_pe, *parent_pe; 14492a485ad7SGavin Shan __be64 frozen_pe_no; 14502a485ad7SGavin Shan __be16 err_type, severity; 14512a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 14522a485ad7SGavin Shan long rc; 14532a485ad7SGavin Shan int state, ret = EEH_NEXT_ERR_NONE; 14542a485ad7SGavin Shan 14552a485ad7SGavin Shan /* 145679231448SAlistair Popple * While running here, it's safe to purge the event queue. The 145779231448SAlistair Popple * event should still be masked. 14582a485ad7SGavin Shan */ 14592a485ad7SGavin Shan eeh_remove_event(NULL, false); 146029310e5eSGavin Shan 146129310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 14622a485ad7SGavin Shan /* 14632a485ad7SGavin Shan * If the subordinate PCI buses of the PHB has been 14642a485ad7SGavin Shan * removed or is exactly under error recovery, we 14652a485ad7SGavin Shan * needn't take care of it any more. 14662a485ad7SGavin Shan */ 146729310e5eSGavin Shan phb = hose->private_data; 14682a485ad7SGavin Shan phb_pe = eeh_phb_pe_get(hose); 14692a485ad7SGavin Shan if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 14702a485ad7SGavin Shan continue; 14712a485ad7SGavin Shan 14722a485ad7SGavin Shan rc = opal_pci_next_error(phb->opal_id, 14732a485ad7SGavin Shan &frozen_pe_no, &err_type, &severity); 14742a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 14752a485ad7SGavin Shan pr_devel("%s: Invalid return value on " 14762a485ad7SGavin Shan "PHB#%x (0x%lx) from opal_pci_next_error", 14772a485ad7SGavin Shan __func__, hose->global_number, rc); 14782a485ad7SGavin Shan continue; 14792a485ad7SGavin Shan } 14802a485ad7SGavin Shan 14812a485ad7SGavin Shan /* If the PHB doesn't have error, stop processing */ 14822a485ad7SGavin Shan if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 14832a485ad7SGavin Shan be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 14842a485ad7SGavin Shan pr_devel("%s: No error found on PHB#%x\n", 14852a485ad7SGavin Shan __func__, hose->global_number); 14862a485ad7SGavin Shan continue; 14872a485ad7SGavin Shan } 14882a485ad7SGavin Shan 14892a485ad7SGavin Shan /* 14902a485ad7SGavin Shan * Processing the error. We're expecting the error with 14912a485ad7SGavin Shan * highest priority reported upon multiple errors on the 14922a485ad7SGavin Shan * specific PHB. 14932a485ad7SGavin Shan */ 14942a485ad7SGavin Shan pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 14952a485ad7SGavin Shan __func__, be16_to_cpu(err_type), 14962a485ad7SGavin Shan be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 14972a485ad7SGavin Shan hose->global_number); 14982a485ad7SGavin Shan switch (be16_to_cpu(err_type)) { 14992a485ad7SGavin Shan case OPAL_EEH_IOC_ERROR: 15002a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 15012a485ad7SGavin Shan pr_err("EEH: dead IOC detected\n"); 15022a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_IOC; 15032a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 15042a485ad7SGavin Shan pr_info("EEH: IOC informative error " 15052a485ad7SGavin Shan "detected\n"); 15062a485ad7SGavin Shan pnv_eeh_get_and_dump_hub_diag(hose); 15072a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15082a485ad7SGavin Shan } 15092a485ad7SGavin Shan 15102a485ad7SGavin Shan break; 15112a485ad7SGavin Shan case OPAL_EEH_PHB_ERROR: 15122a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 15132a485ad7SGavin Shan *pe = phb_pe; 15142a485ad7SGavin Shan pr_err("EEH: dead PHB#%x detected, " 15152a485ad7SGavin Shan "location: %s\n", 15162a485ad7SGavin Shan hose->global_number, 15172a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15182a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_PHB; 15192a485ad7SGavin Shan } else if (be16_to_cpu(severity) == 15202a485ad7SGavin Shan OPAL_EEH_SEV_PHB_FENCED) { 15212a485ad7SGavin Shan *pe = phb_pe; 15222a485ad7SGavin Shan pr_err("EEH: Fenced PHB#%x detected, " 15232a485ad7SGavin Shan "location: %s\n", 15242a485ad7SGavin Shan hose->global_number, 15252a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15262a485ad7SGavin Shan ret = EEH_NEXT_ERR_FENCED_PHB; 15272a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 15282a485ad7SGavin Shan pr_info("EEH: PHB#%x informative error " 15292a485ad7SGavin Shan "detected, location: %s\n", 15302a485ad7SGavin Shan hose->global_number, 15312a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15322a485ad7SGavin Shan pnv_eeh_get_phb_diag(phb_pe); 15332a485ad7SGavin Shan pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 15342a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15352a485ad7SGavin Shan } 15362a485ad7SGavin Shan 15372a485ad7SGavin Shan break; 15382a485ad7SGavin Shan case OPAL_EEH_PE_ERROR: 15392a485ad7SGavin Shan /* 15402a485ad7SGavin Shan * If we can't find the corresponding PE, we 15412a485ad7SGavin Shan * just try to unfreeze. 15422a485ad7SGavin Shan */ 15432a485ad7SGavin Shan if (pnv_eeh_get_pe(hose, 15442a485ad7SGavin Shan be64_to_cpu(frozen_pe_no), pe)) { 15452a485ad7SGavin Shan pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 15460f36db77SGavin Shan hose->global_number, be64_to_cpu(frozen_pe_no)); 15472a485ad7SGavin Shan pr_info("EEH: PHB location: %s\n", 15482a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 154979cd9520SGavin Shan 155079cd9520SGavin Shan /* Dump PHB diag-data */ 155179cd9520SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, 155279cd9520SGavin Shan phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE); 155379cd9520SGavin Shan if (rc == OPAL_SUCCESS) 155479cd9520SGavin Shan pnv_pci_dump_phb_diag_data(hose, 155579cd9520SGavin Shan phb->diag.blob); 155679cd9520SGavin Shan 155779cd9520SGavin Shan /* Try best to clear it */ 15582a485ad7SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 1559d63e51b3SGavin Shan be64_to_cpu(frozen_pe_no), 15602a485ad7SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 15612a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15622a485ad7SGavin Shan } else if ((*pe)->state & EEH_PE_ISOLATED || 15632a485ad7SGavin Shan eeh_pe_passed(*pe)) { 15642a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15652a485ad7SGavin Shan } else { 15662a485ad7SGavin Shan pr_err("EEH: Frozen PE#%x " 15672a485ad7SGavin Shan "on PHB#%x detected\n", 15682a485ad7SGavin Shan (*pe)->addr, 15692a485ad7SGavin Shan (*pe)->phb->global_number); 15702a485ad7SGavin Shan pr_err("EEH: PE location: %s, " 15712a485ad7SGavin Shan "PHB location: %s\n", 15722a485ad7SGavin Shan eeh_pe_loc_get(*pe), 15732a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15742a485ad7SGavin Shan ret = EEH_NEXT_ERR_FROZEN_PE; 15752a485ad7SGavin Shan } 15762a485ad7SGavin Shan 15772a485ad7SGavin Shan break; 15782a485ad7SGavin Shan default: 15792a485ad7SGavin Shan pr_warn("%s: Unexpected error type %d\n", 15802a485ad7SGavin Shan __func__, be16_to_cpu(err_type)); 15812a485ad7SGavin Shan } 15822a485ad7SGavin Shan 15832a485ad7SGavin Shan /* 15842a485ad7SGavin Shan * EEH core will try recover from fenced PHB or 15852a485ad7SGavin Shan * frozen PE. In the time for frozen PE, EEH core 15862a485ad7SGavin Shan * enable IO path for that before collecting logs, 15872a485ad7SGavin Shan * but it ruins the site. So we have to dump the 15882a485ad7SGavin Shan * log in advance here. 15892a485ad7SGavin Shan */ 15902a485ad7SGavin Shan if ((ret == EEH_NEXT_ERR_FROZEN_PE || 15912a485ad7SGavin Shan ret == EEH_NEXT_ERR_FENCED_PHB) && 15922a485ad7SGavin Shan !((*pe)->state & EEH_PE_ISOLATED)) { 15932a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 15942a485ad7SGavin Shan pnv_eeh_get_phb_diag(*pe); 15952a485ad7SGavin Shan 15962a485ad7SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 15972a485ad7SGavin Shan pnv_pci_dump_phb_diag_data((*pe)->phb, 15982a485ad7SGavin Shan (*pe)->data); 15992a485ad7SGavin Shan } 16002a485ad7SGavin Shan 16012a485ad7SGavin Shan /* 16022a485ad7SGavin Shan * We probably have the frozen parent PE out there and 16032a485ad7SGavin Shan * we need have to handle frozen parent PE firstly. 16042a485ad7SGavin Shan */ 16052a485ad7SGavin Shan if (ret == EEH_NEXT_ERR_FROZEN_PE) { 16062a485ad7SGavin Shan parent_pe = (*pe)->parent; 16072a485ad7SGavin Shan while (parent_pe) { 16082a485ad7SGavin Shan /* Hit the ceiling ? */ 16092a485ad7SGavin Shan if (parent_pe->type & EEH_PE_PHB) 16102a485ad7SGavin Shan break; 16112a485ad7SGavin Shan 16122a485ad7SGavin Shan /* Frozen parent PE ? */ 16132a485ad7SGavin Shan state = eeh_ops->get_state(parent_pe, NULL); 16142a485ad7SGavin Shan if (state > 0 && 16152a485ad7SGavin Shan (state & active_flags) != active_flags) 16162a485ad7SGavin Shan *pe = parent_pe; 16172a485ad7SGavin Shan 16182a485ad7SGavin Shan /* Next parent level */ 16192a485ad7SGavin Shan parent_pe = parent_pe->parent; 16202a485ad7SGavin Shan } 16212a485ad7SGavin Shan 16222a485ad7SGavin Shan /* We possibly migrate to another PE */ 16232a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 16242a485ad7SGavin Shan } 16252a485ad7SGavin Shan 16262a485ad7SGavin Shan /* 16272a485ad7SGavin Shan * If we have no errors on the specific PHB or only 16282a485ad7SGavin Shan * informative error there, we continue poking it. 16292a485ad7SGavin Shan * Otherwise, we need actions to be taken by upper 16302a485ad7SGavin Shan * layer. 16312a485ad7SGavin Shan */ 16322a485ad7SGavin Shan if (ret > EEH_NEXT_ERR_INF) 163329310e5eSGavin Shan break; 163429310e5eSGavin Shan } 163529310e5eSGavin Shan 163679231448SAlistair Popple /* Unmask the event */ 1637b8d65e96SAlistair Popple if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 163879231448SAlistair Popple enable_irq(eeh_event_irq); 163979231448SAlistair Popple 16402a485ad7SGavin Shan return ret; 164129310e5eSGavin Shan } 164229310e5eSGavin Shan 16430dc2830eSWei Yang static int pnv_eeh_restore_vf_config(struct pci_dn *pdn) 16440dc2830eSWei Yang { 16450dc2830eSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 16460dc2830eSWei Yang u32 devctl, cmd, cap2, aer_capctl; 16470dc2830eSWei Yang int old_mps; 16480dc2830eSWei Yang 16490dc2830eSWei Yang if (edev->pcie_cap) { 16500dc2830eSWei Yang /* Restore MPS */ 16510dc2830eSWei Yang old_mps = (ffs(pdn->mps) - 8) << 5; 16520dc2830eSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 16530dc2830eSWei Yang 2, &devctl); 16540dc2830eSWei Yang devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; 16550dc2830eSWei Yang devctl |= old_mps; 16560dc2830eSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 16570dc2830eSWei Yang 2, devctl); 16580dc2830eSWei Yang 16590dc2830eSWei Yang /* Disable Completion Timeout */ 16600dc2830eSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2, 16610dc2830eSWei Yang 4, &cap2); 16620dc2830eSWei Yang if (cap2 & 0x10) { 16630dc2830eSWei Yang eeh_ops->read_config(pdn, 16640dc2830eSWei Yang edev->pcie_cap + PCI_EXP_DEVCTL2, 16650dc2830eSWei Yang 4, &cap2); 16660dc2830eSWei Yang cap2 |= 0x10; 16670dc2830eSWei Yang eeh_ops->write_config(pdn, 16680dc2830eSWei Yang edev->pcie_cap + PCI_EXP_DEVCTL2, 16690dc2830eSWei Yang 4, cap2); 16700dc2830eSWei Yang } 16710dc2830eSWei Yang } 16720dc2830eSWei Yang 16730dc2830eSWei Yang /* Enable SERR and parity checking */ 16740dc2830eSWei Yang eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd); 16750dc2830eSWei Yang cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 16760dc2830eSWei Yang eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd); 16770dc2830eSWei Yang 16780dc2830eSWei Yang /* Enable report various errors */ 16790dc2830eSWei Yang if (edev->pcie_cap) { 16800dc2830eSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 16810dc2830eSWei Yang 2, &devctl); 16820dc2830eSWei Yang devctl &= ~PCI_EXP_DEVCTL_CERE; 16830dc2830eSWei Yang devctl |= (PCI_EXP_DEVCTL_NFERE | 16840dc2830eSWei Yang PCI_EXP_DEVCTL_FERE | 16850dc2830eSWei Yang PCI_EXP_DEVCTL_URRE); 16860dc2830eSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 16870dc2830eSWei Yang 2, devctl); 16880dc2830eSWei Yang } 16890dc2830eSWei Yang 16900dc2830eSWei Yang /* Enable ECRC generation and check */ 16910dc2830eSWei Yang if (edev->pcie_cap && edev->aer_cap) { 16920dc2830eSWei Yang eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP, 16930dc2830eSWei Yang 4, &aer_capctl); 16940dc2830eSWei Yang aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 16950dc2830eSWei Yang eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP, 16960dc2830eSWei Yang 4, aer_capctl); 16970dc2830eSWei Yang } 16980dc2830eSWei Yang 16990dc2830eSWei Yang return 0; 17000dc2830eSWei Yang } 17010dc2830eSWei Yang 17020bd78587SGavin Shan static int pnv_eeh_restore_config(struct pci_dn *pdn) 17039be3beccSGavin Shan { 17040bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 17059be3beccSGavin Shan struct pnv_phb *phb; 17069be3beccSGavin Shan s64 ret; 17079be3beccSGavin Shan 17089be3beccSGavin Shan if (!edev) 17099be3beccSGavin Shan return -EEXIST; 17109be3beccSGavin Shan 17110dc2830eSWei Yang /* 17120dc2830eSWei Yang * We have to restore the PCI config space after reset since the 17130dc2830eSWei Yang * firmware can't see SRIOV VFs. 17140dc2830eSWei Yang * 17150dc2830eSWei Yang * FIXME: The MPS, error routing rules, timeout setting are worthy 17160dc2830eSWei Yang * to be exported by firmware in extendible way. 17170dc2830eSWei Yang */ 17180dc2830eSWei Yang if (edev->physfn) { 17190dc2830eSWei Yang ret = pnv_eeh_restore_vf_config(pdn); 17200dc2830eSWei Yang } else { 17219be3beccSGavin Shan phb = edev->phb->private_data; 17229be3beccSGavin Shan ret = opal_pci_reinit(phb->opal_id, 17239be3beccSGavin Shan OPAL_REINIT_PCI_DEV, edev->config_addr); 17240dc2830eSWei Yang } 17250dc2830eSWei Yang 17269be3beccSGavin Shan if (ret) { 17279be3beccSGavin Shan pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 17289be3beccSGavin Shan __func__, edev->config_addr, ret); 17299be3beccSGavin Shan return -EIO; 17309be3beccSGavin Shan } 17319be3beccSGavin Shan 17329be3beccSGavin Shan return 0; 17339be3beccSGavin Shan } 17349be3beccSGavin Shan 173501f3bfb7SGavin Shan static struct eeh_ops pnv_eeh_ops = { 173629310e5eSGavin Shan .name = "powernv", 173701f3bfb7SGavin Shan .init = pnv_eeh_init, 173801f3bfb7SGavin Shan .post_init = pnv_eeh_post_init, 1739ff57b454SGavin Shan .probe = pnv_eeh_probe, 174001f3bfb7SGavin Shan .set_option = pnv_eeh_set_option, 174101f3bfb7SGavin Shan .get_pe_addr = pnv_eeh_get_pe_addr, 174201f3bfb7SGavin Shan .get_state = pnv_eeh_get_state, 174301f3bfb7SGavin Shan .reset = pnv_eeh_reset, 174401f3bfb7SGavin Shan .wait_state = pnv_eeh_wait_state, 174501f3bfb7SGavin Shan .get_log = pnv_eeh_get_log, 174601f3bfb7SGavin Shan .configure_bridge = pnv_eeh_configure_bridge, 174701f3bfb7SGavin Shan .err_inject = pnv_eeh_err_inject, 174801f3bfb7SGavin Shan .read_config = pnv_eeh_read_config, 174901f3bfb7SGavin Shan .write_config = pnv_eeh_write_config, 175001f3bfb7SGavin Shan .next_error = pnv_eeh_next_error, 175101f3bfb7SGavin Shan .restore_config = pnv_eeh_restore_config 175229310e5eSGavin Shan }; 175329310e5eSGavin Shan 1754c29fa27dSWei Yang void pcibios_bus_add_device(struct pci_dev *pdev) 1755c29fa27dSWei Yang { 1756c29fa27dSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 1757c29fa27dSWei Yang 1758c29fa27dSWei Yang if (!pdev->is_virtfn) 1759c29fa27dSWei Yang return; 1760c29fa27dSWei Yang 1761c29fa27dSWei Yang /* 1762c29fa27dSWei Yang * The following operations will fail if VF's sysfs files 1763c29fa27dSWei Yang * aren't created or its resources aren't finalized. 1764c29fa27dSWei Yang */ 1765c29fa27dSWei Yang eeh_add_device_early(pdn); 1766c29fa27dSWei Yang eeh_add_device_late(pdev); 1767c29fa27dSWei Yang eeh_sysfs_add_device(pdev); 1768c29fa27dSWei Yang } 1769c29fa27dSWei Yang 17700dc2830eSWei Yang #ifdef CONFIG_PCI_IOV 17710dc2830eSWei Yang static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 17720dc2830eSWei Yang { 17730dc2830eSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 17740dc2830eSWei Yang int parent_mps; 17750dc2830eSWei Yang 17760dc2830eSWei Yang if (!pdev->is_virtfn) 17770dc2830eSWei Yang return; 17780dc2830eSWei Yang 17790dc2830eSWei Yang /* Synchronize MPS for VF and PF */ 17800dc2830eSWei Yang parent_mps = pcie_get_mps(pdev->physfn); 17810dc2830eSWei Yang if ((128 << pdev->pcie_mpss) >= parent_mps) 17820dc2830eSWei Yang pcie_set_mps(pdev, parent_mps); 17830dc2830eSWei Yang pdn->mps = pcie_get_mps(pdev); 17840dc2830eSWei Yang } 17850dc2830eSWei Yang DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 17860dc2830eSWei Yang #endif /* CONFIG_PCI_IOV */ 17870dc2830eSWei Yang 178829310e5eSGavin Shan /** 178929310e5eSGavin Shan * eeh_powernv_init - Register platform dependent EEH operations 179029310e5eSGavin Shan * 179129310e5eSGavin Shan * EEH initialization on powernv platform. This function should be 179229310e5eSGavin Shan * called before any EEH related functions. 179329310e5eSGavin Shan */ 179429310e5eSGavin Shan static int __init eeh_powernv_init(void) 179529310e5eSGavin Shan { 179629310e5eSGavin Shan int ret = -EINVAL; 179729310e5eSGavin Shan 1798bb593c00SGavin Shan eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE); 179901f3bfb7SGavin Shan ret = eeh_ops_register(&pnv_eeh_ops); 180029310e5eSGavin Shan if (!ret) 180129310e5eSGavin Shan pr_info("EEH: PowerNV platform initialized\n"); 180229310e5eSGavin Shan else 180329310e5eSGavin Shan pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 180429310e5eSGavin Shan 180529310e5eSGavin Shan return ret; 180629310e5eSGavin Shan } 1807b14726c5SMichael Ellerman machine_early_initcall(powernv, eeh_powernv_init); 1808