129310e5eSGavin Shan /* 229310e5eSGavin Shan * The file intends to implement the platform dependent EEH operations on 329310e5eSGavin Shan * powernv platform. Actually, the powernv was created in order to fully 429310e5eSGavin Shan * hypervisor support. 529310e5eSGavin Shan * 629310e5eSGavin Shan * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 729310e5eSGavin Shan * 829310e5eSGavin Shan * This program is free software; you can redistribute it and/or modify 929310e5eSGavin Shan * it under the terms of the GNU General Public License as published by 1029310e5eSGavin Shan * the Free Software Foundation; either version 2 of the License, or 1129310e5eSGavin Shan * (at your option) any later version. 1229310e5eSGavin Shan */ 1329310e5eSGavin Shan 1429310e5eSGavin Shan #include <linux/atomic.h> 154cf17445SGavin Shan #include <linux/debugfs.h> 1629310e5eSGavin Shan #include <linux/delay.h> 1729310e5eSGavin Shan #include <linux/export.h> 1829310e5eSGavin Shan #include <linux/init.h> 1979231448SAlistair Popple #include <linux/interrupt.h> 2029310e5eSGavin Shan #include <linux/list.h> 2129310e5eSGavin Shan #include <linux/msi.h> 2229310e5eSGavin Shan #include <linux/of.h> 2329310e5eSGavin Shan #include <linux/pci.h> 2429310e5eSGavin Shan #include <linux/proc_fs.h> 2529310e5eSGavin Shan #include <linux/rbtree.h> 2629310e5eSGavin Shan #include <linux/sched.h> 2729310e5eSGavin Shan #include <linux/seq_file.h> 2829310e5eSGavin Shan #include <linux/spinlock.h> 2929310e5eSGavin Shan 3029310e5eSGavin Shan #include <asm/eeh.h> 3129310e5eSGavin Shan #include <asm/eeh_event.h> 3229310e5eSGavin Shan #include <asm/firmware.h> 3329310e5eSGavin Shan #include <asm/io.h> 3429310e5eSGavin Shan #include <asm/iommu.h> 3529310e5eSGavin Shan #include <asm/machdep.h> 3629310e5eSGavin Shan #include <asm/msi_bitmap.h> 3729310e5eSGavin Shan #include <asm/opal.h> 3829310e5eSGavin Shan #include <asm/ppc-pci.h> 3929310e5eSGavin Shan 4029310e5eSGavin Shan #include "powernv.h" 4129310e5eSGavin Shan #include "pci.h" 4229310e5eSGavin Shan 434cf17445SGavin Shan static bool pnv_eeh_nb_init = false; 4479231448SAlistair Popple static int eeh_event_irq = -EINVAL; 454cf17445SGavin Shan 4629310e5eSGavin Shan /** 4701f3bfb7SGavin Shan * pnv_eeh_init - EEH platform dependent initialization 4829310e5eSGavin Shan * 4929310e5eSGavin Shan * EEH platform dependent initialization on powernv 5029310e5eSGavin Shan */ 5101f3bfb7SGavin Shan static int pnv_eeh_init(void) 5229310e5eSGavin Shan { 53dc561fb9SGavin Shan struct pci_controller *hose; 54dc561fb9SGavin Shan struct pnv_phb *phb; 55dc561fb9SGavin Shan 5629310e5eSGavin Shan /* We require OPALv3 */ 5729310e5eSGavin Shan if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 580dae2743SGavin Shan pr_warn("%s: OPALv3 is required !\n", 590dae2743SGavin Shan __func__); 6029310e5eSGavin Shan return -EINVAL; 6129310e5eSGavin Shan } 6229310e5eSGavin Shan 6305b1721dSGavin Shan /* Set probe mode */ 6405b1721dSGavin Shan eeh_add_flag(EEH_PROBE_MODE_DEV); 6529310e5eSGavin Shan 66dc561fb9SGavin Shan /* 67dc561fb9SGavin Shan * P7IOC blocks PCI config access to frozen PE, but PHB3 68dc561fb9SGavin Shan * doesn't do that. So we have to selectively enable I/O 69dc561fb9SGavin Shan * prior to collecting error log. 70dc561fb9SGavin Shan */ 71dc561fb9SGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 72dc561fb9SGavin Shan phb = hose->private_data; 73dc561fb9SGavin Shan 74dc561fb9SGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC) 75dc561fb9SGavin Shan eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 762aa5cf9eSGavin Shan 772aa5cf9eSGavin Shan /* 782aa5cf9eSGavin Shan * PE#0 should be regarded as valid by EEH core 792aa5cf9eSGavin Shan * if it's not the reserved one. Currently, we 802aa5cf9eSGavin Shan * have the reserved PE#0 and PE#127 for PHB3 812aa5cf9eSGavin Shan * and P7IOC separately. So we should regard 822aa5cf9eSGavin Shan * PE#0 as valid for P7IOC. 832aa5cf9eSGavin Shan */ 842aa5cf9eSGavin Shan if (phb->ioda.reserved_pe != 0) 852aa5cf9eSGavin Shan eeh_add_flag(EEH_VALID_PE_ZERO); 862aa5cf9eSGavin Shan 87dc561fb9SGavin Shan break; 88dc561fb9SGavin Shan } 89dc561fb9SGavin Shan 9029310e5eSGavin Shan return 0; 9129310e5eSGavin Shan } 9229310e5eSGavin Shan 9379231448SAlistair Popple static irqreturn_t pnv_eeh_event(int irq, void *data) 944cf17445SGavin Shan { 954cf17445SGavin Shan /* 9679231448SAlistair Popple * We simply send a special EEH event if EEH has been 9779231448SAlistair Popple * enabled. We don't care about EEH events until we've 9879231448SAlistair Popple * finished processing the outstanding ones. Event processing 9979231448SAlistair Popple * gets unmasked in next_error() if EEH is enabled. 1004cf17445SGavin Shan */ 10179231448SAlistair Popple disable_irq_nosync(irq); 1024cf17445SGavin Shan 1034cf17445SGavin Shan if (eeh_enabled()) 1044cf17445SGavin Shan eeh_send_failure_event(NULL); 1054cf17445SGavin Shan 10679231448SAlistair Popple return IRQ_HANDLED; 1074cf17445SGavin Shan } 1084cf17445SGavin Shan 1094cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 1104cf17445SGavin Shan static ssize_t pnv_eeh_ei_write(struct file *filp, 1114cf17445SGavin Shan const char __user *user_buf, 1124cf17445SGavin Shan size_t count, loff_t *ppos) 1134cf17445SGavin Shan { 1144cf17445SGavin Shan struct pci_controller *hose = filp->private_data; 1154cf17445SGavin Shan struct eeh_dev *edev; 1164cf17445SGavin Shan struct eeh_pe *pe; 1174cf17445SGavin Shan int pe_no, type, func; 1184cf17445SGavin Shan unsigned long addr, mask; 1194cf17445SGavin Shan char buf[50]; 1204cf17445SGavin Shan int ret; 1214cf17445SGavin Shan 1224cf17445SGavin Shan if (!eeh_ops || !eeh_ops->err_inject) 1234cf17445SGavin Shan return -ENXIO; 1244cf17445SGavin Shan 1254cf17445SGavin Shan /* Copy over argument buffer */ 1264cf17445SGavin Shan ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 1274cf17445SGavin Shan if (!ret) 1284cf17445SGavin Shan return -EFAULT; 1294cf17445SGavin Shan 1304cf17445SGavin Shan /* Retrieve parameters */ 1314cf17445SGavin Shan ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 1324cf17445SGavin Shan &pe_no, &type, &func, &addr, &mask); 1334cf17445SGavin Shan if (ret != 5) 1344cf17445SGavin Shan return -EINVAL; 1354cf17445SGavin Shan 1364cf17445SGavin Shan /* Retrieve PE */ 1374cf17445SGavin Shan edev = kzalloc(sizeof(*edev), GFP_KERNEL); 1384cf17445SGavin Shan if (!edev) 1394cf17445SGavin Shan return -ENOMEM; 1404cf17445SGavin Shan edev->phb = hose; 1414cf17445SGavin Shan edev->pe_config_addr = pe_no; 1424cf17445SGavin Shan pe = eeh_pe_get(edev); 1434cf17445SGavin Shan kfree(edev); 1444cf17445SGavin Shan if (!pe) 1454cf17445SGavin Shan return -ENODEV; 1464cf17445SGavin Shan 1474cf17445SGavin Shan /* Do error injection */ 1484cf17445SGavin Shan ret = eeh_ops->err_inject(pe, type, func, addr, mask); 1494cf17445SGavin Shan return ret < 0 ? ret : count; 1504cf17445SGavin Shan } 1514cf17445SGavin Shan 1524cf17445SGavin Shan static const struct file_operations pnv_eeh_ei_fops = { 1534cf17445SGavin Shan .open = simple_open, 1544cf17445SGavin Shan .llseek = no_llseek, 1554cf17445SGavin Shan .write = pnv_eeh_ei_write, 1564cf17445SGavin Shan }; 1574cf17445SGavin Shan 1584cf17445SGavin Shan static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 1594cf17445SGavin Shan { 1604cf17445SGavin Shan struct pci_controller *hose = data; 1614cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1624cf17445SGavin Shan 1634cf17445SGavin Shan out_be64(phb->regs + offset, val); 1644cf17445SGavin Shan return 0; 1654cf17445SGavin Shan } 1664cf17445SGavin Shan 1674cf17445SGavin Shan static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 1684cf17445SGavin Shan { 1694cf17445SGavin Shan struct pci_controller *hose = data; 1704cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1714cf17445SGavin Shan 1724cf17445SGavin Shan *val = in_be64(phb->regs + offset); 1734cf17445SGavin Shan return 0; 1744cf17445SGavin Shan } 1754cf17445SGavin Shan 1764cf17445SGavin Shan static int pnv_eeh_outb_dbgfs_set(void *data, u64 val) 1774cf17445SGavin Shan { 1784cf17445SGavin Shan return pnv_eeh_dbgfs_set(data, 0xD10, val); 1794cf17445SGavin Shan } 1804cf17445SGavin Shan 1814cf17445SGavin Shan static int pnv_eeh_outb_dbgfs_get(void *data, u64 *val) 1824cf17445SGavin Shan { 1834cf17445SGavin Shan return pnv_eeh_dbgfs_get(data, 0xD10, val); 1844cf17445SGavin Shan } 1854cf17445SGavin Shan 1864cf17445SGavin Shan static int pnv_eeh_inbA_dbgfs_set(void *data, u64 val) 1874cf17445SGavin Shan { 1884cf17445SGavin Shan return pnv_eeh_dbgfs_set(data, 0xD90, val); 1894cf17445SGavin Shan } 1904cf17445SGavin Shan 1914cf17445SGavin Shan static int pnv_eeh_inbA_dbgfs_get(void *data, u64 *val) 1924cf17445SGavin Shan { 1934cf17445SGavin Shan return pnv_eeh_dbgfs_get(data, 0xD90, val); 1944cf17445SGavin Shan } 1954cf17445SGavin Shan 1964cf17445SGavin Shan static int pnv_eeh_inbB_dbgfs_set(void *data, u64 val) 1974cf17445SGavin Shan { 1984cf17445SGavin Shan return pnv_eeh_dbgfs_set(data, 0xE10, val); 1994cf17445SGavin Shan } 2004cf17445SGavin Shan 2014cf17445SGavin Shan static int pnv_eeh_inbB_dbgfs_get(void *data, u64 *val) 2024cf17445SGavin Shan { 2034cf17445SGavin Shan return pnv_eeh_dbgfs_get(data, 0xE10, val); 2044cf17445SGavin Shan } 2054cf17445SGavin Shan 2064cf17445SGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_outb_dbgfs_ops, pnv_eeh_outb_dbgfs_get, 2074cf17445SGavin Shan pnv_eeh_outb_dbgfs_set, "0x%llx\n"); 2084cf17445SGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbA_dbgfs_ops, pnv_eeh_inbA_dbgfs_get, 2094cf17445SGavin Shan pnv_eeh_inbA_dbgfs_set, "0x%llx\n"); 2104cf17445SGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbB_dbgfs_ops, pnv_eeh_inbB_dbgfs_get, 2114cf17445SGavin Shan pnv_eeh_inbB_dbgfs_set, "0x%llx\n"); 2124cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 2134cf17445SGavin Shan 21429310e5eSGavin Shan /** 21501f3bfb7SGavin Shan * pnv_eeh_post_init - EEH platform dependent post initialization 21629310e5eSGavin Shan * 21729310e5eSGavin Shan * EEH platform dependent post initialization on powernv. When 21829310e5eSGavin Shan * the function is called, the EEH PEs and devices should have 21929310e5eSGavin Shan * been built. If the I/O cache staff has been built, EEH is 22029310e5eSGavin Shan * ready to supply service. 22129310e5eSGavin Shan */ 22201f3bfb7SGavin Shan static int pnv_eeh_post_init(void) 22329310e5eSGavin Shan { 22429310e5eSGavin Shan struct pci_controller *hose; 22529310e5eSGavin Shan struct pnv_phb *phb; 22629310e5eSGavin Shan int ret = 0; 22729310e5eSGavin Shan 2284cf17445SGavin Shan /* Register OPAL event notifier */ 2294cf17445SGavin Shan if (!pnv_eeh_nb_init) { 23079231448SAlistair Popple eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 23179231448SAlistair Popple if (eeh_event_irq < 0) { 23279231448SAlistair Popple pr_err("%s: Can't register OPAL event interrupt (%d)\n", 23379231448SAlistair Popple __func__, eeh_event_irq); 23479231448SAlistair Popple return eeh_event_irq; 23579231448SAlistair Popple } 23679231448SAlistair Popple 23779231448SAlistair Popple ret = request_irq(eeh_event_irq, pnv_eeh_event, 23879231448SAlistair Popple IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 23979231448SAlistair Popple if (ret < 0) { 24079231448SAlistair Popple irq_dispose_mapping(eeh_event_irq); 24179231448SAlistair Popple pr_err("%s: Can't request OPAL event interrupt (%d)\n", 24279231448SAlistair Popple __func__, eeh_event_irq); 2434cf17445SGavin Shan return ret; 2444cf17445SGavin Shan } 2454cf17445SGavin Shan 2464cf17445SGavin Shan pnv_eeh_nb_init = true; 2474cf17445SGavin Shan } 2484cf17445SGavin Shan 24979231448SAlistair Popple if (!eeh_enabled()) 25079231448SAlistair Popple disable_irq(eeh_event_irq); 25179231448SAlistair Popple 25229310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 25329310e5eSGavin Shan phb = hose->private_data; 25429310e5eSGavin Shan 2554cf17445SGavin Shan /* 2564cf17445SGavin Shan * If EEH is enabled, we're going to rely on that. 2574cf17445SGavin Shan * Otherwise, we restore to conventional mechanism 2584cf17445SGavin Shan * to clear frozen PE during PCI config access. 2594cf17445SGavin Shan */ 2604cf17445SGavin Shan if (eeh_enabled()) 2614cf17445SGavin Shan phb->flags |= PNV_PHB_FLAG_EEH; 2624cf17445SGavin Shan else 2634cf17445SGavin Shan phb->flags &= ~PNV_PHB_FLAG_EEH; 2644cf17445SGavin Shan 2654cf17445SGavin Shan /* Create debugfs entries */ 2664cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 2674cf17445SGavin Shan if (phb->has_dbgfs || !phb->dbgfs) 2684cf17445SGavin Shan continue; 2694cf17445SGavin Shan 2704cf17445SGavin Shan phb->has_dbgfs = 1; 2714cf17445SGavin Shan debugfs_create_file("err_injct", 0200, 2724cf17445SGavin Shan phb->dbgfs, hose, 2734cf17445SGavin Shan &pnv_eeh_ei_fops); 2744cf17445SGavin Shan 2754cf17445SGavin Shan debugfs_create_file("err_injct_outbound", 0600, 2764cf17445SGavin Shan phb->dbgfs, hose, 2774cf17445SGavin Shan &pnv_eeh_outb_dbgfs_ops); 2784cf17445SGavin Shan debugfs_create_file("err_injct_inboundA", 0600, 2794cf17445SGavin Shan phb->dbgfs, hose, 2804cf17445SGavin Shan &pnv_eeh_inbA_dbgfs_ops); 2814cf17445SGavin Shan debugfs_create_file("err_injct_inboundB", 0600, 2824cf17445SGavin Shan phb->dbgfs, hose, 2834cf17445SGavin Shan &pnv_eeh_inbB_dbgfs_ops); 2844cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 28529310e5eSGavin Shan } 2864cf17445SGavin Shan 28729310e5eSGavin Shan 28829310e5eSGavin Shan return ret; 28929310e5eSGavin Shan } 29029310e5eSGavin Shan 291ff57b454SGavin Shan static int pnv_eeh_cap_start(struct pci_dn *pdn) 292ff57b454SGavin Shan { 293ff57b454SGavin Shan u32 status; 294ff57b454SGavin Shan 295ff57b454SGavin Shan if (!pdn) 296ff57b454SGavin Shan return 0; 297ff57b454SGavin Shan 298ff57b454SGavin Shan pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 299ff57b454SGavin Shan if (!(status & PCI_STATUS_CAP_LIST)) 300ff57b454SGavin Shan return 0; 301ff57b454SGavin Shan 302ff57b454SGavin Shan return PCI_CAPABILITY_LIST; 303ff57b454SGavin Shan } 304ff57b454SGavin Shan 305ff57b454SGavin Shan static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 306ff57b454SGavin Shan { 307ff57b454SGavin Shan int pos = pnv_eeh_cap_start(pdn); 308ff57b454SGavin Shan int cnt = 48; /* Maximal number of capabilities */ 309ff57b454SGavin Shan u32 id; 310ff57b454SGavin Shan 311ff57b454SGavin Shan if (!pos) 312ff57b454SGavin Shan return 0; 313ff57b454SGavin Shan 314ff57b454SGavin Shan while (cnt--) { 315ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos, 1, &pos); 316ff57b454SGavin Shan if (pos < 0x40) 317ff57b454SGavin Shan break; 318ff57b454SGavin Shan 319ff57b454SGavin Shan pos &= ~3; 320ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 321ff57b454SGavin Shan if (id == 0xff) 322ff57b454SGavin Shan break; 323ff57b454SGavin Shan 324ff57b454SGavin Shan /* Found */ 325ff57b454SGavin Shan if (id == cap) 326ff57b454SGavin Shan return pos; 327ff57b454SGavin Shan 328ff57b454SGavin Shan /* Next one */ 329ff57b454SGavin Shan pos += PCI_CAP_LIST_NEXT; 330ff57b454SGavin Shan } 331ff57b454SGavin Shan 332ff57b454SGavin Shan return 0; 333ff57b454SGavin Shan } 334ff57b454SGavin Shan 335ff57b454SGavin Shan static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 336ff57b454SGavin Shan { 337ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 338ff57b454SGavin Shan u32 header; 339ff57b454SGavin Shan int pos = 256, ttl = (4096 - 256) / 8; 340ff57b454SGavin Shan 341ff57b454SGavin Shan if (!edev || !edev->pcie_cap) 342ff57b454SGavin Shan return 0; 343ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 344ff57b454SGavin Shan return 0; 345ff57b454SGavin Shan else if (!header) 346ff57b454SGavin Shan return 0; 347ff57b454SGavin Shan 348ff57b454SGavin Shan while (ttl-- > 0) { 349ff57b454SGavin Shan if (PCI_EXT_CAP_ID(header) == cap && pos) 350ff57b454SGavin Shan return pos; 351ff57b454SGavin Shan 352ff57b454SGavin Shan pos = PCI_EXT_CAP_NEXT(header); 353ff57b454SGavin Shan if (pos < 256) 354ff57b454SGavin Shan break; 355ff57b454SGavin Shan 356ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 357ff57b454SGavin Shan break; 358ff57b454SGavin Shan } 359ff57b454SGavin Shan 360ff57b454SGavin Shan return 0; 361ff57b454SGavin Shan } 362ff57b454SGavin Shan 36329310e5eSGavin Shan /** 364ff57b454SGavin Shan * pnv_eeh_probe - Do probe on PCI device 365ff57b454SGavin Shan * @pdn: PCI device node 366ff57b454SGavin Shan * @data: unused 36729310e5eSGavin Shan * 36829310e5eSGavin Shan * When EEH module is installed during system boot, all PCI devices 36929310e5eSGavin Shan * are checked one by one to see if it supports EEH. The function 37029310e5eSGavin Shan * is introduced for the purpose. By default, EEH has been enabled 37129310e5eSGavin Shan * on all PCI devices. That's to say, we only need do necessary 37229310e5eSGavin Shan * initialization on the corresponding eeh device and create PE 37329310e5eSGavin Shan * accordingly. 37429310e5eSGavin Shan * 37529310e5eSGavin Shan * It's notable that's unsafe to retrieve the EEH device through 37629310e5eSGavin Shan * the corresponding PCI device. During the PCI device hotplug, which 37729310e5eSGavin Shan * was possiblly triggered by EEH core, the binding between EEH device 37829310e5eSGavin Shan * and the PCI device isn't built yet. 37929310e5eSGavin Shan */ 380ff57b454SGavin Shan static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 38129310e5eSGavin Shan { 382ff57b454SGavin Shan struct pci_controller *hose = pdn->phb; 38329310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 384ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 385ff57b454SGavin Shan uint32_t pcie_flags; 386dadcd6d6SMike Qiu int ret; 38729310e5eSGavin Shan 38829310e5eSGavin Shan /* 38929310e5eSGavin Shan * When probing the root bridge, which doesn't have any 39029310e5eSGavin Shan * subordinate PCI devices. We don't have OF node for 39129310e5eSGavin Shan * the root bridge. So it's not reasonable to continue 39229310e5eSGavin Shan * the probing. 39329310e5eSGavin Shan */ 394ff57b454SGavin Shan if (!edev || edev->pe) 395ff57b454SGavin Shan return NULL; 39629310e5eSGavin Shan 39729310e5eSGavin Shan /* Skip for PCI-ISA bridge */ 398ff57b454SGavin Shan if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 399ff57b454SGavin Shan return NULL; 40029310e5eSGavin Shan 40129310e5eSGavin Shan /* Initialize eeh device */ 402ff57b454SGavin Shan edev->class_code = pdn->class_code; 403ab55d218SGavin Shan edev->mode &= 0xFFFFFF00; 404ff57b454SGavin Shan edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 405ff57b454SGavin Shan edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 406ff57b454SGavin Shan edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 407ff57b454SGavin Shan if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 4084b83bd45SGavin Shan edev->mode |= EEH_DEV_BRIDGE; 409ff57b454SGavin Shan if (edev->pcie_cap) { 410ff57b454SGavin Shan pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 411ff57b454SGavin Shan 2, &pcie_flags); 412ff57b454SGavin Shan pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 413ff57b454SGavin Shan if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 4144b83bd45SGavin Shan edev->mode |= EEH_DEV_ROOT_PORT; 415ff57b454SGavin Shan else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 4164b83bd45SGavin Shan edev->mode |= EEH_DEV_DS_PORT; 417ff57b454SGavin Shan } 4184b83bd45SGavin Shan } 4194b83bd45SGavin Shan 420ff57b454SGavin Shan edev->config_addr = (pdn->busno << 8) | (pdn->devfn); 421ff57b454SGavin Shan edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr]; 42229310e5eSGavin Shan 42329310e5eSGavin Shan /* Create PE */ 424dadcd6d6SMike Qiu ret = eeh_add_to_parent_pe(edev); 425dadcd6d6SMike Qiu if (ret) { 426ff57b454SGavin Shan pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%d)\n", 427ff57b454SGavin Shan __func__, hose->global_number, pdn->busno, 428ff57b454SGavin Shan PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 429ff57b454SGavin Shan return NULL; 430dadcd6d6SMike Qiu } 431dadcd6d6SMike Qiu 432dadcd6d6SMike Qiu /* 433b6541db1SGavin Shan * If the PE contains any one of following adapters, the 434b6541db1SGavin Shan * PCI config space can't be accessed when dumping EEH log. 435b6541db1SGavin Shan * Otherwise, we will run into fenced PHB caused by shortage 436b6541db1SGavin Shan * of outbound credits in the adapter. The PCI config access 437b6541db1SGavin Shan * should be blocked until PE reset. MMIO access is dropped 438b6541db1SGavin Shan * by hardware certainly. In order to drop PCI config requests, 439b6541db1SGavin Shan * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 440b6541db1SGavin Shan * will be checked in the backend for PE state retrival. If 441b6541db1SGavin Shan * the PE becomes frozen for the first time and the flag has 442b6541db1SGavin Shan * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 443b6541db1SGavin Shan * that PE to block its config space. 444b6541db1SGavin Shan * 445b6541db1SGavin Shan * Broadcom Austin 4-ports NICs (14e4:1657) 446179ea48bSGavin Shan * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 447b6541db1SGavin Shan */ 448ff57b454SGavin Shan if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 449ff57b454SGavin Shan pdn->device_id == 0x1657) || 450ff57b454SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 451ff57b454SGavin Shan pdn->device_id == 0x168e)) 452b6541db1SGavin Shan edev->pe->state |= EEH_PE_CFG_RESTRICTED; 453b6541db1SGavin Shan 454b6541db1SGavin Shan /* 455dadcd6d6SMike Qiu * Cache the PE primary bus, which can't be fetched when 456dadcd6d6SMike Qiu * full hotplug is in progress. In that case, all child 457dadcd6d6SMike Qiu * PCI devices of the PE are expected to be removed prior 458dadcd6d6SMike Qiu * to PE reset. 459dadcd6d6SMike Qiu */ 460dadcd6d6SMike Qiu if (!edev->pe->bus) 461ff57b454SGavin Shan edev->pe->bus = pci_find_bus(hose->global_number, 462ff57b454SGavin Shan pdn->busno); 46329310e5eSGavin Shan 46429310e5eSGavin Shan /* 46529310e5eSGavin Shan * Enable EEH explicitly so that we will do EEH check 46629310e5eSGavin Shan * while accessing I/O stuff 46729310e5eSGavin Shan */ 46805b1721dSGavin Shan eeh_add_flag(EEH_ENABLED); 46929310e5eSGavin Shan 47029310e5eSGavin Shan /* Save memory bars */ 47129310e5eSGavin Shan eeh_save_bars(edev); 47229310e5eSGavin Shan 473ff57b454SGavin Shan return NULL; 47429310e5eSGavin Shan } 47529310e5eSGavin Shan 47629310e5eSGavin Shan /** 47701f3bfb7SGavin Shan * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 47829310e5eSGavin Shan * @pe: EEH PE 47929310e5eSGavin Shan * @option: operation to be issued 48029310e5eSGavin Shan * 48129310e5eSGavin Shan * The function is used to control the EEH functionality globally. 48229310e5eSGavin Shan * Currently, following options are support according to PAPR: 48329310e5eSGavin Shan * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 48429310e5eSGavin Shan */ 48501f3bfb7SGavin Shan static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 48629310e5eSGavin Shan { 48729310e5eSGavin Shan struct pci_controller *hose = pe->phb; 48829310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 4897e3e4f8dSGavin Shan bool freeze_pe = false; 4907e3e4f8dSGavin Shan int opt, ret = 0; 4917e3e4f8dSGavin Shan s64 rc; 49229310e5eSGavin Shan 4937e3e4f8dSGavin Shan /* Sanity check on option */ 4947e3e4f8dSGavin Shan switch (option) { 4957e3e4f8dSGavin Shan case EEH_OPT_DISABLE: 4967e3e4f8dSGavin Shan return -EPERM; 4977e3e4f8dSGavin Shan case EEH_OPT_ENABLE: 4987e3e4f8dSGavin Shan return 0; 4997e3e4f8dSGavin Shan case EEH_OPT_THAW_MMIO: 5007e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 5017e3e4f8dSGavin Shan break; 5027e3e4f8dSGavin Shan case EEH_OPT_THAW_DMA: 5037e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 5047e3e4f8dSGavin Shan break; 5057e3e4f8dSGavin Shan case EEH_OPT_FREEZE_PE: 5067e3e4f8dSGavin Shan freeze_pe = true; 5077e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 5087e3e4f8dSGavin Shan break; 5097e3e4f8dSGavin Shan default: 5107e3e4f8dSGavin Shan pr_warn("%s: Invalid option %d\n", __func__, option); 5117e3e4f8dSGavin Shan return -EINVAL; 5127e3e4f8dSGavin Shan } 5137e3e4f8dSGavin Shan 5147e3e4f8dSGavin Shan /* If PHB supports compound PE, to handle it */ 5157e3e4f8dSGavin Shan if (freeze_pe) { 5167e3e4f8dSGavin Shan if (phb->freeze_pe) { 5177e3e4f8dSGavin Shan phb->freeze_pe(phb, pe->addr); 5187e3e4f8dSGavin Shan } else { 5197e3e4f8dSGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 5207e3e4f8dSGavin Shan pe->addr, opt); 5217e3e4f8dSGavin Shan if (rc != OPAL_SUCCESS) { 5227e3e4f8dSGavin Shan pr_warn("%s: Failure %lld freezing " 5237e3e4f8dSGavin Shan "PHB#%x-PE#%x\n", 5247e3e4f8dSGavin Shan __func__, rc, 5257e3e4f8dSGavin Shan phb->hose->global_number, pe->addr); 5267e3e4f8dSGavin Shan ret = -EIO; 5277e3e4f8dSGavin Shan } 5287e3e4f8dSGavin Shan } 5297e3e4f8dSGavin Shan } else { 5307e3e4f8dSGavin Shan if (phb->unfreeze_pe) { 5317e3e4f8dSGavin Shan ret = phb->unfreeze_pe(phb, pe->addr, opt); 5327e3e4f8dSGavin Shan } else { 5337e3e4f8dSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 5347e3e4f8dSGavin Shan pe->addr, opt); 5357e3e4f8dSGavin Shan if (rc != OPAL_SUCCESS) { 5367e3e4f8dSGavin Shan pr_warn("%s: Failure %lld enable %d " 5377e3e4f8dSGavin Shan "for PHB#%x-PE#%x\n", 5387e3e4f8dSGavin Shan __func__, rc, option, 5397e3e4f8dSGavin Shan phb->hose->global_number, pe->addr); 5407e3e4f8dSGavin Shan ret = -EIO; 5417e3e4f8dSGavin Shan } 5427e3e4f8dSGavin Shan } 5437e3e4f8dSGavin Shan } 54429310e5eSGavin Shan 54529310e5eSGavin Shan return ret; 54629310e5eSGavin Shan } 54729310e5eSGavin Shan 54829310e5eSGavin Shan /** 54901f3bfb7SGavin Shan * pnv_eeh_get_pe_addr - Retrieve PE address 55029310e5eSGavin Shan * @pe: EEH PE 55129310e5eSGavin Shan * 55229310e5eSGavin Shan * Retrieve the PE address according to the given tranditional 55329310e5eSGavin Shan * PCI BDF (Bus/Device/Function) address. 55429310e5eSGavin Shan */ 55501f3bfb7SGavin Shan static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 55629310e5eSGavin Shan { 55729310e5eSGavin Shan return pe->addr; 55829310e5eSGavin Shan } 55929310e5eSGavin Shan 56040ae5f69SGavin Shan static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 56140ae5f69SGavin Shan { 56240ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 56340ae5f69SGavin Shan s64 rc; 56440ae5f69SGavin Shan 56540ae5f69SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 56640ae5f69SGavin Shan PNV_PCI_DIAG_BUF_SIZE); 56740ae5f69SGavin Shan if (rc != OPAL_SUCCESS) 56840ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 56940ae5f69SGavin Shan __func__, rc, pe->phb->global_number); 57040ae5f69SGavin Shan } 57140ae5f69SGavin Shan 57240ae5f69SGavin Shan static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 57340ae5f69SGavin Shan { 57440ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 57540ae5f69SGavin Shan u8 fstate; 57640ae5f69SGavin Shan __be16 pcierr; 57740ae5f69SGavin Shan s64 rc; 57840ae5f69SGavin Shan int result = 0; 57940ae5f69SGavin Shan 58040ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 58140ae5f69SGavin Shan pe->addr, 58240ae5f69SGavin Shan &fstate, 58340ae5f69SGavin Shan &pcierr, 58440ae5f69SGavin Shan NULL); 58540ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 58640ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x state\n", 58740ae5f69SGavin Shan __func__, rc, phb->hose->global_number); 58840ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 58940ae5f69SGavin Shan } 59040ae5f69SGavin Shan 59140ae5f69SGavin Shan /* 59240ae5f69SGavin Shan * Check PHB state. If the PHB is frozen for the 59340ae5f69SGavin Shan * first time, to dump the PHB diag-data. 59440ae5f69SGavin Shan */ 59540ae5f69SGavin Shan if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 59640ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 59740ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 59840ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 59940ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 60040ae5f69SGavin Shan } else if (!(pe->state & EEH_PE_ISOLATED)) { 60140ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 60240ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 60340ae5f69SGavin Shan 60440ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 60540ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 60640ae5f69SGavin Shan } 60740ae5f69SGavin Shan 60840ae5f69SGavin Shan return result; 60940ae5f69SGavin Shan } 61040ae5f69SGavin Shan 61140ae5f69SGavin Shan static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 61240ae5f69SGavin Shan { 61340ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 61440ae5f69SGavin Shan u8 fstate; 61540ae5f69SGavin Shan __be16 pcierr; 61640ae5f69SGavin Shan s64 rc; 61740ae5f69SGavin Shan int result; 61840ae5f69SGavin Shan 61940ae5f69SGavin Shan /* 62040ae5f69SGavin Shan * We don't clobber hardware frozen state until PE 62140ae5f69SGavin Shan * reset is completed. In order to keep EEH core 62240ae5f69SGavin Shan * moving forward, we have to return operational 62340ae5f69SGavin Shan * state during PE reset. 62440ae5f69SGavin Shan */ 62540ae5f69SGavin Shan if (pe->state & EEH_PE_RESET) { 62640ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 62740ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 62840ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 62940ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 63040ae5f69SGavin Shan return result; 63140ae5f69SGavin Shan } 63240ae5f69SGavin Shan 63340ae5f69SGavin Shan /* 63440ae5f69SGavin Shan * Fetch PE state from hardware. If the PHB 63540ae5f69SGavin Shan * supports compound PE, let it handle that. 63640ae5f69SGavin Shan */ 63740ae5f69SGavin Shan if (phb->get_pe_state) { 63840ae5f69SGavin Shan fstate = phb->get_pe_state(phb, pe->addr); 63940ae5f69SGavin Shan } else { 64040ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 64140ae5f69SGavin Shan pe->addr, 64240ae5f69SGavin Shan &fstate, 64340ae5f69SGavin Shan &pcierr, 64440ae5f69SGavin Shan NULL); 64540ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 64640ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 64740ae5f69SGavin Shan __func__, rc, phb->hose->global_number, 64840ae5f69SGavin Shan pe->addr); 64940ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 65040ae5f69SGavin Shan } 65140ae5f69SGavin Shan } 65240ae5f69SGavin Shan 65340ae5f69SGavin Shan /* Figure out state */ 65440ae5f69SGavin Shan switch (fstate) { 65540ae5f69SGavin Shan case OPAL_EEH_STOPPED_NOT_FROZEN: 65640ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 65740ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 65840ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 65940ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 66040ae5f69SGavin Shan break; 66140ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_FREEZE: 66240ae5f69SGavin Shan result = (EEH_STATE_DMA_ACTIVE | 66340ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 66440ae5f69SGavin Shan break; 66540ae5f69SGavin Shan case OPAL_EEH_STOPPED_DMA_FREEZE: 66640ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 66740ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED); 66840ae5f69SGavin Shan break; 66940ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 67040ae5f69SGavin Shan result = 0; 67140ae5f69SGavin Shan break; 67240ae5f69SGavin Shan case OPAL_EEH_STOPPED_RESET: 67340ae5f69SGavin Shan result = EEH_STATE_RESET_ACTIVE; 67440ae5f69SGavin Shan break; 67540ae5f69SGavin Shan case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 67640ae5f69SGavin Shan result = EEH_STATE_UNAVAILABLE; 67740ae5f69SGavin Shan break; 67840ae5f69SGavin Shan case OPAL_EEH_STOPPED_PERM_UNAVAIL: 67940ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 68040ae5f69SGavin Shan break; 68140ae5f69SGavin Shan default: 68240ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 68340ae5f69SGavin Shan pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 68440ae5f69SGavin Shan __func__, phb->hose->global_number, 68540ae5f69SGavin Shan pe->addr, fstate); 68640ae5f69SGavin Shan } 68740ae5f69SGavin Shan 68840ae5f69SGavin Shan /* 68940ae5f69SGavin Shan * If PHB supports compound PE, to freeze all 69040ae5f69SGavin Shan * slave PEs for consistency. 69140ae5f69SGavin Shan * 69240ae5f69SGavin Shan * If the PE is switching to frozen state for the 69340ae5f69SGavin Shan * first time, to dump the PHB diag-data. 69440ae5f69SGavin Shan */ 69540ae5f69SGavin Shan if (!(result & EEH_STATE_NOT_SUPPORT) && 69640ae5f69SGavin Shan !(result & EEH_STATE_UNAVAILABLE) && 69740ae5f69SGavin Shan !(result & EEH_STATE_MMIO_ACTIVE) && 69840ae5f69SGavin Shan !(result & EEH_STATE_DMA_ACTIVE) && 69940ae5f69SGavin Shan !(pe->state & EEH_PE_ISOLATED)) { 70040ae5f69SGavin Shan if (phb->freeze_pe) 70140ae5f69SGavin Shan phb->freeze_pe(phb, pe->addr); 70240ae5f69SGavin Shan 70340ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 70440ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 70540ae5f69SGavin Shan 70640ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 70740ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 70840ae5f69SGavin Shan } 70940ae5f69SGavin Shan 71040ae5f69SGavin Shan return result; 71140ae5f69SGavin Shan } 71240ae5f69SGavin Shan 71329310e5eSGavin Shan /** 71401f3bfb7SGavin Shan * pnv_eeh_get_state - Retrieve PE state 71529310e5eSGavin Shan * @pe: EEH PE 71629310e5eSGavin Shan * @delay: delay while PE state is temporarily unavailable 71729310e5eSGavin Shan * 71829310e5eSGavin Shan * Retrieve the state of the specified PE. For IODA-compitable 71929310e5eSGavin Shan * platform, it should be retrieved from IODA table. Therefore, 72029310e5eSGavin Shan * we prefer passing down to hardware implementation to handle 72129310e5eSGavin Shan * it. 72229310e5eSGavin Shan */ 72301f3bfb7SGavin Shan static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 72429310e5eSGavin Shan { 72540ae5f69SGavin Shan int ret; 72629310e5eSGavin Shan 72740ae5f69SGavin Shan if (pe->type & EEH_PE_PHB) 72840ae5f69SGavin Shan ret = pnv_eeh_get_phb_state(pe); 72940ae5f69SGavin Shan else 73040ae5f69SGavin Shan ret = pnv_eeh_get_pe_state(pe); 73140ae5f69SGavin Shan 73240ae5f69SGavin Shan if (!delay) 73340ae5f69SGavin Shan return ret; 73429310e5eSGavin Shan 73529310e5eSGavin Shan /* 73629310e5eSGavin Shan * If the PE state is temporarily unavailable, 73729310e5eSGavin Shan * to inform the EEH core delay for default 73829310e5eSGavin Shan * period (1 second) 73929310e5eSGavin Shan */ 74029310e5eSGavin Shan *delay = 0; 74129310e5eSGavin Shan if (ret & EEH_STATE_UNAVAILABLE) 74229310e5eSGavin Shan *delay = 1000; 74329310e5eSGavin Shan 74429310e5eSGavin Shan return ret; 74529310e5eSGavin Shan } 74629310e5eSGavin Shan 747cadf364dSGavin Shan static s64 pnv_eeh_phb_poll(struct pnv_phb *phb) 748cadf364dSGavin Shan { 749cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 750cadf364dSGavin Shan 751cadf364dSGavin Shan while (1) { 752cadf364dSGavin Shan rc = opal_pci_poll(phb->opal_id); 753cadf364dSGavin Shan if (rc <= 0) 754cadf364dSGavin Shan break; 755cadf364dSGavin Shan 756cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 757cadf364dSGavin Shan udelay(1000 * rc); 758cadf364dSGavin Shan else 759cadf364dSGavin Shan msleep(rc); 760cadf364dSGavin Shan } 761cadf364dSGavin Shan 762cadf364dSGavin Shan return rc; 763cadf364dSGavin Shan } 764cadf364dSGavin Shan 765cadf364dSGavin Shan int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 766cadf364dSGavin Shan { 767cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 768cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 769cadf364dSGavin Shan 770cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 771cadf364dSGavin Shan __func__, hose->global_number, option); 772cadf364dSGavin Shan 773cadf364dSGavin Shan /* Issue PHB complete reset request */ 774cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL || 775cadf364dSGavin Shan option == EEH_RESET_HOT) 776cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 777cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 778cadf364dSGavin Shan OPAL_ASSERT_RESET); 779cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 780cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 781cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 782cadf364dSGavin Shan OPAL_DEASSERT_RESET); 783cadf364dSGavin Shan if (rc < 0) 784cadf364dSGavin Shan goto out; 785cadf364dSGavin Shan 786cadf364dSGavin Shan /* 787cadf364dSGavin Shan * Poll state of the PHB until the request is done 788cadf364dSGavin Shan * successfully. The PHB reset is usually PHB complete 789cadf364dSGavin Shan * reset followed by hot reset on root bus. So we also 790cadf364dSGavin Shan * need the PCI bus settlement delay. 791cadf364dSGavin Shan */ 792cadf364dSGavin Shan rc = pnv_eeh_phb_poll(phb); 793cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) { 794cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 795cadf364dSGavin Shan udelay(1000 * EEH_PE_RST_SETTLE_TIME); 796cadf364dSGavin Shan else 797cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 798cadf364dSGavin Shan } 799cadf364dSGavin Shan out: 800cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 801cadf364dSGavin Shan return -EIO; 802cadf364dSGavin Shan 803cadf364dSGavin Shan return 0; 804cadf364dSGavin Shan } 805cadf364dSGavin Shan 806cadf364dSGavin Shan static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 807cadf364dSGavin Shan { 808cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 809cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 810cadf364dSGavin Shan 811cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 812cadf364dSGavin Shan __func__, hose->global_number, option); 813cadf364dSGavin Shan 814cadf364dSGavin Shan /* 815cadf364dSGavin Shan * During the reset deassert time, we needn't care 816cadf364dSGavin Shan * the reset scope because the firmware does nothing 817cadf364dSGavin Shan * for fundamental or hot reset during deassert phase. 818cadf364dSGavin Shan */ 819cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL) 820cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 821cadf364dSGavin Shan OPAL_RESET_PCI_FUNDAMENTAL, 822cadf364dSGavin Shan OPAL_ASSERT_RESET); 823cadf364dSGavin Shan else if (option == EEH_RESET_HOT) 824cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 825cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 826cadf364dSGavin Shan OPAL_ASSERT_RESET); 827cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 828cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 829cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 830cadf364dSGavin Shan OPAL_DEASSERT_RESET); 831cadf364dSGavin Shan if (rc < 0) 832cadf364dSGavin Shan goto out; 833cadf364dSGavin Shan 834cadf364dSGavin Shan /* Poll state of the PHB until the request is done */ 835cadf364dSGavin Shan rc = pnv_eeh_phb_poll(phb); 836cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) 837cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 838cadf364dSGavin Shan out: 839cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 840cadf364dSGavin Shan return -EIO; 841cadf364dSGavin Shan 842cadf364dSGavin Shan return 0; 843cadf364dSGavin Shan } 844cadf364dSGavin Shan 845cadf364dSGavin Shan static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 846cadf364dSGavin Shan { 8470bd78587SGavin Shan struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 8480bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 849cadf364dSGavin Shan int aer = edev ? edev->aer_cap : 0; 850cadf364dSGavin Shan u32 ctrl; 851cadf364dSGavin Shan 852cadf364dSGavin Shan pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 853cadf364dSGavin Shan __func__, pci_domain_nr(dev->bus), 854cadf364dSGavin Shan dev->bus->number, option); 855cadf364dSGavin Shan 856cadf364dSGavin Shan switch (option) { 857cadf364dSGavin Shan case EEH_RESET_FUNDAMENTAL: 858cadf364dSGavin Shan case EEH_RESET_HOT: 859cadf364dSGavin Shan /* Don't report linkDown event */ 860cadf364dSGavin Shan if (aer) { 8610bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 862cadf364dSGavin Shan 4, &ctrl); 863cadf364dSGavin Shan ctrl |= PCI_ERR_UNC_SURPDN; 8640bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 865cadf364dSGavin Shan 4, ctrl); 866cadf364dSGavin Shan } 867cadf364dSGavin Shan 8680bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 869cadf364dSGavin Shan ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 8700bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 871cadf364dSGavin Shan 872cadf364dSGavin Shan msleep(EEH_PE_RST_HOLD_TIME); 873cadf364dSGavin Shan break; 874cadf364dSGavin Shan case EEH_RESET_DEACTIVATE: 8750bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 876cadf364dSGavin Shan ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 8770bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 878cadf364dSGavin Shan 879cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 880cadf364dSGavin Shan 881cadf364dSGavin Shan /* Continue reporting linkDown event */ 882cadf364dSGavin Shan if (aer) { 8830bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 884cadf364dSGavin Shan 4, &ctrl); 885cadf364dSGavin Shan ctrl &= ~PCI_ERR_UNC_SURPDN; 8860bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 887cadf364dSGavin Shan 4, ctrl); 888cadf364dSGavin Shan } 889cadf364dSGavin Shan 890cadf364dSGavin Shan break; 891cadf364dSGavin Shan } 892cadf364dSGavin Shan 893cadf364dSGavin Shan return 0; 894cadf364dSGavin Shan } 895cadf364dSGavin Shan 896cadf364dSGavin Shan void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 897cadf364dSGavin Shan { 898cadf364dSGavin Shan struct pci_controller *hose; 899cadf364dSGavin Shan 900cadf364dSGavin Shan if (pci_is_root_bus(dev->bus)) { 901cadf364dSGavin Shan hose = pci_bus_to_host(dev->bus); 902cadf364dSGavin Shan pnv_eeh_root_reset(hose, EEH_RESET_HOT); 903cadf364dSGavin Shan pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 904cadf364dSGavin Shan } else { 905cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 906cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 907cadf364dSGavin Shan } 908cadf364dSGavin Shan } 909cadf364dSGavin Shan 91029310e5eSGavin Shan /** 91101f3bfb7SGavin Shan * pnv_eeh_reset - Reset the specified PE 91229310e5eSGavin Shan * @pe: EEH PE 91329310e5eSGavin Shan * @option: reset option 91429310e5eSGavin Shan * 915cadf364dSGavin Shan * Do reset on the indicated PE. For PCI bus sensitive PE, 916cadf364dSGavin Shan * we need to reset the parent p2p bridge. The PHB has to 917cadf364dSGavin Shan * be reinitialized if the p2p bridge is root bridge. For 918cadf364dSGavin Shan * PCI device sensitive PE, we will try to reset the device 919cadf364dSGavin Shan * through FLR. For now, we don't have OPAL APIs to do HARD 920cadf364dSGavin Shan * reset yet, so all reset would be SOFT (HOT) reset. 92129310e5eSGavin Shan */ 92201f3bfb7SGavin Shan static int pnv_eeh_reset(struct eeh_pe *pe, int option) 92329310e5eSGavin Shan { 92429310e5eSGavin Shan struct pci_controller *hose = pe->phb; 925cadf364dSGavin Shan struct pci_bus *bus; 926cadf364dSGavin Shan int ret; 92729310e5eSGavin Shan 928cadf364dSGavin Shan /* 929cadf364dSGavin Shan * For PHB reset, we always have complete reset. For those PEs whose 930cadf364dSGavin Shan * primary bus derived from root complex (root bus) or root port 931cadf364dSGavin Shan * (usually bus#1), we apply hot or fundamental reset on the root port. 932cadf364dSGavin Shan * For other PEs, we always have hot reset on the PE primary bus. 933cadf364dSGavin Shan * 934cadf364dSGavin Shan * Here, we have different design to pHyp, which always clear the 935cadf364dSGavin Shan * frozen state during PE reset. However, the good idea here from 936cadf364dSGavin Shan * benh is to keep frozen state before we get PE reset done completely 937cadf364dSGavin Shan * (until BAR restore). With the frozen state, HW drops illegal IO 938cadf364dSGavin Shan * or MMIO access, which can incur recrusive frozen PE during PE 939cadf364dSGavin Shan * reset. The side effect is that EEH core has to clear the frozen 940cadf364dSGavin Shan * state explicitly after BAR restore. 941cadf364dSGavin Shan */ 942cadf364dSGavin Shan if (pe->type & EEH_PE_PHB) { 943cadf364dSGavin Shan ret = pnv_eeh_phb_reset(hose, option); 944cadf364dSGavin Shan } else { 945cadf364dSGavin Shan struct pnv_phb *phb; 946cadf364dSGavin Shan s64 rc; 947cadf364dSGavin Shan 948cadf364dSGavin Shan /* 949cadf364dSGavin Shan * The frozen PE might be caused by PAPR error injection 950cadf364dSGavin Shan * registers, which are expected to be cleared after hitting 951cadf364dSGavin Shan * frozen PE as stated in the hardware spec. Unfortunately, 952cadf364dSGavin Shan * that's not true on P7IOC. So we have to clear it manually 953cadf364dSGavin Shan * to avoid recursive EEH errors during recovery. 954cadf364dSGavin Shan */ 955cadf364dSGavin Shan phb = hose->private_data; 956cadf364dSGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC && 957cadf364dSGavin Shan (option == EEH_RESET_HOT || 958cadf364dSGavin Shan option == EEH_RESET_FUNDAMENTAL)) { 959cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 960cadf364dSGavin Shan OPAL_RESET_PHB_ERROR, 961cadf364dSGavin Shan OPAL_ASSERT_RESET); 962cadf364dSGavin Shan if (rc != OPAL_SUCCESS) { 963cadf364dSGavin Shan pr_warn("%s: Failure %lld clearing " 964cadf364dSGavin Shan "error injection registers\n", 965cadf364dSGavin Shan __func__, rc); 966cadf364dSGavin Shan return -EIO; 967cadf364dSGavin Shan } 968cadf364dSGavin Shan } 969cadf364dSGavin Shan 970cadf364dSGavin Shan bus = eeh_pe_bus_get(pe); 971cadf364dSGavin Shan if (pci_is_root_bus(bus) || 972cadf364dSGavin Shan pci_is_root_bus(bus->parent)) 973cadf364dSGavin Shan ret = pnv_eeh_root_reset(hose, option); 974cadf364dSGavin Shan else 975cadf364dSGavin Shan ret = pnv_eeh_bridge_reset(bus->self, option); 976cadf364dSGavin Shan } 97729310e5eSGavin Shan 97829310e5eSGavin Shan return ret; 97929310e5eSGavin Shan } 98029310e5eSGavin Shan 98129310e5eSGavin Shan /** 98201f3bfb7SGavin Shan * pnv_eeh_wait_state - Wait for PE state 98329310e5eSGavin Shan * @pe: EEH PE 9842ac3990cSWei Yang * @max_wait: maximal period in millisecond 98529310e5eSGavin Shan * 98629310e5eSGavin Shan * Wait for the state of associated PE. It might take some time 98729310e5eSGavin Shan * to retrieve the PE's state. 98829310e5eSGavin Shan */ 98901f3bfb7SGavin Shan static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) 99029310e5eSGavin Shan { 99129310e5eSGavin Shan int ret; 99229310e5eSGavin Shan int mwait; 99329310e5eSGavin Shan 99429310e5eSGavin Shan while (1) { 99501f3bfb7SGavin Shan ret = pnv_eeh_get_state(pe, &mwait); 99629310e5eSGavin Shan 99729310e5eSGavin Shan /* 99829310e5eSGavin Shan * If the PE's state is temporarily unavailable, 99929310e5eSGavin Shan * we have to wait for the specified time. Otherwise, 100029310e5eSGavin Shan * the PE's state will be returned immediately. 100129310e5eSGavin Shan */ 100229310e5eSGavin Shan if (ret != EEH_STATE_UNAVAILABLE) 100329310e5eSGavin Shan return ret; 100429310e5eSGavin Shan 100529310e5eSGavin Shan if (max_wait <= 0) { 10060dae2743SGavin Shan pr_warn("%s: Timeout getting PE#%x's state (%d)\n", 100729310e5eSGavin Shan __func__, pe->addr, max_wait); 100829310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 100929310e5eSGavin Shan } 101029310e5eSGavin Shan 1011e17866d5SWei Yang max_wait -= mwait; 101229310e5eSGavin Shan msleep(mwait); 101329310e5eSGavin Shan } 101429310e5eSGavin Shan 101529310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 101629310e5eSGavin Shan } 101729310e5eSGavin Shan 101829310e5eSGavin Shan /** 101901f3bfb7SGavin Shan * pnv_eeh_get_log - Retrieve error log 102029310e5eSGavin Shan * @pe: EEH PE 102129310e5eSGavin Shan * @severity: temporary or permanent error log 102229310e5eSGavin Shan * @drv_log: driver log to be combined with retrieved error log 102329310e5eSGavin Shan * @len: length of driver log 102429310e5eSGavin Shan * 102529310e5eSGavin Shan * Retrieve the temporary or permanent error from the PE. 102629310e5eSGavin Shan */ 102701f3bfb7SGavin Shan static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 102829310e5eSGavin Shan char *drv_log, unsigned long len) 102929310e5eSGavin Shan { 103095edcdeaSGavin Shan if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 103195edcdeaSGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 103229310e5eSGavin Shan 103395edcdeaSGavin Shan return 0; 103429310e5eSGavin Shan } 103529310e5eSGavin Shan 103629310e5eSGavin Shan /** 103701f3bfb7SGavin Shan * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 103829310e5eSGavin Shan * @pe: EEH PE 103929310e5eSGavin Shan * 104029310e5eSGavin Shan * The function will be called to reconfigure the bridges included 104129310e5eSGavin Shan * in the specified PE so that the mulfunctional PE would be recovered 104229310e5eSGavin Shan * again. 104329310e5eSGavin Shan */ 104401f3bfb7SGavin Shan static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 104529310e5eSGavin Shan { 1046bbe170edSGavin Shan return 0; 104729310e5eSGavin Shan } 104829310e5eSGavin Shan 104929310e5eSGavin Shan /** 105001f3bfb7SGavin Shan * pnv_pe_err_inject - Inject specified error to the indicated PE 1051131c123aSGavin Shan * @pe: the indicated PE 1052131c123aSGavin Shan * @type: error type 1053131c123aSGavin Shan * @func: specific error type 1054131c123aSGavin Shan * @addr: address 1055131c123aSGavin Shan * @mask: address mask 1056131c123aSGavin Shan * 1057131c123aSGavin Shan * The routine is called to inject specified error, which is 1058131c123aSGavin Shan * determined by @type and @func, to the indicated PE for 1059131c123aSGavin Shan * testing purpose. 1060131c123aSGavin Shan */ 106101f3bfb7SGavin Shan static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1062131c123aSGavin Shan unsigned long addr, unsigned long mask) 1063131c123aSGavin Shan { 1064131c123aSGavin Shan struct pci_controller *hose = pe->phb; 1065131c123aSGavin Shan struct pnv_phb *phb = hose->private_data; 1066fa646c3cSGavin Shan s64 rc; 1067131c123aSGavin Shan 1068fa646c3cSGavin Shan /* Sanity check on error type */ 1069fa646c3cSGavin Shan if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1070fa646c3cSGavin Shan type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1071fa646c3cSGavin Shan pr_warn("%s: Invalid error type %d\n", 1072fa646c3cSGavin Shan __func__, type); 1073fa646c3cSGavin Shan return -ERANGE; 1074fa646c3cSGavin Shan } 1075131c123aSGavin Shan 1076fa646c3cSGavin Shan if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1077fa646c3cSGavin Shan func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1078fa646c3cSGavin Shan pr_warn("%s: Invalid error function %d\n", 1079fa646c3cSGavin Shan __func__, func); 1080fa646c3cSGavin Shan return -ERANGE; 1081fa646c3cSGavin Shan } 1082fa646c3cSGavin Shan 1083fa646c3cSGavin Shan /* Firmware supports error injection ? */ 1084fa646c3cSGavin Shan if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1085fa646c3cSGavin Shan pr_warn("%s: Firmware doesn't support error injection\n", 1086fa646c3cSGavin Shan __func__); 1087fa646c3cSGavin Shan return -ENXIO; 1088fa646c3cSGavin Shan } 1089fa646c3cSGavin Shan 1090fa646c3cSGavin Shan /* Do error injection */ 1091fa646c3cSGavin Shan rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1092fa646c3cSGavin Shan type, func, addr, mask); 1093fa646c3cSGavin Shan if (rc != OPAL_SUCCESS) { 1094fa646c3cSGavin Shan pr_warn("%s: Failure %lld injecting error " 1095fa646c3cSGavin Shan "%d-%d to PHB#%x-PE#%x\n", 1096fa646c3cSGavin Shan __func__, rc, type, func, 1097fa646c3cSGavin Shan hose->global_number, pe->addr); 1098fa646c3cSGavin Shan return -EIO; 1099fa646c3cSGavin Shan } 1100fa646c3cSGavin Shan 1101fa646c3cSGavin Shan return 0; 1102131c123aSGavin Shan } 1103131c123aSGavin Shan 11040bd78587SGavin Shan static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1105d2cfbcd7SGavin Shan { 11060bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1107d2cfbcd7SGavin Shan 1108d2cfbcd7SGavin Shan if (!edev || !edev->pe) 1109d2cfbcd7SGavin Shan return false; 1110d2cfbcd7SGavin Shan 1111d2cfbcd7SGavin Shan if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1112d2cfbcd7SGavin Shan return true; 1113d2cfbcd7SGavin Shan 1114d2cfbcd7SGavin Shan return false; 1115d2cfbcd7SGavin Shan } 1116d2cfbcd7SGavin Shan 11170bd78587SGavin Shan static int pnv_eeh_read_config(struct pci_dn *pdn, 1118d2cfbcd7SGavin Shan int where, int size, u32 *val) 1119d2cfbcd7SGavin Shan { 11203532a741SGavin Shan if (!pdn) 11213532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 11223532a741SGavin Shan 11230bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) { 1124d2cfbcd7SGavin Shan *val = 0xFFFFFFFF; 1125d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1126d2cfbcd7SGavin Shan } 1127d2cfbcd7SGavin Shan 11283532a741SGavin Shan return pnv_pci_cfg_read(pdn, where, size, val); 1129d2cfbcd7SGavin Shan } 1130d2cfbcd7SGavin Shan 11310bd78587SGavin Shan static int pnv_eeh_write_config(struct pci_dn *pdn, 1132d2cfbcd7SGavin Shan int where, int size, u32 val) 1133d2cfbcd7SGavin Shan { 11343532a741SGavin Shan if (!pdn) 11353532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 11363532a741SGavin Shan 11370bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) 1138d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1139d2cfbcd7SGavin Shan 11403532a741SGavin Shan return pnv_pci_cfg_write(pdn, where, size, val); 1141d2cfbcd7SGavin Shan } 1142d2cfbcd7SGavin Shan 11432a485ad7SGavin Shan static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 11442a485ad7SGavin Shan { 11452a485ad7SGavin Shan /* GEM */ 11462a485ad7SGavin Shan if (data->gemXfir || data->gemRfir || 11472a485ad7SGavin Shan data->gemRirqfir || data->gemMask || data->gemRwof) 11482a485ad7SGavin Shan pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 11492a485ad7SGavin Shan be64_to_cpu(data->gemXfir), 11502a485ad7SGavin Shan be64_to_cpu(data->gemRfir), 11512a485ad7SGavin Shan be64_to_cpu(data->gemRirqfir), 11522a485ad7SGavin Shan be64_to_cpu(data->gemMask), 11532a485ad7SGavin Shan be64_to_cpu(data->gemRwof)); 11542a485ad7SGavin Shan 11552a485ad7SGavin Shan /* LEM */ 11562a485ad7SGavin Shan if (data->lemFir || data->lemErrMask || 11572a485ad7SGavin Shan data->lemAction0 || data->lemAction1 || data->lemWof) 11582a485ad7SGavin Shan pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 11592a485ad7SGavin Shan be64_to_cpu(data->lemFir), 11602a485ad7SGavin Shan be64_to_cpu(data->lemErrMask), 11612a485ad7SGavin Shan be64_to_cpu(data->lemAction0), 11622a485ad7SGavin Shan be64_to_cpu(data->lemAction1), 11632a485ad7SGavin Shan be64_to_cpu(data->lemWof)); 11642a485ad7SGavin Shan } 11652a485ad7SGavin Shan 11662a485ad7SGavin Shan static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 11672a485ad7SGavin Shan { 11682a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 11692a485ad7SGavin Shan struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag; 11702a485ad7SGavin Shan long rc; 11712a485ad7SGavin Shan 11722a485ad7SGavin Shan rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 11732a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 11742a485ad7SGavin Shan pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 11752a485ad7SGavin Shan __func__, phb->hub_id, rc); 11762a485ad7SGavin Shan return; 11772a485ad7SGavin Shan } 11782a485ad7SGavin Shan 11792a485ad7SGavin Shan switch (data->type) { 11802a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_RGC: 11812a485ad7SGavin Shan pr_info("P7IOC diag-data for RGC\n\n"); 11822a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 11832a485ad7SGavin Shan if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 11842a485ad7SGavin Shan pr_info(" RGC: %016llx %016llx\n", 11852a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcStatus), 11862a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcLdcp)); 11872a485ad7SGavin Shan break; 11882a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_BI: 11892a485ad7SGavin Shan pr_info("P7IOC diag-data for BI %s\n\n", 11902a485ad7SGavin Shan data->bi.biDownbound ? "Downbound" : "Upbound"); 11912a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 11922a485ad7SGavin Shan if (data->bi.biLdcp0 || data->bi.biLdcp1 || 11932a485ad7SGavin Shan data->bi.biLdcp2 || data->bi.biFenceStatus) 11942a485ad7SGavin Shan pr_info(" BI: %016llx %016llx %016llx %016llx\n", 11952a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp0), 11962a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp1), 11972a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp2), 11982a485ad7SGavin Shan be64_to_cpu(data->bi.biFenceStatus)); 11992a485ad7SGavin Shan break; 12002a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_CI: 12012a485ad7SGavin Shan pr_info("P7IOC diag-data for CI Port %d\n\n", 12022a485ad7SGavin Shan data->ci.ciPort); 12032a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 12042a485ad7SGavin Shan if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 12052a485ad7SGavin Shan pr_info(" CI: %016llx %016llx\n", 12062a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortStatus), 12072a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortLdcp)); 12082a485ad7SGavin Shan break; 12092a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_MISC: 12102a485ad7SGavin Shan pr_info("P7IOC diag-data for MISC\n\n"); 12112a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 12122a485ad7SGavin Shan break; 12132a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_I2C: 12142a485ad7SGavin Shan pr_info("P7IOC diag-data for I2C\n\n"); 12152a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 12162a485ad7SGavin Shan break; 12172a485ad7SGavin Shan default: 12182a485ad7SGavin Shan pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 12192a485ad7SGavin Shan __func__, phb->hub_id, data->type); 12202a485ad7SGavin Shan } 12212a485ad7SGavin Shan } 12222a485ad7SGavin Shan 12232a485ad7SGavin Shan static int pnv_eeh_get_pe(struct pci_controller *hose, 12242a485ad7SGavin Shan u16 pe_no, struct eeh_pe **pe) 12252a485ad7SGavin Shan { 12262a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 12272a485ad7SGavin Shan struct pnv_ioda_pe *pnv_pe; 12282a485ad7SGavin Shan struct eeh_pe *dev_pe; 12292a485ad7SGavin Shan struct eeh_dev edev; 12302a485ad7SGavin Shan 12312a485ad7SGavin Shan /* 12322a485ad7SGavin Shan * If PHB supports compound PE, to fetch 12332a485ad7SGavin Shan * the master PE because slave PE is invisible 12342a485ad7SGavin Shan * to EEH core. 12352a485ad7SGavin Shan */ 12362a485ad7SGavin Shan pnv_pe = &phb->ioda.pe_array[pe_no]; 12372a485ad7SGavin Shan if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 12382a485ad7SGavin Shan pnv_pe = pnv_pe->master; 12392a485ad7SGavin Shan WARN_ON(!pnv_pe || 12402a485ad7SGavin Shan !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 12412a485ad7SGavin Shan pe_no = pnv_pe->pe_number; 12422a485ad7SGavin Shan } 12432a485ad7SGavin Shan 12442a485ad7SGavin Shan /* Find the PE according to PE# */ 12452a485ad7SGavin Shan memset(&edev, 0, sizeof(struct eeh_dev)); 12462a485ad7SGavin Shan edev.phb = hose; 12472a485ad7SGavin Shan edev.pe_config_addr = pe_no; 12482a485ad7SGavin Shan dev_pe = eeh_pe_get(&edev); 12492a485ad7SGavin Shan if (!dev_pe) 12502a485ad7SGavin Shan return -EEXIST; 12512a485ad7SGavin Shan 12522a485ad7SGavin Shan /* Freeze the (compound) PE */ 12532a485ad7SGavin Shan *pe = dev_pe; 12542a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 12552a485ad7SGavin Shan phb->freeze_pe(phb, pe_no); 12562a485ad7SGavin Shan 12572a485ad7SGavin Shan /* 12582a485ad7SGavin Shan * At this point, we're sure the (compound) PE should 12592a485ad7SGavin Shan * have been frozen. However, we still need poke until 12602a485ad7SGavin Shan * hitting the frozen PE on top level. 12612a485ad7SGavin Shan */ 12622a485ad7SGavin Shan dev_pe = dev_pe->parent; 12632a485ad7SGavin Shan while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 12642a485ad7SGavin Shan int ret; 12652a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | 12662a485ad7SGavin Shan EEH_STATE_DMA_ACTIVE); 12672a485ad7SGavin Shan 12682a485ad7SGavin Shan ret = eeh_ops->get_state(dev_pe, NULL); 12692a485ad7SGavin Shan if (ret <= 0 || (ret & active_flags) == active_flags) { 12702a485ad7SGavin Shan dev_pe = dev_pe->parent; 12712a485ad7SGavin Shan continue; 12722a485ad7SGavin Shan } 12732a485ad7SGavin Shan 12742a485ad7SGavin Shan /* Frozen parent PE */ 12752a485ad7SGavin Shan *pe = dev_pe; 12762a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 12772a485ad7SGavin Shan phb->freeze_pe(phb, dev_pe->addr); 12782a485ad7SGavin Shan 12792a485ad7SGavin Shan /* Next one */ 12802a485ad7SGavin Shan dev_pe = dev_pe->parent; 12812a485ad7SGavin Shan } 12822a485ad7SGavin Shan 12832a485ad7SGavin Shan return 0; 12842a485ad7SGavin Shan } 12852a485ad7SGavin Shan 1286131c123aSGavin Shan /** 128701f3bfb7SGavin Shan * pnv_eeh_next_error - Retrieve next EEH error to handle 128829310e5eSGavin Shan * @pe: Affected PE 128929310e5eSGavin Shan * 12902a485ad7SGavin Shan * The function is expected to be called by EEH core while it gets 12912a485ad7SGavin Shan * special EEH event (without binding PE). The function calls to 12922a485ad7SGavin Shan * OPAL APIs for next error to handle. The informational error is 12932a485ad7SGavin Shan * handled internally by platform. However, the dead IOC, dead PHB, 12942a485ad7SGavin Shan * fenced PHB and frozen PE should be handled by EEH core eventually. 129529310e5eSGavin Shan */ 129601f3bfb7SGavin Shan static int pnv_eeh_next_error(struct eeh_pe **pe) 129729310e5eSGavin Shan { 129829310e5eSGavin Shan struct pci_controller *hose; 12992a485ad7SGavin Shan struct pnv_phb *phb; 13002a485ad7SGavin Shan struct eeh_pe *phb_pe, *parent_pe; 13012a485ad7SGavin Shan __be64 frozen_pe_no; 13022a485ad7SGavin Shan __be16 err_type, severity; 13032a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 13042a485ad7SGavin Shan long rc; 13052a485ad7SGavin Shan int state, ret = EEH_NEXT_ERR_NONE; 13062a485ad7SGavin Shan 13072a485ad7SGavin Shan /* 130879231448SAlistair Popple * While running here, it's safe to purge the event queue. The 130979231448SAlistair Popple * event should still be masked. 13102a485ad7SGavin Shan */ 13112a485ad7SGavin Shan eeh_remove_event(NULL, false); 131229310e5eSGavin Shan 131329310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 13142a485ad7SGavin Shan /* 13152a485ad7SGavin Shan * If the subordinate PCI buses of the PHB has been 13162a485ad7SGavin Shan * removed or is exactly under error recovery, we 13172a485ad7SGavin Shan * needn't take care of it any more. 13182a485ad7SGavin Shan */ 131929310e5eSGavin Shan phb = hose->private_data; 13202a485ad7SGavin Shan phb_pe = eeh_phb_pe_get(hose); 13212a485ad7SGavin Shan if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 13222a485ad7SGavin Shan continue; 13232a485ad7SGavin Shan 13242a485ad7SGavin Shan rc = opal_pci_next_error(phb->opal_id, 13252a485ad7SGavin Shan &frozen_pe_no, &err_type, &severity); 13262a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 13272a485ad7SGavin Shan pr_devel("%s: Invalid return value on " 13282a485ad7SGavin Shan "PHB#%x (0x%lx) from opal_pci_next_error", 13292a485ad7SGavin Shan __func__, hose->global_number, rc); 13302a485ad7SGavin Shan continue; 13312a485ad7SGavin Shan } 13322a485ad7SGavin Shan 13332a485ad7SGavin Shan /* If the PHB doesn't have error, stop processing */ 13342a485ad7SGavin Shan if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 13352a485ad7SGavin Shan be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 13362a485ad7SGavin Shan pr_devel("%s: No error found on PHB#%x\n", 13372a485ad7SGavin Shan __func__, hose->global_number); 13382a485ad7SGavin Shan continue; 13392a485ad7SGavin Shan } 13402a485ad7SGavin Shan 13412a485ad7SGavin Shan /* 13422a485ad7SGavin Shan * Processing the error. We're expecting the error with 13432a485ad7SGavin Shan * highest priority reported upon multiple errors on the 13442a485ad7SGavin Shan * specific PHB. 13452a485ad7SGavin Shan */ 13462a485ad7SGavin Shan pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 13472a485ad7SGavin Shan __func__, be16_to_cpu(err_type), 13482a485ad7SGavin Shan be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 13492a485ad7SGavin Shan hose->global_number); 13502a485ad7SGavin Shan switch (be16_to_cpu(err_type)) { 13512a485ad7SGavin Shan case OPAL_EEH_IOC_ERROR: 13522a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 13532a485ad7SGavin Shan pr_err("EEH: dead IOC detected\n"); 13542a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_IOC; 13552a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 13562a485ad7SGavin Shan pr_info("EEH: IOC informative error " 13572a485ad7SGavin Shan "detected\n"); 13582a485ad7SGavin Shan pnv_eeh_get_and_dump_hub_diag(hose); 13592a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 13602a485ad7SGavin Shan } 13612a485ad7SGavin Shan 13622a485ad7SGavin Shan break; 13632a485ad7SGavin Shan case OPAL_EEH_PHB_ERROR: 13642a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 13652a485ad7SGavin Shan *pe = phb_pe; 13662a485ad7SGavin Shan pr_err("EEH: dead PHB#%x detected, " 13672a485ad7SGavin Shan "location: %s\n", 13682a485ad7SGavin Shan hose->global_number, 13692a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 13702a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_PHB; 13712a485ad7SGavin Shan } else if (be16_to_cpu(severity) == 13722a485ad7SGavin Shan OPAL_EEH_SEV_PHB_FENCED) { 13732a485ad7SGavin Shan *pe = phb_pe; 13742a485ad7SGavin Shan pr_err("EEH: Fenced PHB#%x detected, " 13752a485ad7SGavin Shan "location: %s\n", 13762a485ad7SGavin Shan hose->global_number, 13772a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 13782a485ad7SGavin Shan ret = EEH_NEXT_ERR_FENCED_PHB; 13792a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 13802a485ad7SGavin Shan pr_info("EEH: PHB#%x informative error " 13812a485ad7SGavin Shan "detected, location: %s\n", 13822a485ad7SGavin Shan hose->global_number, 13832a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 13842a485ad7SGavin Shan pnv_eeh_get_phb_diag(phb_pe); 13852a485ad7SGavin Shan pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 13862a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 13872a485ad7SGavin Shan } 13882a485ad7SGavin Shan 13892a485ad7SGavin Shan break; 13902a485ad7SGavin Shan case OPAL_EEH_PE_ERROR: 13912a485ad7SGavin Shan /* 13922a485ad7SGavin Shan * If we can't find the corresponding PE, we 13932a485ad7SGavin Shan * just try to unfreeze. 13942a485ad7SGavin Shan */ 13952a485ad7SGavin Shan if (pnv_eeh_get_pe(hose, 13962a485ad7SGavin Shan be64_to_cpu(frozen_pe_no), pe)) { 13972a485ad7SGavin Shan /* Try best to clear it */ 13982a485ad7SGavin Shan pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 13992a485ad7SGavin Shan hose->global_number, frozen_pe_no); 14002a485ad7SGavin Shan pr_info("EEH: PHB location: %s\n", 14012a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14022a485ad7SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 14032a485ad7SGavin Shan frozen_pe_no, 14042a485ad7SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 14052a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 14062a485ad7SGavin Shan } else if ((*pe)->state & EEH_PE_ISOLATED || 14072a485ad7SGavin Shan eeh_pe_passed(*pe)) { 14082a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 14092a485ad7SGavin Shan } else { 14102a485ad7SGavin Shan pr_err("EEH: Frozen PE#%x " 14112a485ad7SGavin Shan "on PHB#%x detected\n", 14122a485ad7SGavin Shan (*pe)->addr, 14132a485ad7SGavin Shan (*pe)->phb->global_number); 14142a485ad7SGavin Shan pr_err("EEH: PE location: %s, " 14152a485ad7SGavin Shan "PHB location: %s\n", 14162a485ad7SGavin Shan eeh_pe_loc_get(*pe), 14172a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14182a485ad7SGavin Shan ret = EEH_NEXT_ERR_FROZEN_PE; 14192a485ad7SGavin Shan } 14202a485ad7SGavin Shan 14212a485ad7SGavin Shan break; 14222a485ad7SGavin Shan default: 14232a485ad7SGavin Shan pr_warn("%s: Unexpected error type %d\n", 14242a485ad7SGavin Shan __func__, be16_to_cpu(err_type)); 14252a485ad7SGavin Shan } 14262a485ad7SGavin Shan 14272a485ad7SGavin Shan /* 14282a485ad7SGavin Shan * EEH core will try recover from fenced PHB or 14292a485ad7SGavin Shan * frozen PE. In the time for frozen PE, EEH core 14302a485ad7SGavin Shan * enable IO path for that before collecting logs, 14312a485ad7SGavin Shan * but it ruins the site. So we have to dump the 14322a485ad7SGavin Shan * log in advance here. 14332a485ad7SGavin Shan */ 14342a485ad7SGavin Shan if ((ret == EEH_NEXT_ERR_FROZEN_PE || 14352a485ad7SGavin Shan ret == EEH_NEXT_ERR_FENCED_PHB) && 14362a485ad7SGavin Shan !((*pe)->state & EEH_PE_ISOLATED)) { 14372a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 14382a485ad7SGavin Shan pnv_eeh_get_phb_diag(*pe); 14392a485ad7SGavin Shan 14402a485ad7SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 14412a485ad7SGavin Shan pnv_pci_dump_phb_diag_data((*pe)->phb, 14422a485ad7SGavin Shan (*pe)->data); 14432a485ad7SGavin Shan } 14442a485ad7SGavin Shan 14452a485ad7SGavin Shan /* 14462a485ad7SGavin Shan * We probably have the frozen parent PE out there and 14472a485ad7SGavin Shan * we need have to handle frozen parent PE firstly. 14482a485ad7SGavin Shan */ 14492a485ad7SGavin Shan if (ret == EEH_NEXT_ERR_FROZEN_PE) { 14502a485ad7SGavin Shan parent_pe = (*pe)->parent; 14512a485ad7SGavin Shan while (parent_pe) { 14522a485ad7SGavin Shan /* Hit the ceiling ? */ 14532a485ad7SGavin Shan if (parent_pe->type & EEH_PE_PHB) 14542a485ad7SGavin Shan break; 14552a485ad7SGavin Shan 14562a485ad7SGavin Shan /* Frozen parent PE ? */ 14572a485ad7SGavin Shan state = eeh_ops->get_state(parent_pe, NULL); 14582a485ad7SGavin Shan if (state > 0 && 14592a485ad7SGavin Shan (state & active_flags) != active_flags) 14602a485ad7SGavin Shan *pe = parent_pe; 14612a485ad7SGavin Shan 14622a485ad7SGavin Shan /* Next parent level */ 14632a485ad7SGavin Shan parent_pe = parent_pe->parent; 14642a485ad7SGavin Shan } 14652a485ad7SGavin Shan 14662a485ad7SGavin Shan /* We possibly migrate to another PE */ 14672a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 14682a485ad7SGavin Shan } 14692a485ad7SGavin Shan 14702a485ad7SGavin Shan /* 14712a485ad7SGavin Shan * If we have no errors on the specific PHB or only 14722a485ad7SGavin Shan * informative error there, we continue poking it. 14732a485ad7SGavin Shan * Otherwise, we need actions to be taken by upper 14742a485ad7SGavin Shan * layer. 14752a485ad7SGavin Shan */ 14762a485ad7SGavin Shan if (ret > EEH_NEXT_ERR_INF) 147729310e5eSGavin Shan break; 147829310e5eSGavin Shan } 147929310e5eSGavin Shan 148079231448SAlistair Popple /* Unmask the event */ 148179231448SAlistair Popple if (eeh_enabled()) 148279231448SAlistair Popple enable_irq(eeh_event_irq); 148379231448SAlistair Popple 14842a485ad7SGavin Shan return ret; 148529310e5eSGavin Shan } 148629310e5eSGavin Shan 14870bd78587SGavin Shan static int pnv_eeh_restore_config(struct pci_dn *pdn) 14889be3beccSGavin Shan { 14890bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 14909be3beccSGavin Shan struct pnv_phb *phb; 14919be3beccSGavin Shan s64 ret; 14929be3beccSGavin Shan 14939be3beccSGavin Shan if (!edev) 14949be3beccSGavin Shan return -EEXIST; 14959be3beccSGavin Shan 14969be3beccSGavin Shan phb = edev->phb->private_data; 14979be3beccSGavin Shan ret = opal_pci_reinit(phb->opal_id, 14989be3beccSGavin Shan OPAL_REINIT_PCI_DEV, edev->config_addr); 14999be3beccSGavin Shan if (ret) { 15009be3beccSGavin Shan pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 15019be3beccSGavin Shan __func__, edev->config_addr, ret); 15029be3beccSGavin Shan return -EIO; 15039be3beccSGavin Shan } 15049be3beccSGavin Shan 15059be3beccSGavin Shan return 0; 15069be3beccSGavin Shan } 15079be3beccSGavin Shan 150801f3bfb7SGavin Shan static struct eeh_ops pnv_eeh_ops = { 150929310e5eSGavin Shan .name = "powernv", 151001f3bfb7SGavin Shan .init = pnv_eeh_init, 151101f3bfb7SGavin Shan .post_init = pnv_eeh_post_init, 1512ff57b454SGavin Shan .probe = pnv_eeh_probe, 151301f3bfb7SGavin Shan .set_option = pnv_eeh_set_option, 151401f3bfb7SGavin Shan .get_pe_addr = pnv_eeh_get_pe_addr, 151501f3bfb7SGavin Shan .get_state = pnv_eeh_get_state, 151601f3bfb7SGavin Shan .reset = pnv_eeh_reset, 151701f3bfb7SGavin Shan .wait_state = pnv_eeh_wait_state, 151801f3bfb7SGavin Shan .get_log = pnv_eeh_get_log, 151901f3bfb7SGavin Shan .configure_bridge = pnv_eeh_configure_bridge, 152001f3bfb7SGavin Shan .err_inject = pnv_eeh_err_inject, 152101f3bfb7SGavin Shan .read_config = pnv_eeh_read_config, 152201f3bfb7SGavin Shan .write_config = pnv_eeh_write_config, 152301f3bfb7SGavin Shan .next_error = pnv_eeh_next_error, 152401f3bfb7SGavin Shan .restore_config = pnv_eeh_restore_config 152529310e5eSGavin Shan }; 152629310e5eSGavin Shan 152729310e5eSGavin Shan /** 152829310e5eSGavin Shan * eeh_powernv_init - Register platform dependent EEH operations 152929310e5eSGavin Shan * 153029310e5eSGavin Shan * EEH initialization on powernv platform. This function should be 153129310e5eSGavin Shan * called before any EEH related functions. 153229310e5eSGavin Shan */ 153329310e5eSGavin Shan static int __init eeh_powernv_init(void) 153429310e5eSGavin Shan { 153529310e5eSGavin Shan int ret = -EINVAL; 153629310e5eSGavin Shan 1537bb593c00SGavin Shan eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE); 153801f3bfb7SGavin Shan ret = eeh_ops_register(&pnv_eeh_ops); 153929310e5eSGavin Shan if (!ret) 154029310e5eSGavin Shan pr_info("EEH: PowerNV platform initialized\n"); 154129310e5eSGavin Shan else 154229310e5eSGavin Shan pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 154329310e5eSGavin Shan 154429310e5eSGavin Shan return ret; 154529310e5eSGavin Shan } 1546b14726c5SMichael Ellerman machine_early_initcall(powernv, eeh_powernv_init); 1547