129310e5eSGavin Shan /* 229310e5eSGavin Shan * The file intends to implement the platform dependent EEH operations on 329310e5eSGavin Shan * powernv platform. Actually, the powernv was created in order to fully 429310e5eSGavin Shan * hypervisor support. 529310e5eSGavin Shan * 629310e5eSGavin Shan * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 729310e5eSGavin Shan * 829310e5eSGavin Shan * This program is free software; you can redistribute it and/or modify 929310e5eSGavin Shan * it under the terms of the GNU General Public License as published by 1029310e5eSGavin Shan * the Free Software Foundation; either version 2 of the License, or 1129310e5eSGavin Shan * (at your option) any later version. 1229310e5eSGavin Shan */ 1329310e5eSGavin Shan 1429310e5eSGavin Shan #include <linux/atomic.h> 154cf17445SGavin Shan #include <linux/debugfs.h> 1629310e5eSGavin Shan #include <linux/delay.h> 1729310e5eSGavin Shan #include <linux/export.h> 1829310e5eSGavin Shan #include <linux/init.h> 1979231448SAlistair Popple #include <linux/interrupt.h> 2029310e5eSGavin Shan #include <linux/list.h> 2129310e5eSGavin Shan #include <linux/msi.h> 2229310e5eSGavin Shan #include <linux/of.h> 2329310e5eSGavin Shan #include <linux/pci.h> 2429310e5eSGavin Shan #include <linux/proc_fs.h> 2529310e5eSGavin Shan #include <linux/rbtree.h> 2629310e5eSGavin Shan #include <linux/sched.h> 2729310e5eSGavin Shan #include <linux/seq_file.h> 2829310e5eSGavin Shan #include <linux/spinlock.h> 2929310e5eSGavin Shan 3029310e5eSGavin Shan #include <asm/eeh.h> 3129310e5eSGavin Shan #include <asm/eeh_event.h> 3229310e5eSGavin Shan #include <asm/firmware.h> 3329310e5eSGavin Shan #include <asm/io.h> 3429310e5eSGavin Shan #include <asm/iommu.h> 3529310e5eSGavin Shan #include <asm/machdep.h> 3629310e5eSGavin Shan #include <asm/msi_bitmap.h> 3729310e5eSGavin Shan #include <asm/opal.h> 3829310e5eSGavin Shan #include <asm/ppc-pci.h> 399c0e1ecbSGavin Shan #include <asm/pnv-pci.h> 4029310e5eSGavin Shan 4129310e5eSGavin Shan #include "powernv.h" 4229310e5eSGavin Shan #include "pci.h" 4329310e5eSGavin Shan 444cf17445SGavin Shan static bool pnv_eeh_nb_init = false; 4579231448SAlistair Popple static int eeh_event_irq = -EINVAL; 464cf17445SGavin Shan 4701f3bfb7SGavin Shan static int pnv_eeh_init(void) 4829310e5eSGavin Shan { 49dc561fb9SGavin Shan struct pci_controller *hose; 50dc561fb9SGavin Shan struct pnv_phb *phb; 515cb1f8fdSRussell Currey int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 52dc561fb9SGavin Shan 53e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 54e4d54f71SStewart Smith pr_warn("%s: OPAL is required !\n", 550dae2743SGavin Shan __func__); 5629310e5eSGavin Shan return -EINVAL; 5729310e5eSGavin Shan } 5829310e5eSGavin Shan 5905b1721dSGavin Shan /* Set probe mode */ 6005b1721dSGavin Shan eeh_add_flag(EEH_PROBE_MODE_DEV); 6129310e5eSGavin Shan 62dc561fb9SGavin Shan /* 63dc561fb9SGavin Shan * P7IOC blocks PCI config access to frozen PE, but PHB3 64dc561fb9SGavin Shan * doesn't do that. So we have to selectively enable I/O 65dc561fb9SGavin Shan * prior to collecting error log. 66dc561fb9SGavin Shan */ 67dc561fb9SGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 68dc561fb9SGavin Shan phb = hose->private_data; 69dc561fb9SGavin Shan 70dc561fb9SGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC) 71dc561fb9SGavin Shan eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 722aa5cf9eSGavin Shan 735cb1f8fdSRussell Currey if (phb->diag_data_size > max_diag_size) 745cb1f8fdSRussell Currey max_diag_size = phb->diag_data_size; 755cb1f8fdSRussell Currey 762aa5cf9eSGavin Shan /* 772aa5cf9eSGavin Shan * PE#0 should be regarded as valid by EEH core 782aa5cf9eSGavin Shan * if it's not the reserved one. Currently, we 79608fb9c2SGavin Shan * have the reserved PE#255 and PE#127 for PHB3 802aa5cf9eSGavin Shan * and P7IOC separately. So we should regard 81608fb9c2SGavin Shan * PE#0 as valid for PHB3 and P7IOC. 822aa5cf9eSGavin Shan */ 8392b8f137SGavin Shan if (phb->ioda.reserved_pe_idx != 0) 842aa5cf9eSGavin Shan eeh_add_flag(EEH_VALID_PE_ZERO); 852aa5cf9eSGavin Shan 86dc561fb9SGavin Shan break; 87dc561fb9SGavin Shan } 88dc561fb9SGavin Shan 895cb1f8fdSRussell Currey eeh_set_pe_aux_size(max_diag_size); 905cb1f8fdSRussell Currey 9129310e5eSGavin Shan return 0; 9229310e5eSGavin Shan } 9329310e5eSGavin Shan 9479231448SAlistair Popple static irqreturn_t pnv_eeh_event(int irq, void *data) 954cf17445SGavin Shan { 964cf17445SGavin Shan /* 9779231448SAlistair Popple * We simply send a special EEH event if EEH has been 9879231448SAlistair Popple * enabled. We don't care about EEH events until we've 9979231448SAlistair Popple * finished processing the outstanding ones. Event processing 10079231448SAlistair Popple * gets unmasked in next_error() if EEH is enabled. 1014cf17445SGavin Shan */ 10279231448SAlistair Popple disable_irq_nosync(irq); 1034cf17445SGavin Shan 1044cf17445SGavin Shan if (eeh_enabled()) 1054cf17445SGavin Shan eeh_send_failure_event(NULL); 1064cf17445SGavin Shan 10779231448SAlistair Popple return IRQ_HANDLED; 1084cf17445SGavin Shan } 1094cf17445SGavin Shan 1104cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 1114cf17445SGavin Shan static ssize_t pnv_eeh_ei_write(struct file *filp, 1124cf17445SGavin Shan const char __user *user_buf, 1134cf17445SGavin Shan size_t count, loff_t *ppos) 1144cf17445SGavin Shan { 1154cf17445SGavin Shan struct pci_controller *hose = filp->private_data; 1164cf17445SGavin Shan struct eeh_pe *pe; 1174cf17445SGavin Shan int pe_no, type, func; 1184cf17445SGavin Shan unsigned long addr, mask; 1194cf17445SGavin Shan char buf[50]; 1204cf17445SGavin Shan int ret; 1214cf17445SGavin Shan 1224cf17445SGavin Shan if (!eeh_ops || !eeh_ops->err_inject) 1234cf17445SGavin Shan return -ENXIO; 1244cf17445SGavin Shan 1254cf17445SGavin Shan /* Copy over argument buffer */ 1264cf17445SGavin Shan ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 1274cf17445SGavin Shan if (!ret) 1284cf17445SGavin Shan return -EFAULT; 1294cf17445SGavin Shan 1304cf17445SGavin Shan /* Retrieve parameters */ 1314cf17445SGavin Shan ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 1324cf17445SGavin Shan &pe_no, &type, &func, &addr, &mask); 1334cf17445SGavin Shan if (ret != 5) 1344cf17445SGavin Shan return -EINVAL; 1354cf17445SGavin Shan 1364cf17445SGavin Shan /* Retrieve PE */ 1378bae6a23SAlexey Kardashevskiy pe = eeh_pe_get(hose, pe_no, 0); 1384cf17445SGavin Shan if (!pe) 1394cf17445SGavin Shan return -ENODEV; 1404cf17445SGavin Shan 1414cf17445SGavin Shan /* Do error injection */ 1424cf17445SGavin Shan ret = eeh_ops->err_inject(pe, type, func, addr, mask); 1434cf17445SGavin Shan return ret < 0 ? ret : count; 1444cf17445SGavin Shan } 1454cf17445SGavin Shan 1464cf17445SGavin Shan static const struct file_operations pnv_eeh_ei_fops = { 1474cf17445SGavin Shan .open = simple_open, 1484cf17445SGavin Shan .llseek = no_llseek, 1494cf17445SGavin Shan .write = pnv_eeh_ei_write, 1504cf17445SGavin Shan }; 1514cf17445SGavin Shan 1524cf17445SGavin Shan static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 1534cf17445SGavin Shan { 1544cf17445SGavin Shan struct pci_controller *hose = data; 1554cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1564cf17445SGavin Shan 1574cf17445SGavin Shan out_be64(phb->regs + offset, val); 1584cf17445SGavin Shan return 0; 1594cf17445SGavin Shan } 1604cf17445SGavin Shan 1614cf17445SGavin Shan static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 1624cf17445SGavin Shan { 1634cf17445SGavin Shan struct pci_controller *hose = data; 1644cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1654cf17445SGavin Shan 1664cf17445SGavin Shan *val = in_be64(phb->regs + offset); 1674cf17445SGavin Shan return 0; 1684cf17445SGavin Shan } 1694cf17445SGavin Shan 170ccc9662dSGavin Shan #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 171ccc9662dSGavin Shan static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 172ccc9662dSGavin Shan { \ 173ccc9662dSGavin Shan return pnv_eeh_dbgfs_set(data, reg, val); \ 174ccc9662dSGavin Shan } \ 175ccc9662dSGavin Shan \ 176ccc9662dSGavin Shan static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 177ccc9662dSGavin Shan { \ 178ccc9662dSGavin Shan return pnv_eeh_dbgfs_get(data, reg, val); \ 179ccc9662dSGavin Shan } \ 180ccc9662dSGavin Shan \ 181ccc9662dSGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 182ccc9662dSGavin Shan pnv_eeh_dbgfs_get_##name, \ 183ccc9662dSGavin Shan pnv_eeh_dbgfs_set_##name, \ 184ccc9662dSGavin Shan "0x%llx\n") 1854cf17445SGavin Shan 186ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 187ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 188ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 1894cf17445SGavin Shan 1904cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 1914cf17445SGavin Shan 19229310e5eSGavin Shan /** 19301f3bfb7SGavin Shan * pnv_eeh_post_init - EEH platform dependent post initialization 19429310e5eSGavin Shan * 19529310e5eSGavin Shan * EEH platform dependent post initialization on powernv. When 19629310e5eSGavin Shan * the function is called, the EEH PEs and devices should have 19729310e5eSGavin Shan * been built. If the I/O cache staff has been built, EEH is 19829310e5eSGavin Shan * ready to supply service. 19929310e5eSGavin Shan */ 20001f3bfb7SGavin Shan static int pnv_eeh_post_init(void) 20129310e5eSGavin Shan { 20229310e5eSGavin Shan struct pci_controller *hose; 20329310e5eSGavin Shan struct pnv_phb *phb; 20429310e5eSGavin Shan int ret = 0; 20529310e5eSGavin Shan 2064cf17445SGavin Shan /* Register OPAL event notifier */ 2074cf17445SGavin Shan if (!pnv_eeh_nb_init) { 20879231448SAlistair Popple eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 20979231448SAlistair Popple if (eeh_event_irq < 0) { 21079231448SAlistair Popple pr_err("%s: Can't register OPAL event interrupt (%d)\n", 21179231448SAlistair Popple __func__, eeh_event_irq); 21279231448SAlistair Popple return eeh_event_irq; 21379231448SAlistair Popple } 21479231448SAlistair Popple 21579231448SAlistair Popple ret = request_irq(eeh_event_irq, pnv_eeh_event, 21679231448SAlistair Popple IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 21779231448SAlistair Popple if (ret < 0) { 21879231448SAlistair Popple irq_dispose_mapping(eeh_event_irq); 21979231448SAlistair Popple pr_err("%s: Can't request OPAL event interrupt (%d)\n", 22079231448SAlistair Popple __func__, eeh_event_irq); 2214cf17445SGavin Shan return ret; 2224cf17445SGavin Shan } 2234cf17445SGavin Shan 2244cf17445SGavin Shan pnv_eeh_nb_init = true; 2254cf17445SGavin Shan } 2264cf17445SGavin Shan 22779231448SAlistair Popple if (!eeh_enabled()) 22879231448SAlistair Popple disable_irq(eeh_event_irq); 22979231448SAlistair Popple 23029310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 23129310e5eSGavin Shan phb = hose->private_data; 23229310e5eSGavin Shan 2334cf17445SGavin Shan /* 2344cf17445SGavin Shan * If EEH is enabled, we're going to rely on that. 2354cf17445SGavin Shan * Otherwise, we restore to conventional mechanism 2364cf17445SGavin Shan * to clear frozen PE during PCI config access. 2374cf17445SGavin Shan */ 2384cf17445SGavin Shan if (eeh_enabled()) 2394cf17445SGavin Shan phb->flags |= PNV_PHB_FLAG_EEH; 2404cf17445SGavin Shan else 2414cf17445SGavin Shan phb->flags &= ~PNV_PHB_FLAG_EEH; 2424cf17445SGavin Shan 2434cf17445SGavin Shan /* Create debugfs entries */ 2444cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 2454cf17445SGavin Shan if (phb->has_dbgfs || !phb->dbgfs) 2464cf17445SGavin Shan continue; 2474cf17445SGavin Shan 2484cf17445SGavin Shan phb->has_dbgfs = 1; 2494cf17445SGavin Shan debugfs_create_file("err_injct", 0200, 2504cf17445SGavin Shan phb->dbgfs, hose, 2514cf17445SGavin Shan &pnv_eeh_ei_fops); 2524cf17445SGavin Shan 2534cf17445SGavin Shan debugfs_create_file("err_injct_outbound", 0600, 2544cf17445SGavin Shan phb->dbgfs, hose, 255ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_outb); 2564cf17445SGavin Shan debugfs_create_file("err_injct_inboundA", 0600, 2574cf17445SGavin Shan phb->dbgfs, hose, 258ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbA); 2594cf17445SGavin Shan debugfs_create_file("err_injct_inboundB", 0600, 2604cf17445SGavin Shan phb->dbgfs, hose, 261ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbB); 2624cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 26329310e5eSGavin Shan } 2644cf17445SGavin Shan 26529310e5eSGavin Shan return ret; 26629310e5eSGavin Shan } 26729310e5eSGavin Shan 2684d6186caSGavin Shan static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 269ff57b454SGavin Shan { 2704d6186caSGavin Shan int pos = PCI_CAPABILITY_LIST; 2714d6186caSGavin Shan int cnt = 48; /* Maximal number of capabilities */ 2724d6186caSGavin Shan u32 status, id; 273ff57b454SGavin Shan 274ff57b454SGavin Shan if (!pdn) 275ff57b454SGavin Shan return 0; 276ff57b454SGavin Shan 2774d6186caSGavin Shan /* Check if the device supports capabilities */ 278ff57b454SGavin Shan pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 279ff57b454SGavin Shan if (!(status & PCI_STATUS_CAP_LIST)) 280ff57b454SGavin Shan return 0; 281ff57b454SGavin Shan 282ff57b454SGavin Shan while (cnt--) { 283ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos, 1, &pos); 284ff57b454SGavin Shan if (pos < 0x40) 285ff57b454SGavin Shan break; 286ff57b454SGavin Shan 287ff57b454SGavin Shan pos &= ~3; 288ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 289ff57b454SGavin Shan if (id == 0xff) 290ff57b454SGavin Shan break; 291ff57b454SGavin Shan 292ff57b454SGavin Shan /* Found */ 293ff57b454SGavin Shan if (id == cap) 294ff57b454SGavin Shan return pos; 295ff57b454SGavin Shan 296ff57b454SGavin Shan /* Next one */ 297ff57b454SGavin Shan pos += PCI_CAP_LIST_NEXT; 298ff57b454SGavin Shan } 299ff57b454SGavin Shan 300ff57b454SGavin Shan return 0; 301ff57b454SGavin Shan } 302ff57b454SGavin Shan 303ff57b454SGavin Shan static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 304ff57b454SGavin Shan { 305ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 306ff57b454SGavin Shan u32 header; 307ff57b454SGavin Shan int pos = 256, ttl = (4096 - 256) / 8; 308ff57b454SGavin Shan 309ff57b454SGavin Shan if (!edev || !edev->pcie_cap) 310ff57b454SGavin Shan return 0; 311ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 312ff57b454SGavin Shan return 0; 313ff57b454SGavin Shan else if (!header) 314ff57b454SGavin Shan return 0; 315ff57b454SGavin Shan 316ff57b454SGavin Shan while (ttl-- > 0) { 317ff57b454SGavin Shan if (PCI_EXT_CAP_ID(header) == cap && pos) 318ff57b454SGavin Shan return pos; 319ff57b454SGavin Shan 320ff57b454SGavin Shan pos = PCI_EXT_CAP_NEXT(header); 321ff57b454SGavin Shan if (pos < 256) 322ff57b454SGavin Shan break; 323ff57b454SGavin Shan 324ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 325ff57b454SGavin Shan break; 326ff57b454SGavin Shan } 327ff57b454SGavin Shan 328ff57b454SGavin Shan return 0; 329ff57b454SGavin Shan } 330ff57b454SGavin Shan 33129310e5eSGavin Shan /** 332ff57b454SGavin Shan * pnv_eeh_probe - Do probe on PCI device 333ff57b454SGavin Shan * @pdn: PCI device node 334ff57b454SGavin Shan * @data: unused 33529310e5eSGavin Shan * 33629310e5eSGavin Shan * When EEH module is installed during system boot, all PCI devices 33729310e5eSGavin Shan * are checked one by one to see if it supports EEH. The function 33829310e5eSGavin Shan * is introduced for the purpose. By default, EEH has been enabled 33929310e5eSGavin Shan * on all PCI devices. That's to say, we only need do necessary 34029310e5eSGavin Shan * initialization on the corresponding eeh device and create PE 34129310e5eSGavin Shan * accordingly. 34229310e5eSGavin Shan * 34329310e5eSGavin Shan * It's notable that's unsafe to retrieve the EEH device through 34429310e5eSGavin Shan * the corresponding PCI device. During the PCI device hotplug, which 34529310e5eSGavin Shan * was possiblly triggered by EEH core, the binding between EEH device 34629310e5eSGavin Shan * and the PCI device isn't built yet. 34729310e5eSGavin Shan */ 348ff57b454SGavin Shan static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 34929310e5eSGavin Shan { 350ff57b454SGavin Shan struct pci_controller *hose = pdn->phb; 35129310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 352ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 353ff57b454SGavin Shan uint32_t pcie_flags; 354dadcd6d6SMike Qiu int ret; 35529310e5eSGavin Shan 35629310e5eSGavin Shan /* 35729310e5eSGavin Shan * When probing the root bridge, which doesn't have any 35829310e5eSGavin Shan * subordinate PCI devices. We don't have OF node for 35929310e5eSGavin Shan * the root bridge. So it's not reasonable to continue 36029310e5eSGavin Shan * the probing. 36129310e5eSGavin Shan */ 362ff57b454SGavin Shan if (!edev || edev->pe) 363ff57b454SGavin Shan return NULL; 36429310e5eSGavin Shan 36529310e5eSGavin Shan /* Skip for PCI-ISA bridge */ 366ff57b454SGavin Shan if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 367ff57b454SGavin Shan return NULL; 36829310e5eSGavin Shan 36929310e5eSGavin Shan /* Initialize eeh device */ 370ff57b454SGavin Shan edev->class_code = pdn->class_code; 371ab55d218SGavin Shan edev->mode &= 0xFFFFFF00; 372ff57b454SGavin Shan edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 373ff57b454SGavin Shan edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 3749312bc5bSWei Yang edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 375ff57b454SGavin Shan edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 376ff57b454SGavin Shan if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 3774b83bd45SGavin Shan edev->mode |= EEH_DEV_BRIDGE; 378ff57b454SGavin Shan if (edev->pcie_cap) { 379ff57b454SGavin Shan pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 380ff57b454SGavin Shan 2, &pcie_flags); 381ff57b454SGavin Shan pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 382ff57b454SGavin Shan if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 3834b83bd45SGavin Shan edev->mode |= EEH_DEV_ROOT_PORT; 384ff57b454SGavin Shan else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 3854b83bd45SGavin Shan edev->mode |= EEH_DEV_DS_PORT; 386ff57b454SGavin Shan } 3874b83bd45SGavin Shan } 3884b83bd45SGavin Shan 389ff57b454SGavin Shan edev->config_addr = (pdn->busno << 8) | (pdn->devfn); 390ff57b454SGavin Shan edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr]; 39129310e5eSGavin Shan 39229310e5eSGavin Shan /* Create PE */ 393dadcd6d6SMike Qiu ret = eeh_add_to_parent_pe(edev); 394dadcd6d6SMike Qiu if (ret) { 3951f52f176SRussell Currey pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n", 396ff57b454SGavin Shan __func__, hose->global_number, pdn->busno, 397ff57b454SGavin Shan PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 398ff57b454SGavin Shan return NULL; 399dadcd6d6SMike Qiu } 400dadcd6d6SMike Qiu 401dadcd6d6SMike Qiu /* 402b6541db1SGavin Shan * If the PE contains any one of following adapters, the 403b6541db1SGavin Shan * PCI config space can't be accessed when dumping EEH log. 404b6541db1SGavin Shan * Otherwise, we will run into fenced PHB caused by shortage 405b6541db1SGavin Shan * of outbound credits in the adapter. The PCI config access 406b6541db1SGavin Shan * should be blocked until PE reset. MMIO access is dropped 407b6541db1SGavin Shan * by hardware certainly. In order to drop PCI config requests, 408b6541db1SGavin Shan * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 409b6541db1SGavin Shan * will be checked in the backend for PE state retrival. If 410b6541db1SGavin Shan * the PE becomes frozen for the first time and the flag has 411b6541db1SGavin Shan * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 412b6541db1SGavin Shan * that PE to block its config space. 413b6541db1SGavin Shan * 414c374ed27SGavin Shan * Broadcom BCM5718 2-ports NICs (14e4:1656) 415b6541db1SGavin Shan * Broadcom Austin 4-ports NICs (14e4:1657) 416353169acSGavin Shan * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 417179ea48bSGavin Shan * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 418b6541db1SGavin Shan */ 419ff57b454SGavin Shan if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 420c374ed27SGavin Shan pdn->device_id == 0x1656) || 421c374ed27SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 422ff57b454SGavin Shan pdn->device_id == 0x1657) || 423ff57b454SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 424353169acSGavin Shan pdn->device_id == 0x168a) || 425353169acSGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 426ff57b454SGavin Shan pdn->device_id == 0x168e)) 427b6541db1SGavin Shan edev->pe->state |= EEH_PE_CFG_RESTRICTED; 428b6541db1SGavin Shan 429b6541db1SGavin Shan /* 430dadcd6d6SMike Qiu * Cache the PE primary bus, which can't be fetched when 431dadcd6d6SMike Qiu * full hotplug is in progress. In that case, all child 432dadcd6d6SMike Qiu * PCI devices of the PE are expected to be removed prior 433dadcd6d6SMike Qiu * to PE reset. 434dadcd6d6SMike Qiu */ 43505ba75f8SGavin Shan if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 436ff57b454SGavin Shan edev->pe->bus = pci_find_bus(hose->global_number, 437ff57b454SGavin Shan pdn->busno); 43805ba75f8SGavin Shan if (edev->pe->bus) 43905ba75f8SGavin Shan edev->pe->state |= EEH_PE_PRI_BUS; 44005ba75f8SGavin Shan } 44129310e5eSGavin Shan 44229310e5eSGavin Shan /* 44329310e5eSGavin Shan * Enable EEH explicitly so that we will do EEH check 44429310e5eSGavin Shan * while accessing I/O stuff 44529310e5eSGavin Shan */ 44605b1721dSGavin Shan eeh_add_flag(EEH_ENABLED); 44729310e5eSGavin Shan 44829310e5eSGavin Shan /* Save memory bars */ 44929310e5eSGavin Shan eeh_save_bars(edev); 45029310e5eSGavin Shan 451ff57b454SGavin Shan return NULL; 45229310e5eSGavin Shan } 45329310e5eSGavin Shan 45429310e5eSGavin Shan /** 45501f3bfb7SGavin Shan * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 45629310e5eSGavin Shan * @pe: EEH PE 45729310e5eSGavin Shan * @option: operation to be issued 45829310e5eSGavin Shan * 45929310e5eSGavin Shan * The function is used to control the EEH functionality globally. 46029310e5eSGavin Shan * Currently, following options are support according to PAPR: 46129310e5eSGavin Shan * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 46229310e5eSGavin Shan */ 46301f3bfb7SGavin Shan static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 46429310e5eSGavin Shan { 46529310e5eSGavin Shan struct pci_controller *hose = pe->phb; 46629310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 4677e3e4f8dSGavin Shan bool freeze_pe = false; 468f9433718SGavin Shan int opt; 4697e3e4f8dSGavin Shan s64 rc; 47029310e5eSGavin Shan 4717e3e4f8dSGavin Shan switch (option) { 4727e3e4f8dSGavin Shan case EEH_OPT_DISABLE: 4737e3e4f8dSGavin Shan return -EPERM; 4747e3e4f8dSGavin Shan case EEH_OPT_ENABLE: 4757e3e4f8dSGavin Shan return 0; 4767e3e4f8dSGavin Shan case EEH_OPT_THAW_MMIO: 4777e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 4787e3e4f8dSGavin Shan break; 4797e3e4f8dSGavin Shan case EEH_OPT_THAW_DMA: 4807e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 4817e3e4f8dSGavin Shan break; 4827e3e4f8dSGavin Shan case EEH_OPT_FREEZE_PE: 4837e3e4f8dSGavin Shan freeze_pe = true; 4847e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 4857e3e4f8dSGavin Shan break; 4867e3e4f8dSGavin Shan default: 4877e3e4f8dSGavin Shan pr_warn("%s: Invalid option %d\n", __func__, option); 4887e3e4f8dSGavin Shan return -EINVAL; 4897e3e4f8dSGavin Shan } 4907e3e4f8dSGavin Shan 491f9433718SGavin Shan /* Freeze master and slave PEs if PHB supports compound PEs */ 4927e3e4f8dSGavin Shan if (freeze_pe) { 4937e3e4f8dSGavin Shan if (phb->freeze_pe) { 4947e3e4f8dSGavin Shan phb->freeze_pe(phb, pe->addr); 495f9433718SGavin Shan return 0; 4967e3e4f8dSGavin Shan } 49729310e5eSGavin Shan 498f9433718SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 499f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 500f9433718SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 501f9433718SGavin Shan __func__, rc, phb->hose->global_number, 502f9433718SGavin Shan pe->addr); 503f9433718SGavin Shan return -EIO; 504f9433718SGavin Shan } 505f9433718SGavin Shan 506f9433718SGavin Shan return 0; 507f9433718SGavin Shan } 508f9433718SGavin Shan 509f9433718SGavin Shan /* Unfreeze master and slave PEs if PHB supports */ 510f9433718SGavin Shan if (phb->unfreeze_pe) 511f9433718SGavin Shan return phb->unfreeze_pe(phb, pe->addr, opt); 512f9433718SGavin Shan 513f9433718SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 514f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 515f9433718SGavin Shan pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 516f9433718SGavin Shan __func__, rc, option, phb->hose->global_number, 517f9433718SGavin Shan pe->addr); 518f9433718SGavin Shan return -EIO; 519f9433718SGavin Shan } 520f9433718SGavin Shan 521f9433718SGavin Shan return 0; 52229310e5eSGavin Shan } 52329310e5eSGavin Shan 52429310e5eSGavin Shan /** 52501f3bfb7SGavin Shan * pnv_eeh_get_pe_addr - Retrieve PE address 52629310e5eSGavin Shan * @pe: EEH PE 52729310e5eSGavin Shan * 52829310e5eSGavin Shan * Retrieve the PE address according to the given tranditional 52929310e5eSGavin Shan * PCI BDF (Bus/Device/Function) address. 53029310e5eSGavin Shan */ 53101f3bfb7SGavin Shan static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 53229310e5eSGavin Shan { 53329310e5eSGavin Shan return pe->addr; 53429310e5eSGavin Shan } 53529310e5eSGavin Shan 53640ae5f69SGavin Shan static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 53740ae5f69SGavin Shan { 53840ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 53940ae5f69SGavin Shan s64 rc; 54040ae5f69SGavin Shan 54140ae5f69SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 5425cb1f8fdSRussell Currey phb->diag_data_size); 54340ae5f69SGavin Shan if (rc != OPAL_SUCCESS) 54440ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 54540ae5f69SGavin Shan __func__, rc, pe->phb->global_number); 54640ae5f69SGavin Shan } 54740ae5f69SGavin Shan 54840ae5f69SGavin Shan static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 54940ae5f69SGavin Shan { 55040ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 55140ae5f69SGavin Shan u8 fstate; 55240ae5f69SGavin Shan __be16 pcierr; 55340ae5f69SGavin Shan s64 rc; 55440ae5f69SGavin Shan int result = 0; 55540ae5f69SGavin Shan 55640ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 55740ae5f69SGavin Shan pe->addr, 55840ae5f69SGavin Shan &fstate, 55940ae5f69SGavin Shan &pcierr, 56040ae5f69SGavin Shan NULL); 56140ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 56240ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x state\n", 56340ae5f69SGavin Shan __func__, rc, phb->hose->global_number); 56440ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 56540ae5f69SGavin Shan } 56640ae5f69SGavin Shan 56740ae5f69SGavin Shan /* 56840ae5f69SGavin Shan * Check PHB state. If the PHB is frozen for the 56940ae5f69SGavin Shan * first time, to dump the PHB diag-data. 57040ae5f69SGavin Shan */ 57140ae5f69SGavin Shan if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 57240ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 57340ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 57440ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 57540ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 57640ae5f69SGavin Shan } else if (!(pe->state & EEH_PE_ISOLATED)) { 57740ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 57840ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 57940ae5f69SGavin Shan 58040ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 58140ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 58240ae5f69SGavin Shan } 58340ae5f69SGavin Shan 58440ae5f69SGavin Shan return result; 58540ae5f69SGavin Shan } 58640ae5f69SGavin Shan 58740ae5f69SGavin Shan static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 58840ae5f69SGavin Shan { 58940ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 59040ae5f69SGavin Shan u8 fstate; 59140ae5f69SGavin Shan __be16 pcierr; 59240ae5f69SGavin Shan s64 rc; 59340ae5f69SGavin Shan int result; 59440ae5f69SGavin Shan 59540ae5f69SGavin Shan /* 59640ae5f69SGavin Shan * We don't clobber hardware frozen state until PE 59740ae5f69SGavin Shan * reset is completed. In order to keep EEH core 59840ae5f69SGavin Shan * moving forward, we have to return operational 59940ae5f69SGavin Shan * state during PE reset. 60040ae5f69SGavin Shan */ 60140ae5f69SGavin Shan if (pe->state & EEH_PE_RESET) { 60240ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 60340ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 60440ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 60540ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 60640ae5f69SGavin Shan return result; 60740ae5f69SGavin Shan } 60840ae5f69SGavin Shan 60940ae5f69SGavin Shan /* 61040ae5f69SGavin Shan * Fetch PE state from hardware. If the PHB 61140ae5f69SGavin Shan * supports compound PE, let it handle that. 61240ae5f69SGavin Shan */ 61340ae5f69SGavin Shan if (phb->get_pe_state) { 61440ae5f69SGavin Shan fstate = phb->get_pe_state(phb, pe->addr); 61540ae5f69SGavin Shan } else { 61640ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 61740ae5f69SGavin Shan pe->addr, 61840ae5f69SGavin Shan &fstate, 61940ae5f69SGavin Shan &pcierr, 62040ae5f69SGavin Shan NULL); 62140ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 62240ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 62340ae5f69SGavin Shan __func__, rc, phb->hose->global_number, 62440ae5f69SGavin Shan pe->addr); 62540ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 62640ae5f69SGavin Shan } 62740ae5f69SGavin Shan } 62840ae5f69SGavin Shan 62940ae5f69SGavin Shan /* Figure out state */ 63040ae5f69SGavin Shan switch (fstate) { 63140ae5f69SGavin Shan case OPAL_EEH_STOPPED_NOT_FROZEN: 63240ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 63340ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 63440ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 63540ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 63640ae5f69SGavin Shan break; 63740ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_FREEZE: 63840ae5f69SGavin Shan result = (EEH_STATE_DMA_ACTIVE | 63940ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 64040ae5f69SGavin Shan break; 64140ae5f69SGavin Shan case OPAL_EEH_STOPPED_DMA_FREEZE: 64240ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 64340ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED); 64440ae5f69SGavin Shan break; 64540ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 64640ae5f69SGavin Shan result = 0; 64740ae5f69SGavin Shan break; 64840ae5f69SGavin Shan case OPAL_EEH_STOPPED_RESET: 64940ae5f69SGavin Shan result = EEH_STATE_RESET_ACTIVE; 65040ae5f69SGavin Shan break; 65140ae5f69SGavin Shan case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 65240ae5f69SGavin Shan result = EEH_STATE_UNAVAILABLE; 65340ae5f69SGavin Shan break; 65440ae5f69SGavin Shan case OPAL_EEH_STOPPED_PERM_UNAVAIL: 65540ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 65640ae5f69SGavin Shan break; 65740ae5f69SGavin Shan default: 65840ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 65940ae5f69SGavin Shan pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 66040ae5f69SGavin Shan __func__, phb->hose->global_number, 66140ae5f69SGavin Shan pe->addr, fstate); 66240ae5f69SGavin Shan } 66340ae5f69SGavin Shan 66440ae5f69SGavin Shan /* 66540ae5f69SGavin Shan * If PHB supports compound PE, to freeze all 66640ae5f69SGavin Shan * slave PEs for consistency. 66740ae5f69SGavin Shan * 66840ae5f69SGavin Shan * If the PE is switching to frozen state for the 66940ae5f69SGavin Shan * first time, to dump the PHB diag-data. 67040ae5f69SGavin Shan */ 67140ae5f69SGavin Shan if (!(result & EEH_STATE_NOT_SUPPORT) && 67240ae5f69SGavin Shan !(result & EEH_STATE_UNAVAILABLE) && 67340ae5f69SGavin Shan !(result & EEH_STATE_MMIO_ACTIVE) && 67440ae5f69SGavin Shan !(result & EEH_STATE_DMA_ACTIVE) && 67540ae5f69SGavin Shan !(pe->state & EEH_PE_ISOLATED)) { 67640ae5f69SGavin Shan if (phb->freeze_pe) 67740ae5f69SGavin Shan phb->freeze_pe(phb, pe->addr); 67840ae5f69SGavin Shan 67940ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 68040ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 68140ae5f69SGavin Shan 68240ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 68340ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 68440ae5f69SGavin Shan } 68540ae5f69SGavin Shan 68640ae5f69SGavin Shan return result; 68740ae5f69SGavin Shan } 68840ae5f69SGavin Shan 68929310e5eSGavin Shan /** 69001f3bfb7SGavin Shan * pnv_eeh_get_state - Retrieve PE state 69129310e5eSGavin Shan * @pe: EEH PE 69229310e5eSGavin Shan * @delay: delay while PE state is temporarily unavailable 69329310e5eSGavin Shan * 69429310e5eSGavin Shan * Retrieve the state of the specified PE. For IODA-compitable 69529310e5eSGavin Shan * platform, it should be retrieved from IODA table. Therefore, 69629310e5eSGavin Shan * we prefer passing down to hardware implementation to handle 69729310e5eSGavin Shan * it. 69829310e5eSGavin Shan */ 69901f3bfb7SGavin Shan static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 70029310e5eSGavin Shan { 70140ae5f69SGavin Shan int ret; 70229310e5eSGavin Shan 70340ae5f69SGavin Shan if (pe->type & EEH_PE_PHB) 70440ae5f69SGavin Shan ret = pnv_eeh_get_phb_state(pe); 70540ae5f69SGavin Shan else 70640ae5f69SGavin Shan ret = pnv_eeh_get_pe_state(pe); 70740ae5f69SGavin Shan 70840ae5f69SGavin Shan if (!delay) 70940ae5f69SGavin Shan return ret; 71029310e5eSGavin Shan 71129310e5eSGavin Shan /* 71229310e5eSGavin Shan * If the PE state is temporarily unavailable, 71329310e5eSGavin Shan * to inform the EEH core delay for default 71429310e5eSGavin Shan * period (1 second) 71529310e5eSGavin Shan */ 71629310e5eSGavin Shan *delay = 0; 71729310e5eSGavin Shan if (ret & EEH_STATE_UNAVAILABLE) 71829310e5eSGavin Shan *delay = 1000; 71929310e5eSGavin Shan 72029310e5eSGavin Shan return ret; 72129310e5eSGavin Shan } 72229310e5eSGavin Shan 723ebe22531SGavin Shan static s64 pnv_eeh_poll(unsigned long id) 724cadf364dSGavin Shan { 725cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 726cadf364dSGavin Shan 727cadf364dSGavin Shan while (1) { 728ebe22531SGavin Shan rc = opal_pci_poll(id); 729cadf364dSGavin Shan if (rc <= 0) 730cadf364dSGavin Shan break; 731cadf364dSGavin Shan 732cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 733cadf364dSGavin Shan udelay(1000 * rc); 734cadf364dSGavin Shan else 735cadf364dSGavin Shan msleep(rc); 736cadf364dSGavin Shan } 737cadf364dSGavin Shan 738cadf364dSGavin Shan return rc; 739cadf364dSGavin Shan } 740cadf364dSGavin Shan 741cadf364dSGavin Shan int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 742cadf364dSGavin Shan { 743cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 744cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 745cadf364dSGavin Shan 746cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 747cadf364dSGavin Shan __func__, hose->global_number, option); 748cadf364dSGavin Shan 749cadf364dSGavin Shan /* Issue PHB complete reset request */ 750cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL || 751cadf364dSGavin Shan option == EEH_RESET_HOT) 752cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 753cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 754cadf364dSGavin Shan OPAL_ASSERT_RESET); 755cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 756cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 757cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 758cadf364dSGavin Shan OPAL_DEASSERT_RESET); 759cadf364dSGavin Shan if (rc < 0) 760cadf364dSGavin Shan goto out; 761cadf364dSGavin Shan 762cadf364dSGavin Shan /* 763cadf364dSGavin Shan * Poll state of the PHB until the request is done 764cadf364dSGavin Shan * successfully. The PHB reset is usually PHB complete 765cadf364dSGavin Shan * reset followed by hot reset on root bus. So we also 766cadf364dSGavin Shan * need the PCI bus settlement delay. 767cadf364dSGavin Shan */ 768fbce44d0SGavin Shan if (rc > 0) 769ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 770cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) { 771cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 772cadf364dSGavin Shan udelay(1000 * EEH_PE_RST_SETTLE_TIME); 773cadf364dSGavin Shan else 774cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 775cadf364dSGavin Shan } 776cadf364dSGavin Shan out: 777cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 778cadf364dSGavin Shan return -EIO; 779cadf364dSGavin Shan 780cadf364dSGavin Shan return 0; 781cadf364dSGavin Shan } 782cadf364dSGavin Shan 783cadf364dSGavin Shan static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 784cadf364dSGavin Shan { 785cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 786cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 787cadf364dSGavin Shan 788cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 789cadf364dSGavin Shan __func__, hose->global_number, option); 790cadf364dSGavin Shan 791cadf364dSGavin Shan /* 792cadf364dSGavin Shan * During the reset deassert time, we needn't care 793cadf364dSGavin Shan * the reset scope because the firmware does nothing 794cadf364dSGavin Shan * for fundamental or hot reset during deassert phase. 795cadf364dSGavin Shan */ 796cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL) 797cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 798cadf364dSGavin Shan OPAL_RESET_PCI_FUNDAMENTAL, 799cadf364dSGavin Shan OPAL_ASSERT_RESET); 800cadf364dSGavin Shan else if (option == EEH_RESET_HOT) 801cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 802cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 803cadf364dSGavin Shan OPAL_ASSERT_RESET); 804cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 805cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 806cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 807cadf364dSGavin Shan OPAL_DEASSERT_RESET); 808cadf364dSGavin Shan if (rc < 0) 809cadf364dSGavin Shan goto out; 810cadf364dSGavin Shan 811cadf364dSGavin Shan /* Poll state of the PHB until the request is done */ 812fbce44d0SGavin Shan if (rc > 0) 813ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 814cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) 815cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 816cadf364dSGavin Shan out: 817cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 818cadf364dSGavin Shan return -EIO; 819cadf364dSGavin Shan 820cadf364dSGavin Shan return 0; 821cadf364dSGavin Shan } 822cadf364dSGavin Shan 8239c0e1ecbSGavin Shan static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 824cadf364dSGavin Shan { 8250bd78587SGavin Shan struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 8260bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 827cadf364dSGavin Shan int aer = edev ? edev->aer_cap : 0; 828cadf364dSGavin Shan u32 ctrl; 829cadf364dSGavin Shan 830cadf364dSGavin Shan pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 831cadf364dSGavin Shan __func__, pci_domain_nr(dev->bus), 832cadf364dSGavin Shan dev->bus->number, option); 833cadf364dSGavin Shan 834cadf364dSGavin Shan switch (option) { 835cadf364dSGavin Shan case EEH_RESET_FUNDAMENTAL: 836cadf364dSGavin Shan case EEH_RESET_HOT: 837cadf364dSGavin Shan /* Don't report linkDown event */ 838cadf364dSGavin Shan if (aer) { 8390bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 840cadf364dSGavin Shan 4, &ctrl); 841cadf364dSGavin Shan ctrl |= PCI_ERR_UNC_SURPDN; 8420bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 843cadf364dSGavin Shan 4, ctrl); 844cadf364dSGavin Shan } 845cadf364dSGavin Shan 8460bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 847cadf364dSGavin Shan ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 8480bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 849cadf364dSGavin Shan 850cadf364dSGavin Shan msleep(EEH_PE_RST_HOLD_TIME); 851cadf364dSGavin Shan break; 852cadf364dSGavin Shan case EEH_RESET_DEACTIVATE: 8530bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 854cadf364dSGavin Shan ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 8550bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 856cadf364dSGavin Shan 857cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 858cadf364dSGavin Shan 859cadf364dSGavin Shan /* Continue reporting linkDown event */ 860cadf364dSGavin Shan if (aer) { 8610bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 862cadf364dSGavin Shan 4, &ctrl); 863cadf364dSGavin Shan ctrl &= ~PCI_ERR_UNC_SURPDN; 8640bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 865cadf364dSGavin Shan 4, ctrl); 866cadf364dSGavin Shan } 867cadf364dSGavin Shan 868cadf364dSGavin Shan break; 869cadf364dSGavin Shan } 870cadf364dSGavin Shan 871cadf364dSGavin Shan return 0; 872cadf364dSGavin Shan } 873cadf364dSGavin Shan 8749c0e1ecbSGavin Shan static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 8759c0e1ecbSGavin Shan { 8769c0e1ecbSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 8779c0e1ecbSGavin Shan struct pnv_phb *phb = hose->private_data; 8789c0e1ecbSGavin Shan struct device_node *dn = pci_device_to_OF_node(pdev); 8799c0e1ecbSGavin Shan uint64_t id = PCI_SLOT_ID(phb->opal_id, 8809c0e1ecbSGavin Shan (pdev->bus->number << 8) | pdev->devfn); 8819c0e1ecbSGavin Shan uint8_t scope; 8829c0e1ecbSGavin Shan int64_t rc; 8839c0e1ecbSGavin Shan 8849c0e1ecbSGavin Shan /* Hot reset to the bus if firmware cannot handle */ 8859c0e1ecbSGavin Shan if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 8869c0e1ecbSGavin Shan return __pnv_eeh_bridge_reset(pdev, option); 8879c0e1ecbSGavin Shan 8889c0e1ecbSGavin Shan switch (option) { 8899c0e1ecbSGavin Shan case EEH_RESET_FUNDAMENTAL: 8909c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_FUNDAMENTAL; 8919c0e1ecbSGavin Shan break; 8929c0e1ecbSGavin Shan case EEH_RESET_HOT: 8939c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_HOT; 8949c0e1ecbSGavin Shan break; 8959c0e1ecbSGavin Shan case EEH_RESET_DEACTIVATE: 8969c0e1ecbSGavin Shan return 0; 8979c0e1ecbSGavin Shan default: 8989c0e1ecbSGavin Shan dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 8999c0e1ecbSGavin Shan __func__, option); 9009c0e1ecbSGavin Shan return -EINVAL; 9019c0e1ecbSGavin Shan } 9029c0e1ecbSGavin Shan 9039c0e1ecbSGavin Shan rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 9049c0e1ecbSGavin Shan if (rc <= OPAL_SUCCESS) 9059c0e1ecbSGavin Shan goto out; 9069c0e1ecbSGavin Shan 9079c0e1ecbSGavin Shan rc = pnv_eeh_poll(id); 9089c0e1ecbSGavin Shan out: 9099c0e1ecbSGavin Shan return (rc == OPAL_SUCCESS) ? 0 : -EIO; 9109c0e1ecbSGavin Shan } 9119c0e1ecbSGavin Shan 912cadf364dSGavin Shan void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 913cadf364dSGavin Shan { 914848912e5SMichael Ellerman struct pci_controller *hose; 915848912e5SMichael Ellerman 916848912e5SMichael Ellerman if (pci_is_root_bus(dev->bus)) { 917848912e5SMichael Ellerman hose = pci_bus_to_host(dev->bus); 918848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_HOT); 919848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 920848912e5SMichael Ellerman } else { 921cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 922cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 923cadf364dSGavin Shan } 924848912e5SMichael Ellerman } 925cadf364dSGavin Shan 9269312bc5bSWei Yang static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 9279312bc5bSWei Yang int pos, u16 mask) 9289312bc5bSWei Yang { 9299312bc5bSWei Yang int i, status = 0; 9309312bc5bSWei Yang 9319312bc5bSWei Yang /* Wait for Transaction Pending bit to be cleared */ 9329312bc5bSWei Yang for (i = 0; i < 4; i++) { 9339312bc5bSWei Yang eeh_ops->read_config(pdn, pos, 2, &status); 9349312bc5bSWei Yang if (!(status & mask)) 9359312bc5bSWei Yang return; 9369312bc5bSWei Yang 9379312bc5bSWei Yang msleep((1 << i) * 100); 9389312bc5bSWei Yang } 9399312bc5bSWei Yang 9409312bc5bSWei Yang pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 9419312bc5bSWei Yang __func__, type, 94269672bd7SAlexey Kardashevskiy pdn->phb->global_number, pdn->busno, 9439312bc5bSWei Yang PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 9449312bc5bSWei Yang } 9459312bc5bSWei Yang 9469312bc5bSWei Yang static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 9479312bc5bSWei Yang { 9489312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9499312bc5bSWei Yang u32 reg = 0; 9509312bc5bSWei Yang 9519312bc5bSWei Yang if (WARN_ON(!edev->pcie_cap)) 9529312bc5bSWei Yang return -ENOTTY; 9539312bc5bSWei Yang 9549312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 9559312bc5bSWei Yang if (!(reg & PCI_EXP_DEVCAP_FLR)) 9569312bc5bSWei Yang return -ENOTTY; 9579312bc5bSWei Yang 9589312bc5bSWei Yang switch (option) { 9599312bc5bSWei Yang case EEH_RESET_HOT: 9609312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 9619312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "", 9629312bc5bSWei Yang edev->pcie_cap + PCI_EXP_DEVSTA, 9639312bc5bSWei Yang PCI_EXP_DEVSTA_TRPND); 9649312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9659312bc5bSWei Yang 4, ®); 9669312bc5bSWei Yang reg |= PCI_EXP_DEVCTL_BCR_FLR; 9679312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9689312bc5bSWei Yang 4, reg); 9699312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 9709312bc5bSWei Yang break; 9719312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 9729312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9739312bc5bSWei Yang 4, ®); 9749312bc5bSWei Yang reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 9759312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9769312bc5bSWei Yang 4, reg); 9779312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 9789312bc5bSWei Yang break; 9799312bc5bSWei Yang } 9809312bc5bSWei Yang 9819312bc5bSWei Yang return 0; 9829312bc5bSWei Yang } 9839312bc5bSWei Yang 9849312bc5bSWei Yang static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 9859312bc5bSWei Yang { 9869312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9879312bc5bSWei Yang u32 cap = 0; 9889312bc5bSWei Yang 9899312bc5bSWei Yang if (WARN_ON(!edev->af_cap)) 9909312bc5bSWei Yang return -ENOTTY; 9919312bc5bSWei Yang 9929312bc5bSWei Yang eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 9939312bc5bSWei Yang if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 9949312bc5bSWei Yang return -ENOTTY; 9959312bc5bSWei Yang 9969312bc5bSWei Yang switch (option) { 9979312bc5bSWei Yang case EEH_RESET_HOT: 9989312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 9999312bc5bSWei Yang /* 10009312bc5bSWei Yang * Wait for Transaction Pending bit to clear. A word-aligned 10019312bc5bSWei Yang * test is used, so we use the conrol offset rather than status 10029312bc5bSWei Yang * and shift the test bit to match. 10039312bc5bSWei Yang */ 10049312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "AF", 10059312bc5bSWei Yang edev->af_cap + PCI_AF_CTRL, 10069312bc5bSWei Yang PCI_AF_STATUS_TP << 8); 10079312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 10089312bc5bSWei Yang 1, PCI_AF_CTRL_FLR); 10099312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 10109312bc5bSWei Yang break; 10119312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 10129312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 10139312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 10149312bc5bSWei Yang break; 10159312bc5bSWei Yang } 10169312bc5bSWei Yang 10179312bc5bSWei Yang return 0; 10189312bc5bSWei Yang } 10199312bc5bSWei Yang 10209312bc5bSWei Yang static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 10219312bc5bSWei Yang { 10229312bc5bSWei Yang struct eeh_dev *edev; 10239312bc5bSWei Yang struct pci_dn *pdn; 10249312bc5bSWei Yang int ret; 10259312bc5bSWei Yang 10269312bc5bSWei Yang /* The VF PE should have only one child device */ 10279312bc5bSWei Yang edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, list); 10289312bc5bSWei Yang pdn = eeh_dev_to_pdn(edev); 10299312bc5bSWei Yang if (!pdn) 10309312bc5bSWei Yang return -ENXIO; 10319312bc5bSWei Yang 10329312bc5bSWei Yang ret = pnv_eeh_do_flr(pdn, option); 10339312bc5bSWei Yang if (!ret) 10349312bc5bSWei Yang return ret; 10359312bc5bSWei Yang 10369312bc5bSWei Yang return pnv_eeh_do_af_flr(pdn, option); 10379312bc5bSWei Yang } 10389312bc5bSWei Yang 103929310e5eSGavin Shan /** 104001f3bfb7SGavin Shan * pnv_eeh_reset - Reset the specified PE 104129310e5eSGavin Shan * @pe: EEH PE 104229310e5eSGavin Shan * @option: reset option 104329310e5eSGavin Shan * 1044cadf364dSGavin Shan * Do reset on the indicated PE. For PCI bus sensitive PE, 1045cadf364dSGavin Shan * we need to reset the parent p2p bridge. The PHB has to 1046cadf364dSGavin Shan * be reinitialized if the p2p bridge is root bridge. For 1047cadf364dSGavin Shan * PCI device sensitive PE, we will try to reset the device 1048cadf364dSGavin Shan * through FLR. For now, we don't have OPAL APIs to do HARD 1049cadf364dSGavin Shan * reset yet, so all reset would be SOFT (HOT) reset. 105029310e5eSGavin Shan */ 105101f3bfb7SGavin Shan static int pnv_eeh_reset(struct eeh_pe *pe, int option) 105229310e5eSGavin Shan { 105329310e5eSGavin Shan struct pci_controller *hose = pe->phb; 10544fad4943SGavin Shan struct pnv_phb *phb; 1055cadf364dSGavin Shan struct pci_bus *bus; 10564fad4943SGavin Shan int64_t rc; 105729310e5eSGavin Shan 1058cadf364dSGavin Shan /* 1059cadf364dSGavin Shan * For PHB reset, we always have complete reset. For those PEs whose 1060cadf364dSGavin Shan * primary bus derived from root complex (root bus) or root port 1061cadf364dSGavin Shan * (usually bus#1), we apply hot or fundamental reset on the root port. 1062cadf364dSGavin Shan * For other PEs, we always have hot reset on the PE primary bus. 1063cadf364dSGavin Shan * 1064cadf364dSGavin Shan * Here, we have different design to pHyp, which always clear the 1065cadf364dSGavin Shan * frozen state during PE reset. However, the good idea here from 1066cadf364dSGavin Shan * benh is to keep frozen state before we get PE reset done completely 1067cadf364dSGavin Shan * (until BAR restore). With the frozen state, HW drops illegal IO 1068cadf364dSGavin Shan * or MMIO access, which can incur recrusive frozen PE during PE 1069cadf364dSGavin Shan * reset. The side effect is that EEH core has to clear the frozen 1070cadf364dSGavin Shan * state explicitly after BAR restore. 1071cadf364dSGavin Shan */ 10724fad4943SGavin Shan if (pe->type & EEH_PE_PHB) 10734fad4943SGavin Shan return pnv_eeh_phb_reset(hose, option); 1074cadf364dSGavin Shan 1075cadf364dSGavin Shan /* 1076cadf364dSGavin Shan * The frozen PE might be caused by PAPR error injection 1077cadf364dSGavin Shan * registers, which are expected to be cleared after hitting 1078cadf364dSGavin Shan * frozen PE as stated in the hardware spec. Unfortunately, 1079cadf364dSGavin Shan * that's not true on P7IOC. So we have to clear it manually 1080cadf364dSGavin Shan * to avoid recursive EEH errors during recovery. 1081cadf364dSGavin Shan */ 1082cadf364dSGavin Shan phb = hose->private_data; 1083cadf364dSGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC && 1084cadf364dSGavin Shan (option == EEH_RESET_HOT || 1085cadf364dSGavin Shan option == EEH_RESET_FUNDAMENTAL)) { 1086cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 1087cadf364dSGavin Shan OPAL_RESET_PHB_ERROR, 1088cadf364dSGavin Shan OPAL_ASSERT_RESET); 1089cadf364dSGavin Shan if (rc != OPAL_SUCCESS) { 10904fad4943SGavin Shan pr_warn("%s: Failure %lld clearing error injection registers\n", 1091cadf364dSGavin Shan __func__, rc); 1092cadf364dSGavin Shan return -EIO; 1093cadf364dSGavin Shan } 1094cadf364dSGavin Shan } 1095cadf364dSGavin Shan 1096e98ddb77SRussell Currey if (pe->type & EEH_PE_VF) 1097e98ddb77SRussell Currey return pnv_eeh_reset_vf_pe(pe, option); 1098e98ddb77SRussell Currey 1099cadf364dSGavin Shan bus = eeh_pe_bus_get(pe); 110004fec21cSRussell Currey if (!bus) { 11011f52f176SRussell Currey pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 110204fec21cSRussell Currey __func__, pe->phb->global_number, pe->addr); 110304fec21cSRussell Currey return -EIO; 110404fec21cSRussell Currey } 110529310e5eSGavin Shan 1106b7da1230SAndrew Donnellan /* 1107b7da1230SAndrew Donnellan * If dealing with the root bus (or the bus underneath the 1108b7da1230SAndrew Donnellan * root port), we reset the bus underneath the root port. 1109b7da1230SAndrew Donnellan * 1110b7da1230SAndrew Donnellan * The cxl driver depends on this behaviour for bi-modal card 1111b7da1230SAndrew Donnellan * switching. 1112b7da1230SAndrew Donnellan */ 11134fad4943SGavin Shan if (pci_is_root_bus(bus) || 11144fad4943SGavin Shan pci_is_root_bus(bus->parent)) 11154fad4943SGavin Shan return pnv_eeh_root_reset(hose, option); 11164fad4943SGavin Shan 11174fad4943SGavin Shan return pnv_eeh_bridge_reset(bus->self, option); 111829310e5eSGavin Shan } 111929310e5eSGavin Shan 112029310e5eSGavin Shan /** 112101f3bfb7SGavin Shan * pnv_eeh_wait_state - Wait for PE state 112229310e5eSGavin Shan * @pe: EEH PE 11232ac3990cSWei Yang * @max_wait: maximal period in millisecond 112429310e5eSGavin Shan * 112529310e5eSGavin Shan * Wait for the state of associated PE. It might take some time 112629310e5eSGavin Shan * to retrieve the PE's state. 112729310e5eSGavin Shan */ 112801f3bfb7SGavin Shan static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) 112929310e5eSGavin Shan { 113029310e5eSGavin Shan int ret; 113129310e5eSGavin Shan int mwait; 113229310e5eSGavin Shan 113329310e5eSGavin Shan while (1) { 113401f3bfb7SGavin Shan ret = pnv_eeh_get_state(pe, &mwait); 113529310e5eSGavin Shan 113629310e5eSGavin Shan /* 113729310e5eSGavin Shan * If the PE's state is temporarily unavailable, 113829310e5eSGavin Shan * we have to wait for the specified time. Otherwise, 113929310e5eSGavin Shan * the PE's state will be returned immediately. 114029310e5eSGavin Shan */ 114129310e5eSGavin Shan if (ret != EEH_STATE_UNAVAILABLE) 114229310e5eSGavin Shan return ret; 114329310e5eSGavin Shan 114429310e5eSGavin Shan if (max_wait <= 0) { 11450dae2743SGavin Shan pr_warn("%s: Timeout getting PE#%x's state (%d)\n", 114629310e5eSGavin Shan __func__, pe->addr, max_wait); 114729310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 114829310e5eSGavin Shan } 114929310e5eSGavin Shan 1150e17866d5SWei Yang max_wait -= mwait; 115129310e5eSGavin Shan msleep(mwait); 115229310e5eSGavin Shan } 115329310e5eSGavin Shan 115429310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 115529310e5eSGavin Shan } 115629310e5eSGavin Shan 115729310e5eSGavin Shan /** 115801f3bfb7SGavin Shan * pnv_eeh_get_log - Retrieve error log 115929310e5eSGavin Shan * @pe: EEH PE 116029310e5eSGavin Shan * @severity: temporary or permanent error log 116129310e5eSGavin Shan * @drv_log: driver log to be combined with retrieved error log 116229310e5eSGavin Shan * @len: length of driver log 116329310e5eSGavin Shan * 116429310e5eSGavin Shan * Retrieve the temporary or permanent error from the PE. 116529310e5eSGavin Shan */ 116601f3bfb7SGavin Shan static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 116729310e5eSGavin Shan char *drv_log, unsigned long len) 116829310e5eSGavin Shan { 116995edcdeaSGavin Shan if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 117095edcdeaSGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 117129310e5eSGavin Shan 117295edcdeaSGavin Shan return 0; 117329310e5eSGavin Shan } 117429310e5eSGavin Shan 117529310e5eSGavin Shan /** 117601f3bfb7SGavin Shan * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 117729310e5eSGavin Shan * @pe: EEH PE 117829310e5eSGavin Shan * 117929310e5eSGavin Shan * The function will be called to reconfigure the bridges included 118029310e5eSGavin Shan * in the specified PE so that the mulfunctional PE would be recovered 118129310e5eSGavin Shan * again. 118229310e5eSGavin Shan */ 118301f3bfb7SGavin Shan static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 118429310e5eSGavin Shan { 1185bbe170edSGavin Shan return 0; 118629310e5eSGavin Shan } 118729310e5eSGavin Shan 118829310e5eSGavin Shan /** 118901f3bfb7SGavin Shan * pnv_pe_err_inject - Inject specified error to the indicated PE 1190131c123aSGavin Shan * @pe: the indicated PE 1191131c123aSGavin Shan * @type: error type 1192131c123aSGavin Shan * @func: specific error type 1193131c123aSGavin Shan * @addr: address 1194131c123aSGavin Shan * @mask: address mask 1195131c123aSGavin Shan * 1196131c123aSGavin Shan * The routine is called to inject specified error, which is 1197131c123aSGavin Shan * determined by @type and @func, to the indicated PE for 1198131c123aSGavin Shan * testing purpose. 1199131c123aSGavin Shan */ 120001f3bfb7SGavin Shan static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1201131c123aSGavin Shan unsigned long addr, unsigned long mask) 1202131c123aSGavin Shan { 1203131c123aSGavin Shan struct pci_controller *hose = pe->phb; 1204131c123aSGavin Shan struct pnv_phb *phb = hose->private_data; 1205fa646c3cSGavin Shan s64 rc; 1206131c123aSGavin Shan 1207fa646c3cSGavin Shan if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1208fa646c3cSGavin Shan type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1209fa646c3cSGavin Shan pr_warn("%s: Invalid error type %d\n", 1210fa646c3cSGavin Shan __func__, type); 1211fa646c3cSGavin Shan return -ERANGE; 1212fa646c3cSGavin Shan } 1213131c123aSGavin Shan 1214fa646c3cSGavin Shan if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1215fa646c3cSGavin Shan func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1216fa646c3cSGavin Shan pr_warn("%s: Invalid error function %d\n", 1217fa646c3cSGavin Shan __func__, func); 1218fa646c3cSGavin Shan return -ERANGE; 1219fa646c3cSGavin Shan } 1220fa646c3cSGavin Shan 1221fa646c3cSGavin Shan /* Firmware supports error injection ? */ 1222fa646c3cSGavin Shan if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1223fa646c3cSGavin Shan pr_warn("%s: Firmware doesn't support error injection\n", 1224fa646c3cSGavin Shan __func__); 1225fa646c3cSGavin Shan return -ENXIO; 1226fa646c3cSGavin Shan } 1227fa646c3cSGavin Shan 1228fa646c3cSGavin Shan /* Do error injection */ 1229fa646c3cSGavin Shan rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1230fa646c3cSGavin Shan type, func, addr, mask); 1231fa646c3cSGavin Shan if (rc != OPAL_SUCCESS) { 1232fa646c3cSGavin Shan pr_warn("%s: Failure %lld injecting error " 1233fa646c3cSGavin Shan "%d-%d to PHB#%x-PE#%x\n", 1234fa646c3cSGavin Shan __func__, rc, type, func, 1235fa646c3cSGavin Shan hose->global_number, pe->addr); 1236fa646c3cSGavin Shan return -EIO; 1237fa646c3cSGavin Shan } 1238fa646c3cSGavin Shan 1239fa646c3cSGavin Shan return 0; 1240131c123aSGavin Shan } 1241131c123aSGavin Shan 12420bd78587SGavin Shan static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1243d2cfbcd7SGavin Shan { 12440bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1245d2cfbcd7SGavin Shan 1246d2cfbcd7SGavin Shan if (!edev || !edev->pe) 1247d2cfbcd7SGavin Shan return false; 1248d2cfbcd7SGavin Shan 12499312bc5bSWei Yang /* 12509312bc5bSWei Yang * We will issue FLR or AF FLR to all VFs, which are contained 12519312bc5bSWei Yang * in VF PE. It relies on the EEH PCI config accessors. So we 12529312bc5bSWei Yang * can't block them during the window. 12539312bc5bSWei Yang */ 12549312bc5bSWei Yang if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 12559312bc5bSWei Yang return false; 12569312bc5bSWei Yang 1257d2cfbcd7SGavin Shan if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1258d2cfbcd7SGavin Shan return true; 1259d2cfbcd7SGavin Shan 1260d2cfbcd7SGavin Shan return false; 1261d2cfbcd7SGavin Shan } 1262d2cfbcd7SGavin Shan 12630bd78587SGavin Shan static int pnv_eeh_read_config(struct pci_dn *pdn, 1264d2cfbcd7SGavin Shan int where, int size, u32 *val) 1265d2cfbcd7SGavin Shan { 12663532a741SGavin Shan if (!pdn) 12673532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12683532a741SGavin Shan 12690bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) { 1270d2cfbcd7SGavin Shan *val = 0xFFFFFFFF; 1271d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1272d2cfbcd7SGavin Shan } 1273d2cfbcd7SGavin Shan 12743532a741SGavin Shan return pnv_pci_cfg_read(pdn, where, size, val); 1275d2cfbcd7SGavin Shan } 1276d2cfbcd7SGavin Shan 12770bd78587SGavin Shan static int pnv_eeh_write_config(struct pci_dn *pdn, 1278d2cfbcd7SGavin Shan int where, int size, u32 val) 1279d2cfbcd7SGavin Shan { 12803532a741SGavin Shan if (!pdn) 12813532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12823532a741SGavin Shan 12830bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) 1284d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1285d2cfbcd7SGavin Shan 12863532a741SGavin Shan return pnv_pci_cfg_write(pdn, where, size, val); 1287d2cfbcd7SGavin Shan } 1288d2cfbcd7SGavin Shan 12892a485ad7SGavin Shan static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 12902a485ad7SGavin Shan { 12912a485ad7SGavin Shan /* GEM */ 12922a485ad7SGavin Shan if (data->gemXfir || data->gemRfir || 12932a485ad7SGavin Shan data->gemRirqfir || data->gemMask || data->gemRwof) 12942a485ad7SGavin Shan pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 12952a485ad7SGavin Shan be64_to_cpu(data->gemXfir), 12962a485ad7SGavin Shan be64_to_cpu(data->gemRfir), 12972a485ad7SGavin Shan be64_to_cpu(data->gemRirqfir), 12982a485ad7SGavin Shan be64_to_cpu(data->gemMask), 12992a485ad7SGavin Shan be64_to_cpu(data->gemRwof)); 13002a485ad7SGavin Shan 13012a485ad7SGavin Shan /* LEM */ 13022a485ad7SGavin Shan if (data->lemFir || data->lemErrMask || 13032a485ad7SGavin Shan data->lemAction0 || data->lemAction1 || data->lemWof) 13042a485ad7SGavin Shan pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 13052a485ad7SGavin Shan be64_to_cpu(data->lemFir), 13062a485ad7SGavin Shan be64_to_cpu(data->lemErrMask), 13072a485ad7SGavin Shan be64_to_cpu(data->lemAction0), 13082a485ad7SGavin Shan be64_to_cpu(data->lemAction1), 13092a485ad7SGavin Shan be64_to_cpu(data->lemWof)); 13102a485ad7SGavin Shan } 13112a485ad7SGavin Shan 13122a485ad7SGavin Shan static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 13132a485ad7SGavin Shan { 13142a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 13155cb1f8fdSRussell Currey struct OpalIoP7IOCErrorData *data = 13165cb1f8fdSRussell Currey (struct OpalIoP7IOCErrorData*)phb->diag_data; 13172a485ad7SGavin Shan long rc; 13182a485ad7SGavin Shan 13192a485ad7SGavin Shan rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 13202a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 13212a485ad7SGavin Shan pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 13222a485ad7SGavin Shan __func__, phb->hub_id, rc); 13232a485ad7SGavin Shan return; 13242a485ad7SGavin Shan } 13252a485ad7SGavin Shan 1326a7032132SGavin Shan switch (be16_to_cpu(data->type)) { 13272a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_RGC: 13282a485ad7SGavin Shan pr_info("P7IOC diag-data for RGC\n\n"); 13292a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13302a485ad7SGavin Shan if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 13312a485ad7SGavin Shan pr_info(" RGC: %016llx %016llx\n", 13322a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcStatus), 13332a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcLdcp)); 13342a485ad7SGavin Shan break; 13352a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_BI: 13362a485ad7SGavin Shan pr_info("P7IOC diag-data for BI %s\n\n", 13372a485ad7SGavin Shan data->bi.biDownbound ? "Downbound" : "Upbound"); 13382a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13392a485ad7SGavin Shan if (data->bi.biLdcp0 || data->bi.biLdcp1 || 13402a485ad7SGavin Shan data->bi.biLdcp2 || data->bi.biFenceStatus) 13412a485ad7SGavin Shan pr_info(" BI: %016llx %016llx %016llx %016llx\n", 13422a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp0), 13432a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp1), 13442a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp2), 13452a485ad7SGavin Shan be64_to_cpu(data->bi.biFenceStatus)); 13462a485ad7SGavin Shan break; 13472a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_CI: 13482a485ad7SGavin Shan pr_info("P7IOC diag-data for CI Port %d\n\n", 13492a485ad7SGavin Shan data->ci.ciPort); 13502a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13512a485ad7SGavin Shan if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 13522a485ad7SGavin Shan pr_info(" CI: %016llx %016llx\n", 13532a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortStatus), 13542a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortLdcp)); 13552a485ad7SGavin Shan break; 13562a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_MISC: 13572a485ad7SGavin Shan pr_info("P7IOC diag-data for MISC\n\n"); 13582a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13592a485ad7SGavin Shan break; 13602a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_I2C: 13612a485ad7SGavin Shan pr_info("P7IOC diag-data for I2C\n\n"); 13622a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13632a485ad7SGavin Shan break; 13642a485ad7SGavin Shan default: 13652a485ad7SGavin Shan pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 13662a485ad7SGavin Shan __func__, phb->hub_id, data->type); 13672a485ad7SGavin Shan } 13682a485ad7SGavin Shan } 13692a485ad7SGavin Shan 13702a485ad7SGavin Shan static int pnv_eeh_get_pe(struct pci_controller *hose, 13712a485ad7SGavin Shan u16 pe_no, struct eeh_pe **pe) 13722a485ad7SGavin Shan { 13732a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 13742a485ad7SGavin Shan struct pnv_ioda_pe *pnv_pe; 13752a485ad7SGavin Shan struct eeh_pe *dev_pe; 13762a485ad7SGavin Shan 13772a485ad7SGavin Shan /* 13782a485ad7SGavin Shan * If PHB supports compound PE, to fetch 13792a485ad7SGavin Shan * the master PE because slave PE is invisible 13802a485ad7SGavin Shan * to EEH core. 13812a485ad7SGavin Shan */ 13822a485ad7SGavin Shan pnv_pe = &phb->ioda.pe_array[pe_no]; 13832a485ad7SGavin Shan if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 13842a485ad7SGavin Shan pnv_pe = pnv_pe->master; 13852a485ad7SGavin Shan WARN_ON(!pnv_pe || 13862a485ad7SGavin Shan !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 13872a485ad7SGavin Shan pe_no = pnv_pe->pe_number; 13882a485ad7SGavin Shan } 13892a485ad7SGavin Shan 13902a485ad7SGavin Shan /* Find the PE according to PE# */ 13918bae6a23SAlexey Kardashevskiy dev_pe = eeh_pe_get(hose, pe_no, 0); 13922a485ad7SGavin Shan if (!dev_pe) 13932a485ad7SGavin Shan return -EEXIST; 13942a485ad7SGavin Shan 13952a485ad7SGavin Shan /* Freeze the (compound) PE */ 13962a485ad7SGavin Shan *pe = dev_pe; 13972a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 13982a485ad7SGavin Shan phb->freeze_pe(phb, pe_no); 13992a485ad7SGavin Shan 14002a485ad7SGavin Shan /* 14012a485ad7SGavin Shan * At this point, we're sure the (compound) PE should 14022a485ad7SGavin Shan * have been frozen. However, we still need poke until 14032a485ad7SGavin Shan * hitting the frozen PE on top level. 14042a485ad7SGavin Shan */ 14052a485ad7SGavin Shan dev_pe = dev_pe->parent; 14062a485ad7SGavin Shan while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 14072a485ad7SGavin Shan int ret; 14082a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | 14092a485ad7SGavin Shan EEH_STATE_DMA_ACTIVE); 14102a485ad7SGavin Shan 14112a485ad7SGavin Shan ret = eeh_ops->get_state(dev_pe, NULL); 14122a485ad7SGavin Shan if (ret <= 0 || (ret & active_flags) == active_flags) { 14132a485ad7SGavin Shan dev_pe = dev_pe->parent; 14142a485ad7SGavin Shan continue; 14152a485ad7SGavin Shan } 14162a485ad7SGavin Shan 14172a485ad7SGavin Shan /* Frozen parent PE */ 14182a485ad7SGavin Shan *pe = dev_pe; 14192a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 14202a485ad7SGavin Shan phb->freeze_pe(phb, dev_pe->addr); 14212a485ad7SGavin Shan 14222a485ad7SGavin Shan /* Next one */ 14232a485ad7SGavin Shan dev_pe = dev_pe->parent; 14242a485ad7SGavin Shan } 14252a485ad7SGavin Shan 14262a485ad7SGavin Shan return 0; 14272a485ad7SGavin Shan } 14282a485ad7SGavin Shan 1429131c123aSGavin Shan /** 143001f3bfb7SGavin Shan * pnv_eeh_next_error - Retrieve next EEH error to handle 143129310e5eSGavin Shan * @pe: Affected PE 143229310e5eSGavin Shan * 14332a485ad7SGavin Shan * The function is expected to be called by EEH core while it gets 14342a485ad7SGavin Shan * special EEH event (without binding PE). The function calls to 14352a485ad7SGavin Shan * OPAL APIs for next error to handle. The informational error is 14362a485ad7SGavin Shan * handled internally by platform. However, the dead IOC, dead PHB, 14372a485ad7SGavin Shan * fenced PHB and frozen PE should be handled by EEH core eventually. 143829310e5eSGavin Shan */ 143901f3bfb7SGavin Shan static int pnv_eeh_next_error(struct eeh_pe **pe) 144029310e5eSGavin Shan { 144129310e5eSGavin Shan struct pci_controller *hose; 14422a485ad7SGavin Shan struct pnv_phb *phb; 14432a485ad7SGavin Shan struct eeh_pe *phb_pe, *parent_pe; 14442a485ad7SGavin Shan __be64 frozen_pe_no; 14452a485ad7SGavin Shan __be16 err_type, severity; 14462a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 14472a485ad7SGavin Shan long rc; 14482a485ad7SGavin Shan int state, ret = EEH_NEXT_ERR_NONE; 14492a485ad7SGavin Shan 14502a485ad7SGavin Shan /* 145179231448SAlistair Popple * While running here, it's safe to purge the event queue. The 145279231448SAlistair Popple * event should still be masked. 14532a485ad7SGavin Shan */ 14542a485ad7SGavin Shan eeh_remove_event(NULL, false); 145529310e5eSGavin Shan 145629310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 14572a485ad7SGavin Shan /* 14582a485ad7SGavin Shan * If the subordinate PCI buses of the PHB has been 14592a485ad7SGavin Shan * removed or is exactly under error recovery, we 14602a485ad7SGavin Shan * needn't take care of it any more. 14612a485ad7SGavin Shan */ 146229310e5eSGavin Shan phb = hose->private_data; 14632a485ad7SGavin Shan phb_pe = eeh_phb_pe_get(hose); 14642a485ad7SGavin Shan if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 14652a485ad7SGavin Shan continue; 14662a485ad7SGavin Shan 14672a485ad7SGavin Shan rc = opal_pci_next_error(phb->opal_id, 14682a485ad7SGavin Shan &frozen_pe_no, &err_type, &severity); 14692a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 14702a485ad7SGavin Shan pr_devel("%s: Invalid return value on " 14712a485ad7SGavin Shan "PHB#%x (0x%lx) from opal_pci_next_error", 14722a485ad7SGavin Shan __func__, hose->global_number, rc); 14732a485ad7SGavin Shan continue; 14742a485ad7SGavin Shan } 14752a485ad7SGavin Shan 14762a485ad7SGavin Shan /* If the PHB doesn't have error, stop processing */ 14772a485ad7SGavin Shan if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 14782a485ad7SGavin Shan be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 14792a485ad7SGavin Shan pr_devel("%s: No error found on PHB#%x\n", 14802a485ad7SGavin Shan __func__, hose->global_number); 14812a485ad7SGavin Shan continue; 14822a485ad7SGavin Shan } 14832a485ad7SGavin Shan 14842a485ad7SGavin Shan /* 14852a485ad7SGavin Shan * Processing the error. We're expecting the error with 14862a485ad7SGavin Shan * highest priority reported upon multiple errors on the 14872a485ad7SGavin Shan * specific PHB. 14882a485ad7SGavin Shan */ 14892a485ad7SGavin Shan pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 14902a485ad7SGavin Shan __func__, be16_to_cpu(err_type), 14912a485ad7SGavin Shan be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 14922a485ad7SGavin Shan hose->global_number); 14932a485ad7SGavin Shan switch (be16_to_cpu(err_type)) { 14942a485ad7SGavin Shan case OPAL_EEH_IOC_ERROR: 14952a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 14962a485ad7SGavin Shan pr_err("EEH: dead IOC detected\n"); 14972a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_IOC; 14982a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 14992a485ad7SGavin Shan pr_info("EEH: IOC informative error " 15002a485ad7SGavin Shan "detected\n"); 15012a485ad7SGavin Shan pnv_eeh_get_and_dump_hub_diag(hose); 15022a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15032a485ad7SGavin Shan } 15042a485ad7SGavin Shan 15052a485ad7SGavin Shan break; 15062a485ad7SGavin Shan case OPAL_EEH_PHB_ERROR: 15072a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 15082a485ad7SGavin Shan *pe = phb_pe; 15092a485ad7SGavin Shan pr_err("EEH: dead PHB#%x detected, " 15102a485ad7SGavin Shan "location: %s\n", 15112a485ad7SGavin Shan hose->global_number, 15122a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15132a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_PHB; 15142a485ad7SGavin Shan } else if (be16_to_cpu(severity) == 15152a485ad7SGavin Shan OPAL_EEH_SEV_PHB_FENCED) { 15162a485ad7SGavin Shan *pe = phb_pe; 15172a485ad7SGavin Shan pr_err("EEH: Fenced PHB#%x detected, " 15182a485ad7SGavin Shan "location: %s\n", 15192a485ad7SGavin Shan hose->global_number, 15202a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15212a485ad7SGavin Shan ret = EEH_NEXT_ERR_FENCED_PHB; 15222a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 15232a485ad7SGavin Shan pr_info("EEH: PHB#%x informative error " 15242a485ad7SGavin Shan "detected, location: %s\n", 15252a485ad7SGavin Shan hose->global_number, 15262a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15272a485ad7SGavin Shan pnv_eeh_get_phb_diag(phb_pe); 15282a485ad7SGavin Shan pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 15292a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15302a485ad7SGavin Shan } 15312a485ad7SGavin Shan 15322a485ad7SGavin Shan break; 15332a485ad7SGavin Shan case OPAL_EEH_PE_ERROR: 15342a485ad7SGavin Shan /* 15352a485ad7SGavin Shan * If we can't find the corresponding PE, we 15362a485ad7SGavin Shan * just try to unfreeze. 15372a485ad7SGavin Shan */ 15382a485ad7SGavin Shan if (pnv_eeh_get_pe(hose, 15392a485ad7SGavin Shan be64_to_cpu(frozen_pe_no), pe)) { 15402a485ad7SGavin Shan pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 15410f36db77SGavin Shan hose->global_number, be64_to_cpu(frozen_pe_no)); 15422a485ad7SGavin Shan pr_info("EEH: PHB location: %s\n", 15432a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 154479cd9520SGavin Shan 154579cd9520SGavin Shan /* Dump PHB diag-data */ 154679cd9520SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, 15475cb1f8fdSRussell Currey phb->diag_data, phb->diag_data_size); 154879cd9520SGavin Shan if (rc == OPAL_SUCCESS) 154979cd9520SGavin Shan pnv_pci_dump_phb_diag_data(hose, 15505cb1f8fdSRussell Currey phb->diag_data); 155179cd9520SGavin Shan 155279cd9520SGavin Shan /* Try best to clear it */ 15532a485ad7SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 1554d63e51b3SGavin Shan be64_to_cpu(frozen_pe_no), 15552a485ad7SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 15562a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15572a485ad7SGavin Shan } else if ((*pe)->state & EEH_PE_ISOLATED || 15582a485ad7SGavin Shan eeh_pe_passed(*pe)) { 15592a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15602a485ad7SGavin Shan } else { 15612a485ad7SGavin Shan pr_err("EEH: Frozen PE#%x " 15622a485ad7SGavin Shan "on PHB#%x detected\n", 15632a485ad7SGavin Shan (*pe)->addr, 15642a485ad7SGavin Shan (*pe)->phb->global_number); 15652a485ad7SGavin Shan pr_err("EEH: PE location: %s, " 15662a485ad7SGavin Shan "PHB location: %s\n", 15672a485ad7SGavin Shan eeh_pe_loc_get(*pe), 15682a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15692a485ad7SGavin Shan ret = EEH_NEXT_ERR_FROZEN_PE; 15702a485ad7SGavin Shan } 15712a485ad7SGavin Shan 15722a485ad7SGavin Shan break; 15732a485ad7SGavin Shan default: 15742a485ad7SGavin Shan pr_warn("%s: Unexpected error type %d\n", 15752a485ad7SGavin Shan __func__, be16_to_cpu(err_type)); 15762a485ad7SGavin Shan } 15772a485ad7SGavin Shan 15782a485ad7SGavin Shan /* 15792a485ad7SGavin Shan * EEH core will try recover from fenced PHB or 15802a485ad7SGavin Shan * frozen PE. In the time for frozen PE, EEH core 15812a485ad7SGavin Shan * enable IO path for that before collecting logs, 15822a485ad7SGavin Shan * but it ruins the site. So we have to dump the 15832a485ad7SGavin Shan * log in advance here. 15842a485ad7SGavin Shan */ 15852a485ad7SGavin Shan if ((ret == EEH_NEXT_ERR_FROZEN_PE || 15862a485ad7SGavin Shan ret == EEH_NEXT_ERR_FENCED_PHB) && 15872a485ad7SGavin Shan !((*pe)->state & EEH_PE_ISOLATED)) { 15882a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 15892a485ad7SGavin Shan pnv_eeh_get_phb_diag(*pe); 15902a485ad7SGavin Shan 15912a485ad7SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 15922a485ad7SGavin Shan pnv_pci_dump_phb_diag_data((*pe)->phb, 15932a485ad7SGavin Shan (*pe)->data); 15942a485ad7SGavin Shan } 15952a485ad7SGavin Shan 15962a485ad7SGavin Shan /* 15972a485ad7SGavin Shan * We probably have the frozen parent PE out there and 15982a485ad7SGavin Shan * we need have to handle frozen parent PE firstly. 15992a485ad7SGavin Shan */ 16002a485ad7SGavin Shan if (ret == EEH_NEXT_ERR_FROZEN_PE) { 16012a485ad7SGavin Shan parent_pe = (*pe)->parent; 16022a485ad7SGavin Shan while (parent_pe) { 16032a485ad7SGavin Shan /* Hit the ceiling ? */ 16042a485ad7SGavin Shan if (parent_pe->type & EEH_PE_PHB) 16052a485ad7SGavin Shan break; 16062a485ad7SGavin Shan 16072a485ad7SGavin Shan /* Frozen parent PE ? */ 16082a485ad7SGavin Shan state = eeh_ops->get_state(parent_pe, NULL); 16092a485ad7SGavin Shan if (state > 0 && 16102a485ad7SGavin Shan (state & active_flags) != active_flags) 16112a485ad7SGavin Shan *pe = parent_pe; 16122a485ad7SGavin Shan 16132a485ad7SGavin Shan /* Next parent level */ 16142a485ad7SGavin Shan parent_pe = parent_pe->parent; 16152a485ad7SGavin Shan } 16162a485ad7SGavin Shan 16172a485ad7SGavin Shan /* We possibly migrate to another PE */ 16182a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 16192a485ad7SGavin Shan } 16202a485ad7SGavin Shan 16212a485ad7SGavin Shan /* 16222a485ad7SGavin Shan * If we have no errors on the specific PHB or only 16232a485ad7SGavin Shan * informative error there, we continue poking it. 16242a485ad7SGavin Shan * Otherwise, we need actions to be taken by upper 16252a485ad7SGavin Shan * layer. 16262a485ad7SGavin Shan */ 16272a485ad7SGavin Shan if (ret > EEH_NEXT_ERR_INF) 162829310e5eSGavin Shan break; 162929310e5eSGavin Shan } 163029310e5eSGavin Shan 163179231448SAlistair Popple /* Unmask the event */ 1632b8d65e96SAlistair Popple if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 163379231448SAlistair Popple enable_irq(eeh_event_irq); 163479231448SAlistair Popple 16352a485ad7SGavin Shan return ret; 163629310e5eSGavin Shan } 163729310e5eSGavin Shan 16380dc2830eSWei Yang static int pnv_eeh_restore_vf_config(struct pci_dn *pdn) 16390dc2830eSWei Yang { 16400dc2830eSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 16410dc2830eSWei Yang u32 devctl, cmd, cap2, aer_capctl; 16420dc2830eSWei Yang int old_mps; 16430dc2830eSWei Yang 16440dc2830eSWei Yang if (edev->pcie_cap) { 16450dc2830eSWei Yang /* Restore MPS */ 16460dc2830eSWei Yang old_mps = (ffs(pdn->mps) - 8) << 5; 16470dc2830eSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 16480dc2830eSWei Yang 2, &devctl); 16490dc2830eSWei Yang devctl &= ~PCI_EXP_DEVCTL_PAYLOAD; 16500dc2830eSWei Yang devctl |= old_mps; 16510dc2830eSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 16520dc2830eSWei Yang 2, devctl); 16530dc2830eSWei Yang 16540dc2830eSWei Yang /* Disable Completion Timeout */ 16550dc2830eSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2, 16560dc2830eSWei Yang 4, &cap2); 16570dc2830eSWei Yang if (cap2 & 0x10) { 16580dc2830eSWei Yang eeh_ops->read_config(pdn, 16590dc2830eSWei Yang edev->pcie_cap + PCI_EXP_DEVCTL2, 16600dc2830eSWei Yang 4, &cap2); 16610dc2830eSWei Yang cap2 |= 0x10; 16620dc2830eSWei Yang eeh_ops->write_config(pdn, 16630dc2830eSWei Yang edev->pcie_cap + PCI_EXP_DEVCTL2, 16640dc2830eSWei Yang 4, cap2); 16650dc2830eSWei Yang } 16660dc2830eSWei Yang } 16670dc2830eSWei Yang 16680dc2830eSWei Yang /* Enable SERR and parity checking */ 16690dc2830eSWei Yang eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd); 16700dc2830eSWei Yang cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 16710dc2830eSWei Yang eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd); 16720dc2830eSWei Yang 16730dc2830eSWei Yang /* Enable report various errors */ 16740dc2830eSWei Yang if (edev->pcie_cap) { 16750dc2830eSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 16760dc2830eSWei Yang 2, &devctl); 16770dc2830eSWei Yang devctl &= ~PCI_EXP_DEVCTL_CERE; 16780dc2830eSWei Yang devctl |= (PCI_EXP_DEVCTL_NFERE | 16790dc2830eSWei Yang PCI_EXP_DEVCTL_FERE | 16800dc2830eSWei Yang PCI_EXP_DEVCTL_URRE); 16810dc2830eSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 16820dc2830eSWei Yang 2, devctl); 16830dc2830eSWei Yang } 16840dc2830eSWei Yang 16850dc2830eSWei Yang /* Enable ECRC generation and check */ 16860dc2830eSWei Yang if (edev->pcie_cap && edev->aer_cap) { 16870dc2830eSWei Yang eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP, 16880dc2830eSWei Yang 4, &aer_capctl); 16890dc2830eSWei Yang aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); 16900dc2830eSWei Yang eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP, 16910dc2830eSWei Yang 4, aer_capctl); 16920dc2830eSWei Yang } 16930dc2830eSWei Yang 16940dc2830eSWei Yang return 0; 16950dc2830eSWei Yang } 16960dc2830eSWei Yang 16970bd78587SGavin Shan static int pnv_eeh_restore_config(struct pci_dn *pdn) 16989be3beccSGavin Shan { 16990bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 17009be3beccSGavin Shan struct pnv_phb *phb; 17019be3beccSGavin Shan s64 ret; 17029be3beccSGavin Shan 17039be3beccSGavin Shan if (!edev) 17049be3beccSGavin Shan return -EEXIST; 17059be3beccSGavin Shan 17060dc2830eSWei Yang /* 17070dc2830eSWei Yang * We have to restore the PCI config space after reset since the 17080dc2830eSWei Yang * firmware can't see SRIOV VFs. 17090dc2830eSWei Yang * 17100dc2830eSWei Yang * FIXME: The MPS, error routing rules, timeout setting are worthy 17110dc2830eSWei Yang * to be exported by firmware in extendible way. 17120dc2830eSWei Yang */ 17130dc2830eSWei Yang if (edev->physfn) { 17140dc2830eSWei Yang ret = pnv_eeh_restore_vf_config(pdn); 17150dc2830eSWei Yang } else { 171669672bd7SAlexey Kardashevskiy phb = pdn->phb->private_data; 17179be3beccSGavin Shan ret = opal_pci_reinit(phb->opal_id, 17189be3beccSGavin Shan OPAL_REINIT_PCI_DEV, edev->config_addr); 17190dc2830eSWei Yang } 17200dc2830eSWei Yang 17219be3beccSGavin Shan if (ret) { 17229be3beccSGavin Shan pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 17239be3beccSGavin Shan __func__, edev->config_addr, ret); 17249be3beccSGavin Shan return -EIO; 17259be3beccSGavin Shan } 17269be3beccSGavin Shan 17279be3beccSGavin Shan return 0; 17289be3beccSGavin Shan } 17299be3beccSGavin Shan 173001f3bfb7SGavin Shan static struct eeh_ops pnv_eeh_ops = { 173129310e5eSGavin Shan .name = "powernv", 173201f3bfb7SGavin Shan .init = pnv_eeh_init, 173301f3bfb7SGavin Shan .post_init = pnv_eeh_post_init, 1734ff57b454SGavin Shan .probe = pnv_eeh_probe, 173501f3bfb7SGavin Shan .set_option = pnv_eeh_set_option, 173601f3bfb7SGavin Shan .get_pe_addr = pnv_eeh_get_pe_addr, 173701f3bfb7SGavin Shan .get_state = pnv_eeh_get_state, 173801f3bfb7SGavin Shan .reset = pnv_eeh_reset, 173901f3bfb7SGavin Shan .wait_state = pnv_eeh_wait_state, 174001f3bfb7SGavin Shan .get_log = pnv_eeh_get_log, 174101f3bfb7SGavin Shan .configure_bridge = pnv_eeh_configure_bridge, 174201f3bfb7SGavin Shan .err_inject = pnv_eeh_err_inject, 174301f3bfb7SGavin Shan .read_config = pnv_eeh_read_config, 174401f3bfb7SGavin Shan .write_config = pnv_eeh_write_config, 174501f3bfb7SGavin Shan .next_error = pnv_eeh_next_error, 174601f3bfb7SGavin Shan .restore_config = pnv_eeh_restore_config 174729310e5eSGavin Shan }; 174829310e5eSGavin Shan 1749c29fa27dSWei Yang void pcibios_bus_add_device(struct pci_dev *pdev) 1750c29fa27dSWei Yang { 1751c29fa27dSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 1752c29fa27dSWei Yang 1753c29fa27dSWei Yang if (!pdev->is_virtfn) 1754c29fa27dSWei Yang return; 1755c29fa27dSWei Yang 1756c29fa27dSWei Yang /* 1757c29fa27dSWei Yang * The following operations will fail if VF's sysfs files 1758c29fa27dSWei Yang * aren't created or its resources aren't finalized. 1759c29fa27dSWei Yang */ 1760c29fa27dSWei Yang eeh_add_device_early(pdn); 1761c29fa27dSWei Yang eeh_add_device_late(pdev); 1762c29fa27dSWei Yang eeh_sysfs_add_device(pdev); 1763c29fa27dSWei Yang } 1764c29fa27dSWei Yang 17650dc2830eSWei Yang #ifdef CONFIG_PCI_IOV 17660dc2830eSWei Yang static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 17670dc2830eSWei Yang { 17680dc2830eSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 17690dc2830eSWei Yang int parent_mps; 17700dc2830eSWei Yang 17710dc2830eSWei Yang if (!pdev->is_virtfn) 17720dc2830eSWei Yang return; 17730dc2830eSWei Yang 17740dc2830eSWei Yang /* Synchronize MPS for VF and PF */ 17750dc2830eSWei Yang parent_mps = pcie_get_mps(pdev->physfn); 17760dc2830eSWei Yang if ((128 << pdev->pcie_mpss) >= parent_mps) 17770dc2830eSWei Yang pcie_set_mps(pdev, parent_mps); 17780dc2830eSWei Yang pdn->mps = pcie_get_mps(pdev); 17790dc2830eSWei Yang } 17800dc2830eSWei Yang DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 17810dc2830eSWei Yang #endif /* CONFIG_PCI_IOV */ 17820dc2830eSWei Yang 178329310e5eSGavin Shan /** 178429310e5eSGavin Shan * eeh_powernv_init - Register platform dependent EEH operations 178529310e5eSGavin Shan * 178629310e5eSGavin Shan * EEH initialization on powernv platform. This function should be 178729310e5eSGavin Shan * called before any EEH related functions. 178829310e5eSGavin Shan */ 178929310e5eSGavin Shan static int __init eeh_powernv_init(void) 179029310e5eSGavin Shan { 179129310e5eSGavin Shan int ret = -EINVAL; 179229310e5eSGavin Shan 179301f3bfb7SGavin Shan ret = eeh_ops_register(&pnv_eeh_ops); 179429310e5eSGavin Shan if (!ret) 179529310e5eSGavin Shan pr_info("EEH: PowerNV platform initialized\n"); 179629310e5eSGavin Shan else 179729310e5eSGavin Shan pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 179829310e5eSGavin Shan 179929310e5eSGavin Shan return ret; 180029310e5eSGavin Shan } 1801b14726c5SMichael Ellerman machine_early_initcall(powernv, eeh_powernv_init); 1802