12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 229310e5eSGavin Shan /* 341732bdcSStewart Smith * PowerNV Platform dependent EEH operations 429310e5eSGavin Shan * 529310e5eSGavin Shan * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 629310e5eSGavin Shan */ 729310e5eSGavin Shan 829310e5eSGavin Shan #include <linux/atomic.h> 94cf17445SGavin Shan #include <linux/debugfs.h> 1029310e5eSGavin Shan #include <linux/delay.h> 1129310e5eSGavin Shan #include <linux/export.h> 1229310e5eSGavin Shan #include <linux/init.h> 1379231448SAlistair Popple #include <linux/interrupt.h> 1429310e5eSGavin Shan #include <linux/list.h> 1529310e5eSGavin Shan #include <linux/msi.h> 1629310e5eSGavin Shan #include <linux/of.h> 1729310e5eSGavin Shan #include <linux/pci.h> 1829310e5eSGavin Shan #include <linux/proc_fs.h> 1929310e5eSGavin Shan #include <linux/rbtree.h> 2029310e5eSGavin Shan #include <linux/sched.h> 2129310e5eSGavin Shan #include <linux/seq_file.h> 2229310e5eSGavin Shan #include <linux/spinlock.h> 2329310e5eSGavin Shan 2429310e5eSGavin Shan #include <asm/eeh.h> 2529310e5eSGavin Shan #include <asm/eeh_event.h> 2629310e5eSGavin Shan #include <asm/firmware.h> 2729310e5eSGavin Shan #include <asm/io.h> 2829310e5eSGavin Shan #include <asm/iommu.h> 2929310e5eSGavin Shan #include <asm/machdep.h> 3029310e5eSGavin Shan #include <asm/msi_bitmap.h> 3129310e5eSGavin Shan #include <asm/opal.h> 3229310e5eSGavin Shan #include <asm/ppc-pci.h> 339c0e1ecbSGavin Shan #include <asm/pnv-pci.h> 3429310e5eSGavin Shan 3529310e5eSGavin Shan #include "powernv.h" 3629310e5eSGavin Shan #include "pci.h" 3729310e5eSGavin Shan 3879231448SAlistair Popple static int eeh_event_irq = -EINVAL; 394cf17445SGavin Shan 40988fc3baSBryant G. Ly void pnv_pcibios_bus_add_device(struct pci_dev *pdev) 41988fc3baSBryant G. Ly { 42988fc3baSBryant G. Ly struct pci_dn *pdn = pci_get_pdn(pdev); 43988fc3baSBryant G. Ly 44988fc3baSBryant G. Ly if (!pdev->is_virtfn) 45988fc3baSBryant G. Ly return; 46988fc3baSBryant G. Ly 47617082a4SSam Bobroff pr_debug("%s: EEH: Setting up device %s.\n", __func__, pci_name(pdev)); 48988fc3baSBryant G. Ly eeh_add_device_early(pdn); 49988fc3baSBryant G. Ly eeh_add_device_late(pdev); 50988fc3baSBryant G. Ly eeh_sysfs_add_device(pdev); 51988fc3baSBryant G. Ly } 52988fc3baSBryant G. Ly 5301f3bfb7SGavin Shan static int pnv_eeh_init(void) 5429310e5eSGavin Shan { 55dc561fb9SGavin Shan struct pci_controller *hose; 56dc561fb9SGavin Shan struct pnv_phb *phb; 575cb1f8fdSRussell Currey int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 58dc561fb9SGavin Shan 59e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 60e4d54f71SStewart Smith pr_warn("%s: OPAL is required !\n", 610dae2743SGavin Shan __func__); 6229310e5eSGavin Shan return -EINVAL; 6329310e5eSGavin Shan } 6429310e5eSGavin Shan 6505b1721dSGavin Shan /* Set probe mode */ 6605b1721dSGavin Shan eeh_add_flag(EEH_PROBE_MODE_DEV); 6729310e5eSGavin Shan 68dc561fb9SGavin Shan /* 69dc561fb9SGavin Shan * P7IOC blocks PCI config access to frozen PE, but PHB3 70dc561fb9SGavin Shan * doesn't do that. So we have to selectively enable I/O 71dc561fb9SGavin Shan * prior to collecting error log. 72dc561fb9SGavin Shan */ 73dc561fb9SGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 74dc561fb9SGavin Shan phb = hose->private_data; 75dc561fb9SGavin Shan 76dc561fb9SGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC) 77dc561fb9SGavin Shan eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 782aa5cf9eSGavin Shan 795cb1f8fdSRussell Currey if (phb->diag_data_size > max_diag_size) 805cb1f8fdSRussell Currey max_diag_size = phb->diag_data_size; 815cb1f8fdSRussell Currey 822aa5cf9eSGavin Shan /* 832aa5cf9eSGavin Shan * PE#0 should be regarded as valid by EEH core 842aa5cf9eSGavin Shan * if it's not the reserved one. Currently, we 85608fb9c2SGavin Shan * have the reserved PE#255 and PE#127 for PHB3 862aa5cf9eSGavin Shan * and P7IOC separately. So we should regard 87608fb9c2SGavin Shan * PE#0 as valid for PHB3 and P7IOC. 882aa5cf9eSGavin Shan */ 8992b8f137SGavin Shan if (phb->ioda.reserved_pe_idx != 0) 902aa5cf9eSGavin Shan eeh_add_flag(EEH_VALID_PE_ZERO); 912aa5cf9eSGavin Shan 92dc561fb9SGavin Shan break; 93dc561fb9SGavin Shan } 94dc561fb9SGavin Shan 955cb1f8fdSRussell Currey eeh_set_pe_aux_size(max_diag_size); 96988fc3baSBryant G. Ly ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device; 975cb1f8fdSRussell Currey 9829310e5eSGavin Shan return 0; 9929310e5eSGavin Shan } 10029310e5eSGavin Shan 10179231448SAlistair Popple static irqreturn_t pnv_eeh_event(int irq, void *data) 1024cf17445SGavin Shan { 1034cf17445SGavin Shan /* 10479231448SAlistair Popple * We simply send a special EEH event if EEH has been 10579231448SAlistair Popple * enabled. We don't care about EEH events until we've 10679231448SAlistair Popple * finished processing the outstanding ones. Event processing 10779231448SAlistair Popple * gets unmasked in next_error() if EEH is enabled. 1084cf17445SGavin Shan */ 10979231448SAlistair Popple disable_irq_nosync(irq); 1104cf17445SGavin Shan 1114cf17445SGavin Shan if (eeh_enabled()) 1124cf17445SGavin Shan eeh_send_failure_event(NULL); 1134cf17445SGavin Shan 11479231448SAlistair Popple return IRQ_HANDLED; 1154cf17445SGavin Shan } 1164cf17445SGavin Shan 1174cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 1184cf17445SGavin Shan static ssize_t pnv_eeh_ei_write(struct file *filp, 1194cf17445SGavin Shan const char __user *user_buf, 1204cf17445SGavin Shan size_t count, loff_t *ppos) 1214cf17445SGavin Shan { 1224cf17445SGavin Shan struct pci_controller *hose = filp->private_data; 1234cf17445SGavin Shan struct eeh_pe *pe; 1244cf17445SGavin Shan int pe_no, type, func; 1254cf17445SGavin Shan unsigned long addr, mask; 1264cf17445SGavin Shan char buf[50]; 1274cf17445SGavin Shan int ret; 1284cf17445SGavin Shan 1294cf17445SGavin Shan if (!eeh_ops || !eeh_ops->err_inject) 1304cf17445SGavin Shan return -ENXIO; 1314cf17445SGavin Shan 1324cf17445SGavin Shan /* Copy over argument buffer */ 1334cf17445SGavin Shan ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 1344cf17445SGavin Shan if (!ret) 1354cf17445SGavin Shan return -EFAULT; 1364cf17445SGavin Shan 1374cf17445SGavin Shan /* Retrieve parameters */ 1384cf17445SGavin Shan ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 1394cf17445SGavin Shan &pe_no, &type, &func, &addr, &mask); 1404cf17445SGavin Shan if (ret != 5) 1414cf17445SGavin Shan return -EINVAL; 1424cf17445SGavin Shan 1434cf17445SGavin Shan /* Retrieve PE */ 1448bae6a23SAlexey Kardashevskiy pe = eeh_pe_get(hose, pe_no, 0); 1454cf17445SGavin Shan if (!pe) 1464cf17445SGavin Shan return -ENODEV; 1474cf17445SGavin Shan 1484cf17445SGavin Shan /* Do error injection */ 1494cf17445SGavin Shan ret = eeh_ops->err_inject(pe, type, func, addr, mask); 1504cf17445SGavin Shan return ret < 0 ? ret : count; 1514cf17445SGavin Shan } 1524cf17445SGavin Shan 1534cf17445SGavin Shan static const struct file_operations pnv_eeh_ei_fops = { 1544cf17445SGavin Shan .open = simple_open, 1554cf17445SGavin Shan .llseek = no_llseek, 1564cf17445SGavin Shan .write = pnv_eeh_ei_write, 1574cf17445SGavin Shan }; 1584cf17445SGavin Shan 1594cf17445SGavin Shan static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 1604cf17445SGavin Shan { 1614cf17445SGavin Shan struct pci_controller *hose = data; 1624cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1634cf17445SGavin Shan 1644cf17445SGavin Shan out_be64(phb->regs + offset, val); 1654cf17445SGavin Shan return 0; 1664cf17445SGavin Shan } 1674cf17445SGavin Shan 1684cf17445SGavin Shan static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 1694cf17445SGavin Shan { 1704cf17445SGavin Shan struct pci_controller *hose = data; 1714cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1724cf17445SGavin Shan 1734cf17445SGavin Shan *val = in_be64(phb->regs + offset); 1744cf17445SGavin Shan return 0; 1754cf17445SGavin Shan } 1764cf17445SGavin Shan 177ccc9662dSGavin Shan #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 178ccc9662dSGavin Shan static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 179ccc9662dSGavin Shan { \ 180ccc9662dSGavin Shan return pnv_eeh_dbgfs_set(data, reg, val); \ 181ccc9662dSGavin Shan } \ 182ccc9662dSGavin Shan \ 183ccc9662dSGavin Shan static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 184ccc9662dSGavin Shan { \ 185ccc9662dSGavin Shan return pnv_eeh_dbgfs_get(data, reg, val); \ 186ccc9662dSGavin Shan } \ 187ccc9662dSGavin Shan \ 188ccc9662dSGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 189ccc9662dSGavin Shan pnv_eeh_dbgfs_get_##name, \ 190ccc9662dSGavin Shan pnv_eeh_dbgfs_set_##name, \ 191ccc9662dSGavin Shan "0x%llx\n") 1924cf17445SGavin Shan 193ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 194ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 195ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 1964cf17445SGavin Shan 1974cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 1984cf17445SGavin Shan 19929310e5eSGavin Shan /** 20001f3bfb7SGavin Shan * pnv_eeh_post_init - EEH platform dependent post initialization 20129310e5eSGavin Shan * 20229310e5eSGavin Shan * EEH platform dependent post initialization on powernv. When 20329310e5eSGavin Shan * the function is called, the EEH PEs and devices should have 20429310e5eSGavin Shan * been built. If the I/O cache staff has been built, EEH is 20529310e5eSGavin Shan * ready to supply service. 20629310e5eSGavin Shan */ 207b9fde58dSBenjamin Herrenschmidt int pnv_eeh_post_init(void) 20829310e5eSGavin Shan { 20929310e5eSGavin Shan struct pci_controller *hose; 21029310e5eSGavin Shan struct pnv_phb *phb; 21129310e5eSGavin Shan int ret = 0; 21229310e5eSGavin Shan 213b9fde58dSBenjamin Herrenschmidt /* Probe devices & build address cache */ 214b9fde58dSBenjamin Herrenschmidt eeh_probe_devices(); 215b9fde58dSBenjamin Herrenschmidt eeh_addr_cache_build(); 216b9fde58dSBenjamin Herrenschmidt 2174cf17445SGavin Shan /* Register OPAL event notifier */ 21879231448SAlistair Popple eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 21979231448SAlistair Popple if (eeh_event_irq < 0) { 22079231448SAlistair Popple pr_err("%s: Can't register OPAL event interrupt (%d)\n", 22179231448SAlistair Popple __func__, eeh_event_irq); 22279231448SAlistair Popple return eeh_event_irq; 22379231448SAlistair Popple } 22479231448SAlistair Popple 22579231448SAlistair Popple ret = request_irq(eeh_event_irq, pnv_eeh_event, 22679231448SAlistair Popple IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 22779231448SAlistair Popple if (ret < 0) { 22879231448SAlistair Popple irq_dispose_mapping(eeh_event_irq); 22979231448SAlistair Popple pr_err("%s: Can't request OPAL event interrupt (%d)\n", 23079231448SAlistair Popple __func__, eeh_event_irq); 2314cf17445SGavin Shan return ret; 2324cf17445SGavin Shan } 2334cf17445SGavin Shan 23479231448SAlistair Popple if (!eeh_enabled()) 23579231448SAlistair Popple disable_irq(eeh_event_irq); 23679231448SAlistair Popple 23729310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 23829310e5eSGavin Shan phb = hose->private_data; 23929310e5eSGavin Shan 2404cf17445SGavin Shan /* 2414cf17445SGavin Shan * If EEH is enabled, we're going to rely on that. 2424cf17445SGavin Shan * Otherwise, we restore to conventional mechanism 2434cf17445SGavin Shan * to clear frozen PE during PCI config access. 2444cf17445SGavin Shan */ 2454cf17445SGavin Shan if (eeh_enabled()) 2464cf17445SGavin Shan phb->flags |= PNV_PHB_FLAG_EEH; 2474cf17445SGavin Shan else 2484cf17445SGavin Shan phb->flags &= ~PNV_PHB_FLAG_EEH; 2494cf17445SGavin Shan 2504cf17445SGavin Shan /* Create debugfs entries */ 2514cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 2524cf17445SGavin Shan if (phb->has_dbgfs || !phb->dbgfs) 2534cf17445SGavin Shan continue; 2544cf17445SGavin Shan 2554cf17445SGavin Shan phb->has_dbgfs = 1; 2564cf17445SGavin Shan debugfs_create_file("err_injct", 0200, 2574cf17445SGavin Shan phb->dbgfs, hose, 2584cf17445SGavin Shan &pnv_eeh_ei_fops); 2594cf17445SGavin Shan 2604cf17445SGavin Shan debugfs_create_file("err_injct_outbound", 0600, 2614cf17445SGavin Shan phb->dbgfs, hose, 262ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_outb); 2634cf17445SGavin Shan debugfs_create_file("err_injct_inboundA", 0600, 2644cf17445SGavin Shan phb->dbgfs, hose, 265ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbA); 2664cf17445SGavin Shan debugfs_create_file("err_injct_inboundB", 0600, 2674cf17445SGavin Shan phb->dbgfs, hose, 268ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbB); 2694cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 27029310e5eSGavin Shan } 2714cf17445SGavin Shan 27229310e5eSGavin Shan return ret; 27329310e5eSGavin Shan } 27429310e5eSGavin Shan 2754d6186caSGavin Shan static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 276ff57b454SGavin Shan { 2774d6186caSGavin Shan int pos = PCI_CAPABILITY_LIST; 2784d6186caSGavin Shan int cnt = 48; /* Maximal number of capabilities */ 2794d6186caSGavin Shan u32 status, id; 280ff57b454SGavin Shan 281ff57b454SGavin Shan if (!pdn) 282ff57b454SGavin Shan return 0; 283ff57b454SGavin Shan 2844d6186caSGavin Shan /* Check if the device supports capabilities */ 285ff57b454SGavin Shan pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 286ff57b454SGavin Shan if (!(status & PCI_STATUS_CAP_LIST)) 287ff57b454SGavin Shan return 0; 288ff57b454SGavin Shan 289ff57b454SGavin Shan while (cnt--) { 290ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos, 1, &pos); 291ff57b454SGavin Shan if (pos < 0x40) 292ff57b454SGavin Shan break; 293ff57b454SGavin Shan 294ff57b454SGavin Shan pos &= ~3; 295ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 296ff57b454SGavin Shan if (id == 0xff) 297ff57b454SGavin Shan break; 298ff57b454SGavin Shan 299ff57b454SGavin Shan /* Found */ 300ff57b454SGavin Shan if (id == cap) 301ff57b454SGavin Shan return pos; 302ff57b454SGavin Shan 303ff57b454SGavin Shan /* Next one */ 304ff57b454SGavin Shan pos += PCI_CAP_LIST_NEXT; 305ff57b454SGavin Shan } 306ff57b454SGavin Shan 307ff57b454SGavin Shan return 0; 308ff57b454SGavin Shan } 309ff57b454SGavin Shan 310ff57b454SGavin Shan static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 311ff57b454SGavin Shan { 312ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 313ff57b454SGavin Shan u32 header; 314ff57b454SGavin Shan int pos = 256, ttl = (4096 - 256) / 8; 315ff57b454SGavin Shan 316ff57b454SGavin Shan if (!edev || !edev->pcie_cap) 317ff57b454SGavin Shan return 0; 318ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 319ff57b454SGavin Shan return 0; 320ff57b454SGavin Shan else if (!header) 321ff57b454SGavin Shan return 0; 322ff57b454SGavin Shan 323ff57b454SGavin Shan while (ttl-- > 0) { 324ff57b454SGavin Shan if (PCI_EXT_CAP_ID(header) == cap && pos) 325ff57b454SGavin Shan return pos; 326ff57b454SGavin Shan 327ff57b454SGavin Shan pos = PCI_EXT_CAP_NEXT(header); 328ff57b454SGavin Shan if (pos < 256) 329ff57b454SGavin Shan break; 330ff57b454SGavin Shan 331ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 332ff57b454SGavin Shan break; 333ff57b454SGavin Shan } 334ff57b454SGavin Shan 335ff57b454SGavin Shan return 0; 336ff57b454SGavin Shan } 337ff57b454SGavin Shan 33829310e5eSGavin Shan /** 339ff57b454SGavin Shan * pnv_eeh_probe - Do probe on PCI device 340ff57b454SGavin Shan * @pdn: PCI device node 341ff57b454SGavin Shan * @data: unused 34229310e5eSGavin Shan * 34329310e5eSGavin Shan * When EEH module is installed during system boot, all PCI devices 34429310e5eSGavin Shan * are checked one by one to see if it supports EEH. The function 34529310e5eSGavin Shan * is introduced for the purpose. By default, EEH has been enabled 34629310e5eSGavin Shan * on all PCI devices. That's to say, we only need do necessary 34729310e5eSGavin Shan * initialization on the corresponding eeh device and create PE 34829310e5eSGavin Shan * accordingly. 34929310e5eSGavin Shan * 35029310e5eSGavin Shan * It's notable that's unsafe to retrieve the EEH device through 35129310e5eSGavin Shan * the corresponding PCI device. During the PCI device hotplug, which 35229310e5eSGavin Shan * was possiblly triggered by EEH core, the binding between EEH device 35329310e5eSGavin Shan * and the PCI device isn't built yet. 35429310e5eSGavin Shan */ 355ff57b454SGavin Shan static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 35629310e5eSGavin Shan { 357ff57b454SGavin Shan struct pci_controller *hose = pdn->phb; 35829310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 359ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 360ff57b454SGavin Shan uint32_t pcie_flags; 361dadcd6d6SMike Qiu int ret; 362405b33a7SAlexey Kardashevskiy int config_addr = (pdn->busno << 8) | (pdn->devfn); 36329310e5eSGavin Shan 364617082a4SSam Bobroff pr_debug("%s: probing %04x:%02x:%02x.%01x\n", 365617082a4SSam Bobroff __func__, hose->global_number, pdn->busno, 366617082a4SSam Bobroff PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 367617082a4SSam Bobroff 36829310e5eSGavin Shan /* 36929310e5eSGavin Shan * When probing the root bridge, which doesn't have any 37029310e5eSGavin Shan * subordinate PCI devices. We don't have OF node for 37129310e5eSGavin Shan * the root bridge. So it's not reasonable to continue 37229310e5eSGavin Shan * the probing. 37329310e5eSGavin Shan */ 374ff57b454SGavin Shan if (!edev || edev->pe) 375ff57b454SGavin Shan return NULL; 37629310e5eSGavin Shan 37729310e5eSGavin Shan /* Skip for PCI-ISA bridge */ 378ff57b454SGavin Shan if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 379ff57b454SGavin Shan return NULL; 38029310e5eSGavin Shan 38129310e5eSGavin Shan /* Initialize eeh device */ 382ff57b454SGavin Shan edev->class_code = pdn->class_code; 383ab55d218SGavin Shan edev->mode &= 0xFFFFFF00; 384ff57b454SGavin Shan edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 385ff57b454SGavin Shan edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 3869312bc5bSWei Yang edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 387ff57b454SGavin Shan edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 388ff57b454SGavin Shan if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 3894b83bd45SGavin Shan edev->mode |= EEH_DEV_BRIDGE; 390ff57b454SGavin Shan if (edev->pcie_cap) { 391ff57b454SGavin Shan pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 392ff57b454SGavin Shan 2, &pcie_flags); 393ff57b454SGavin Shan pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 394ff57b454SGavin Shan if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 3954b83bd45SGavin Shan edev->mode |= EEH_DEV_ROOT_PORT; 396ff57b454SGavin Shan else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 3974b83bd45SGavin Shan edev->mode |= EEH_DEV_DS_PORT; 398ff57b454SGavin Shan } 3994b83bd45SGavin Shan } 4004b83bd45SGavin Shan 401405b33a7SAlexey Kardashevskiy edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; 40229310e5eSGavin Shan 40329310e5eSGavin Shan /* Create PE */ 404dadcd6d6SMike Qiu ret = eeh_add_to_parent_pe(edev); 405dadcd6d6SMike Qiu if (ret) { 4061f52f176SRussell Currey pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n", 407ff57b454SGavin Shan __func__, hose->global_number, pdn->busno, 408ff57b454SGavin Shan PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 409ff57b454SGavin Shan return NULL; 410dadcd6d6SMike Qiu } 411dadcd6d6SMike Qiu 412dadcd6d6SMike Qiu /* 413b6541db1SGavin Shan * If the PE contains any one of following adapters, the 414b6541db1SGavin Shan * PCI config space can't be accessed when dumping EEH log. 415b6541db1SGavin Shan * Otherwise, we will run into fenced PHB caused by shortage 416b6541db1SGavin Shan * of outbound credits in the adapter. The PCI config access 417b6541db1SGavin Shan * should be blocked until PE reset. MMIO access is dropped 418b6541db1SGavin Shan * by hardware certainly. In order to drop PCI config requests, 419b6541db1SGavin Shan * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 420b6541db1SGavin Shan * will be checked in the backend for PE state retrival. If 421b6541db1SGavin Shan * the PE becomes frozen for the first time and the flag has 422b6541db1SGavin Shan * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 423b6541db1SGavin Shan * that PE to block its config space. 424b6541db1SGavin Shan * 425c374ed27SGavin Shan * Broadcom BCM5718 2-ports NICs (14e4:1656) 426b6541db1SGavin Shan * Broadcom Austin 4-ports NICs (14e4:1657) 427353169acSGavin Shan * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 428179ea48bSGavin Shan * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 429b6541db1SGavin Shan */ 430ff57b454SGavin Shan if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 431c374ed27SGavin Shan pdn->device_id == 0x1656) || 432c374ed27SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 433ff57b454SGavin Shan pdn->device_id == 0x1657) || 434ff57b454SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 435353169acSGavin Shan pdn->device_id == 0x168a) || 436353169acSGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 437ff57b454SGavin Shan pdn->device_id == 0x168e)) 438b6541db1SGavin Shan edev->pe->state |= EEH_PE_CFG_RESTRICTED; 439b6541db1SGavin Shan 440b6541db1SGavin Shan /* 441dadcd6d6SMike Qiu * Cache the PE primary bus, which can't be fetched when 442dadcd6d6SMike Qiu * full hotplug is in progress. In that case, all child 443dadcd6d6SMike Qiu * PCI devices of the PE are expected to be removed prior 444dadcd6d6SMike Qiu * to PE reset. 445dadcd6d6SMike Qiu */ 44605ba75f8SGavin Shan if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 447ff57b454SGavin Shan edev->pe->bus = pci_find_bus(hose->global_number, 448ff57b454SGavin Shan pdn->busno); 44905ba75f8SGavin Shan if (edev->pe->bus) 45005ba75f8SGavin Shan edev->pe->state |= EEH_PE_PRI_BUS; 45105ba75f8SGavin Shan } 45229310e5eSGavin Shan 45329310e5eSGavin Shan /* 45429310e5eSGavin Shan * Enable EEH explicitly so that we will do EEH check 45529310e5eSGavin Shan * while accessing I/O stuff 45629310e5eSGavin Shan */ 45705b1721dSGavin Shan eeh_add_flag(EEH_ENABLED); 45829310e5eSGavin Shan 45929310e5eSGavin Shan /* Save memory bars */ 46029310e5eSGavin Shan eeh_save_bars(edev); 46129310e5eSGavin Shan 462617082a4SSam Bobroff pr_debug("%s: EEH enabled on %02x:%02x.%01x PHB#%x-PE#%x\n", 463617082a4SSam Bobroff __func__, pdn->busno, PCI_SLOT(pdn->devfn), 464617082a4SSam Bobroff PCI_FUNC(pdn->devfn), edev->pe->phb->global_number, 465617082a4SSam Bobroff edev->pe->addr); 466617082a4SSam Bobroff 467ff57b454SGavin Shan return NULL; 46829310e5eSGavin Shan } 46929310e5eSGavin Shan 47029310e5eSGavin Shan /** 47101f3bfb7SGavin Shan * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 47229310e5eSGavin Shan * @pe: EEH PE 47329310e5eSGavin Shan * @option: operation to be issued 47429310e5eSGavin Shan * 47529310e5eSGavin Shan * The function is used to control the EEH functionality globally. 47629310e5eSGavin Shan * Currently, following options are support according to PAPR: 47729310e5eSGavin Shan * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 47829310e5eSGavin Shan */ 47901f3bfb7SGavin Shan static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 48029310e5eSGavin Shan { 48129310e5eSGavin Shan struct pci_controller *hose = pe->phb; 48229310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 4837e3e4f8dSGavin Shan bool freeze_pe = false; 484f9433718SGavin Shan int opt; 4857e3e4f8dSGavin Shan s64 rc; 48629310e5eSGavin Shan 4877e3e4f8dSGavin Shan switch (option) { 4887e3e4f8dSGavin Shan case EEH_OPT_DISABLE: 4897e3e4f8dSGavin Shan return -EPERM; 4907e3e4f8dSGavin Shan case EEH_OPT_ENABLE: 4917e3e4f8dSGavin Shan return 0; 4927e3e4f8dSGavin Shan case EEH_OPT_THAW_MMIO: 4937e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 4947e3e4f8dSGavin Shan break; 4957e3e4f8dSGavin Shan case EEH_OPT_THAW_DMA: 4967e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 4977e3e4f8dSGavin Shan break; 4987e3e4f8dSGavin Shan case EEH_OPT_FREEZE_PE: 4997e3e4f8dSGavin Shan freeze_pe = true; 5007e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 5017e3e4f8dSGavin Shan break; 5027e3e4f8dSGavin Shan default: 5037e3e4f8dSGavin Shan pr_warn("%s: Invalid option %d\n", __func__, option); 5047e3e4f8dSGavin Shan return -EINVAL; 5057e3e4f8dSGavin Shan } 5067e3e4f8dSGavin Shan 507f9433718SGavin Shan /* Freeze master and slave PEs if PHB supports compound PEs */ 5087e3e4f8dSGavin Shan if (freeze_pe) { 5097e3e4f8dSGavin Shan if (phb->freeze_pe) { 5107e3e4f8dSGavin Shan phb->freeze_pe(phb, pe->addr); 511f9433718SGavin Shan return 0; 5127e3e4f8dSGavin Shan } 51329310e5eSGavin Shan 514f9433718SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 515f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 516f9433718SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 517f9433718SGavin Shan __func__, rc, phb->hose->global_number, 518f9433718SGavin Shan pe->addr); 519f9433718SGavin Shan return -EIO; 520f9433718SGavin Shan } 521f9433718SGavin Shan 522f9433718SGavin Shan return 0; 523f9433718SGavin Shan } 524f9433718SGavin Shan 525f9433718SGavin Shan /* Unfreeze master and slave PEs if PHB supports */ 526f9433718SGavin Shan if (phb->unfreeze_pe) 527f9433718SGavin Shan return phb->unfreeze_pe(phb, pe->addr, opt); 528f9433718SGavin Shan 529f9433718SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 530f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 531f9433718SGavin Shan pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 532f9433718SGavin Shan __func__, rc, option, phb->hose->global_number, 533f9433718SGavin Shan pe->addr); 534f9433718SGavin Shan return -EIO; 535f9433718SGavin Shan } 536f9433718SGavin Shan 537f9433718SGavin Shan return 0; 53829310e5eSGavin Shan } 53929310e5eSGavin Shan 54029310e5eSGavin Shan /** 54101f3bfb7SGavin Shan * pnv_eeh_get_pe_addr - Retrieve PE address 54229310e5eSGavin Shan * @pe: EEH PE 54329310e5eSGavin Shan * 54429310e5eSGavin Shan * Retrieve the PE address according to the given tranditional 54529310e5eSGavin Shan * PCI BDF (Bus/Device/Function) address. 54629310e5eSGavin Shan */ 54701f3bfb7SGavin Shan static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 54829310e5eSGavin Shan { 54929310e5eSGavin Shan return pe->addr; 55029310e5eSGavin Shan } 55129310e5eSGavin Shan 55240ae5f69SGavin Shan static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 55340ae5f69SGavin Shan { 55440ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 55540ae5f69SGavin Shan s64 rc; 55640ae5f69SGavin Shan 55740ae5f69SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 5585cb1f8fdSRussell Currey phb->diag_data_size); 55940ae5f69SGavin Shan if (rc != OPAL_SUCCESS) 56040ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 56140ae5f69SGavin Shan __func__, rc, pe->phb->global_number); 56240ae5f69SGavin Shan } 56340ae5f69SGavin Shan 56440ae5f69SGavin Shan static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 56540ae5f69SGavin Shan { 56640ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 567c2057701SAlexey Kardashevskiy u8 fstate = 0; 568c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 56940ae5f69SGavin Shan s64 rc; 57040ae5f69SGavin Shan int result = 0; 57140ae5f69SGavin Shan 57240ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 57340ae5f69SGavin Shan pe->addr, 57440ae5f69SGavin Shan &fstate, 57540ae5f69SGavin Shan &pcierr, 57640ae5f69SGavin Shan NULL); 57740ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 57840ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x state\n", 57940ae5f69SGavin Shan __func__, rc, phb->hose->global_number); 58040ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 58140ae5f69SGavin Shan } 58240ae5f69SGavin Shan 58340ae5f69SGavin Shan /* 58440ae5f69SGavin Shan * Check PHB state. If the PHB is frozen for the 58540ae5f69SGavin Shan * first time, to dump the PHB diag-data. 58640ae5f69SGavin Shan */ 58740ae5f69SGavin Shan if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 58840ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 58940ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 59040ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 59140ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 59240ae5f69SGavin Shan } else if (!(pe->state & EEH_PE_ISOLATED)) { 593e762bb89SSam Bobroff eeh_pe_mark_isolated(pe); 59440ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 59540ae5f69SGavin Shan 59640ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 59740ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 59840ae5f69SGavin Shan } 59940ae5f69SGavin Shan 60040ae5f69SGavin Shan return result; 60140ae5f69SGavin Shan } 60240ae5f69SGavin Shan 60340ae5f69SGavin Shan static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 60440ae5f69SGavin Shan { 60540ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 606c2057701SAlexey Kardashevskiy u8 fstate = 0; 607c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 60840ae5f69SGavin Shan s64 rc; 60940ae5f69SGavin Shan int result; 61040ae5f69SGavin Shan 61140ae5f69SGavin Shan /* 61240ae5f69SGavin Shan * We don't clobber hardware frozen state until PE 61340ae5f69SGavin Shan * reset is completed. In order to keep EEH core 61440ae5f69SGavin Shan * moving forward, we have to return operational 61540ae5f69SGavin Shan * state during PE reset. 61640ae5f69SGavin Shan */ 61740ae5f69SGavin Shan if (pe->state & EEH_PE_RESET) { 61840ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 61940ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 62040ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 62140ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 62240ae5f69SGavin Shan return result; 62340ae5f69SGavin Shan } 62440ae5f69SGavin Shan 62540ae5f69SGavin Shan /* 62640ae5f69SGavin Shan * Fetch PE state from hardware. If the PHB 62740ae5f69SGavin Shan * supports compound PE, let it handle that. 62840ae5f69SGavin Shan */ 62940ae5f69SGavin Shan if (phb->get_pe_state) { 63040ae5f69SGavin Shan fstate = phb->get_pe_state(phb, pe->addr); 63140ae5f69SGavin Shan } else { 63240ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 63340ae5f69SGavin Shan pe->addr, 63440ae5f69SGavin Shan &fstate, 63540ae5f69SGavin Shan &pcierr, 63640ae5f69SGavin Shan NULL); 63740ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 63840ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 63940ae5f69SGavin Shan __func__, rc, phb->hose->global_number, 64040ae5f69SGavin Shan pe->addr); 64140ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 64240ae5f69SGavin Shan } 64340ae5f69SGavin Shan } 64440ae5f69SGavin Shan 64540ae5f69SGavin Shan /* Figure out state */ 64640ae5f69SGavin Shan switch (fstate) { 64740ae5f69SGavin Shan case OPAL_EEH_STOPPED_NOT_FROZEN: 64840ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 64940ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 65040ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 65140ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 65240ae5f69SGavin Shan break; 65340ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_FREEZE: 65440ae5f69SGavin Shan result = (EEH_STATE_DMA_ACTIVE | 65540ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 65640ae5f69SGavin Shan break; 65740ae5f69SGavin Shan case OPAL_EEH_STOPPED_DMA_FREEZE: 65840ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 65940ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED); 66040ae5f69SGavin Shan break; 66140ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 66240ae5f69SGavin Shan result = 0; 66340ae5f69SGavin Shan break; 66440ae5f69SGavin Shan case OPAL_EEH_STOPPED_RESET: 66540ae5f69SGavin Shan result = EEH_STATE_RESET_ACTIVE; 66640ae5f69SGavin Shan break; 66740ae5f69SGavin Shan case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 66840ae5f69SGavin Shan result = EEH_STATE_UNAVAILABLE; 66940ae5f69SGavin Shan break; 67040ae5f69SGavin Shan case OPAL_EEH_STOPPED_PERM_UNAVAIL: 67140ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 67240ae5f69SGavin Shan break; 67340ae5f69SGavin Shan default: 67440ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 67540ae5f69SGavin Shan pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 67640ae5f69SGavin Shan __func__, phb->hose->global_number, 67740ae5f69SGavin Shan pe->addr, fstate); 67840ae5f69SGavin Shan } 67940ae5f69SGavin Shan 68040ae5f69SGavin Shan /* 68140ae5f69SGavin Shan * If PHB supports compound PE, to freeze all 68240ae5f69SGavin Shan * slave PEs for consistency. 68340ae5f69SGavin Shan * 68440ae5f69SGavin Shan * If the PE is switching to frozen state for the 68540ae5f69SGavin Shan * first time, to dump the PHB diag-data. 68640ae5f69SGavin Shan */ 68740ae5f69SGavin Shan if (!(result & EEH_STATE_NOT_SUPPORT) && 68840ae5f69SGavin Shan !(result & EEH_STATE_UNAVAILABLE) && 68940ae5f69SGavin Shan !(result & EEH_STATE_MMIO_ACTIVE) && 69040ae5f69SGavin Shan !(result & EEH_STATE_DMA_ACTIVE) && 69140ae5f69SGavin Shan !(pe->state & EEH_PE_ISOLATED)) { 69240ae5f69SGavin Shan if (phb->freeze_pe) 69340ae5f69SGavin Shan phb->freeze_pe(phb, pe->addr); 69440ae5f69SGavin Shan 695e762bb89SSam Bobroff eeh_pe_mark_isolated(pe); 69640ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 69740ae5f69SGavin Shan 69840ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 69940ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 70040ae5f69SGavin Shan } 70140ae5f69SGavin Shan 70240ae5f69SGavin Shan return result; 70340ae5f69SGavin Shan } 70440ae5f69SGavin Shan 70529310e5eSGavin Shan /** 70601f3bfb7SGavin Shan * pnv_eeh_get_state - Retrieve PE state 70729310e5eSGavin Shan * @pe: EEH PE 70829310e5eSGavin Shan * @delay: delay while PE state is temporarily unavailable 70929310e5eSGavin Shan * 71029310e5eSGavin Shan * Retrieve the state of the specified PE. For IODA-compitable 71129310e5eSGavin Shan * platform, it should be retrieved from IODA table. Therefore, 71229310e5eSGavin Shan * we prefer passing down to hardware implementation to handle 71329310e5eSGavin Shan * it. 71429310e5eSGavin Shan */ 71501f3bfb7SGavin Shan static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 71629310e5eSGavin Shan { 71740ae5f69SGavin Shan int ret; 71829310e5eSGavin Shan 71940ae5f69SGavin Shan if (pe->type & EEH_PE_PHB) 72040ae5f69SGavin Shan ret = pnv_eeh_get_phb_state(pe); 72140ae5f69SGavin Shan else 72240ae5f69SGavin Shan ret = pnv_eeh_get_pe_state(pe); 72340ae5f69SGavin Shan 72440ae5f69SGavin Shan if (!delay) 72540ae5f69SGavin Shan return ret; 72629310e5eSGavin Shan 72729310e5eSGavin Shan /* 72829310e5eSGavin Shan * If the PE state is temporarily unavailable, 72929310e5eSGavin Shan * to inform the EEH core delay for default 73029310e5eSGavin Shan * period (1 second) 73129310e5eSGavin Shan */ 73229310e5eSGavin Shan *delay = 0; 73329310e5eSGavin Shan if (ret & EEH_STATE_UNAVAILABLE) 73429310e5eSGavin Shan *delay = 1000; 73529310e5eSGavin Shan 73629310e5eSGavin Shan return ret; 73729310e5eSGavin Shan } 73829310e5eSGavin Shan 739ebe22531SGavin Shan static s64 pnv_eeh_poll(unsigned long id) 740cadf364dSGavin Shan { 741cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 742cadf364dSGavin Shan 743cadf364dSGavin Shan while (1) { 744ebe22531SGavin Shan rc = opal_pci_poll(id); 745cadf364dSGavin Shan if (rc <= 0) 746cadf364dSGavin Shan break; 747cadf364dSGavin Shan 748cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 749cadf364dSGavin Shan udelay(1000 * rc); 750cadf364dSGavin Shan else 751cadf364dSGavin Shan msleep(rc); 752cadf364dSGavin Shan } 753cadf364dSGavin Shan 754cadf364dSGavin Shan return rc; 755cadf364dSGavin Shan } 756cadf364dSGavin Shan 757cadf364dSGavin Shan int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 758cadf364dSGavin Shan { 759cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 760cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 761cadf364dSGavin Shan 762cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 763cadf364dSGavin Shan __func__, hose->global_number, option); 764cadf364dSGavin Shan 765cadf364dSGavin Shan /* Issue PHB complete reset request */ 766cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL || 767cadf364dSGavin Shan option == EEH_RESET_HOT) 768cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 769cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 770cadf364dSGavin Shan OPAL_ASSERT_RESET); 771cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 772cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 773cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 774cadf364dSGavin Shan OPAL_DEASSERT_RESET); 775cadf364dSGavin Shan if (rc < 0) 776cadf364dSGavin Shan goto out; 777cadf364dSGavin Shan 778cadf364dSGavin Shan /* 779cadf364dSGavin Shan * Poll state of the PHB until the request is done 780cadf364dSGavin Shan * successfully. The PHB reset is usually PHB complete 781cadf364dSGavin Shan * reset followed by hot reset on root bus. So we also 782cadf364dSGavin Shan * need the PCI bus settlement delay. 783cadf364dSGavin Shan */ 784fbce44d0SGavin Shan if (rc > 0) 785ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 786cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) { 787cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 788cadf364dSGavin Shan udelay(1000 * EEH_PE_RST_SETTLE_TIME); 789cadf364dSGavin Shan else 790cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 791cadf364dSGavin Shan } 792cadf364dSGavin Shan out: 793cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 794cadf364dSGavin Shan return -EIO; 795cadf364dSGavin Shan 796cadf364dSGavin Shan return 0; 797cadf364dSGavin Shan } 798cadf364dSGavin Shan 799cadf364dSGavin Shan static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 800cadf364dSGavin Shan { 801cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 802cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 803cadf364dSGavin Shan 804cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 805cadf364dSGavin Shan __func__, hose->global_number, option); 806cadf364dSGavin Shan 807cadf364dSGavin Shan /* 808cadf364dSGavin Shan * During the reset deassert time, we needn't care 809cadf364dSGavin Shan * the reset scope because the firmware does nothing 810cadf364dSGavin Shan * for fundamental or hot reset during deassert phase. 811cadf364dSGavin Shan */ 812cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL) 813cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 814cadf364dSGavin Shan OPAL_RESET_PCI_FUNDAMENTAL, 815cadf364dSGavin Shan OPAL_ASSERT_RESET); 816cadf364dSGavin Shan else if (option == EEH_RESET_HOT) 817cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 818cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 819cadf364dSGavin Shan OPAL_ASSERT_RESET); 820cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 821cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 822cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 823cadf364dSGavin Shan OPAL_DEASSERT_RESET); 824cadf364dSGavin Shan if (rc < 0) 825cadf364dSGavin Shan goto out; 826cadf364dSGavin Shan 827cadf364dSGavin Shan /* Poll state of the PHB until the request is done */ 828fbce44d0SGavin Shan if (rc > 0) 829ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 830cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) 831cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 832cadf364dSGavin Shan out: 833cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 834cadf364dSGavin Shan return -EIO; 835cadf364dSGavin Shan 836cadf364dSGavin Shan return 0; 837cadf364dSGavin Shan } 838cadf364dSGavin Shan 8399c0e1ecbSGavin Shan static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 840cadf364dSGavin Shan { 8410bd78587SGavin Shan struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 8420bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 843cadf364dSGavin Shan int aer = edev ? edev->aer_cap : 0; 844cadf364dSGavin Shan u32 ctrl; 845cadf364dSGavin Shan 846cadf364dSGavin Shan pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 847cadf364dSGavin Shan __func__, pci_domain_nr(dev->bus), 848cadf364dSGavin Shan dev->bus->number, option); 849cadf364dSGavin Shan 850cadf364dSGavin Shan switch (option) { 851cadf364dSGavin Shan case EEH_RESET_FUNDAMENTAL: 852cadf364dSGavin Shan case EEH_RESET_HOT: 853cadf364dSGavin Shan /* Don't report linkDown event */ 854cadf364dSGavin Shan if (aer) { 8550bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 856cadf364dSGavin Shan 4, &ctrl); 857cadf364dSGavin Shan ctrl |= PCI_ERR_UNC_SURPDN; 8580bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 859cadf364dSGavin Shan 4, ctrl); 860cadf364dSGavin Shan } 861cadf364dSGavin Shan 8620bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 863cadf364dSGavin Shan ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 8640bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 865cadf364dSGavin Shan 866cadf364dSGavin Shan msleep(EEH_PE_RST_HOLD_TIME); 867cadf364dSGavin Shan break; 868cadf364dSGavin Shan case EEH_RESET_DEACTIVATE: 8690bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 870cadf364dSGavin Shan ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 8710bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 872cadf364dSGavin Shan 873cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 874cadf364dSGavin Shan 875cadf364dSGavin Shan /* Continue reporting linkDown event */ 876cadf364dSGavin Shan if (aer) { 8770bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 878cadf364dSGavin Shan 4, &ctrl); 879cadf364dSGavin Shan ctrl &= ~PCI_ERR_UNC_SURPDN; 8800bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 881cadf364dSGavin Shan 4, ctrl); 882cadf364dSGavin Shan } 883cadf364dSGavin Shan 884cadf364dSGavin Shan break; 885cadf364dSGavin Shan } 886cadf364dSGavin Shan 887cadf364dSGavin Shan return 0; 888cadf364dSGavin Shan } 889cadf364dSGavin Shan 8909c0e1ecbSGavin Shan static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 8919c0e1ecbSGavin Shan { 8929c0e1ecbSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 8939c0e1ecbSGavin Shan struct pnv_phb *phb = hose->private_data; 8949c0e1ecbSGavin Shan struct device_node *dn = pci_device_to_OF_node(pdev); 8959c0e1ecbSGavin Shan uint64_t id = PCI_SLOT_ID(phb->opal_id, 8969c0e1ecbSGavin Shan (pdev->bus->number << 8) | pdev->devfn); 8979c0e1ecbSGavin Shan uint8_t scope; 8989c0e1ecbSGavin Shan int64_t rc; 8999c0e1ecbSGavin Shan 9009c0e1ecbSGavin Shan /* Hot reset to the bus if firmware cannot handle */ 9019c0e1ecbSGavin Shan if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 9029c0e1ecbSGavin Shan return __pnv_eeh_bridge_reset(pdev, option); 9039c0e1ecbSGavin Shan 9049c0e1ecbSGavin Shan switch (option) { 9059c0e1ecbSGavin Shan case EEH_RESET_FUNDAMENTAL: 9069c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_FUNDAMENTAL; 9079c0e1ecbSGavin Shan break; 9089c0e1ecbSGavin Shan case EEH_RESET_HOT: 9099c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_HOT; 9109c0e1ecbSGavin Shan break; 9119c0e1ecbSGavin Shan case EEH_RESET_DEACTIVATE: 9129c0e1ecbSGavin Shan return 0; 9139c0e1ecbSGavin Shan default: 9149c0e1ecbSGavin Shan dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 9159c0e1ecbSGavin Shan __func__, option); 9169c0e1ecbSGavin Shan return -EINVAL; 9179c0e1ecbSGavin Shan } 9189c0e1ecbSGavin Shan 9199c0e1ecbSGavin Shan rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 9209c0e1ecbSGavin Shan if (rc <= OPAL_SUCCESS) 9219c0e1ecbSGavin Shan goto out; 9229c0e1ecbSGavin Shan 9239c0e1ecbSGavin Shan rc = pnv_eeh_poll(id); 9249c0e1ecbSGavin Shan out: 9259c0e1ecbSGavin Shan return (rc == OPAL_SUCCESS) ? 0 : -EIO; 9269c0e1ecbSGavin Shan } 9279c0e1ecbSGavin Shan 928cadf364dSGavin Shan void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 929cadf364dSGavin Shan { 930848912e5SMichael Ellerman struct pci_controller *hose; 931848912e5SMichael Ellerman 932848912e5SMichael Ellerman if (pci_is_root_bus(dev->bus)) { 933848912e5SMichael Ellerman hose = pci_bus_to_host(dev->bus); 934848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_HOT); 935848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 936848912e5SMichael Ellerman } else { 937cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 938cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 939cadf364dSGavin Shan } 940848912e5SMichael Ellerman } 941cadf364dSGavin Shan 9429312bc5bSWei Yang static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 9439312bc5bSWei Yang int pos, u16 mask) 9449312bc5bSWei Yang { 9459312bc5bSWei Yang int i, status = 0; 9469312bc5bSWei Yang 9479312bc5bSWei Yang /* Wait for Transaction Pending bit to be cleared */ 9489312bc5bSWei Yang for (i = 0; i < 4; i++) { 9499312bc5bSWei Yang eeh_ops->read_config(pdn, pos, 2, &status); 9509312bc5bSWei Yang if (!(status & mask)) 9519312bc5bSWei Yang return; 9529312bc5bSWei Yang 9539312bc5bSWei Yang msleep((1 << i) * 100); 9549312bc5bSWei Yang } 9559312bc5bSWei Yang 9569312bc5bSWei Yang pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 9579312bc5bSWei Yang __func__, type, 95869672bd7SAlexey Kardashevskiy pdn->phb->global_number, pdn->busno, 9599312bc5bSWei Yang PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 9609312bc5bSWei Yang } 9619312bc5bSWei Yang 9629312bc5bSWei Yang static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 9639312bc5bSWei Yang { 9649312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9659312bc5bSWei Yang u32 reg = 0; 9669312bc5bSWei Yang 9679312bc5bSWei Yang if (WARN_ON(!edev->pcie_cap)) 9689312bc5bSWei Yang return -ENOTTY; 9699312bc5bSWei Yang 9709312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 9719312bc5bSWei Yang if (!(reg & PCI_EXP_DEVCAP_FLR)) 9729312bc5bSWei Yang return -ENOTTY; 9739312bc5bSWei Yang 9749312bc5bSWei Yang switch (option) { 9759312bc5bSWei Yang case EEH_RESET_HOT: 9769312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 9779312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "", 9789312bc5bSWei Yang edev->pcie_cap + PCI_EXP_DEVSTA, 9799312bc5bSWei Yang PCI_EXP_DEVSTA_TRPND); 9809312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9819312bc5bSWei Yang 4, ®); 9829312bc5bSWei Yang reg |= PCI_EXP_DEVCTL_BCR_FLR; 9839312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9849312bc5bSWei Yang 4, reg); 9859312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 9869312bc5bSWei Yang break; 9879312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 9889312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9899312bc5bSWei Yang 4, ®); 9909312bc5bSWei Yang reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 9919312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9929312bc5bSWei Yang 4, reg); 9939312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 9949312bc5bSWei Yang break; 9959312bc5bSWei Yang } 9969312bc5bSWei Yang 9979312bc5bSWei Yang return 0; 9989312bc5bSWei Yang } 9999312bc5bSWei Yang 10009312bc5bSWei Yang static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 10019312bc5bSWei Yang { 10029312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 10039312bc5bSWei Yang u32 cap = 0; 10049312bc5bSWei Yang 10059312bc5bSWei Yang if (WARN_ON(!edev->af_cap)) 10069312bc5bSWei Yang return -ENOTTY; 10079312bc5bSWei Yang 10089312bc5bSWei Yang eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 10099312bc5bSWei Yang if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 10109312bc5bSWei Yang return -ENOTTY; 10119312bc5bSWei Yang 10129312bc5bSWei Yang switch (option) { 10139312bc5bSWei Yang case EEH_RESET_HOT: 10149312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 10159312bc5bSWei Yang /* 10169312bc5bSWei Yang * Wait for Transaction Pending bit to clear. A word-aligned 10179312bc5bSWei Yang * test is used, so we use the conrol offset rather than status 10189312bc5bSWei Yang * and shift the test bit to match. 10199312bc5bSWei Yang */ 10209312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "AF", 10219312bc5bSWei Yang edev->af_cap + PCI_AF_CTRL, 10229312bc5bSWei Yang PCI_AF_STATUS_TP << 8); 10239312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 10249312bc5bSWei Yang 1, PCI_AF_CTRL_FLR); 10259312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 10269312bc5bSWei Yang break; 10279312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 10289312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 10299312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 10309312bc5bSWei Yang break; 10319312bc5bSWei Yang } 10329312bc5bSWei Yang 10339312bc5bSWei Yang return 0; 10349312bc5bSWei Yang } 10359312bc5bSWei Yang 10369312bc5bSWei Yang static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 10379312bc5bSWei Yang { 10389312bc5bSWei Yang struct eeh_dev *edev; 10399312bc5bSWei Yang struct pci_dn *pdn; 10409312bc5bSWei Yang int ret; 10419312bc5bSWei Yang 10429312bc5bSWei Yang /* The VF PE should have only one child device */ 104380e65b00SSam Bobroff edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); 10449312bc5bSWei Yang pdn = eeh_dev_to_pdn(edev); 10459312bc5bSWei Yang if (!pdn) 10469312bc5bSWei Yang return -ENXIO; 10479312bc5bSWei Yang 10489312bc5bSWei Yang ret = pnv_eeh_do_flr(pdn, option); 10499312bc5bSWei Yang if (!ret) 10509312bc5bSWei Yang return ret; 10519312bc5bSWei Yang 10529312bc5bSWei Yang return pnv_eeh_do_af_flr(pdn, option); 10539312bc5bSWei Yang } 10549312bc5bSWei Yang 105529310e5eSGavin Shan /** 105601f3bfb7SGavin Shan * pnv_eeh_reset - Reset the specified PE 105729310e5eSGavin Shan * @pe: EEH PE 105829310e5eSGavin Shan * @option: reset option 105929310e5eSGavin Shan * 1060cadf364dSGavin Shan * Do reset on the indicated PE. For PCI bus sensitive PE, 1061cadf364dSGavin Shan * we need to reset the parent p2p bridge. The PHB has to 1062cadf364dSGavin Shan * be reinitialized if the p2p bridge is root bridge. For 1063cadf364dSGavin Shan * PCI device sensitive PE, we will try to reset the device 1064cadf364dSGavin Shan * through FLR. For now, we don't have OPAL APIs to do HARD 1065cadf364dSGavin Shan * reset yet, so all reset would be SOFT (HOT) reset. 106629310e5eSGavin Shan */ 106701f3bfb7SGavin Shan static int pnv_eeh_reset(struct eeh_pe *pe, int option) 106829310e5eSGavin Shan { 106929310e5eSGavin Shan struct pci_controller *hose = pe->phb; 10704fad4943SGavin Shan struct pnv_phb *phb; 1071cadf364dSGavin Shan struct pci_bus *bus; 10724fad4943SGavin Shan int64_t rc; 107329310e5eSGavin Shan 1074cadf364dSGavin Shan /* 1075cadf364dSGavin Shan * For PHB reset, we always have complete reset. For those PEs whose 1076cadf364dSGavin Shan * primary bus derived from root complex (root bus) or root port 1077cadf364dSGavin Shan * (usually bus#1), we apply hot or fundamental reset on the root port. 1078cadf364dSGavin Shan * For other PEs, we always have hot reset on the PE primary bus. 1079cadf364dSGavin Shan * 1080cadf364dSGavin Shan * Here, we have different design to pHyp, which always clear the 1081cadf364dSGavin Shan * frozen state during PE reset. However, the good idea here from 1082cadf364dSGavin Shan * benh is to keep frozen state before we get PE reset done completely 1083cadf364dSGavin Shan * (until BAR restore). With the frozen state, HW drops illegal IO 1084cadf364dSGavin Shan * or MMIO access, which can incur recrusive frozen PE during PE 1085cadf364dSGavin Shan * reset. The side effect is that EEH core has to clear the frozen 1086cadf364dSGavin Shan * state explicitly after BAR restore. 1087cadf364dSGavin Shan */ 10884fad4943SGavin Shan if (pe->type & EEH_PE_PHB) 10894fad4943SGavin Shan return pnv_eeh_phb_reset(hose, option); 1090cadf364dSGavin Shan 1091cadf364dSGavin Shan /* 1092cadf364dSGavin Shan * The frozen PE might be caused by PAPR error injection 1093cadf364dSGavin Shan * registers, which are expected to be cleared after hitting 1094cadf364dSGavin Shan * frozen PE as stated in the hardware spec. Unfortunately, 1095cadf364dSGavin Shan * that's not true on P7IOC. So we have to clear it manually 1096cadf364dSGavin Shan * to avoid recursive EEH errors during recovery. 1097cadf364dSGavin Shan */ 1098cadf364dSGavin Shan phb = hose->private_data; 1099cadf364dSGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC && 1100cadf364dSGavin Shan (option == EEH_RESET_HOT || 1101cadf364dSGavin Shan option == EEH_RESET_FUNDAMENTAL)) { 1102cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 1103cadf364dSGavin Shan OPAL_RESET_PHB_ERROR, 1104cadf364dSGavin Shan OPAL_ASSERT_RESET); 1105cadf364dSGavin Shan if (rc != OPAL_SUCCESS) { 11064fad4943SGavin Shan pr_warn("%s: Failure %lld clearing error injection registers\n", 1107cadf364dSGavin Shan __func__, rc); 1108cadf364dSGavin Shan return -EIO; 1109cadf364dSGavin Shan } 1110cadf364dSGavin Shan } 1111cadf364dSGavin Shan 1112e98ddb77SRussell Currey if (pe->type & EEH_PE_VF) 1113e98ddb77SRussell Currey return pnv_eeh_reset_vf_pe(pe, option); 1114e98ddb77SRussell Currey 1115cadf364dSGavin Shan bus = eeh_pe_bus_get(pe); 111604fec21cSRussell Currey if (!bus) { 11171f52f176SRussell Currey pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 111804fec21cSRussell Currey __func__, pe->phb->global_number, pe->addr); 111904fec21cSRussell Currey return -EIO; 112004fec21cSRussell Currey } 112129310e5eSGavin Shan 1122b7da1230SAndrew Donnellan /* 1123b7da1230SAndrew Donnellan * If dealing with the root bus (or the bus underneath the 1124b7da1230SAndrew Donnellan * root port), we reset the bus underneath the root port. 1125b7da1230SAndrew Donnellan * 1126b7da1230SAndrew Donnellan * The cxl driver depends on this behaviour for bi-modal card 1127b7da1230SAndrew Donnellan * switching. 1128b7da1230SAndrew Donnellan */ 11294fad4943SGavin Shan if (pci_is_root_bus(bus) || 11304fad4943SGavin Shan pci_is_root_bus(bus->parent)) 11314fad4943SGavin Shan return pnv_eeh_root_reset(hose, option); 11324fad4943SGavin Shan 11334fad4943SGavin Shan return pnv_eeh_bridge_reset(bus->self, option); 113429310e5eSGavin Shan } 113529310e5eSGavin Shan 113629310e5eSGavin Shan /** 113701f3bfb7SGavin Shan * pnv_eeh_get_log - Retrieve error log 113829310e5eSGavin Shan * @pe: EEH PE 113929310e5eSGavin Shan * @severity: temporary or permanent error log 114029310e5eSGavin Shan * @drv_log: driver log to be combined with retrieved error log 114129310e5eSGavin Shan * @len: length of driver log 114229310e5eSGavin Shan * 114329310e5eSGavin Shan * Retrieve the temporary or permanent error from the PE. 114429310e5eSGavin Shan */ 114501f3bfb7SGavin Shan static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 114629310e5eSGavin Shan char *drv_log, unsigned long len) 114729310e5eSGavin Shan { 114895edcdeaSGavin Shan if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 114995edcdeaSGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 115029310e5eSGavin Shan 115195edcdeaSGavin Shan return 0; 115229310e5eSGavin Shan } 115329310e5eSGavin Shan 115429310e5eSGavin Shan /** 115501f3bfb7SGavin Shan * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 115629310e5eSGavin Shan * @pe: EEH PE 115729310e5eSGavin Shan * 115829310e5eSGavin Shan * The function will be called to reconfigure the bridges included 115929310e5eSGavin Shan * in the specified PE so that the mulfunctional PE would be recovered 116029310e5eSGavin Shan * again. 116129310e5eSGavin Shan */ 116201f3bfb7SGavin Shan static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 116329310e5eSGavin Shan { 1164bbe170edSGavin Shan return 0; 116529310e5eSGavin Shan } 116629310e5eSGavin Shan 116729310e5eSGavin Shan /** 116801f3bfb7SGavin Shan * pnv_pe_err_inject - Inject specified error to the indicated PE 1169131c123aSGavin Shan * @pe: the indicated PE 1170131c123aSGavin Shan * @type: error type 1171131c123aSGavin Shan * @func: specific error type 1172131c123aSGavin Shan * @addr: address 1173131c123aSGavin Shan * @mask: address mask 1174131c123aSGavin Shan * 1175131c123aSGavin Shan * The routine is called to inject specified error, which is 1176131c123aSGavin Shan * determined by @type and @func, to the indicated PE for 1177131c123aSGavin Shan * testing purpose. 1178131c123aSGavin Shan */ 117901f3bfb7SGavin Shan static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1180131c123aSGavin Shan unsigned long addr, unsigned long mask) 1181131c123aSGavin Shan { 1182131c123aSGavin Shan struct pci_controller *hose = pe->phb; 1183131c123aSGavin Shan struct pnv_phb *phb = hose->private_data; 1184fa646c3cSGavin Shan s64 rc; 1185131c123aSGavin Shan 1186fa646c3cSGavin Shan if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1187fa646c3cSGavin Shan type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1188fa646c3cSGavin Shan pr_warn("%s: Invalid error type %d\n", 1189fa646c3cSGavin Shan __func__, type); 1190fa646c3cSGavin Shan return -ERANGE; 1191fa646c3cSGavin Shan } 1192131c123aSGavin Shan 1193fa646c3cSGavin Shan if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1194fa646c3cSGavin Shan func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1195fa646c3cSGavin Shan pr_warn("%s: Invalid error function %d\n", 1196fa646c3cSGavin Shan __func__, func); 1197fa646c3cSGavin Shan return -ERANGE; 1198fa646c3cSGavin Shan } 1199fa646c3cSGavin Shan 1200fa646c3cSGavin Shan /* Firmware supports error injection ? */ 1201fa646c3cSGavin Shan if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1202fa646c3cSGavin Shan pr_warn("%s: Firmware doesn't support error injection\n", 1203fa646c3cSGavin Shan __func__); 1204fa646c3cSGavin Shan return -ENXIO; 1205fa646c3cSGavin Shan } 1206fa646c3cSGavin Shan 1207fa646c3cSGavin Shan /* Do error injection */ 1208fa646c3cSGavin Shan rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1209fa646c3cSGavin Shan type, func, addr, mask); 1210fa646c3cSGavin Shan if (rc != OPAL_SUCCESS) { 1211fa646c3cSGavin Shan pr_warn("%s: Failure %lld injecting error " 1212fa646c3cSGavin Shan "%d-%d to PHB#%x-PE#%x\n", 1213fa646c3cSGavin Shan __func__, rc, type, func, 1214fa646c3cSGavin Shan hose->global_number, pe->addr); 1215fa646c3cSGavin Shan return -EIO; 1216fa646c3cSGavin Shan } 1217fa646c3cSGavin Shan 1218fa646c3cSGavin Shan return 0; 1219131c123aSGavin Shan } 1220131c123aSGavin Shan 12210bd78587SGavin Shan static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1222d2cfbcd7SGavin Shan { 12230bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1224d2cfbcd7SGavin Shan 1225d2cfbcd7SGavin Shan if (!edev || !edev->pe) 1226d2cfbcd7SGavin Shan return false; 1227d2cfbcd7SGavin Shan 12289312bc5bSWei Yang /* 12299312bc5bSWei Yang * We will issue FLR or AF FLR to all VFs, which are contained 12309312bc5bSWei Yang * in VF PE. It relies on the EEH PCI config accessors. So we 12319312bc5bSWei Yang * can't block them during the window. 12329312bc5bSWei Yang */ 12339312bc5bSWei Yang if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 12349312bc5bSWei Yang return false; 12359312bc5bSWei Yang 1236d2cfbcd7SGavin Shan if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1237d2cfbcd7SGavin Shan return true; 1238d2cfbcd7SGavin Shan 1239d2cfbcd7SGavin Shan return false; 1240d2cfbcd7SGavin Shan } 1241d2cfbcd7SGavin Shan 12420bd78587SGavin Shan static int pnv_eeh_read_config(struct pci_dn *pdn, 1243d2cfbcd7SGavin Shan int where, int size, u32 *val) 1244d2cfbcd7SGavin Shan { 12453532a741SGavin Shan if (!pdn) 12463532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12473532a741SGavin Shan 12480bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) { 1249d2cfbcd7SGavin Shan *val = 0xFFFFFFFF; 1250d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1251d2cfbcd7SGavin Shan } 1252d2cfbcd7SGavin Shan 12533532a741SGavin Shan return pnv_pci_cfg_read(pdn, where, size, val); 1254d2cfbcd7SGavin Shan } 1255d2cfbcd7SGavin Shan 12560bd78587SGavin Shan static int pnv_eeh_write_config(struct pci_dn *pdn, 1257d2cfbcd7SGavin Shan int where, int size, u32 val) 1258d2cfbcd7SGavin Shan { 12593532a741SGavin Shan if (!pdn) 12603532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12613532a741SGavin Shan 12620bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) 1263d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1264d2cfbcd7SGavin Shan 12653532a741SGavin Shan return pnv_pci_cfg_write(pdn, where, size, val); 1266d2cfbcd7SGavin Shan } 1267d2cfbcd7SGavin Shan 12682a485ad7SGavin Shan static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 12692a485ad7SGavin Shan { 12702a485ad7SGavin Shan /* GEM */ 12712a485ad7SGavin Shan if (data->gemXfir || data->gemRfir || 12722a485ad7SGavin Shan data->gemRirqfir || data->gemMask || data->gemRwof) 12732a485ad7SGavin Shan pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 12742a485ad7SGavin Shan be64_to_cpu(data->gemXfir), 12752a485ad7SGavin Shan be64_to_cpu(data->gemRfir), 12762a485ad7SGavin Shan be64_to_cpu(data->gemRirqfir), 12772a485ad7SGavin Shan be64_to_cpu(data->gemMask), 12782a485ad7SGavin Shan be64_to_cpu(data->gemRwof)); 12792a485ad7SGavin Shan 12802a485ad7SGavin Shan /* LEM */ 12812a485ad7SGavin Shan if (data->lemFir || data->lemErrMask || 12822a485ad7SGavin Shan data->lemAction0 || data->lemAction1 || data->lemWof) 12832a485ad7SGavin Shan pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 12842a485ad7SGavin Shan be64_to_cpu(data->lemFir), 12852a485ad7SGavin Shan be64_to_cpu(data->lemErrMask), 12862a485ad7SGavin Shan be64_to_cpu(data->lemAction0), 12872a485ad7SGavin Shan be64_to_cpu(data->lemAction1), 12882a485ad7SGavin Shan be64_to_cpu(data->lemWof)); 12892a485ad7SGavin Shan } 12902a485ad7SGavin Shan 12912a485ad7SGavin Shan static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 12922a485ad7SGavin Shan { 12932a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 12945cb1f8fdSRussell Currey struct OpalIoP7IOCErrorData *data = 12955cb1f8fdSRussell Currey (struct OpalIoP7IOCErrorData*)phb->diag_data; 12962a485ad7SGavin Shan long rc; 12972a485ad7SGavin Shan 12982a485ad7SGavin Shan rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 12992a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 13002a485ad7SGavin Shan pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 13012a485ad7SGavin Shan __func__, phb->hub_id, rc); 13022a485ad7SGavin Shan return; 13032a485ad7SGavin Shan } 13042a485ad7SGavin Shan 1305a7032132SGavin Shan switch (be16_to_cpu(data->type)) { 13062a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_RGC: 13072a485ad7SGavin Shan pr_info("P7IOC diag-data for RGC\n\n"); 13082a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13092a485ad7SGavin Shan if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 13102a485ad7SGavin Shan pr_info(" RGC: %016llx %016llx\n", 13112a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcStatus), 13122a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcLdcp)); 13132a485ad7SGavin Shan break; 13142a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_BI: 13152a485ad7SGavin Shan pr_info("P7IOC diag-data for BI %s\n\n", 13162a485ad7SGavin Shan data->bi.biDownbound ? "Downbound" : "Upbound"); 13172a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13182a485ad7SGavin Shan if (data->bi.biLdcp0 || data->bi.biLdcp1 || 13192a485ad7SGavin Shan data->bi.biLdcp2 || data->bi.biFenceStatus) 13202a485ad7SGavin Shan pr_info(" BI: %016llx %016llx %016llx %016llx\n", 13212a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp0), 13222a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp1), 13232a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp2), 13242a485ad7SGavin Shan be64_to_cpu(data->bi.biFenceStatus)); 13252a485ad7SGavin Shan break; 13262a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_CI: 13272a485ad7SGavin Shan pr_info("P7IOC diag-data for CI Port %d\n\n", 13282a485ad7SGavin Shan data->ci.ciPort); 13292a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13302a485ad7SGavin Shan if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 13312a485ad7SGavin Shan pr_info(" CI: %016llx %016llx\n", 13322a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortStatus), 13332a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortLdcp)); 13342a485ad7SGavin Shan break; 13352a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_MISC: 13362a485ad7SGavin Shan pr_info("P7IOC diag-data for MISC\n\n"); 13372a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13382a485ad7SGavin Shan break; 13392a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_I2C: 13402a485ad7SGavin Shan pr_info("P7IOC diag-data for I2C\n\n"); 13412a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13422a485ad7SGavin Shan break; 13432a485ad7SGavin Shan default: 13442a485ad7SGavin Shan pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 13452a485ad7SGavin Shan __func__, phb->hub_id, data->type); 13462a485ad7SGavin Shan } 13472a485ad7SGavin Shan } 13482a485ad7SGavin Shan 13492a485ad7SGavin Shan static int pnv_eeh_get_pe(struct pci_controller *hose, 13502a485ad7SGavin Shan u16 pe_no, struct eeh_pe **pe) 13512a485ad7SGavin Shan { 13522a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 13532a485ad7SGavin Shan struct pnv_ioda_pe *pnv_pe; 13542a485ad7SGavin Shan struct eeh_pe *dev_pe; 13552a485ad7SGavin Shan 13562a485ad7SGavin Shan /* 13572a485ad7SGavin Shan * If PHB supports compound PE, to fetch 13582a485ad7SGavin Shan * the master PE because slave PE is invisible 13592a485ad7SGavin Shan * to EEH core. 13602a485ad7SGavin Shan */ 13612a485ad7SGavin Shan pnv_pe = &phb->ioda.pe_array[pe_no]; 13622a485ad7SGavin Shan if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 13632a485ad7SGavin Shan pnv_pe = pnv_pe->master; 13642a485ad7SGavin Shan WARN_ON(!pnv_pe || 13652a485ad7SGavin Shan !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 13662a485ad7SGavin Shan pe_no = pnv_pe->pe_number; 13672a485ad7SGavin Shan } 13682a485ad7SGavin Shan 13692a485ad7SGavin Shan /* Find the PE according to PE# */ 13708bae6a23SAlexey Kardashevskiy dev_pe = eeh_pe_get(hose, pe_no, 0); 13712a485ad7SGavin Shan if (!dev_pe) 13722a485ad7SGavin Shan return -EEXIST; 13732a485ad7SGavin Shan 13742a485ad7SGavin Shan /* Freeze the (compound) PE */ 13752a485ad7SGavin Shan *pe = dev_pe; 13762a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 13772a485ad7SGavin Shan phb->freeze_pe(phb, pe_no); 13782a485ad7SGavin Shan 13792a485ad7SGavin Shan /* 13802a485ad7SGavin Shan * At this point, we're sure the (compound) PE should 13812a485ad7SGavin Shan * have been frozen. However, we still need poke until 13822a485ad7SGavin Shan * hitting the frozen PE on top level. 13832a485ad7SGavin Shan */ 13842a485ad7SGavin Shan dev_pe = dev_pe->parent; 13852a485ad7SGavin Shan while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 13862a485ad7SGavin Shan int ret; 13872a485ad7SGavin Shan ret = eeh_ops->get_state(dev_pe, NULL); 138834a286a4SSam Bobroff if (ret <= 0 || eeh_state_active(ret)) { 13892a485ad7SGavin Shan dev_pe = dev_pe->parent; 13902a485ad7SGavin Shan continue; 13912a485ad7SGavin Shan } 13922a485ad7SGavin Shan 13932a485ad7SGavin Shan /* Frozen parent PE */ 13942a485ad7SGavin Shan *pe = dev_pe; 13952a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 13962a485ad7SGavin Shan phb->freeze_pe(phb, dev_pe->addr); 13972a485ad7SGavin Shan 13982a485ad7SGavin Shan /* Next one */ 13992a485ad7SGavin Shan dev_pe = dev_pe->parent; 14002a485ad7SGavin Shan } 14012a485ad7SGavin Shan 14022a485ad7SGavin Shan return 0; 14032a485ad7SGavin Shan } 14042a485ad7SGavin Shan 1405131c123aSGavin Shan /** 140601f3bfb7SGavin Shan * pnv_eeh_next_error - Retrieve next EEH error to handle 140729310e5eSGavin Shan * @pe: Affected PE 140829310e5eSGavin Shan * 14092a485ad7SGavin Shan * The function is expected to be called by EEH core while it gets 14102a485ad7SGavin Shan * special EEH event (without binding PE). The function calls to 14112a485ad7SGavin Shan * OPAL APIs for next error to handle. The informational error is 14122a485ad7SGavin Shan * handled internally by platform. However, the dead IOC, dead PHB, 14132a485ad7SGavin Shan * fenced PHB and frozen PE should be handled by EEH core eventually. 141429310e5eSGavin Shan */ 141501f3bfb7SGavin Shan static int pnv_eeh_next_error(struct eeh_pe **pe) 141629310e5eSGavin Shan { 141729310e5eSGavin Shan struct pci_controller *hose; 14182a485ad7SGavin Shan struct pnv_phb *phb; 14192a485ad7SGavin Shan struct eeh_pe *phb_pe, *parent_pe; 14202a485ad7SGavin Shan __be64 frozen_pe_no; 14212a485ad7SGavin Shan __be16 err_type, severity; 14222a485ad7SGavin Shan long rc; 14232a485ad7SGavin Shan int state, ret = EEH_NEXT_ERR_NONE; 14242a485ad7SGavin Shan 14252a485ad7SGavin Shan /* 142679231448SAlistair Popple * While running here, it's safe to purge the event queue. The 142779231448SAlistair Popple * event should still be masked. 14282a485ad7SGavin Shan */ 14292a485ad7SGavin Shan eeh_remove_event(NULL, false); 143029310e5eSGavin Shan 143129310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 14322a485ad7SGavin Shan /* 14332a485ad7SGavin Shan * If the subordinate PCI buses of the PHB has been 14342a485ad7SGavin Shan * removed or is exactly under error recovery, we 14352a485ad7SGavin Shan * needn't take care of it any more. 14362a485ad7SGavin Shan */ 143729310e5eSGavin Shan phb = hose->private_data; 14382a485ad7SGavin Shan phb_pe = eeh_phb_pe_get(hose); 14392a485ad7SGavin Shan if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 14402a485ad7SGavin Shan continue; 14412a485ad7SGavin Shan 14422a485ad7SGavin Shan rc = opal_pci_next_error(phb->opal_id, 14432a485ad7SGavin Shan &frozen_pe_no, &err_type, &severity); 14442a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 14452a485ad7SGavin Shan pr_devel("%s: Invalid return value on " 14462a485ad7SGavin Shan "PHB#%x (0x%lx) from opal_pci_next_error", 14472a485ad7SGavin Shan __func__, hose->global_number, rc); 14482a485ad7SGavin Shan continue; 14492a485ad7SGavin Shan } 14502a485ad7SGavin Shan 14512a485ad7SGavin Shan /* If the PHB doesn't have error, stop processing */ 14522a485ad7SGavin Shan if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 14532a485ad7SGavin Shan be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 14542a485ad7SGavin Shan pr_devel("%s: No error found on PHB#%x\n", 14552a485ad7SGavin Shan __func__, hose->global_number); 14562a485ad7SGavin Shan continue; 14572a485ad7SGavin Shan } 14582a485ad7SGavin Shan 14592a485ad7SGavin Shan /* 14602a485ad7SGavin Shan * Processing the error. We're expecting the error with 14612a485ad7SGavin Shan * highest priority reported upon multiple errors on the 14622a485ad7SGavin Shan * specific PHB. 14632a485ad7SGavin Shan */ 14642a485ad7SGavin Shan pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 14652a485ad7SGavin Shan __func__, be16_to_cpu(err_type), 14662a485ad7SGavin Shan be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 14672a485ad7SGavin Shan hose->global_number); 14682a485ad7SGavin Shan switch (be16_to_cpu(err_type)) { 14692a485ad7SGavin Shan case OPAL_EEH_IOC_ERROR: 14702a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 14712a485ad7SGavin Shan pr_err("EEH: dead IOC detected\n"); 14722a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_IOC; 14732a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 14742a485ad7SGavin Shan pr_info("EEH: IOC informative error " 14752a485ad7SGavin Shan "detected\n"); 14762a485ad7SGavin Shan pnv_eeh_get_and_dump_hub_diag(hose); 14772a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 14782a485ad7SGavin Shan } 14792a485ad7SGavin Shan 14802a485ad7SGavin Shan break; 14812a485ad7SGavin Shan case OPAL_EEH_PHB_ERROR: 14822a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 14832a485ad7SGavin Shan *pe = phb_pe; 14842a485ad7SGavin Shan pr_err("EEH: dead PHB#%x detected, " 14852a485ad7SGavin Shan "location: %s\n", 14862a485ad7SGavin Shan hose->global_number, 14872a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14882a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_PHB; 14892a485ad7SGavin Shan } else if (be16_to_cpu(severity) == 14902a485ad7SGavin Shan OPAL_EEH_SEV_PHB_FENCED) { 14912a485ad7SGavin Shan *pe = phb_pe; 14922a485ad7SGavin Shan pr_err("EEH: Fenced PHB#%x detected, " 14932a485ad7SGavin Shan "location: %s\n", 14942a485ad7SGavin Shan hose->global_number, 14952a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14962a485ad7SGavin Shan ret = EEH_NEXT_ERR_FENCED_PHB; 14972a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 14982a485ad7SGavin Shan pr_info("EEH: PHB#%x informative error " 14992a485ad7SGavin Shan "detected, location: %s\n", 15002a485ad7SGavin Shan hose->global_number, 15012a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15022a485ad7SGavin Shan pnv_eeh_get_phb_diag(phb_pe); 15032a485ad7SGavin Shan pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 15042a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15052a485ad7SGavin Shan } 15062a485ad7SGavin Shan 15072a485ad7SGavin Shan break; 15082a485ad7SGavin Shan case OPAL_EEH_PE_ERROR: 15092a485ad7SGavin Shan /* 15102a485ad7SGavin Shan * If we can't find the corresponding PE, we 15112a485ad7SGavin Shan * just try to unfreeze. 15122a485ad7SGavin Shan */ 15132a485ad7SGavin Shan if (pnv_eeh_get_pe(hose, 15142a485ad7SGavin Shan be64_to_cpu(frozen_pe_no), pe)) { 15152a485ad7SGavin Shan pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 15160f36db77SGavin Shan hose->global_number, be64_to_cpu(frozen_pe_no)); 15172a485ad7SGavin Shan pr_info("EEH: PHB location: %s\n", 15182a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 151979cd9520SGavin Shan 152079cd9520SGavin Shan /* Dump PHB diag-data */ 152179cd9520SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, 15225cb1f8fdSRussell Currey phb->diag_data, phb->diag_data_size); 152379cd9520SGavin Shan if (rc == OPAL_SUCCESS) 152479cd9520SGavin Shan pnv_pci_dump_phb_diag_data(hose, 15255cb1f8fdSRussell Currey phb->diag_data); 152679cd9520SGavin Shan 152779cd9520SGavin Shan /* Try best to clear it */ 15282a485ad7SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 1529d63e51b3SGavin Shan be64_to_cpu(frozen_pe_no), 15302a485ad7SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 15312a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15322a485ad7SGavin Shan } else if ((*pe)->state & EEH_PE_ISOLATED || 15332a485ad7SGavin Shan eeh_pe_passed(*pe)) { 15342a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15352a485ad7SGavin Shan } else { 15362a485ad7SGavin Shan pr_err("EEH: Frozen PE#%x " 15372a485ad7SGavin Shan "on PHB#%x detected\n", 15382a485ad7SGavin Shan (*pe)->addr, 15392a485ad7SGavin Shan (*pe)->phb->global_number); 15402a485ad7SGavin Shan pr_err("EEH: PE location: %s, " 15412a485ad7SGavin Shan "PHB location: %s\n", 15422a485ad7SGavin Shan eeh_pe_loc_get(*pe), 15432a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15442a485ad7SGavin Shan ret = EEH_NEXT_ERR_FROZEN_PE; 15452a485ad7SGavin Shan } 15462a485ad7SGavin Shan 15472a485ad7SGavin Shan break; 15482a485ad7SGavin Shan default: 15492a485ad7SGavin Shan pr_warn("%s: Unexpected error type %d\n", 15502a485ad7SGavin Shan __func__, be16_to_cpu(err_type)); 15512a485ad7SGavin Shan } 15522a485ad7SGavin Shan 15532a485ad7SGavin Shan /* 15542a485ad7SGavin Shan * EEH core will try recover from fenced PHB or 15552a485ad7SGavin Shan * frozen PE. In the time for frozen PE, EEH core 15562a485ad7SGavin Shan * enable IO path for that before collecting logs, 15572a485ad7SGavin Shan * but it ruins the site. So we have to dump the 15582a485ad7SGavin Shan * log in advance here. 15592a485ad7SGavin Shan */ 15602a485ad7SGavin Shan if ((ret == EEH_NEXT_ERR_FROZEN_PE || 15612a485ad7SGavin Shan ret == EEH_NEXT_ERR_FENCED_PHB) && 15622a485ad7SGavin Shan !((*pe)->state & EEH_PE_ISOLATED)) { 1563e762bb89SSam Bobroff eeh_pe_mark_isolated(*pe); 15642a485ad7SGavin Shan pnv_eeh_get_phb_diag(*pe); 15652a485ad7SGavin Shan 15662a485ad7SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 15672a485ad7SGavin Shan pnv_pci_dump_phb_diag_data((*pe)->phb, 15682a485ad7SGavin Shan (*pe)->data); 15692a485ad7SGavin Shan } 15702a485ad7SGavin Shan 15712a485ad7SGavin Shan /* 15722a485ad7SGavin Shan * We probably have the frozen parent PE out there and 15732a485ad7SGavin Shan * we need have to handle frozen parent PE firstly. 15742a485ad7SGavin Shan */ 15752a485ad7SGavin Shan if (ret == EEH_NEXT_ERR_FROZEN_PE) { 15762a485ad7SGavin Shan parent_pe = (*pe)->parent; 15772a485ad7SGavin Shan while (parent_pe) { 15782a485ad7SGavin Shan /* Hit the ceiling ? */ 15792a485ad7SGavin Shan if (parent_pe->type & EEH_PE_PHB) 15802a485ad7SGavin Shan break; 15812a485ad7SGavin Shan 15822a485ad7SGavin Shan /* Frozen parent PE ? */ 15832a485ad7SGavin Shan state = eeh_ops->get_state(parent_pe, NULL); 158434a286a4SSam Bobroff if (state > 0 && !eeh_state_active(state)) 15852a485ad7SGavin Shan *pe = parent_pe; 15862a485ad7SGavin Shan 15872a485ad7SGavin Shan /* Next parent level */ 15882a485ad7SGavin Shan parent_pe = parent_pe->parent; 15892a485ad7SGavin Shan } 15902a485ad7SGavin Shan 15912a485ad7SGavin Shan /* We possibly migrate to another PE */ 1592e762bb89SSam Bobroff eeh_pe_mark_isolated(*pe); 15932a485ad7SGavin Shan } 15942a485ad7SGavin Shan 15952a485ad7SGavin Shan /* 15962a485ad7SGavin Shan * If we have no errors on the specific PHB or only 15972a485ad7SGavin Shan * informative error there, we continue poking it. 15982a485ad7SGavin Shan * Otherwise, we need actions to be taken by upper 15992a485ad7SGavin Shan * layer. 16002a485ad7SGavin Shan */ 16012a485ad7SGavin Shan if (ret > EEH_NEXT_ERR_INF) 160229310e5eSGavin Shan break; 160329310e5eSGavin Shan } 160429310e5eSGavin Shan 160579231448SAlistair Popple /* Unmask the event */ 1606b8d65e96SAlistair Popple if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 160779231448SAlistair Popple enable_irq(eeh_event_irq); 160879231448SAlistair Popple 16092a485ad7SGavin Shan return ret; 161029310e5eSGavin Shan } 161129310e5eSGavin Shan 16120bd78587SGavin Shan static int pnv_eeh_restore_config(struct pci_dn *pdn) 16139be3beccSGavin Shan { 16140bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 16159be3beccSGavin Shan struct pnv_phb *phb; 161664ba3dc7SBryant G. Ly s64 ret = 0; 1617405b33a7SAlexey Kardashevskiy int config_addr = (pdn->busno << 8) | (pdn->devfn); 16189be3beccSGavin Shan 16199be3beccSGavin Shan if (!edev) 16209be3beccSGavin Shan return -EEXIST; 16219be3beccSGavin Shan 16220dc2830eSWei Yang /* 16230dc2830eSWei Yang * We have to restore the PCI config space after reset since the 16240dc2830eSWei Yang * firmware can't see SRIOV VFs. 16250dc2830eSWei Yang * 16260dc2830eSWei Yang * FIXME: The MPS, error routing rules, timeout setting are worthy 16270dc2830eSWei Yang * to be exported by firmware in extendible way. 16280dc2830eSWei Yang */ 16290dc2830eSWei Yang if (edev->physfn) { 163064ba3dc7SBryant G. Ly ret = eeh_restore_vf_config(pdn); 16310dc2830eSWei Yang } else { 163269672bd7SAlexey Kardashevskiy phb = pdn->phb->private_data; 16339be3beccSGavin Shan ret = opal_pci_reinit(phb->opal_id, 1634405b33a7SAlexey Kardashevskiy OPAL_REINIT_PCI_DEV, config_addr); 16350dc2830eSWei Yang } 16360dc2830eSWei Yang 16379be3beccSGavin Shan if (ret) { 16389be3beccSGavin Shan pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 1639405b33a7SAlexey Kardashevskiy __func__, config_addr, ret); 16409be3beccSGavin Shan return -EIO; 16419be3beccSGavin Shan } 16429be3beccSGavin Shan 164364ba3dc7SBryant G. Ly return ret; 16449be3beccSGavin Shan } 16459be3beccSGavin Shan 164601f3bfb7SGavin Shan static struct eeh_ops pnv_eeh_ops = { 164729310e5eSGavin Shan .name = "powernv", 164801f3bfb7SGavin Shan .init = pnv_eeh_init, 1649ff57b454SGavin Shan .probe = pnv_eeh_probe, 165001f3bfb7SGavin Shan .set_option = pnv_eeh_set_option, 165101f3bfb7SGavin Shan .get_pe_addr = pnv_eeh_get_pe_addr, 165201f3bfb7SGavin Shan .get_state = pnv_eeh_get_state, 165301f3bfb7SGavin Shan .reset = pnv_eeh_reset, 165401f3bfb7SGavin Shan .get_log = pnv_eeh_get_log, 165501f3bfb7SGavin Shan .configure_bridge = pnv_eeh_configure_bridge, 165601f3bfb7SGavin Shan .err_inject = pnv_eeh_err_inject, 165701f3bfb7SGavin Shan .read_config = pnv_eeh_read_config, 165801f3bfb7SGavin Shan .write_config = pnv_eeh_write_config, 165901f3bfb7SGavin Shan .next_error = pnv_eeh_next_error, 166067923cfcSBryant G. Ly .restore_config = pnv_eeh_restore_config, 166167923cfcSBryant G. Ly .notify_resume = NULL 166229310e5eSGavin Shan }; 166329310e5eSGavin Shan 16640dc2830eSWei Yang #ifdef CONFIG_PCI_IOV 16650dc2830eSWei Yang static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 16660dc2830eSWei Yang { 16670dc2830eSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 16680dc2830eSWei Yang int parent_mps; 16690dc2830eSWei Yang 16700dc2830eSWei Yang if (!pdev->is_virtfn) 16710dc2830eSWei Yang return; 16720dc2830eSWei Yang 16730dc2830eSWei Yang /* Synchronize MPS for VF and PF */ 16740dc2830eSWei Yang parent_mps = pcie_get_mps(pdev->physfn); 16750dc2830eSWei Yang if ((128 << pdev->pcie_mpss) >= parent_mps) 16760dc2830eSWei Yang pcie_set_mps(pdev, parent_mps); 16770dc2830eSWei Yang pdn->mps = pcie_get_mps(pdev); 16780dc2830eSWei Yang } 16790dc2830eSWei Yang DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 16800dc2830eSWei Yang #endif /* CONFIG_PCI_IOV */ 16810dc2830eSWei Yang 168229310e5eSGavin Shan /** 168329310e5eSGavin Shan * eeh_powernv_init - Register platform dependent EEH operations 168429310e5eSGavin Shan * 168529310e5eSGavin Shan * EEH initialization on powernv platform. This function should be 168629310e5eSGavin Shan * called before any EEH related functions. 168729310e5eSGavin Shan */ 168829310e5eSGavin Shan static int __init eeh_powernv_init(void) 168929310e5eSGavin Shan { 169029310e5eSGavin Shan int ret = -EINVAL; 169129310e5eSGavin Shan 169201f3bfb7SGavin Shan ret = eeh_ops_register(&pnv_eeh_ops); 169329310e5eSGavin Shan if (!ret) 169429310e5eSGavin Shan pr_info("EEH: PowerNV platform initialized\n"); 169529310e5eSGavin Shan else 169629310e5eSGavin Shan pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 169729310e5eSGavin Shan 169829310e5eSGavin Shan return ret; 169929310e5eSGavin Shan } 1700b14726c5SMichael Ellerman machine_early_initcall(powernv, eeh_powernv_init); 1701