129310e5eSGavin Shan /* 229310e5eSGavin Shan * The file intends to implement the platform dependent EEH operations on 329310e5eSGavin Shan * powernv platform. Actually, the powernv was created in order to fully 429310e5eSGavin Shan * hypervisor support. 529310e5eSGavin Shan * 629310e5eSGavin Shan * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 729310e5eSGavin Shan * 829310e5eSGavin Shan * This program is free software; you can redistribute it and/or modify 929310e5eSGavin Shan * it under the terms of the GNU General Public License as published by 1029310e5eSGavin Shan * the Free Software Foundation; either version 2 of the License, or 1129310e5eSGavin Shan * (at your option) any later version. 1229310e5eSGavin Shan */ 1329310e5eSGavin Shan 1429310e5eSGavin Shan #include <linux/atomic.h> 154cf17445SGavin Shan #include <linux/debugfs.h> 1629310e5eSGavin Shan #include <linux/delay.h> 1729310e5eSGavin Shan #include <linux/export.h> 1829310e5eSGavin Shan #include <linux/init.h> 1929310e5eSGavin Shan #include <linux/list.h> 2029310e5eSGavin Shan #include <linux/msi.h> 2129310e5eSGavin Shan #include <linux/of.h> 2229310e5eSGavin Shan #include <linux/pci.h> 2329310e5eSGavin Shan #include <linux/proc_fs.h> 2429310e5eSGavin Shan #include <linux/rbtree.h> 2529310e5eSGavin Shan #include <linux/sched.h> 2629310e5eSGavin Shan #include <linux/seq_file.h> 2729310e5eSGavin Shan #include <linux/spinlock.h> 2829310e5eSGavin Shan 2929310e5eSGavin Shan #include <asm/eeh.h> 3029310e5eSGavin Shan #include <asm/eeh_event.h> 3129310e5eSGavin Shan #include <asm/firmware.h> 3229310e5eSGavin Shan #include <asm/io.h> 3329310e5eSGavin Shan #include <asm/iommu.h> 3429310e5eSGavin Shan #include <asm/machdep.h> 3529310e5eSGavin Shan #include <asm/msi_bitmap.h> 3629310e5eSGavin Shan #include <asm/opal.h> 3729310e5eSGavin Shan #include <asm/ppc-pci.h> 3829310e5eSGavin Shan 3929310e5eSGavin Shan #include "powernv.h" 4029310e5eSGavin Shan #include "pci.h" 4129310e5eSGavin Shan 424cf17445SGavin Shan static bool pnv_eeh_nb_init = false; 434cf17445SGavin Shan 4429310e5eSGavin Shan /** 4501f3bfb7SGavin Shan * pnv_eeh_init - EEH platform dependent initialization 4629310e5eSGavin Shan * 4729310e5eSGavin Shan * EEH platform dependent initialization on powernv 4829310e5eSGavin Shan */ 4901f3bfb7SGavin Shan static int pnv_eeh_init(void) 5029310e5eSGavin Shan { 51dc561fb9SGavin Shan struct pci_controller *hose; 52dc561fb9SGavin Shan struct pnv_phb *phb; 53dc561fb9SGavin Shan 5429310e5eSGavin Shan /* We require OPALv3 */ 5529310e5eSGavin Shan if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 560dae2743SGavin Shan pr_warn("%s: OPALv3 is required !\n", 570dae2743SGavin Shan __func__); 5829310e5eSGavin Shan return -EINVAL; 5929310e5eSGavin Shan } 6029310e5eSGavin Shan 6105b1721dSGavin Shan /* Set probe mode */ 6205b1721dSGavin Shan eeh_add_flag(EEH_PROBE_MODE_DEV); 6329310e5eSGavin Shan 64dc561fb9SGavin Shan /* 65dc561fb9SGavin Shan * P7IOC blocks PCI config access to frozen PE, but PHB3 66dc561fb9SGavin Shan * doesn't do that. So we have to selectively enable I/O 67dc561fb9SGavin Shan * prior to collecting error log. 68dc561fb9SGavin Shan */ 69dc561fb9SGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 70dc561fb9SGavin Shan phb = hose->private_data; 71dc561fb9SGavin Shan 72dc561fb9SGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC) 73dc561fb9SGavin Shan eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 742aa5cf9eSGavin Shan 752aa5cf9eSGavin Shan /* 762aa5cf9eSGavin Shan * PE#0 should be regarded as valid by EEH core 772aa5cf9eSGavin Shan * if it's not the reserved one. Currently, we 782aa5cf9eSGavin Shan * have the reserved PE#0 and PE#127 for PHB3 792aa5cf9eSGavin Shan * and P7IOC separately. So we should regard 802aa5cf9eSGavin Shan * PE#0 as valid for P7IOC. 812aa5cf9eSGavin Shan */ 822aa5cf9eSGavin Shan if (phb->ioda.reserved_pe != 0) 832aa5cf9eSGavin Shan eeh_add_flag(EEH_VALID_PE_ZERO); 842aa5cf9eSGavin Shan 85dc561fb9SGavin Shan break; 86dc561fb9SGavin Shan } 87dc561fb9SGavin Shan 8829310e5eSGavin Shan return 0; 8929310e5eSGavin Shan } 9029310e5eSGavin Shan 914cf17445SGavin Shan static int pnv_eeh_event(struct notifier_block *nb, 924cf17445SGavin Shan unsigned long events, void *change) 934cf17445SGavin Shan { 944cf17445SGavin Shan uint64_t changed_evts = (uint64_t)change; 954cf17445SGavin Shan 964cf17445SGavin Shan /* 974cf17445SGavin Shan * We simply send special EEH event if EEH has 984cf17445SGavin Shan * been enabled, or clear pending events in 994cf17445SGavin Shan * case that we enable EEH soon 1004cf17445SGavin Shan */ 1014cf17445SGavin Shan if (!(changed_evts & OPAL_EVENT_PCI_ERROR) || 1024cf17445SGavin Shan !(events & OPAL_EVENT_PCI_ERROR)) 1034cf17445SGavin Shan return 0; 1044cf17445SGavin Shan 1054cf17445SGavin Shan if (eeh_enabled()) 1064cf17445SGavin Shan eeh_send_failure_event(NULL); 1074cf17445SGavin Shan else 1084cf17445SGavin Shan opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul); 1094cf17445SGavin Shan 1104cf17445SGavin Shan return 0; 1114cf17445SGavin Shan } 1124cf17445SGavin Shan 1134cf17445SGavin Shan static struct notifier_block pnv_eeh_nb = { 1144cf17445SGavin Shan .notifier_call = pnv_eeh_event, 1154cf17445SGavin Shan .next = NULL, 1164cf17445SGavin Shan .priority = 0 1174cf17445SGavin Shan }; 1184cf17445SGavin Shan 1194cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 1204cf17445SGavin Shan static ssize_t pnv_eeh_ei_write(struct file *filp, 1214cf17445SGavin Shan const char __user *user_buf, 1224cf17445SGavin Shan size_t count, loff_t *ppos) 1234cf17445SGavin Shan { 1244cf17445SGavin Shan struct pci_controller *hose = filp->private_data; 1254cf17445SGavin Shan struct eeh_dev *edev; 1264cf17445SGavin Shan struct eeh_pe *pe; 1274cf17445SGavin Shan int pe_no, type, func; 1284cf17445SGavin Shan unsigned long addr, mask; 1294cf17445SGavin Shan char buf[50]; 1304cf17445SGavin Shan int ret; 1314cf17445SGavin Shan 1324cf17445SGavin Shan if (!eeh_ops || !eeh_ops->err_inject) 1334cf17445SGavin Shan return -ENXIO; 1344cf17445SGavin Shan 1354cf17445SGavin Shan /* Copy over argument buffer */ 1364cf17445SGavin Shan ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 1374cf17445SGavin Shan if (!ret) 1384cf17445SGavin Shan return -EFAULT; 1394cf17445SGavin Shan 1404cf17445SGavin Shan /* Retrieve parameters */ 1414cf17445SGavin Shan ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 1424cf17445SGavin Shan &pe_no, &type, &func, &addr, &mask); 1434cf17445SGavin Shan if (ret != 5) 1444cf17445SGavin Shan return -EINVAL; 1454cf17445SGavin Shan 1464cf17445SGavin Shan /* Retrieve PE */ 1474cf17445SGavin Shan edev = kzalloc(sizeof(*edev), GFP_KERNEL); 1484cf17445SGavin Shan if (!edev) 1494cf17445SGavin Shan return -ENOMEM; 1504cf17445SGavin Shan edev->phb = hose; 1514cf17445SGavin Shan edev->pe_config_addr = pe_no; 1524cf17445SGavin Shan pe = eeh_pe_get(edev); 1534cf17445SGavin Shan kfree(edev); 1544cf17445SGavin Shan if (!pe) 1554cf17445SGavin Shan return -ENODEV; 1564cf17445SGavin Shan 1574cf17445SGavin Shan /* Do error injection */ 1584cf17445SGavin Shan ret = eeh_ops->err_inject(pe, type, func, addr, mask); 1594cf17445SGavin Shan return ret < 0 ? ret : count; 1604cf17445SGavin Shan } 1614cf17445SGavin Shan 1624cf17445SGavin Shan static const struct file_operations pnv_eeh_ei_fops = { 1634cf17445SGavin Shan .open = simple_open, 1644cf17445SGavin Shan .llseek = no_llseek, 1654cf17445SGavin Shan .write = pnv_eeh_ei_write, 1664cf17445SGavin Shan }; 1674cf17445SGavin Shan 1684cf17445SGavin Shan static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 1694cf17445SGavin Shan { 1704cf17445SGavin Shan struct pci_controller *hose = data; 1714cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1724cf17445SGavin Shan 1734cf17445SGavin Shan out_be64(phb->regs + offset, val); 1744cf17445SGavin Shan return 0; 1754cf17445SGavin Shan } 1764cf17445SGavin Shan 1774cf17445SGavin Shan static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 1784cf17445SGavin Shan { 1794cf17445SGavin Shan struct pci_controller *hose = data; 1804cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1814cf17445SGavin Shan 1824cf17445SGavin Shan *val = in_be64(phb->regs + offset); 1834cf17445SGavin Shan return 0; 1844cf17445SGavin Shan } 1854cf17445SGavin Shan 1864cf17445SGavin Shan static int pnv_eeh_outb_dbgfs_set(void *data, u64 val) 1874cf17445SGavin Shan { 1884cf17445SGavin Shan return pnv_eeh_dbgfs_set(data, 0xD10, val); 1894cf17445SGavin Shan } 1904cf17445SGavin Shan 1914cf17445SGavin Shan static int pnv_eeh_outb_dbgfs_get(void *data, u64 *val) 1924cf17445SGavin Shan { 1934cf17445SGavin Shan return pnv_eeh_dbgfs_get(data, 0xD10, val); 1944cf17445SGavin Shan } 1954cf17445SGavin Shan 1964cf17445SGavin Shan static int pnv_eeh_inbA_dbgfs_set(void *data, u64 val) 1974cf17445SGavin Shan { 1984cf17445SGavin Shan return pnv_eeh_dbgfs_set(data, 0xD90, val); 1994cf17445SGavin Shan } 2004cf17445SGavin Shan 2014cf17445SGavin Shan static int pnv_eeh_inbA_dbgfs_get(void *data, u64 *val) 2024cf17445SGavin Shan { 2034cf17445SGavin Shan return pnv_eeh_dbgfs_get(data, 0xD90, val); 2044cf17445SGavin Shan } 2054cf17445SGavin Shan 2064cf17445SGavin Shan static int pnv_eeh_inbB_dbgfs_set(void *data, u64 val) 2074cf17445SGavin Shan { 2084cf17445SGavin Shan return pnv_eeh_dbgfs_set(data, 0xE10, val); 2094cf17445SGavin Shan } 2104cf17445SGavin Shan 2114cf17445SGavin Shan static int pnv_eeh_inbB_dbgfs_get(void *data, u64 *val) 2124cf17445SGavin Shan { 2134cf17445SGavin Shan return pnv_eeh_dbgfs_get(data, 0xE10, val); 2144cf17445SGavin Shan } 2154cf17445SGavin Shan 2164cf17445SGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_outb_dbgfs_ops, pnv_eeh_outb_dbgfs_get, 2174cf17445SGavin Shan pnv_eeh_outb_dbgfs_set, "0x%llx\n"); 2184cf17445SGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbA_dbgfs_ops, pnv_eeh_inbA_dbgfs_get, 2194cf17445SGavin Shan pnv_eeh_inbA_dbgfs_set, "0x%llx\n"); 2204cf17445SGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbB_dbgfs_ops, pnv_eeh_inbB_dbgfs_get, 2214cf17445SGavin Shan pnv_eeh_inbB_dbgfs_set, "0x%llx\n"); 2224cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 2234cf17445SGavin Shan 22429310e5eSGavin Shan /** 22501f3bfb7SGavin Shan * pnv_eeh_post_init - EEH platform dependent post initialization 22629310e5eSGavin Shan * 22729310e5eSGavin Shan * EEH platform dependent post initialization on powernv. When 22829310e5eSGavin Shan * the function is called, the EEH PEs and devices should have 22929310e5eSGavin Shan * been built. If the I/O cache staff has been built, EEH is 23029310e5eSGavin Shan * ready to supply service. 23129310e5eSGavin Shan */ 23201f3bfb7SGavin Shan static int pnv_eeh_post_init(void) 23329310e5eSGavin Shan { 23429310e5eSGavin Shan struct pci_controller *hose; 23529310e5eSGavin Shan struct pnv_phb *phb; 23629310e5eSGavin Shan int ret = 0; 23729310e5eSGavin Shan 2384cf17445SGavin Shan /* Register OPAL event notifier */ 2394cf17445SGavin Shan if (!pnv_eeh_nb_init) { 2404cf17445SGavin Shan ret = opal_notifier_register(&pnv_eeh_nb); 2414cf17445SGavin Shan if (ret) { 2424cf17445SGavin Shan pr_warn("%s: Can't register OPAL event notifier (%d)\n", 2434cf17445SGavin Shan __func__, ret); 2444cf17445SGavin Shan return ret; 2454cf17445SGavin Shan } 2464cf17445SGavin Shan 2474cf17445SGavin Shan pnv_eeh_nb_init = true; 2484cf17445SGavin Shan } 2494cf17445SGavin Shan 25029310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 25129310e5eSGavin Shan phb = hose->private_data; 25229310e5eSGavin Shan 2534cf17445SGavin Shan /* 2544cf17445SGavin Shan * If EEH is enabled, we're going to rely on that. 2554cf17445SGavin Shan * Otherwise, we restore to conventional mechanism 2564cf17445SGavin Shan * to clear frozen PE during PCI config access. 2574cf17445SGavin Shan */ 2584cf17445SGavin Shan if (eeh_enabled()) 2594cf17445SGavin Shan phb->flags |= PNV_PHB_FLAG_EEH; 2604cf17445SGavin Shan else 2614cf17445SGavin Shan phb->flags &= ~PNV_PHB_FLAG_EEH; 2624cf17445SGavin Shan 2634cf17445SGavin Shan /* Create debugfs entries */ 2644cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 2654cf17445SGavin Shan if (phb->has_dbgfs || !phb->dbgfs) 2664cf17445SGavin Shan continue; 2674cf17445SGavin Shan 2684cf17445SGavin Shan phb->has_dbgfs = 1; 2694cf17445SGavin Shan debugfs_create_file("err_injct", 0200, 2704cf17445SGavin Shan phb->dbgfs, hose, 2714cf17445SGavin Shan &pnv_eeh_ei_fops); 2724cf17445SGavin Shan 2734cf17445SGavin Shan debugfs_create_file("err_injct_outbound", 0600, 2744cf17445SGavin Shan phb->dbgfs, hose, 2754cf17445SGavin Shan &pnv_eeh_outb_dbgfs_ops); 2764cf17445SGavin Shan debugfs_create_file("err_injct_inboundA", 0600, 2774cf17445SGavin Shan phb->dbgfs, hose, 2784cf17445SGavin Shan &pnv_eeh_inbA_dbgfs_ops); 2794cf17445SGavin Shan debugfs_create_file("err_injct_inboundB", 0600, 2804cf17445SGavin Shan phb->dbgfs, hose, 2814cf17445SGavin Shan &pnv_eeh_inbB_dbgfs_ops); 2824cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 28329310e5eSGavin Shan } 2844cf17445SGavin Shan 28529310e5eSGavin Shan 28629310e5eSGavin Shan return ret; 28729310e5eSGavin Shan } 28829310e5eSGavin Shan 28929310e5eSGavin Shan /** 29001f3bfb7SGavin Shan * pnv_eeh_dev_probe - Do probe on PCI device 29129310e5eSGavin Shan * @dev: PCI device 29229310e5eSGavin Shan * @flag: unused 29329310e5eSGavin Shan * 29429310e5eSGavin Shan * When EEH module is installed during system boot, all PCI devices 29529310e5eSGavin Shan * are checked one by one to see if it supports EEH. The function 29629310e5eSGavin Shan * is introduced for the purpose. By default, EEH has been enabled 29729310e5eSGavin Shan * on all PCI devices. That's to say, we only need do necessary 29829310e5eSGavin Shan * initialization on the corresponding eeh device and create PE 29929310e5eSGavin Shan * accordingly. 30029310e5eSGavin Shan * 30129310e5eSGavin Shan * It's notable that's unsafe to retrieve the EEH device through 30229310e5eSGavin Shan * the corresponding PCI device. During the PCI device hotplug, which 30329310e5eSGavin Shan * was possiblly triggered by EEH core, the binding between EEH device 30429310e5eSGavin Shan * and the PCI device isn't built yet. 30529310e5eSGavin Shan */ 30601f3bfb7SGavin Shan static int pnv_eeh_dev_probe(struct pci_dev *dev, void *flag) 30729310e5eSGavin Shan { 30829310e5eSGavin Shan struct pci_controller *hose = pci_bus_to_host(dev->bus); 30929310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 31029310e5eSGavin Shan struct device_node *dn = pci_device_to_OF_node(dev); 31129310e5eSGavin Shan struct eeh_dev *edev = of_node_to_eeh_dev(dn); 312dadcd6d6SMike Qiu int ret; 31329310e5eSGavin Shan 31429310e5eSGavin Shan /* 31529310e5eSGavin Shan * When probing the root bridge, which doesn't have any 31629310e5eSGavin Shan * subordinate PCI devices. We don't have OF node for 31729310e5eSGavin Shan * the root bridge. So it's not reasonable to continue 31829310e5eSGavin Shan * the probing. 31929310e5eSGavin Shan */ 320f5c57710SGavin Shan if (!dn || !edev || edev->pe) 32129310e5eSGavin Shan return 0; 32229310e5eSGavin Shan 32329310e5eSGavin Shan /* Skip for PCI-ISA bridge */ 32429310e5eSGavin Shan if ((dev->class >> 8) == PCI_CLASS_BRIDGE_ISA) 32529310e5eSGavin Shan return 0; 32629310e5eSGavin Shan 32729310e5eSGavin Shan /* Initialize eeh device */ 32829310e5eSGavin Shan edev->class_code = dev->class; 329ab55d218SGavin Shan edev->mode &= 0xFFFFFF00; 3304b83bd45SGavin Shan if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) 3314b83bd45SGavin Shan edev->mode |= EEH_DEV_BRIDGE; 3322a18dfc6SGavin Shan edev->pcix_cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); 3334b83bd45SGavin Shan if (pci_is_pcie(dev)) { 3344b83bd45SGavin Shan edev->pcie_cap = pci_pcie_cap(dev); 3354b83bd45SGavin Shan 3364b83bd45SGavin Shan if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) 3374b83bd45SGavin Shan edev->mode |= EEH_DEV_ROOT_PORT; 3384b83bd45SGavin Shan else if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) 3394b83bd45SGavin Shan edev->mode |= EEH_DEV_DS_PORT; 3402a18dfc6SGavin Shan 3412a18dfc6SGavin Shan edev->aer_cap = pci_find_ext_capability(dev, 3422a18dfc6SGavin Shan PCI_EXT_CAP_ID_ERR); 3434b83bd45SGavin Shan } 3444b83bd45SGavin Shan 34529310e5eSGavin Shan edev->config_addr = ((dev->bus->number << 8) | dev->devfn); 34629310e5eSGavin Shan edev->pe_config_addr = phb->bdfn_to_pe(phb, dev->bus, dev->devfn & 0xff); 34729310e5eSGavin Shan 34829310e5eSGavin Shan /* Create PE */ 349dadcd6d6SMike Qiu ret = eeh_add_to_parent_pe(edev); 350dadcd6d6SMike Qiu if (ret) { 351dadcd6d6SMike Qiu pr_warn("%s: Can't add PCI dev %s to parent PE (%d)\n", 352dadcd6d6SMike Qiu __func__, pci_name(dev), ret); 353dadcd6d6SMike Qiu return ret; 354dadcd6d6SMike Qiu } 355dadcd6d6SMike Qiu 356dadcd6d6SMike Qiu /* 357b6541db1SGavin Shan * If the PE contains any one of following adapters, the 358b6541db1SGavin Shan * PCI config space can't be accessed when dumping EEH log. 359b6541db1SGavin Shan * Otherwise, we will run into fenced PHB caused by shortage 360b6541db1SGavin Shan * of outbound credits in the adapter. The PCI config access 361b6541db1SGavin Shan * should be blocked until PE reset. MMIO access is dropped 362b6541db1SGavin Shan * by hardware certainly. In order to drop PCI config requests, 363b6541db1SGavin Shan * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 364b6541db1SGavin Shan * will be checked in the backend for PE state retrival. If 365b6541db1SGavin Shan * the PE becomes frozen for the first time and the flag has 366b6541db1SGavin Shan * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 367b6541db1SGavin Shan * that PE to block its config space. 368b6541db1SGavin Shan * 369b6541db1SGavin Shan * Broadcom Austin 4-ports NICs (14e4:1657) 370179ea48bSGavin Shan * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 371b6541db1SGavin Shan */ 372179ea48bSGavin Shan if ((dev->vendor == PCI_VENDOR_ID_BROADCOM && dev->device == 0x1657) || 373179ea48bSGavin Shan (dev->vendor == PCI_VENDOR_ID_BROADCOM && dev->device == 0x168e)) 374b6541db1SGavin Shan edev->pe->state |= EEH_PE_CFG_RESTRICTED; 375b6541db1SGavin Shan 376b6541db1SGavin Shan /* 377dadcd6d6SMike Qiu * Cache the PE primary bus, which can't be fetched when 378dadcd6d6SMike Qiu * full hotplug is in progress. In that case, all child 379dadcd6d6SMike Qiu * PCI devices of the PE are expected to be removed prior 380dadcd6d6SMike Qiu * to PE reset. 381dadcd6d6SMike Qiu */ 382dadcd6d6SMike Qiu if (!edev->pe->bus) 383dadcd6d6SMike Qiu edev->pe->bus = dev->bus; 38429310e5eSGavin Shan 38529310e5eSGavin Shan /* 38629310e5eSGavin Shan * Enable EEH explicitly so that we will do EEH check 38729310e5eSGavin Shan * while accessing I/O stuff 38829310e5eSGavin Shan */ 38905b1721dSGavin Shan eeh_add_flag(EEH_ENABLED); 39029310e5eSGavin Shan 39129310e5eSGavin Shan /* Save memory bars */ 39229310e5eSGavin Shan eeh_save_bars(edev); 39329310e5eSGavin Shan 39429310e5eSGavin Shan return 0; 39529310e5eSGavin Shan } 39629310e5eSGavin Shan 39729310e5eSGavin Shan /** 39801f3bfb7SGavin Shan * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 39929310e5eSGavin Shan * @pe: EEH PE 40029310e5eSGavin Shan * @option: operation to be issued 40129310e5eSGavin Shan * 40229310e5eSGavin Shan * The function is used to control the EEH functionality globally. 40329310e5eSGavin Shan * Currently, following options are support according to PAPR: 40429310e5eSGavin Shan * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 40529310e5eSGavin Shan */ 40601f3bfb7SGavin Shan static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 40729310e5eSGavin Shan { 40829310e5eSGavin Shan struct pci_controller *hose = pe->phb; 40929310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 4107e3e4f8dSGavin Shan bool freeze_pe = false; 4117e3e4f8dSGavin Shan int opt, ret = 0; 4127e3e4f8dSGavin Shan s64 rc; 41329310e5eSGavin Shan 4147e3e4f8dSGavin Shan /* Sanity check on option */ 4157e3e4f8dSGavin Shan switch (option) { 4167e3e4f8dSGavin Shan case EEH_OPT_DISABLE: 4177e3e4f8dSGavin Shan return -EPERM; 4187e3e4f8dSGavin Shan case EEH_OPT_ENABLE: 4197e3e4f8dSGavin Shan return 0; 4207e3e4f8dSGavin Shan case EEH_OPT_THAW_MMIO: 4217e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 4227e3e4f8dSGavin Shan break; 4237e3e4f8dSGavin Shan case EEH_OPT_THAW_DMA: 4247e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 4257e3e4f8dSGavin Shan break; 4267e3e4f8dSGavin Shan case EEH_OPT_FREEZE_PE: 4277e3e4f8dSGavin Shan freeze_pe = true; 4287e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 4297e3e4f8dSGavin Shan break; 4307e3e4f8dSGavin Shan default: 4317e3e4f8dSGavin Shan pr_warn("%s: Invalid option %d\n", __func__, option); 4327e3e4f8dSGavin Shan return -EINVAL; 4337e3e4f8dSGavin Shan } 4347e3e4f8dSGavin Shan 4357e3e4f8dSGavin Shan /* If PHB supports compound PE, to handle it */ 4367e3e4f8dSGavin Shan if (freeze_pe) { 4377e3e4f8dSGavin Shan if (phb->freeze_pe) { 4387e3e4f8dSGavin Shan phb->freeze_pe(phb, pe->addr); 4397e3e4f8dSGavin Shan } else { 4407e3e4f8dSGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, 4417e3e4f8dSGavin Shan pe->addr, opt); 4427e3e4f8dSGavin Shan if (rc != OPAL_SUCCESS) { 4437e3e4f8dSGavin Shan pr_warn("%s: Failure %lld freezing " 4447e3e4f8dSGavin Shan "PHB#%x-PE#%x\n", 4457e3e4f8dSGavin Shan __func__, rc, 4467e3e4f8dSGavin Shan phb->hose->global_number, pe->addr); 4477e3e4f8dSGavin Shan ret = -EIO; 4487e3e4f8dSGavin Shan } 4497e3e4f8dSGavin Shan } 4507e3e4f8dSGavin Shan } else { 4517e3e4f8dSGavin Shan if (phb->unfreeze_pe) { 4527e3e4f8dSGavin Shan ret = phb->unfreeze_pe(phb, pe->addr, opt); 4537e3e4f8dSGavin Shan } else { 4547e3e4f8dSGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, 4557e3e4f8dSGavin Shan pe->addr, opt); 4567e3e4f8dSGavin Shan if (rc != OPAL_SUCCESS) { 4577e3e4f8dSGavin Shan pr_warn("%s: Failure %lld enable %d " 4587e3e4f8dSGavin Shan "for PHB#%x-PE#%x\n", 4597e3e4f8dSGavin Shan __func__, rc, option, 4607e3e4f8dSGavin Shan phb->hose->global_number, pe->addr); 4617e3e4f8dSGavin Shan ret = -EIO; 4627e3e4f8dSGavin Shan } 4637e3e4f8dSGavin Shan } 4647e3e4f8dSGavin Shan } 46529310e5eSGavin Shan 46629310e5eSGavin Shan return ret; 46729310e5eSGavin Shan } 46829310e5eSGavin Shan 46929310e5eSGavin Shan /** 47001f3bfb7SGavin Shan * pnv_eeh_get_pe_addr - Retrieve PE address 47129310e5eSGavin Shan * @pe: EEH PE 47229310e5eSGavin Shan * 47329310e5eSGavin Shan * Retrieve the PE address according to the given tranditional 47429310e5eSGavin Shan * PCI BDF (Bus/Device/Function) address. 47529310e5eSGavin Shan */ 47601f3bfb7SGavin Shan static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 47729310e5eSGavin Shan { 47829310e5eSGavin Shan return pe->addr; 47929310e5eSGavin Shan } 48029310e5eSGavin Shan 48140ae5f69SGavin Shan static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 48240ae5f69SGavin Shan { 48340ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 48440ae5f69SGavin Shan s64 rc; 48540ae5f69SGavin Shan 48640ae5f69SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 48740ae5f69SGavin Shan PNV_PCI_DIAG_BUF_SIZE); 48840ae5f69SGavin Shan if (rc != OPAL_SUCCESS) 48940ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 49040ae5f69SGavin Shan __func__, rc, pe->phb->global_number); 49140ae5f69SGavin Shan } 49240ae5f69SGavin Shan 49340ae5f69SGavin Shan static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 49440ae5f69SGavin Shan { 49540ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 49640ae5f69SGavin Shan u8 fstate; 49740ae5f69SGavin Shan __be16 pcierr; 49840ae5f69SGavin Shan s64 rc; 49940ae5f69SGavin Shan int result = 0; 50040ae5f69SGavin Shan 50140ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 50240ae5f69SGavin Shan pe->addr, 50340ae5f69SGavin Shan &fstate, 50440ae5f69SGavin Shan &pcierr, 50540ae5f69SGavin Shan NULL); 50640ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 50740ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x state\n", 50840ae5f69SGavin Shan __func__, rc, phb->hose->global_number); 50940ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 51040ae5f69SGavin Shan } 51140ae5f69SGavin Shan 51240ae5f69SGavin Shan /* 51340ae5f69SGavin Shan * Check PHB state. If the PHB is frozen for the 51440ae5f69SGavin Shan * first time, to dump the PHB diag-data. 51540ae5f69SGavin Shan */ 51640ae5f69SGavin Shan if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 51740ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 51840ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 51940ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 52040ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 52140ae5f69SGavin Shan } else if (!(pe->state & EEH_PE_ISOLATED)) { 52240ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 52340ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 52440ae5f69SGavin Shan 52540ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 52640ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 52740ae5f69SGavin Shan } 52840ae5f69SGavin Shan 52940ae5f69SGavin Shan return result; 53040ae5f69SGavin Shan } 53140ae5f69SGavin Shan 53240ae5f69SGavin Shan static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 53340ae5f69SGavin Shan { 53440ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 53540ae5f69SGavin Shan u8 fstate; 53640ae5f69SGavin Shan __be16 pcierr; 53740ae5f69SGavin Shan s64 rc; 53840ae5f69SGavin Shan int result; 53940ae5f69SGavin Shan 54040ae5f69SGavin Shan /* 54140ae5f69SGavin Shan * We don't clobber hardware frozen state until PE 54240ae5f69SGavin Shan * reset is completed. In order to keep EEH core 54340ae5f69SGavin Shan * moving forward, we have to return operational 54440ae5f69SGavin Shan * state during PE reset. 54540ae5f69SGavin Shan */ 54640ae5f69SGavin Shan if (pe->state & EEH_PE_RESET) { 54740ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 54840ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 54940ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 55040ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 55140ae5f69SGavin Shan return result; 55240ae5f69SGavin Shan } 55340ae5f69SGavin Shan 55440ae5f69SGavin Shan /* 55540ae5f69SGavin Shan * Fetch PE state from hardware. If the PHB 55640ae5f69SGavin Shan * supports compound PE, let it handle that. 55740ae5f69SGavin Shan */ 55840ae5f69SGavin Shan if (phb->get_pe_state) { 55940ae5f69SGavin Shan fstate = phb->get_pe_state(phb, pe->addr); 56040ae5f69SGavin Shan } else { 56140ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 56240ae5f69SGavin Shan pe->addr, 56340ae5f69SGavin Shan &fstate, 56440ae5f69SGavin Shan &pcierr, 56540ae5f69SGavin Shan NULL); 56640ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 56740ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 56840ae5f69SGavin Shan __func__, rc, phb->hose->global_number, 56940ae5f69SGavin Shan pe->addr); 57040ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 57140ae5f69SGavin Shan } 57240ae5f69SGavin Shan } 57340ae5f69SGavin Shan 57440ae5f69SGavin Shan /* Figure out state */ 57540ae5f69SGavin Shan switch (fstate) { 57640ae5f69SGavin Shan case OPAL_EEH_STOPPED_NOT_FROZEN: 57740ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 57840ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 57940ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 58040ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 58140ae5f69SGavin Shan break; 58240ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_FREEZE: 58340ae5f69SGavin Shan result = (EEH_STATE_DMA_ACTIVE | 58440ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 58540ae5f69SGavin Shan break; 58640ae5f69SGavin Shan case OPAL_EEH_STOPPED_DMA_FREEZE: 58740ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 58840ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED); 58940ae5f69SGavin Shan break; 59040ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 59140ae5f69SGavin Shan result = 0; 59240ae5f69SGavin Shan break; 59340ae5f69SGavin Shan case OPAL_EEH_STOPPED_RESET: 59440ae5f69SGavin Shan result = EEH_STATE_RESET_ACTIVE; 59540ae5f69SGavin Shan break; 59640ae5f69SGavin Shan case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 59740ae5f69SGavin Shan result = EEH_STATE_UNAVAILABLE; 59840ae5f69SGavin Shan break; 59940ae5f69SGavin Shan case OPAL_EEH_STOPPED_PERM_UNAVAIL: 60040ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 60140ae5f69SGavin Shan break; 60240ae5f69SGavin Shan default: 60340ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 60440ae5f69SGavin Shan pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 60540ae5f69SGavin Shan __func__, phb->hose->global_number, 60640ae5f69SGavin Shan pe->addr, fstate); 60740ae5f69SGavin Shan } 60840ae5f69SGavin Shan 60940ae5f69SGavin Shan /* 61040ae5f69SGavin Shan * If PHB supports compound PE, to freeze all 61140ae5f69SGavin Shan * slave PEs for consistency. 61240ae5f69SGavin Shan * 61340ae5f69SGavin Shan * If the PE is switching to frozen state for the 61440ae5f69SGavin Shan * first time, to dump the PHB diag-data. 61540ae5f69SGavin Shan */ 61640ae5f69SGavin Shan if (!(result & EEH_STATE_NOT_SUPPORT) && 61740ae5f69SGavin Shan !(result & EEH_STATE_UNAVAILABLE) && 61840ae5f69SGavin Shan !(result & EEH_STATE_MMIO_ACTIVE) && 61940ae5f69SGavin Shan !(result & EEH_STATE_DMA_ACTIVE) && 62040ae5f69SGavin Shan !(pe->state & EEH_PE_ISOLATED)) { 62140ae5f69SGavin Shan if (phb->freeze_pe) 62240ae5f69SGavin Shan phb->freeze_pe(phb, pe->addr); 62340ae5f69SGavin Shan 62440ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 62540ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 62640ae5f69SGavin Shan 62740ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 62840ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 62940ae5f69SGavin Shan } 63040ae5f69SGavin Shan 63140ae5f69SGavin Shan return result; 63240ae5f69SGavin Shan } 63340ae5f69SGavin Shan 63429310e5eSGavin Shan /** 63501f3bfb7SGavin Shan * pnv_eeh_get_state - Retrieve PE state 63629310e5eSGavin Shan * @pe: EEH PE 63729310e5eSGavin Shan * @delay: delay while PE state is temporarily unavailable 63829310e5eSGavin Shan * 63929310e5eSGavin Shan * Retrieve the state of the specified PE. For IODA-compitable 64029310e5eSGavin Shan * platform, it should be retrieved from IODA table. Therefore, 64129310e5eSGavin Shan * we prefer passing down to hardware implementation to handle 64229310e5eSGavin Shan * it. 64329310e5eSGavin Shan */ 64401f3bfb7SGavin Shan static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 64529310e5eSGavin Shan { 64640ae5f69SGavin Shan int ret; 64729310e5eSGavin Shan 64840ae5f69SGavin Shan if (pe->type & EEH_PE_PHB) 64940ae5f69SGavin Shan ret = pnv_eeh_get_phb_state(pe); 65040ae5f69SGavin Shan else 65140ae5f69SGavin Shan ret = pnv_eeh_get_pe_state(pe); 65240ae5f69SGavin Shan 65340ae5f69SGavin Shan if (!delay) 65440ae5f69SGavin Shan return ret; 65529310e5eSGavin Shan 65629310e5eSGavin Shan /* 65729310e5eSGavin Shan * If the PE state is temporarily unavailable, 65829310e5eSGavin Shan * to inform the EEH core delay for default 65929310e5eSGavin Shan * period (1 second) 66029310e5eSGavin Shan */ 66129310e5eSGavin Shan *delay = 0; 66229310e5eSGavin Shan if (ret & EEH_STATE_UNAVAILABLE) 66329310e5eSGavin Shan *delay = 1000; 66429310e5eSGavin Shan 66529310e5eSGavin Shan return ret; 66629310e5eSGavin Shan } 66729310e5eSGavin Shan 668cadf364dSGavin Shan static s64 pnv_eeh_phb_poll(struct pnv_phb *phb) 669cadf364dSGavin Shan { 670cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 671cadf364dSGavin Shan 672cadf364dSGavin Shan while (1) { 673cadf364dSGavin Shan rc = opal_pci_poll(phb->opal_id); 674cadf364dSGavin Shan if (rc <= 0) 675cadf364dSGavin Shan break; 676cadf364dSGavin Shan 677cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 678cadf364dSGavin Shan udelay(1000 * rc); 679cadf364dSGavin Shan else 680cadf364dSGavin Shan msleep(rc); 681cadf364dSGavin Shan } 682cadf364dSGavin Shan 683cadf364dSGavin Shan return rc; 684cadf364dSGavin Shan } 685cadf364dSGavin Shan 686cadf364dSGavin Shan int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 687cadf364dSGavin Shan { 688cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 689cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 690cadf364dSGavin Shan 691cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 692cadf364dSGavin Shan __func__, hose->global_number, option); 693cadf364dSGavin Shan 694cadf364dSGavin Shan /* Issue PHB complete reset request */ 695cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL || 696cadf364dSGavin Shan option == EEH_RESET_HOT) 697cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 698cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 699cadf364dSGavin Shan OPAL_ASSERT_RESET); 700cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 701cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 702cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 703cadf364dSGavin Shan OPAL_DEASSERT_RESET); 704cadf364dSGavin Shan if (rc < 0) 705cadf364dSGavin Shan goto out; 706cadf364dSGavin Shan 707cadf364dSGavin Shan /* 708cadf364dSGavin Shan * Poll state of the PHB until the request is done 709cadf364dSGavin Shan * successfully. The PHB reset is usually PHB complete 710cadf364dSGavin Shan * reset followed by hot reset on root bus. So we also 711cadf364dSGavin Shan * need the PCI bus settlement delay. 712cadf364dSGavin Shan */ 713cadf364dSGavin Shan rc = pnv_eeh_phb_poll(phb); 714cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) { 715cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 716cadf364dSGavin Shan udelay(1000 * EEH_PE_RST_SETTLE_TIME); 717cadf364dSGavin Shan else 718cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 719cadf364dSGavin Shan } 720cadf364dSGavin Shan out: 721cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 722cadf364dSGavin Shan return -EIO; 723cadf364dSGavin Shan 724cadf364dSGavin Shan return 0; 725cadf364dSGavin Shan } 726cadf364dSGavin Shan 727cadf364dSGavin Shan static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 728cadf364dSGavin Shan { 729cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 730cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 731cadf364dSGavin Shan 732cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 733cadf364dSGavin Shan __func__, hose->global_number, option); 734cadf364dSGavin Shan 735cadf364dSGavin Shan /* 736cadf364dSGavin Shan * During the reset deassert time, we needn't care 737cadf364dSGavin Shan * the reset scope because the firmware does nothing 738cadf364dSGavin Shan * for fundamental or hot reset during deassert phase. 739cadf364dSGavin Shan */ 740cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL) 741cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 742cadf364dSGavin Shan OPAL_RESET_PCI_FUNDAMENTAL, 743cadf364dSGavin Shan OPAL_ASSERT_RESET); 744cadf364dSGavin Shan else if (option == EEH_RESET_HOT) 745cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 746cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 747cadf364dSGavin Shan OPAL_ASSERT_RESET); 748cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 749cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 750cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 751cadf364dSGavin Shan OPAL_DEASSERT_RESET); 752cadf364dSGavin Shan if (rc < 0) 753cadf364dSGavin Shan goto out; 754cadf364dSGavin Shan 755cadf364dSGavin Shan /* Poll state of the PHB until the request is done */ 756cadf364dSGavin Shan rc = pnv_eeh_phb_poll(phb); 757cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) 758cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 759cadf364dSGavin Shan out: 760cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 761cadf364dSGavin Shan return -EIO; 762cadf364dSGavin Shan 763cadf364dSGavin Shan return 0; 764cadf364dSGavin Shan } 765cadf364dSGavin Shan 766cadf364dSGavin Shan static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 767cadf364dSGavin Shan { 768cadf364dSGavin Shan struct device_node *dn = pci_device_to_OF_node(dev); 769cadf364dSGavin Shan struct eeh_dev *edev = of_node_to_eeh_dev(dn); 770cadf364dSGavin Shan int aer = edev ? edev->aer_cap : 0; 771cadf364dSGavin Shan u32 ctrl; 772cadf364dSGavin Shan 773cadf364dSGavin Shan pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 774cadf364dSGavin Shan __func__, pci_domain_nr(dev->bus), 775cadf364dSGavin Shan dev->bus->number, option); 776cadf364dSGavin Shan 777cadf364dSGavin Shan switch (option) { 778cadf364dSGavin Shan case EEH_RESET_FUNDAMENTAL: 779cadf364dSGavin Shan case EEH_RESET_HOT: 780cadf364dSGavin Shan /* Don't report linkDown event */ 781cadf364dSGavin Shan if (aer) { 782cadf364dSGavin Shan eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK, 783cadf364dSGavin Shan 4, &ctrl); 784cadf364dSGavin Shan ctrl |= PCI_ERR_UNC_SURPDN; 785cadf364dSGavin Shan eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK, 786cadf364dSGavin Shan 4, ctrl); 787cadf364dSGavin Shan } 788cadf364dSGavin Shan 789cadf364dSGavin Shan eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl); 790cadf364dSGavin Shan ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 791cadf364dSGavin Shan eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl); 792cadf364dSGavin Shan 793cadf364dSGavin Shan msleep(EEH_PE_RST_HOLD_TIME); 794cadf364dSGavin Shan break; 795cadf364dSGavin Shan case EEH_RESET_DEACTIVATE: 796cadf364dSGavin Shan eeh_ops->read_config(dn, PCI_BRIDGE_CONTROL, 2, &ctrl); 797cadf364dSGavin Shan ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 798cadf364dSGavin Shan eeh_ops->write_config(dn, PCI_BRIDGE_CONTROL, 2, ctrl); 799cadf364dSGavin Shan 800cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 801cadf364dSGavin Shan 802cadf364dSGavin Shan /* Continue reporting linkDown event */ 803cadf364dSGavin Shan if (aer) { 804cadf364dSGavin Shan eeh_ops->read_config(dn, aer + PCI_ERR_UNCOR_MASK, 805cadf364dSGavin Shan 4, &ctrl); 806cadf364dSGavin Shan ctrl &= ~PCI_ERR_UNC_SURPDN; 807cadf364dSGavin Shan eeh_ops->write_config(dn, aer + PCI_ERR_UNCOR_MASK, 808cadf364dSGavin Shan 4, ctrl); 809cadf364dSGavin Shan } 810cadf364dSGavin Shan 811cadf364dSGavin Shan break; 812cadf364dSGavin Shan } 813cadf364dSGavin Shan 814cadf364dSGavin Shan return 0; 815cadf364dSGavin Shan } 816cadf364dSGavin Shan 817cadf364dSGavin Shan void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 818cadf364dSGavin Shan { 819cadf364dSGavin Shan struct pci_controller *hose; 820cadf364dSGavin Shan 821cadf364dSGavin Shan if (pci_is_root_bus(dev->bus)) { 822cadf364dSGavin Shan hose = pci_bus_to_host(dev->bus); 823cadf364dSGavin Shan pnv_eeh_root_reset(hose, EEH_RESET_HOT); 824cadf364dSGavin Shan pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 825cadf364dSGavin Shan } else { 826cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 827cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 828cadf364dSGavin Shan } 829cadf364dSGavin Shan } 830cadf364dSGavin Shan 83129310e5eSGavin Shan /** 83201f3bfb7SGavin Shan * pnv_eeh_reset - Reset the specified PE 83329310e5eSGavin Shan * @pe: EEH PE 83429310e5eSGavin Shan * @option: reset option 83529310e5eSGavin Shan * 836cadf364dSGavin Shan * Do reset on the indicated PE. For PCI bus sensitive PE, 837cadf364dSGavin Shan * we need to reset the parent p2p bridge. The PHB has to 838cadf364dSGavin Shan * be reinitialized if the p2p bridge is root bridge. For 839cadf364dSGavin Shan * PCI device sensitive PE, we will try to reset the device 840cadf364dSGavin Shan * through FLR. For now, we don't have OPAL APIs to do HARD 841cadf364dSGavin Shan * reset yet, so all reset would be SOFT (HOT) reset. 84229310e5eSGavin Shan */ 84301f3bfb7SGavin Shan static int pnv_eeh_reset(struct eeh_pe *pe, int option) 84429310e5eSGavin Shan { 84529310e5eSGavin Shan struct pci_controller *hose = pe->phb; 846cadf364dSGavin Shan struct pci_bus *bus; 847cadf364dSGavin Shan int ret; 84829310e5eSGavin Shan 849cadf364dSGavin Shan /* 850cadf364dSGavin Shan * For PHB reset, we always have complete reset. For those PEs whose 851cadf364dSGavin Shan * primary bus derived from root complex (root bus) or root port 852cadf364dSGavin Shan * (usually bus#1), we apply hot or fundamental reset on the root port. 853cadf364dSGavin Shan * For other PEs, we always have hot reset on the PE primary bus. 854cadf364dSGavin Shan * 855cadf364dSGavin Shan * Here, we have different design to pHyp, which always clear the 856cadf364dSGavin Shan * frozen state during PE reset. However, the good idea here from 857cadf364dSGavin Shan * benh is to keep frozen state before we get PE reset done completely 858cadf364dSGavin Shan * (until BAR restore). With the frozen state, HW drops illegal IO 859cadf364dSGavin Shan * or MMIO access, which can incur recrusive frozen PE during PE 860cadf364dSGavin Shan * reset. The side effect is that EEH core has to clear the frozen 861cadf364dSGavin Shan * state explicitly after BAR restore. 862cadf364dSGavin Shan */ 863cadf364dSGavin Shan if (pe->type & EEH_PE_PHB) { 864cadf364dSGavin Shan ret = pnv_eeh_phb_reset(hose, option); 865cadf364dSGavin Shan } else { 866cadf364dSGavin Shan struct pnv_phb *phb; 867cadf364dSGavin Shan s64 rc; 868cadf364dSGavin Shan 869cadf364dSGavin Shan /* 870cadf364dSGavin Shan * The frozen PE might be caused by PAPR error injection 871cadf364dSGavin Shan * registers, which are expected to be cleared after hitting 872cadf364dSGavin Shan * frozen PE as stated in the hardware spec. Unfortunately, 873cadf364dSGavin Shan * that's not true on P7IOC. So we have to clear it manually 874cadf364dSGavin Shan * to avoid recursive EEH errors during recovery. 875cadf364dSGavin Shan */ 876cadf364dSGavin Shan phb = hose->private_data; 877cadf364dSGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC && 878cadf364dSGavin Shan (option == EEH_RESET_HOT || 879cadf364dSGavin Shan option == EEH_RESET_FUNDAMENTAL)) { 880cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 881cadf364dSGavin Shan OPAL_RESET_PHB_ERROR, 882cadf364dSGavin Shan OPAL_ASSERT_RESET); 883cadf364dSGavin Shan if (rc != OPAL_SUCCESS) { 884cadf364dSGavin Shan pr_warn("%s: Failure %lld clearing " 885cadf364dSGavin Shan "error injection registers\n", 886cadf364dSGavin Shan __func__, rc); 887cadf364dSGavin Shan return -EIO; 888cadf364dSGavin Shan } 889cadf364dSGavin Shan } 890cadf364dSGavin Shan 891cadf364dSGavin Shan bus = eeh_pe_bus_get(pe); 892cadf364dSGavin Shan if (pci_is_root_bus(bus) || 893cadf364dSGavin Shan pci_is_root_bus(bus->parent)) 894cadf364dSGavin Shan ret = pnv_eeh_root_reset(hose, option); 895cadf364dSGavin Shan else 896cadf364dSGavin Shan ret = pnv_eeh_bridge_reset(bus->self, option); 897cadf364dSGavin Shan } 89829310e5eSGavin Shan 89929310e5eSGavin Shan return ret; 90029310e5eSGavin Shan } 90129310e5eSGavin Shan 90229310e5eSGavin Shan /** 90301f3bfb7SGavin Shan * pnv_eeh_wait_state - Wait for PE state 90429310e5eSGavin Shan * @pe: EEH PE 90529310e5eSGavin Shan * @max_wait: maximal period in microsecond 90629310e5eSGavin Shan * 90729310e5eSGavin Shan * Wait for the state of associated PE. It might take some time 90829310e5eSGavin Shan * to retrieve the PE's state. 90929310e5eSGavin Shan */ 91001f3bfb7SGavin Shan static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) 91129310e5eSGavin Shan { 91229310e5eSGavin Shan int ret; 91329310e5eSGavin Shan int mwait; 91429310e5eSGavin Shan 91529310e5eSGavin Shan while (1) { 91601f3bfb7SGavin Shan ret = pnv_eeh_get_state(pe, &mwait); 91729310e5eSGavin Shan 91829310e5eSGavin Shan /* 91929310e5eSGavin Shan * If the PE's state is temporarily unavailable, 92029310e5eSGavin Shan * we have to wait for the specified time. Otherwise, 92129310e5eSGavin Shan * the PE's state will be returned immediately. 92229310e5eSGavin Shan */ 92329310e5eSGavin Shan if (ret != EEH_STATE_UNAVAILABLE) 92429310e5eSGavin Shan return ret; 92529310e5eSGavin Shan 92629310e5eSGavin Shan max_wait -= mwait; 92729310e5eSGavin Shan if (max_wait <= 0) { 9280dae2743SGavin Shan pr_warn("%s: Timeout getting PE#%x's state (%d)\n", 92929310e5eSGavin Shan __func__, pe->addr, max_wait); 93029310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 93129310e5eSGavin Shan } 93229310e5eSGavin Shan 93329310e5eSGavin Shan msleep(mwait); 93429310e5eSGavin Shan } 93529310e5eSGavin Shan 93629310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 93729310e5eSGavin Shan } 93829310e5eSGavin Shan 93929310e5eSGavin Shan /** 94001f3bfb7SGavin Shan * pnv_eeh_get_log - Retrieve error log 94129310e5eSGavin Shan * @pe: EEH PE 94229310e5eSGavin Shan * @severity: temporary or permanent error log 94329310e5eSGavin Shan * @drv_log: driver log to be combined with retrieved error log 94429310e5eSGavin Shan * @len: length of driver log 94529310e5eSGavin Shan * 94629310e5eSGavin Shan * Retrieve the temporary or permanent error from the PE. 94729310e5eSGavin Shan */ 94801f3bfb7SGavin Shan static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 94929310e5eSGavin Shan char *drv_log, unsigned long len) 95029310e5eSGavin Shan { 95195edcdeaSGavin Shan if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 95295edcdeaSGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 95329310e5eSGavin Shan 95495edcdeaSGavin Shan return 0; 95529310e5eSGavin Shan } 95629310e5eSGavin Shan 95729310e5eSGavin Shan /** 95801f3bfb7SGavin Shan * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 95929310e5eSGavin Shan * @pe: EEH PE 96029310e5eSGavin Shan * 96129310e5eSGavin Shan * The function will be called to reconfigure the bridges included 96229310e5eSGavin Shan * in the specified PE so that the mulfunctional PE would be recovered 96329310e5eSGavin Shan * again. 96429310e5eSGavin Shan */ 96501f3bfb7SGavin Shan static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 96629310e5eSGavin Shan { 967bbe170edSGavin Shan return 0; 96829310e5eSGavin Shan } 96929310e5eSGavin Shan 97029310e5eSGavin Shan /** 97101f3bfb7SGavin Shan * pnv_pe_err_inject - Inject specified error to the indicated PE 972131c123aSGavin Shan * @pe: the indicated PE 973131c123aSGavin Shan * @type: error type 974131c123aSGavin Shan * @func: specific error type 975131c123aSGavin Shan * @addr: address 976131c123aSGavin Shan * @mask: address mask 977131c123aSGavin Shan * 978131c123aSGavin Shan * The routine is called to inject specified error, which is 979131c123aSGavin Shan * determined by @type and @func, to the indicated PE for 980131c123aSGavin Shan * testing purpose. 981131c123aSGavin Shan */ 98201f3bfb7SGavin Shan static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 983131c123aSGavin Shan unsigned long addr, unsigned long mask) 984131c123aSGavin Shan { 985131c123aSGavin Shan struct pci_controller *hose = pe->phb; 986131c123aSGavin Shan struct pnv_phb *phb = hose->private_data; 987fa646c3cSGavin Shan s64 rc; 988131c123aSGavin Shan 989fa646c3cSGavin Shan /* Sanity check on error type */ 990fa646c3cSGavin Shan if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 991fa646c3cSGavin Shan type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 992fa646c3cSGavin Shan pr_warn("%s: Invalid error type %d\n", 993fa646c3cSGavin Shan __func__, type); 994fa646c3cSGavin Shan return -ERANGE; 995fa646c3cSGavin Shan } 996131c123aSGavin Shan 997fa646c3cSGavin Shan if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 998fa646c3cSGavin Shan func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 999fa646c3cSGavin Shan pr_warn("%s: Invalid error function %d\n", 1000fa646c3cSGavin Shan __func__, func); 1001fa646c3cSGavin Shan return -ERANGE; 1002fa646c3cSGavin Shan } 1003fa646c3cSGavin Shan 1004fa646c3cSGavin Shan /* Firmware supports error injection ? */ 1005fa646c3cSGavin Shan if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1006fa646c3cSGavin Shan pr_warn("%s: Firmware doesn't support error injection\n", 1007fa646c3cSGavin Shan __func__); 1008fa646c3cSGavin Shan return -ENXIO; 1009fa646c3cSGavin Shan } 1010fa646c3cSGavin Shan 1011fa646c3cSGavin Shan /* Do error injection */ 1012fa646c3cSGavin Shan rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1013fa646c3cSGavin Shan type, func, addr, mask); 1014fa646c3cSGavin Shan if (rc != OPAL_SUCCESS) { 1015fa646c3cSGavin Shan pr_warn("%s: Failure %lld injecting error " 1016fa646c3cSGavin Shan "%d-%d to PHB#%x-PE#%x\n", 1017fa646c3cSGavin Shan __func__, rc, type, func, 1018fa646c3cSGavin Shan hose->global_number, pe->addr); 1019fa646c3cSGavin Shan return -EIO; 1020fa646c3cSGavin Shan } 1021fa646c3cSGavin Shan 1022fa646c3cSGavin Shan return 0; 1023131c123aSGavin Shan } 1024131c123aSGavin Shan 102501f3bfb7SGavin Shan static inline bool pnv_eeh_cfg_blocked(struct device_node *dn) 1026d2cfbcd7SGavin Shan { 1027d2cfbcd7SGavin Shan struct eeh_dev *edev = of_node_to_eeh_dev(dn); 1028d2cfbcd7SGavin Shan 1029d2cfbcd7SGavin Shan if (!edev || !edev->pe) 1030d2cfbcd7SGavin Shan return false; 1031d2cfbcd7SGavin Shan 1032d2cfbcd7SGavin Shan if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1033d2cfbcd7SGavin Shan return true; 1034d2cfbcd7SGavin Shan 1035d2cfbcd7SGavin Shan return false; 1036d2cfbcd7SGavin Shan } 1037d2cfbcd7SGavin Shan 103801f3bfb7SGavin Shan static int pnv_eeh_read_config(struct device_node *dn, 1039d2cfbcd7SGavin Shan int where, int size, u32 *val) 1040d2cfbcd7SGavin Shan { 10413532a741SGavin Shan struct pci_dn *pdn = PCI_DN(dn); 10423532a741SGavin Shan 10433532a741SGavin Shan if (!pdn) 10443532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 10453532a741SGavin Shan 104601f3bfb7SGavin Shan if (pnv_eeh_cfg_blocked(dn)) { 1047d2cfbcd7SGavin Shan *val = 0xFFFFFFFF; 1048d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1049d2cfbcd7SGavin Shan } 1050d2cfbcd7SGavin Shan 10513532a741SGavin Shan return pnv_pci_cfg_read(pdn, where, size, val); 1052d2cfbcd7SGavin Shan } 1053d2cfbcd7SGavin Shan 105401f3bfb7SGavin Shan static int pnv_eeh_write_config(struct device_node *dn, 1055d2cfbcd7SGavin Shan int where, int size, u32 val) 1056d2cfbcd7SGavin Shan { 10573532a741SGavin Shan struct pci_dn *pdn = PCI_DN(dn); 10583532a741SGavin Shan 10593532a741SGavin Shan if (!pdn) 10603532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 10613532a741SGavin Shan 106201f3bfb7SGavin Shan if (pnv_eeh_cfg_blocked(dn)) 1063d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1064d2cfbcd7SGavin Shan 10653532a741SGavin Shan return pnv_pci_cfg_write(pdn, where, size, val); 1066d2cfbcd7SGavin Shan } 1067d2cfbcd7SGavin Shan 10682a485ad7SGavin Shan static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 10692a485ad7SGavin Shan { 10702a485ad7SGavin Shan /* GEM */ 10712a485ad7SGavin Shan if (data->gemXfir || data->gemRfir || 10722a485ad7SGavin Shan data->gemRirqfir || data->gemMask || data->gemRwof) 10732a485ad7SGavin Shan pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 10742a485ad7SGavin Shan be64_to_cpu(data->gemXfir), 10752a485ad7SGavin Shan be64_to_cpu(data->gemRfir), 10762a485ad7SGavin Shan be64_to_cpu(data->gemRirqfir), 10772a485ad7SGavin Shan be64_to_cpu(data->gemMask), 10782a485ad7SGavin Shan be64_to_cpu(data->gemRwof)); 10792a485ad7SGavin Shan 10802a485ad7SGavin Shan /* LEM */ 10812a485ad7SGavin Shan if (data->lemFir || data->lemErrMask || 10822a485ad7SGavin Shan data->lemAction0 || data->lemAction1 || data->lemWof) 10832a485ad7SGavin Shan pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 10842a485ad7SGavin Shan be64_to_cpu(data->lemFir), 10852a485ad7SGavin Shan be64_to_cpu(data->lemErrMask), 10862a485ad7SGavin Shan be64_to_cpu(data->lemAction0), 10872a485ad7SGavin Shan be64_to_cpu(data->lemAction1), 10882a485ad7SGavin Shan be64_to_cpu(data->lemWof)); 10892a485ad7SGavin Shan } 10902a485ad7SGavin Shan 10912a485ad7SGavin Shan static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 10922a485ad7SGavin Shan { 10932a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 10942a485ad7SGavin Shan struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag; 10952a485ad7SGavin Shan long rc; 10962a485ad7SGavin Shan 10972a485ad7SGavin Shan rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 10982a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 10992a485ad7SGavin Shan pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 11002a485ad7SGavin Shan __func__, phb->hub_id, rc); 11012a485ad7SGavin Shan return; 11022a485ad7SGavin Shan } 11032a485ad7SGavin Shan 11042a485ad7SGavin Shan switch (data->type) { 11052a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_RGC: 11062a485ad7SGavin Shan pr_info("P7IOC diag-data for RGC\n\n"); 11072a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 11082a485ad7SGavin Shan if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 11092a485ad7SGavin Shan pr_info(" RGC: %016llx %016llx\n", 11102a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcStatus), 11112a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcLdcp)); 11122a485ad7SGavin Shan break; 11132a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_BI: 11142a485ad7SGavin Shan pr_info("P7IOC diag-data for BI %s\n\n", 11152a485ad7SGavin Shan data->bi.biDownbound ? "Downbound" : "Upbound"); 11162a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 11172a485ad7SGavin Shan if (data->bi.biLdcp0 || data->bi.biLdcp1 || 11182a485ad7SGavin Shan data->bi.biLdcp2 || data->bi.biFenceStatus) 11192a485ad7SGavin Shan pr_info(" BI: %016llx %016llx %016llx %016llx\n", 11202a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp0), 11212a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp1), 11222a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp2), 11232a485ad7SGavin Shan be64_to_cpu(data->bi.biFenceStatus)); 11242a485ad7SGavin Shan break; 11252a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_CI: 11262a485ad7SGavin Shan pr_info("P7IOC diag-data for CI Port %d\n\n", 11272a485ad7SGavin Shan data->ci.ciPort); 11282a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 11292a485ad7SGavin Shan if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 11302a485ad7SGavin Shan pr_info(" CI: %016llx %016llx\n", 11312a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortStatus), 11322a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortLdcp)); 11332a485ad7SGavin Shan break; 11342a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_MISC: 11352a485ad7SGavin Shan pr_info("P7IOC diag-data for MISC\n\n"); 11362a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 11372a485ad7SGavin Shan break; 11382a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_I2C: 11392a485ad7SGavin Shan pr_info("P7IOC diag-data for I2C\n\n"); 11402a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 11412a485ad7SGavin Shan break; 11422a485ad7SGavin Shan default: 11432a485ad7SGavin Shan pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 11442a485ad7SGavin Shan __func__, phb->hub_id, data->type); 11452a485ad7SGavin Shan } 11462a485ad7SGavin Shan } 11472a485ad7SGavin Shan 11482a485ad7SGavin Shan static int pnv_eeh_get_pe(struct pci_controller *hose, 11492a485ad7SGavin Shan u16 pe_no, struct eeh_pe **pe) 11502a485ad7SGavin Shan { 11512a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 11522a485ad7SGavin Shan struct pnv_ioda_pe *pnv_pe; 11532a485ad7SGavin Shan struct eeh_pe *dev_pe; 11542a485ad7SGavin Shan struct eeh_dev edev; 11552a485ad7SGavin Shan 11562a485ad7SGavin Shan /* 11572a485ad7SGavin Shan * If PHB supports compound PE, to fetch 11582a485ad7SGavin Shan * the master PE because slave PE is invisible 11592a485ad7SGavin Shan * to EEH core. 11602a485ad7SGavin Shan */ 11612a485ad7SGavin Shan pnv_pe = &phb->ioda.pe_array[pe_no]; 11622a485ad7SGavin Shan if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 11632a485ad7SGavin Shan pnv_pe = pnv_pe->master; 11642a485ad7SGavin Shan WARN_ON(!pnv_pe || 11652a485ad7SGavin Shan !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 11662a485ad7SGavin Shan pe_no = pnv_pe->pe_number; 11672a485ad7SGavin Shan } 11682a485ad7SGavin Shan 11692a485ad7SGavin Shan /* Find the PE according to PE# */ 11702a485ad7SGavin Shan memset(&edev, 0, sizeof(struct eeh_dev)); 11712a485ad7SGavin Shan edev.phb = hose; 11722a485ad7SGavin Shan edev.pe_config_addr = pe_no; 11732a485ad7SGavin Shan dev_pe = eeh_pe_get(&edev); 11742a485ad7SGavin Shan if (!dev_pe) 11752a485ad7SGavin Shan return -EEXIST; 11762a485ad7SGavin Shan 11772a485ad7SGavin Shan /* Freeze the (compound) PE */ 11782a485ad7SGavin Shan *pe = dev_pe; 11792a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 11802a485ad7SGavin Shan phb->freeze_pe(phb, pe_no); 11812a485ad7SGavin Shan 11822a485ad7SGavin Shan /* 11832a485ad7SGavin Shan * At this point, we're sure the (compound) PE should 11842a485ad7SGavin Shan * have been frozen. However, we still need poke until 11852a485ad7SGavin Shan * hitting the frozen PE on top level. 11862a485ad7SGavin Shan */ 11872a485ad7SGavin Shan dev_pe = dev_pe->parent; 11882a485ad7SGavin Shan while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 11892a485ad7SGavin Shan int ret; 11902a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | 11912a485ad7SGavin Shan EEH_STATE_DMA_ACTIVE); 11922a485ad7SGavin Shan 11932a485ad7SGavin Shan ret = eeh_ops->get_state(dev_pe, NULL); 11942a485ad7SGavin Shan if (ret <= 0 || (ret & active_flags) == active_flags) { 11952a485ad7SGavin Shan dev_pe = dev_pe->parent; 11962a485ad7SGavin Shan continue; 11972a485ad7SGavin Shan } 11982a485ad7SGavin Shan 11992a485ad7SGavin Shan /* Frozen parent PE */ 12002a485ad7SGavin Shan *pe = dev_pe; 12012a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 12022a485ad7SGavin Shan phb->freeze_pe(phb, dev_pe->addr); 12032a485ad7SGavin Shan 12042a485ad7SGavin Shan /* Next one */ 12052a485ad7SGavin Shan dev_pe = dev_pe->parent; 12062a485ad7SGavin Shan } 12072a485ad7SGavin Shan 12082a485ad7SGavin Shan return 0; 12092a485ad7SGavin Shan } 12102a485ad7SGavin Shan 1211131c123aSGavin Shan /** 121201f3bfb7SGavin Shan * pnv_eeh_next_error - Retrieve next EEH error to handle 121329310e5eSGavin Shan * @pe: Affected PE 121429310e5eSGavin Shan * 12152a485ad7SGavin Shan * The function is expected to be called by EEH core while it gets 12162a485ad7SGavin Shan * special EEH event (without binding PE). The function calls to 12172a485ad7SGavin Shan * OPAL APIs for next error to handle. The informational error is 12182a485ad7SGavin Shan * handled internally by platform. However, the dead IOC, dead PHB, 12192a485ad7SGavin Shan * fenced PHB and frozen PE should be handled by EEH core eventually. 122029310e5eSGavin Shan */ 122101f3bfb7SGavin Shan static int pnv_eeh_next_error(struct eeh_pe **pe) 122229310e5eSGavin Shan { 122329310e5eSGavin Shan struct pci_controller *hose; 12242a485ad7SGavin Shan struct pnv_phb *phb; 12252a485ad7SGavin Shan struct eeh_pe *phb_pe, *parent_pe; 12262a485ad7SGavin Shan __be64 frozen_pe_no; 12272a485ad7SGavin Shan __be16 err_type, severity; 12282a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 12292a485ad7SGavin Shan long rc; 12302a485ad7SGavin Shan int state, ret = EEH_NEXT_ERR_NONE; 12312a485ad7SGavin Shan 12322a485ad7SGavin Shan /* 12332a485ad7SGavin Shan * While running here, it's safe to purge the event queue. 12342a485ad7SGavin Shan * And we should keep the cached OPAL notifier event sychronized 12352a485ad7SGavin Shan * between the kernel and firmware. 12362a485ad7SGavin Shan */ 12372a485ad7SGavin Shan eeh_remove_event(NULL, false); 12382a485ad7SGavin Shan opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul); 123929310e5eSGavin Shan 124029310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 12412a485ad7SGavin Shan /* 12422a485ad7SGavin Shan * If the subordinate PCI buses of the PHB has been 12432a485ad7SGavin Shan * removed or is exactly under error recovery, we 12442a485ad7SGavin Shan * needn't take care of it any more. 12452a485ad7SGavin Shan */ 124629310e5eSGavin Shan phb = hose->private_data; 12472a485ad7SGavin Shan phb_pe = eeh_phb_pe_get(hose); 12482a485ad7SGavin Shan if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 12492a485ad7SGavin Shan continue; 12502a485ad7SGavin Shan 12512a485ad7SGavin Shan rc = opal_pci_next_error(phb->opal_id, 12522a485ad7SGavin Shan &frozen_pe_no, &err_type, &severity); 12532a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 12542a485ad7SGavin Shan pr_devel("%s: Invalid return value on " 12552a485ad7SGavin Shan "PHB#%x (0x%lx) from opal_pci_next_error", 12562a485ad7SGavin Shan __func__, hose->global_number, rc); 12572a485ad7SGavin Shan continue; 12582a485ad7SGavin Shan } 12592a485ad7SGavin Shan 12602a485ad7SGavin Shan /* If the PHB doesn't have error, stop processing */ 12612a485ad7SGavin Shan if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 12622a485ad7SGavin Shan be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 12632a485ad7SGavin Shan pr_devel("%s: No error found on PHB#%x\n", 12642a485ad7SGavin Shan __func__, hose->global_number); 12652a485ad7SGavin Shan continue; 12662a485ad7SGavin Shan } 12672a485ad7SGavin Shan 12682a485ad7SGavin Shan /* 12692a485ad7SGavin Shan * Processing the error. We're expecting the error with 12702a485ad7SGavin Shan * highest priority reported upon multiple errors on the 12712a485ad7SGavin Shan * specific PHB. 12722a485ad7SGavin Shan */ 12732a485ad7SGavin Shan pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 12742a485ad7SGavin Shan __func__, be16_to_cpu(err_type), 12752a485ad7SGavin Shan be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 12762a485ad7SGavin Shan hose->global_number); 12772a485ad7SGavin Shan switch (be16_to_cpu(err_type)) { 12782a485ad7SGavin Shan case OPAL_EEH_IOC_ERROR: 12792a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 12802a485ad7SGavin Shan pr_err("EEH: dead IOC detected\n"); 12812a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_IOC; 12822a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 12832a485ad7SGavin Shan pr_info("EEH: IOC informative error " 12842a485ad7SGavin Shan "detected\n"); 12852a485ad7SGavin Shan pnv_eeh_get_and_dump_hub_diag(hose); 12862a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 12872a485ad7SGavin Shan } 12882a485ad7SGavin Shan 12892a485ad7SGavin Shan break; 12902a485ad7SGavin Shan case OPAL_EEH_PHB_ERROR: 12912a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 12922a485ad7SGavin Shan *pe = phb_pe; 12932a485ad7SGavin Shan pr_err("EEH: dead PHB#%x detected, " 12942a485ad7SGavin Shan "location: %s\n", 12952a485ad7SGavin Shan hose->global_number, 12962a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 12972a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_PHB; 12982a485ad7SGavin Shan } else if (be16_to_cpu(severity) == 12992a485ad7SGavin Shan OPAL_EEH_SEV_PHB_FENCED) { 13002a485ad7SGavin Shan *pe = phb_pe; 13012a485ad7SGavin Shan pr_err("EEH: Fenced PHB#%x detected, " 13022a485ad7SGavin Shan "location: %s\n", 13032a485ad7SGavin Shan hose->global_number, 13042a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 13052a485ad7SGavin Shan ret = EEH_NEXT_ERR_FENCED_PHB; 13062a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 13072a485ad7SGavin Shan pr_info("EEH: PHB#%x informative error " 13082a485ad7SGavin Shan "detected, location: %s\n", 13092a485ad7SGavin Shan hose->global_number, 13102a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 13112a485ad7SGavin Shan pnv_eeh_get_phb_diag(phb_pe); 13122a485ad7SGavin Shan pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 13132a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 13142a485ad7SGavin Shan } 13152a485ad7SGavin Shan 13162a485ad7SGavin Shan break; 13172a485ad7SGavin Shan case OPAL_EEH_PE_ERROR: 13182a485ad7SGavin Shan /* 13192a485ad7SGavin Shan * If we can't find the corresponding PE, we 13202a485ad7SGavin Shan * just try to unfreeze. 13212a485ad7SGavin Shan */ 13222a485ad7SGavin Shan if (pnv_eeh_get_pe(hose, 13232a485ad7SGavin Shan be64_to_cpu(frozen_pe_no), pe)) { 13242a485ad7SGavin Shan /* Try best to clear it */ 13252a485ad7SGavin Shan pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 13262a485ad7SGavin Shan hose->global_number, frozen_pe_no); 13272a485ad7SGavin Shan pr_info("EEH: PHB location: %s\n", 13282a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 13292a485ad7SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 13302a485ad7SGavin Shan frozen_pe_no, 13312a485ad7SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 13322a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 13332a485ad7SGavin Shan } else if ((*pe)->state & EEH_PE_ISOLATED || 13342a485ad7SGavin Shan eeh_pe_passed(*pe)) { 13352a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 13362a485ad7SGavin Shan } else { 13372a485ad7SGavin Shan pr_err("EEH: Frozen PE#%x " 13382a485ad7SGavin Shan "on PHB#%x detected\n", 13392a485ad7SGavin Shan (*pe)->addr, 13402a485ad7SGavin Shan (*pe)->phb->global_number); 13412a485ad7SGavin Shan pr_err("EEH: PE location: %s, " 13422a485ad7SGavin Shan "PHB location: %s\n", 13432a485ad7SGavin Shan eeh_pe_loc_get(*pe), 13442a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 13452a485ad7SGavin Shan ret = EEH_NEXT_ERR_FROZEN_PE; 13462a485ad7SGavin Shan } 13472a485ad7SGavin Shan 13482a485ad7SGavin Shan break; 13492a485ad7SGavin Shan default: 13502a485ad7SGavin Shan pr_warn("%s: Unexpected error type %d\n", 13512a485ad7SGavin Shan __func__, be16_to_cpu(err_type)); 13522a485ad7SGavin Shan } 13532a485ad7SGavin Shan 13542a485ad7SGavin Shan /* 13552a485ad7SGavin Shan * EEH core will try recover from fenced PHB or 13562a485ad7SGavin Shan * frozen PE. In the time for frozen PE, EEH core 13572a485ad7SGavin Shan * enable IO path for that before collecting logs, 13582a485ad7SGavin Shan * but it ruins the site. So we have to dump the 13592a485ad7SGavin Shan * log in advance here. 13602a485ad7SGavin Shan */ 13612a485ad7SGavin Shan if ((ret == EEH_NEXT_ERR_FROZEN_PE || 13622a485ad7SGavin Shan ret == EEH_NEXT_ERR_FENCED_PHB) && 13632a485ad7SGavin Shan !((*pe)->state & EEH_PE_ISOLATED)) { 13642a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 13652a485ad7SGavin Shan pnv_eeh_get_phb_diag(*pe); 13662a485ad7SGavin Shan 13672a485ad7SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 13682a485ad7SGavin Shan pnv_pci_dump_phb_diag_data((*pe)->phb, 13692a485ad7SGavin Shan (*pe)->data); 13702a485ad7SGavin Shan } 13712a485ad7SGavin Shan 13722a485ad7SGavin Shan /* 13732a485ad7SGavin Shan * We probably have the frozen parent PE out there and 13742a485ad7SGavin Shan * we need have to handle frozen parent PE firstly. 13752a485ad7SGavin Shan */ 13762a485ad7SGavin Shan if (ret == EEH_NEXT_ERR_FROZEN_PE) { 13772a485ad7SGavin Shan parent_pe = (*pe)->parent; 13782a485ad7SGavin Shan while (parent_pe) { 13792a485ad7SGavin Shan /* Hit the ceiling ? */ 13802a485ad7SGavin Shan if (parent_pe->type & EEH_PE_PHB) 13812a485ad7SGavin Shan break; 13822a485ad7SGavin Shan 13832a485ad7SGavin Shan /* Frozen parent PE ? */ 13842a485ad7SGavin Shan state = eeh_ops->get_state(parent_pe, NULL); 13852a485ad7SGavin Shan if (state > 0 && 13862a485ad7SGavin Shan (state & active_flags) != active_flags) 13872a485ad7SGavin Shan *pe = parent_pe; 13882a485ad7SGavin Shan 13892a485ad7SGavin Shan /* Next parent level */ 13902a485ad7SGavin Shan parent_pe = parent_pe->parent; 13912a485ad7SGavin Shan } 13922a485ad7SGavin Shan 13932a485ad7SGavin Shan /* We possibly migrate to another PE */ 13942a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 13952a485ad7SGavin Shan } 13962a485ad7SGavin Shan 13972a485ad7SGavin Shan /* 13982a485ad7SGavin Shan * If we have no errors on the specific PHB or only 13992a485ad7SGavin Shan * informative error there, we continue poking it. 14002a485ad7SGavin Shan * Otherwise, we need actions to be taken by upper 14012a485ad7SGavin Shan * layer. 14022a485ad7SGavin Shan */ 14032a485ad7SGavin Shan if (ret > EEH_NEXT_ERR_INF) 140429310e5eSGavin Shan break; 140529310e5eSGavin Shan } 140629310e5eSGavin Shan 14072a485ad7SGavin Shan return ret; 140829310e5eSGavin Shan } 140929310e5eSGavin Shan 141001f3bfb7SGavin Shan static int pnv_eeh_restore_config(struct device_node *dn) 14119be3beccSGavin Shan { 14129be3beccSGavin Shan struct eeh_dev *edev = of_node_to_eeh_dev(dn); 14139be3beccSGavin Shan struct pnv_phb *phb; 14149be3beccSGavin Shan s64 ret; 14159be3beccSGavin Shan 14169be3beccSGavin Shan if (!edev) 14179be3beccSGavin Shan return -EEXIST; 14189be3beccSGavin Shan 14199be3beccSGavin Shan phb = edev->phb->private_data; 14209be3beccSGavin Shan ret = opal_pci_reinit(phb->opal_id, 14219be3beccSGavin Shan OPAL_REINIT_PCI_DEV, edev->config_addr); 14229be3beccSGavin Shan if (ret) { 14239be3beccSGavin Shan pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 14249be3beccSGavin Shan __func__, edev->config_addr, ret); 14259be3beccSGavin Shan return -EIO; 14269be3beccSGavin Shan } 14279be3beccSGavin Shan 14289be3beccSGavin Shan return 0; 14299be3beccSGavin Shan } 14309be3beccSGavin Shan 143101f3bfb7SGavin Shan static struct eeh_ops pnv_eeh_ops = { 143229310e5eSGavin Shan .name = "powernv", 143301f3bfb7SGavin Shan .init = pnv_eeh_init, 143401f3bfb7SGavin Shan .post_init = pnv_eeh_post_init, 143529310e5eSGavin Shan .of_probe = NULL, 143601f3bfb7SGavin Shan .dev_probe = pnv_eeh_dev_probe, 143701f3bfb7SGavin Shan .set_option = pnv_eeh_set_option, 143801f3bfb7SGavin Shan .get_pe_addr = pnv_eeh_get_pe_addr, 143901f3bfb7SGavin Shan .get_state = pnv_eeh_get_state, 144001f3bfb7SGavin Shan .reset = pnv_eeh_reset, 144101f3bfb7SGavin Shan .wait_state = pnv_eeh_wait_state, 144201f3bfb7SGavin Shan .get_log = pnv_eeh_get_log, 144301f3bfb7SGavin Shan .configure_bridge = pnv_eeh_configure_bridge, 144401f3bfb7SGavin Shan .err_inject = pnv_eeh_err_inject, 144501f3bfb7SGavin Shan .read_config = pnv_eeh_read_config, 144601f3bfb7SGavin Shan .write_config = pnv_eeh_write_config, 144701f3bfb7SGavin Shan .next_error = pnv_eeh_next_error, 144801f3bfb7SGavin Shan .restore_config = pnv_eeh_restore_config 144929310e5eSGavin Shan }; 145029310e5eSGavin Shan 145129310e5eSGavin Shan /** 145229310e5eSGavin Shan * eeh_powernv_init - Register platform dependent EEH operations 145329310e5eSGavin Shan * 145429310e5eSGavin Shan * EEH initialization on powernv platform. This function should be 145529310e5eSGavin Shan * called before any EEH related functions. 145629310e5eSGavin Shan */ 145729310e5eSGavin Shan static int __init eeh_powernv_init(void) 145829310e5eSGavin Shan { 145929310e5eSGavin Shan int ret = -EINVAL; 146029310e5eSGavin Shan 1461bb593c00SGavin Shan eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE); 146201f3bfb7SGavin Shan ret = eeh_ops_register(&pnv_eeh_ops); 146329310e5eSGavin Shan if (!ret) 146429310e5eSGavin Shan pr_info("EEH: PowerNV platform initialized\n"); 146529310e5eSGavin Shan else 146629310e5eSGavin Shan pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 146729310e5eSGavin Shan 146829310e5eSGavin Shan return ret; 146929310e5eSGavin Shan } 1470b14726c5SMichael Ellerman machine_early_initcall(powernv, eeh_powernv_init); 1471