129310e5eSGavin Shan /* 229310e5eSGavin Shan * The file intends to implement the platform dependent EEH operations on 329310e5eSGavin Shan * powernv platform. Actually, the powernv was created in order to fully 429310e5eSGavin Shan * hypervisor support. 529310e5eSGavin Shan * 629310e5eSGavin Shan * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 729310e5eSGavin Shan * 829310e5eSGavin Shan * This program is free software; you can redistribute it and/or modify 929310e5eSGavin Shan * it under the terms of the GNU General Public License as published by 1029310e5eSGavin Shan * the Free Software Foundation; either version 2 of the License, or 1129310e5eSGavin Shan * (at your option) any later version. 1229310e5eSGavin Shan */ 1329310e5eSGavin Shan 1429310e5eSGavin Shan #include <linux/atomic.h> 154cf17445SGavin Shan #include <linux/debugfs.h> 1629310e5eSGavin Shan #include <linux/delay.h> 1729310e5eSGavin Shan #include <linux/export.h> 1829310e5eSGavin Shan #include <linux/init.h> 1979231448SAlistair Popple #include <linux/interrupt.h> 2029310e5eSGavin Shan #include <linux/list.h> 2129310e5eSGavin Shan #include <linux/msi.h> 2229310e5eSGavin Shan #include <linux/of.h> 2329310e5eSGavin Shan #include <linux/pci.h> 2429310e5eSGavin Shan #include <linux/proc_fs.h> 2529310e5eSGavin Shan #include <linux/rbtree.h> 2629310e5eSGavin Shan #include <linux/sched.h> 2729310e5eSGavin Shan #include <linux/seq_file.h> 2829310e5eSGavin Shan #include <linux/spinlock.h> 2929310e5eSGavin Shan 3029310e5eSGavin Shan #include <asm/eeh.h> 3129310e5eSGavin Shan #include <asm/eeh_event.h> 3229310e5eSGavin Shan #include <asm/firmware.h> 3329310e5eSGavin Shan #include <asm/io.h> 3429310e5eSGavin Shan #include <asm/iommu.h> 3529310e5eSGavin Shan #include <asm/machdep.h> 3629310e5eSGavin Shan #include <asm/msi_bitmap.h> 3729310e5eSGavin Shan #include <asm/opal.h> 3829310e5eSGavin Shan #include <asm/ppc-pci.h> 3929310e5eSGavin Shan 4029310e5eSGavin Shan #include "powernv.h" 4129310e5eSGavin Shan #include "pci.h" 4229310e5eSGavin Shan 434cf17445SGavin Shan static bool pnv_eeh_nb_init = false; 4479231448SAlistair Popple static int eeh_event_irq = -EINVAL; 454cf17445SGavin Shan 4601f3bfb7SGavin Shan static int pnv_eeh_init(void) 4729310e5eSGavin Shan { 48dc561fb9SGavin Shan struct pci_controller *hose; 49dc561fb9SGavin Shan struct pnv_phb *phb; 50dc561fb9SGavin Shan 5129310e5eSGavin Shan if (!firmware_has_feature(FW_FEATURE_OPALv3)) { 520dae2743SGavin Shan pr_warn("%s: OPALv3 is required !\n", 530dae2743SGavin Shan __func__); 5429310e5eSGavin Shan return -EINVAL; 5529310e5eSGavin Shan } 5629310e5eSGavin Shan 5705b1721dSGavin Shan /* Set probe mode */ 5805b1721dSGavin Shan eeh_add_flag(EEH_PROBE_MODE_DEV); 5929310e5eSGavin Shan 60dc561fb9SGavin Shan /* 61dc561fb9SGavin Shan * P7IOC blocks PCI config access to frozen PE, but PHB3 62dc561fb9SGavin Shan * doesn't do that. So we have to selectively enable I/O 63dc561fb9SGavin Shan * prior to collecting error log. 64dc561fb9SGavin Shan */ 65dc561fb9SGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 66dc561fb9SGavin Shan phb = hose->private_data; 67dc561fb9SGavin Shan 68dc561fb9SGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC) 69dc561fb9SGavin Shan eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 702aa5cf9eSGavin Shan 712aa5cf9eSGavin Shan /* 722aa5cf9eSGavin Shan * PE#0 should be regarded as valid by EEH core 732aa5cf9eSGavin Shan * if it's not the reserved one. Currently, we 74608fb9c2SGavin Shan * have the reserved PE#255 and PE#127 for PHB3 752aa5cf9eSGavin Shan * and P7IOC separately. So we should regard 76608fb9c2SGavin Shan * PE#0 as valid for PHB3 and P7IOC. 772aa5cf9eSGavin Shan */ 782aa5cf9eSGavin Shan if (phb->ioda.reserved_pe != 0) 792aa5cf9eSGavin Shan eeh_add_flag(EEH_VALID_PE_ZERO); 802aa5cf9eSGavin Shan 81dc561fb9SGavin Shan break; 82dc561fb9SGavin Shan } 83dc561fb9SGavin Shan 8429310e5eSGavin Shan return 0; 8529310e5eSGavin Shan } 8629310e5eSGavin Shan 8779231448SAlistair Popple static irqreturn_t pnv_eeh_event(int irq, void *data) 884cf17445SGavin Shan { 894cf17445SGavin Shan /* 9079231448SAlistair Popple * We simply send a special EEH event if EEH has been 9179231448SAlistair Popple * enabled. We don't care about EEH events until we've 9279231448SAlistair Popple * finished processing the outstanding ones. Event processing 9379231448SAlistair Popple * gets unmasked in next_error() if EEH is enabled. 944cf17445SGavin Shan */ 9579231448SAlistair Popple disable_irq_nosync(irq); 964cf17445SGavin Shan 974cf17445SGavin Shan if (eeh_enabled()) 984cf17445SGavin Shan eeh_send_failure_event(NULL); 994cf17445SGavin Shan 10079231448SAlistair Popple return IRQ_HANDLED; 1014cf17445SGavin Shan } 1024cf17445SGavin Shan 1034cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 1044cf17445SGavin Shan static ssize_t pnv_eeh_ei_write(struct file *filp, 1054cf17445SGavin Shan const char __user *user_buf, 1064cf17445SGavin Shan size_t count, loff_t *ppos) 1074cf17445SGavin Shan { 1084cf17445SGavin Shan struct pci_controller *hose = filp->private_data; 1094cf17445SGavin Shan struct eeh_dev *edev; 1104cf17445SGavin Shan struct eeh_pe *pe; 1114cf17445SGavin Shan int pe_no, type, func; 1124cf17445SGavin Shan unsigned long addr, mask; 1134cf17445SGavin Shan char buf[50]; 1144cf17445SGavin Shan int ret; 1154cf17445SGavin Shan 1164cf17445SGavin Shan if (!eeh_ops || !eeh_ops->err_inject) 1174cf17445SGavin Shan return -ENXIO; 1184cf17445SGavin Shan 1194cf17445SGavin Shan /* Copy over argument buffer */ 1204cf17445SGavin Shan ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 1214cf17445SGavin Shan if (!ret) 1224cf17445SGavin Shan return -EFAULT; 1234cf17445SGavin Shan 1244cf17445SGavin Shan /* Retrieve parameters */ 1254cf17445SGavin Shan ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 1264cf17445SGavin Shan &pe_no, &type, &func, &addr, &mask); 1274cf17445SGavin Shan if (ret != 5) 1284cf17445SGavin Shan return -EINVAL; 1294cf17445SGavin Shan 1304cf17445SGavin Shan /* Retrieve PE */ 1314cf17445SGavin Shan edev = kzalloc(sizeof(*edev), GFP_KERNEL); 1324cf17445SGavin Shan if (!edev) 1334cf17445SGavin Shan return -ENOMEM; 1344cf17445SGavin Shan edev->phb = hose; 1354cf17445SGavin Shan edev->pe_config_addr = pe_no; 1364cf17445SGavin Shan pe = eeh_pe_get(edev); 1374cf17445SGavin Shan kfree(edev); 1384cf17445SGavin Shan if (!pe) 1394cf17445SGavin Shan return -ENODEV; 1404cf17445SGavin Shan 1414cf17445SGavin Shan /* Do error injection */ 1424cf17445SGavin Shan ret = eeh_ops->err_inject(pe, type, func, addr, mask); 1434cf17445SGavin Shan return ret < 0 ? ret : count; 1444cf17445SGavin Shan } 1454cf17445SGavin Shan 1464cf17445SGavin Shan static const struct file_operations pnv_eeh_ei_fops = { 1474cf17445SGavin Shan .open = simple_open, 1484cf17445SGavin Shan .llseek = no_llseek, 1494cf17445SGavin Shan .write = pnv_eeh_ei_write, 1504cf17445SGavin Shan }; 1514cf17445SGavin Shan 1524cf17445SGavin Shan static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 1534cf17445SGavin Shan { 1544cf17445SGavin Shan struct pci_controller *hose = data; 1554cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1564cf17445SGavin Shan 1574cf17445SGavin Shan out_be64(phb->regs + offset, val); 1584cf17445SGavin Shan return 0; 1594cf17445SGavin Shan } 1604cf17445SGavin Shan 1614cf17445SGavin Shan static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 1624cf17445SGavin Shan { 1634cf17445SGavin Shan struct pci_controller *hose = data; 1644cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1654cf17445SGavin Shan 1664cf17445SGavin Shan *val = in_be64(phb->regs + offset); 1674cf17445SGavin Shan return 0; 1684cf17445SGavin Shan } 1694cf17445SGavin Shan 1704cf17445SGavin Shan static int pnv_eeh_outb_dbgfs_set(void *data, u64 val) 1714cf17445SGavin Shan { 1724cf17445SGavin Shan return pnv_eeh_dbgfs_set(data, 0xD10, val); 1734cf17445SGavin Shan } 1744cf17445SGavin Shan 1754cf17445SGavin Shan static int pnv_eeh_outb_dbgfs_get(void *data, u64 *val) 1764cf17445SGavin Shan { 1774cf17445SGavin Shan return pnv_eeh_dbgfs_get(data, 0xD10, val); 1784cf17445SGavin Shan } 1794cf17445SGavin Shan 1804cf17445SGavin Shan static int pnv_eeh_inbA_dbgfs_set(void *data, u64 val) 1814cf17445SGavin Shan { 1824cf17445SGavin Shan return pnv_eeh_dbgfs_set(data, 0xD90, val); 1834cf17445SGavin Shan } 1844cf17445SGavin Shan 1854cf17445SGavin Shan static int pnv_eeh_inbA_dbgfs_get(void *data, u64 *val) 1864cf17445SGavin Shan { 1874cf17445SGavin Shan return pnv_eeh_dbgfs_get(data, 0xD90, val); 1884cf17445SGavin Shan } 1894cf17445SGavin Shan 1904cf17445SGavin Shan static int pnv_eeh_inbB_dbgfs_set(void *data, u64 val) 1914cf17445SGavin Shan { 1924cf17445SGavin Shan return pnv_eeh_dbgfs_set(data, 0xE10, val); 1934cf17445SGavin Shan } 1944cf17445SGavin Shan 1954cf17445SGavin Shan static int pnv_eeh_inbB_dbgfs_get(void *data, u64 *val) 1964cf17445SGavin Shan { 1974cf17445SGavin Shan return pnv_eeh_dbgfs_get(data, 0xE10, val); 1984cf17445SGavin Shan } 1994cf17445SGavin Shan 2004cf17445SGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_outb_dbgfs_ops, pnv_eeh_outb_dbgfs_get, 2014cf17445SGavin Shan pnv_eeh_outb_dbgfs_set, "0x%llx\n"); 2024cf17445SGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbA_dbgfs_ops, pnv_eeh_inbA_dbgfs_get, 2034cf17445SGavin Shan pnv_eeh_inbA_dbgfs_set, "0x%llx\n"); 2044cf17445SGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_inbB_dbgfs_ops, pnv_eeh_inbB_dbgfs_get, 2054cf17445SGavin Shan pnv_eeh_inbB_dbgfs_set, "0x%llx\n"); 2064cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 2074cf17445SGavin Shan 20829310e5eSGavin Shan /** 20901f3bfb7SGavin Shan * pnv_eeh_post_init - EEH platform dependent post initialization 21029310e5eSGavin Shan * 21129310e5eSGavin Shan * EEH platform dependent post initialization on powernv. When 21229310e5eSGavin Shan * the function is called, the EEH PEs and devices should have 21329310e5eSGavin Shan * been built. If the I/O cache staff has been built, EEH is 21429310e5eSGavin Shan * ready to supply service. 21529310e5eSGavin Shan */ 21601f3bfb7SGavin Shan static int pnv_eeh_post_init(void) 21729310e5eSGavin Shan { 21829310e5eSGavin Shan struct pci_controller *hose; 21929310e5eSGavin Shan struct pnv_phb *phb; 22029310e5eSGavin Shan int ret = 0; 22129310e5eSGavin Shan 2224cf17445SGavin Shan /* Register OPAL event notifier */ 2234cf17445SGavin Shan if (!pnv_eeh_nb_init) { 22479231448SAlistair Popple eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 22579231448SAlistair Popple if (eeh_event_irq < 0) { 22679231448SAlistair Popple pr_err("%s: Can't register OPAL event interrupt (%d)\n", 22779231448SAlistair Popple __func__, eeh_event_irq); 22879231448SAlistair Popple return eeh_event_irq; 22979231448SAlistair Popple } 23079231448SAlistair Popple 23179231448SAlistair Popple ret = request_irq(eeh_event_irq, pnv_eeh_event, 23279231448SAlistair Popple IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 23379231448SAlistair Popple if (ret < 0) { 23479231448SAlistair Popple irq_dispose_mapping(eeh_event_irq); 23579231448SAlistair Popple pr_err("%s: Can't request OPAL event interrupt (%d)\n", 23679231448SAlistair Popple __func__, eeh_event_irq); 2374cf17445SGavin Shan return ret; 2384cf17445SGavin Shan } 2394cf17445SGavin Shan 2404cf17445SGavin Shan pnv_eeh_nb_init = true; 2414cf17445SGavin Shan } 2424cf17445SGavin Shan 24379231448SAlistair Popple if (!eeh_enabled()) 24479231448SAlistair Popple disable_irq(eeh_event_irq); 24579231448SAlistair Popple 24629310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 24729310e5eSGavin Shan phb = hose->private_data; 24829310e5eSGavin Shan 2494cf17445SGavin Shan /* 2504cf17445SGavin Shan * If EEH is enabled, we're going to rely on that. 2514cf17445SGavin Shan * Otherwise, we restore to conventional mechanism 2524cf17445SGavin Shan * to clear frozen PE during PCI config access. 2534cf17445SGavin Shan */ 2544cf17445SGavin Shan if (eeh_enabled()) 2554cf17445SGavin Shan phb->flags |= PNV_PHB_FLAG_EEH; 2564cf17445SGavin Shan else 2574cf17445SGavin Shan phb->flags &= ~PNV_PHB_FLAG_EEH; 2584cf17445SGavin Shan 2594cf17445SGavin Shan /* Create debugfs entries */ 2604cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 2614cf17445SGavin Shan if (phb->has_dbgfs || !phb->dbgfs) 2624cf17445SGavin Shan continue; 2634cf17445SGavin Shan 2644cf17445SGavin Shan phb->has_dbgfs = 1; 2654cf17445SGavin Shan debugfs_create_file("err_injct", 0200, 2664cf17445SGavin Shan phb->dbgfs, hose, 2674cf17445SGavin Shan &pnv_eeh_ei_fops); 2684cf17445SGavin Shan 2694cf17445SGavin Shan debugfs_create_file("err_injct_outbound", 0600, 2704cf17445SGavin Shan phb->dbgfs, hose, 2714cf17445SGavin Shan &pnv_eeh_outb_dbgfs_ops); 2724cf17445SGavin Shan debugfs_create_file("err_injct_inboundA", 0600, 2734cf17445SGavin Shan phb->dbgfs, hose, 2744cf17445SGavin Shan &pnv_eeh_inbA_dbgfs_ops); 2754cf17445SGavin Shan debugfs_create_file("err_injct_inboundB", 0600, 2764cf17445SGavin Shan phb->dbgfs, hose, 2774cf17445SGavin Shan &pnv_eeh_inbB_dbgfs_ops); 2784cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 27929310e5eSGavin Shan } 2804cf17445SGavin Shan 28129310e5eSGavin Shan return ret; 28229310e5eSGavin Shan } 28329310e5eSGavin Shan 2844d6186caSGavin Shan static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 285ff57b454SGavin Shan { 2864d6186caSGavin Shan int pos = PCI_CAPABILITY_LIST; 2874d6186caSGavin Shan int cnt = 48; /* Maximal number of capabilities */ 2884d6186caSGavin Shan u32 status, id; 289ff57b454SGavin Shan 290ff57b454SGavin Shan if (!pdn) 291ff57b454SGavin Shan return 0; 292ff57b454SGavin Shan 2934d6186caSGavin Shan /* Check if the device supports capabilities */ 294ff57b454SGavin Shan pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 295ff57b454SGavin Shan if (!(status & PCI_STATUS_CAP_LIST)) 296ff57b454SGavin Shan return 0; 297ff57b454SGavin Shan 298ff57b454SGavin Shan while (cnt--) { 299ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos, 1, &pos); 300ff57b454SGavin Shan if (pos < 0x40) 301ff57b454SGavin Shan break; 302ff57b454SGavin Shan 303ff57b454SGavin Shan pos &= ~3; 304ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 305ff57b454SGavin Shan if (id == 0xff) 306ff57b454SGavin Shan break; 307ff57b454SGavin Shan 308ff57b454SGavin Shan /* Found */ 309ff57b454SGavin Shan if (id == cap) 310ff57b454SGavin Shan return pos; 311ff57b454SGavin Shan 312ff57b454SGavin Shan /* Next one */ 313ff57b454SGavin Shan pos += PCI_CAP_LIST_NEXT; 314ff57b454SGavin Shan } 315ff57b454SGavin Shan 316ff57b454SGavin Shan return 0; 317ff57b454SGavin Shan } 318ff57b454SGavin Shan 319ff57b454SGavin Shan static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 320ff57b454SGavin Shan { 321ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 322ff57b454SGavin Shan u32 header; 323ff57b454SGavin Shan int pos = 256, ttl = (4096 - 256) / 8; 324ff57b454SGavin Shan 325ff57b454SGavin Shan if (!edev || !edev->pcie_cap) 326ff57b454SGavin Shan return 0; 327ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 328ff57b454SGavin Shan return 0; 329ff57b454SGavin Shan else if (!header) 330ff57b454SGavin Shan return 0; 331ff57b454SGavin Shan 332ff57b454SGavin Shan while (ttl-- > 0) { 333ff57b454SGavin Shan if (PCI_EXT_CAP_ID(header) == cap && pos) 334ff57b454SGavin Shan return pos; 335ff57b454SGavin Shan 336ff57b454SGavin Shan pos = PCI_EXT_CAP_NEXT(header); 337ff57b454SGavin Shan if (pos < 256) 338ff57b454SGavin Shan break; 339ff57b454SGavin Shan 340ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 341ff57b454SGavin Shan break; 342ff57b454SGavin Shan } 343ff57b454SGavin Shan 344ff57b454SGavin Shan return 0; 345ff57b454SGavin Shan } 346ff57b454SGavin Shan 34729310e5eSGavin Shan /** 348ff57b454SGavin Shan * pnv_eeh_probe - Do probe on PCI device 349ff57b454SGavin Shan * @pdn: PCI device node 350ff57b454SGavin Shan * @data: unused 35129310e5eSGavin Shan * 35229310e5eSGavin Shan * When EEH module is installed during system boot, all PCI devices 35329310e5eSGavin Shan * are checked one by one to see if it supports EEH. The function 35429310e5eSGavin Shan * is introduced for the purpose. By default, EEH has been enabled 35529310e5eSGavin Shan * on all PCI devices. That's to say, we only need do necessary 35629310e5eSGavin Shan * initialization on the corresponding eeh device and create PE 35729310e5eSGavin Shan * accordingly. 35829310e5eSGavin Shan * 35929310e5eSGavin Shan * It's notable that's unsafe to retrieve the EEH device through 36029310e5eSGavin Shan * the corresponding PCI device. During the PCI device hotplug, which 36129310e5eSGavin Shan * was possiblly triggered by EEH core, the binding between EEH device 36229310e5eSGavin Shan * and the PCI device isn't built yet. 36329310e5eSGavin Shan */ 364ff57b454SGavin Shan static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 36529310e5eSGavin Shan { 366ff57b454SGavin Shan struct pci_controller *hose = pdn->phb; 36729310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 368ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 369ff57b454SGavin Shan uint32_t pcie_flags; 370dadcd6d6SMike Qiu int ret; 37129310e5eSGavin Shan 37229310e5eSGavin Shan /* 37329310e5eSGavin Shan * When probing the root bridge, which doesn't have any 37429310e5eSGavin Shan * subordinate PCI devices. We don't have OF node for 37529310e5eSGavin Shan * the root bridge. So it's not reasonable to continue 37629310e5eSGavin Shan * the probing. 37729310e5eSGavin Shan */ 378ff57b454SGavin Shan if (!edev || edev->pe) 379ff57b454SGavin Shan return NULL; 38029310e5eSGavin Shan 38129310e5eSGavin Shan /* Skip for PCI-ISA bridge */ 382ff57b454SGavin Shan if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 383ff57b454SGavin Shan return NULL; 38429310e5eSGavin Shan 38529310e5eSGavin Shan /* Initialize eeh device */ 386ff57b454SGavin Shan edev->class_code = pdn->class_code; 387ab55d218SGavin Shan edev->mode &= 0xFFFFFF00; 388ff57b454SGavin Shan edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 389ff57b454SGavin Shan edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 390ff57b454SGavin Shan edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 391ff57b454SGavin Shan if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 3924b83bd45SGavin Shan edev->mode |= EEH_DEV_BRIDGE; 393ff57b454SGavin Shan if (edev->pcie_cap) { 394ff57b454SGavin Shan pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 395ff57b454SGavin Shan 2, &pcie_flags); 396ff57b454SGavin Shan pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 397ff57b454SGavin Shan if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 3984b83bd45SGavin Shan edev->mode |= EEH_DEV_ROOT_PORT; 399ff57b454SGavin Shan else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 4004b83bd45SGavin Shan edev->mode |= EEH_DEV_DS_PORT; 401ff57b454SGavin Shan } 4024b83bd45SGavin Shan } 4034b83bd45SGavin Shan 404ff57b454SGavin Shan edev->config_addr = (pdn->busno << 8) | (pdn->devfn); 405ff57b454SGavin Shan edev->pe_config_addr = phb->ioda.pe_rmap[edev->config_addr]; 40629310e5eSGavin Shan 40729310e5eSGavin Shan /* Create PE */ 408dadcd6d6SMike Qiu ret = eeh_add_to_parent_pe(edev); 409dadcd6d6SMike Qiu if (ret) { 410ff57b454SGavin Shan pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%d)\n", 411ff57b454SGavin Shan __func__, hose->global_number, pdn->busno, 412ff57b454SGavin Shan PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 413ff57b454SGavin Shan return NULL; 414dadcd6d6SMike Qiu } 415dadcd6d6SMike Qiu 416dadcd6d6SMike Qiu /* 417b6541db1SGavin Shan * If the PE contains any one of following adapters, the 418b6541db1SGavin Shan * PCI config space can't be accessed when dumping EEH log. 419b6541db1SGavin Shan * Otherwise, we will run into fenced PHB caused by shortage 420b6541db1SGavin Shan * of outbound credits in the adapter. The PCI config access 421b6541db1SGavin Shan * should be blocked until PE reset. MMIO access is dropped 422b6541db1SGavin Shan * by hardware certainly. In order to drop PCI config requests, 423b6541db1SGavin Shan * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 424b6541db1SGavin Shan * will be checked in the backend for PE state retrival. If 425b6541db1SGavin Shan * the PE becomes frozen for the first time and the flag has 426b6541db1SGavin Shan * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 427b6541db1SGavin Shan * that PE to block its config space. 428b6541db1SGavin Shan * 429b6541db1SGavin Shan * Broadcom Austin 4-ports NICs (14e4:1657) 430353169acSGavin Shan * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 431179ea48bSGavin Shan * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 432b6541db1SGavin Shan */ 433ff57b454SGavin Shan if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 434ff57b454SGavin Shan pdn->device_id == 0x1657) || 435ff57b454SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 436353169acSGavin Shan pdn->device_id == 0x168a) || 437353169acSGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 438ff57b454SGavin Shan pdn->device_id == 0x168e)) 439b6541db1SGavin Shan edev->pe->state |= EEH_PE_CFG_RESTRICTED; 440b6541db1SGavin Shan 441b6541db1SGavin Shan /* 442dadcd6d6SMike Qiu * Cache the PE primary bus, which can't be fetched when 443dadcd6d6SMike Qiu * full hotplug is in progress. In that case, all child 444dadcd6d6SMike Qiu * PCI devices of the PE are expected to be removed prior 445dadcd6d6SMike Qiu * to PE reset. 446dadcd6d6SMike Qiu */ 447dadcd6d6SMike Qiu if (!edev->pe->bus) 448ff57b454SGavin Shan edev->pe->bus = pci_find_bus(hose->global_number, 449ff57b454SGavin Shan pdn->busno); 45029310e5eSGavin Shan 45129310e5eSGavin Shan /* 45229310e5eSGavin Shan * Enable EEH explicitly so that we will do EEH check 45329310e5eSGavin Shan * while accessing I/O stuff 45429310e5eSGavin Shan */ 45505b1721dSGavin Shan eeh_add_flag(EEH_ENABLED); 45629310e5eSGavin Shan 45729310e5eSGavin Shan /* Save memory bars */ 45829310e5eSGavin Shan eeh_save_bars(edev); 45929310e5eSGavin Shan 460ff57b454SGavin Shan return NULL; 46129310e5eSGavin Shan } 46229310e5eSGavin Shan 46329310e5eSGavin Shan /** 46401f3bfb7SGavin Shan * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 46529310e5eSGavin Shan * @pe: EEH PE 46629310e5eSGavin Shan * @option: operation to be issued 46729310e5eSGavin Shan * 46829310e5eSGavin Shan * The function is used to control the EEH functionality globally. 46929310e5eSGavin Shan * Currently, following options are support according to PAPR: 47029310e5eSGavin Shan * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 47129310e5eSGavin Shan */ 47201f3bfb7SGavin Shan static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 47329310e5eSGavin Shan { 47429310e5eSGavin Shan struct pci_controller *hose = pe->phb; 47529310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 4767e3e4f8dSGavin Shan bool freeze_pe = false; 477f9433718SGavin Shan int opt; 4787e3e4f8dSGavin Shan s64 rc; 47929310e5eSGavin Shan 4807e3e4f8dSGavin Shan switch (option) { 4817e3e4f8dSGavin Shan case EEH_OPT_DISABLE: 4827e3e4f8dSGavin Shan return -EPERM; 4837e3e4f8dSGavin Shan case EEH_OPT_ENABLE: 4847e3e4f8dSGavin Shan return 0; 4857e3e4f8dSGavin Shan case EEH_OPT_THAW_MMIO: 4867e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 4877e3e4f8dSGavin Shan break; 4887e3e4f8dSGavin Shan case EEH_OPT_THAW_DMA: 4897e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 4907e3e4f8dSGavin Shan break; 4917e3e4f8dSGavin Shan case EEH_OPT_FREEZE_PE: 4927e3e4f8dSGavin Shan freeze_pe = true; 4937e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 4947e3e4f8dSGavin Shan break; 4957e3e4f8dSGavin Shan default: 4967e3e4f8dSGavin Shan pr_warn("%s: Invalid option %d\n", __func__, option); 4977e3e4f8dSGavin Shan return -EINVAL; 4987e3e4f8dSGavin Shan } 4997e3e4f8dSGavin Shan 500f9433718SGavin Shan /* Freeze master and slave PEs if PHB supports compound PEs */ 5017e3e4f8dSGavin Shan if (freeze_pe) { 5027e3e4f8dSGavin Shan if (phb->freeze_pe) { 5037e3e4f8dSGavin Shan phb->freeze_pe(phb, pe->addr); 504f9433718SGavin Shan return 0; 5057e3e4f8dSGavin Shan } 50629310e5eSGavin Shan 507f9433718SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 508f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 509f9433718SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 510f9433718SGavin Shan __func__, rc, phb->hose->global_number, 511f9433718SGavin Shan pe->addr); 512f9433718SGavin Shan return -EIO; 513f9433718SGavin Shan } 514f9433718SGavin Shan 515f9433718SGavin Shan return 0; 516f9433718SGavin Shan } 517f9433718SGavin Shan 518f9433718SGavin Shan /* Unfreeze master and slave PEs if PHB supports */ 519f9433718SGavin Shan if (phb->unfreeze_pe) 520f9433718SGavin Shan return phb->unfreeze_pe(phb, pe->addr, opt); 521f9433718SGavin Shan 522f9433718SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 523f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 524f9433718SGavin Shan pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 525f9433718SGavin Shan __func__, rc, option, phb->hose->global_number, 526f9433718SGavin Shan pe->addr); 527f9433718SGavin Shan return -EIO; 528f9433718SGavin Shan } 529f9433718SGavin Shan 530f9433718SGavin Shan return 0; 53129310e5eSGavin Shan } 53229310e5eSGavin Shan 53329310e5eSGavin Shan /** 53401f3bfb7SGavin Shan * pnv_eeh_get_pe_addr - Retrieve PE address 53529310e5eSGavin Shan * @pe: EEH PE 53629310e5eSGavin Shan * 53729310e5eSGavin Shan * Retrieve the PE address according to the given tranditional 53829310e5eSGavin Shan * PCI BDF (Bus/Device/Function) address. 53929310e5eSGavin Shan */ 54001f3bfb7SGavin Shan static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 54129310e5eSGavin Shan { 54229310e5eSGavin Shan return pe->addr; 54329310e5eSGavin Shan } 54429310e5eSGavin Shan 54540ae5f69SGavin Shan static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 54640ae5f69SGavin Shan { 54740ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 54840ae5f69SGavin Shan s64 rc; 54940ae5f69SGavin Shan 55040ae5f69SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 55140ae5f69SGavin Shan PNV_PCI_DIAG_BUF_SIZE); 55240ae5f69SGavin Shan if (rc != OPAL_SUCCESS) 55340ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 55440ae5f69SGavin Shan __func__, rc, pe->phb->global_number); 55540ae5f69SGavin Shan } 55640ae5f69SGavin Shan 55740ae5f69SGavin Shan static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 55840ae5f69SGavin Shan { 55940ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 56040ae5f69SGavin Shan u8 fstate; 56140ae5f69SGavin Shan __be16 pcierr; 56240ae5f69SGavin Shan s64 rc; 56340ae5f69SGavin Shan int result = 0; 56440ae5f69SGavin Shan 56540ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 56640ae5f69SGavin Shan pe->addr, 56740ae5f69SGavin Shan &fstate, 56840ae5f69SGavin Shan &pcierr, 56940ae5f69SGavin Shan NULL); 57040ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 57140ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x state\n", 57240ae5f69SGavin Shan __func__, rc, phb->hose->global_number); 57340ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 57440ae5f69SGavin Shan } 57540ae5f69SGavin Shan 57640ae5f69SGavin Shan /* 57740ae5f69SGavin Shan * Check PHB state. If the PHB is frozen for the 57840ae5f69SGavin Shan * first time, to dump the PHB diag-data. 57940ae5f69SGavin Shan */ 58040ae5f69SGavin Shan if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 58140ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 58240ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 58340ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 58440ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 58540ae5f69SGavin Shan } else if (!(pe->state & EEH_PE_ISOLATED)) { 58640ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 58740ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 58840ae5f69SGavin Shan 58940ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 59040ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 59140ae5f69SGavin Shan } 59240ae5f69SGavin Shan 59340ae5f69SGavin Shan return result; 59440ae5f69SGavin Shan } 59540ae5f69SGavin Shan 59640ae5f69SGavin Shan static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 59740ae5f69SGavin Shan { 59840ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 59940ae5f69SGavin Shan u8 fstate; 60040ae5f69SGavin Shan __be16 pcierr; 60140ae5f69SGavin Shan s64 rc; 60240ae5f69SGavin Shan int result; 60340ae5f69SGavin Shan 60440ae5f69SGavin Shan /* 60540ae5f69SGavin Shan * We don't clobber hardware frozen state until PE 60640ae5f69SGavin Shan * reset is completed. In order to keep EEH core 60740ae5f69SGavin Shan * moving forward, we have to return operational 60840ae5f69SGavin Shan * state during PE reset. 60940ae5f69SGavin Shan */ 61040ae5f69SGavin Shan if (pe->state & EEH_PE_RESET) { 61140ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 61240ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 61340ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 61440ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 61540ae5f69SGavin Shan return result; 61640ae5f69SGavin Shan } 61740ae5f69SGavin Shan 61840ae5f69SGavin Shan /* 61940ae5f69SGavin Shan * Fetch PE state from hardware. If the PHB 62040ae5f69SGavin Shan * supports compound PE, let it handle that. 62140ae5f69SGavin Shan */ 62240ae5f69SGavin Shan if (phb->get_pe_state) { 62340ae5f69SGavin Shan fstate = phb->get_pe_state(phb, pe->addr); 62440ae5f69SGavin Shan } else { 62540ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 62640ae5f69SGavin Shan pe->addr, 62740ae5f69SGavin Shan &fstate, 62840ae5f69SGavin Shan &pcierr, 62940ae5f69SGavin Shan NULL); 63040ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 63140ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 63240ae5f69SGavin Shan __func__, rc, phb->hose->global_number, 63340ae5f69SGavin Shan pe->addr); 63440ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 63540ae5f69SGavin Shan } 63640ae5f69SGavin Shan } 63740ae5f69SGavin Shan 63840ae5f69SGavin Shan /* Figure out state */ 63940ae5f69SGavin Shan switch (fstate) { 64040ae5f69SGavin Shan case OPAL_EEH_STOPPED_NOT_FROZEN: 64140ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 64240ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 64340ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 64440ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 64540ae5f69SGavin Shan break; 64640ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_FREEZE: 64740ae5f69SGavin Shan result = (EEH_STATE_DMA_ACTIVE | 64840ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 64940ae5f69SGavin Shan break; 65040ae5f69SGavin Shan case OPAL_EEH_STOPPED_DMA_FREEZE: 65140ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 65240ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED); 65340ae5f69SGavin Shan break; 65440ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 65540ae5f69SGavin Shan result = 0; 65640ae5f69SGavin Shan break; 65740ae5f69SGavin Shan case OPAL_EEH_STOPPED_RESET: 65840ae5f69SGavin Shan result = EEH_STATE_RESET_ACTIVE; 65940ae5f69SGavin Shan break; 66040ae5f69SGavin Shan case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 66140ae5f69SGavin Shan result = EEH_STATE_UNAVAILABLE; 66240ae5f69SGavin Shan break; 66340ae5f69SGavin Shan case OPAL_EEH_STOPPED_PERM_UNAVAIL: 66440ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 66540ae5f69SGavin Shan break; 66640ae5f69SGavin Shan default: 66740ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 66840ae5f69SGavin Shan pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 66940ae5f69SGavin Shan __func__, phb->hose->global_number, 67040ae5f69SGavin Shan pe->addr, fstate); 67140ae5f69SGavin Shan } 67240ae5f69SGavin Shan 67340ae5f69SGavin Shan /* 67440ae5f69SGavin Shan * If PHB supports compound PE, to freeze all 67540ae5f69SGavin Shan * slave PEs for consistency. 67640ae5f69SGavin Shan * 67740ae5f69SGavin Shan * If the PE is switching to frozen state for the 67840ae5f69SGavin Shan * first time, to dump the PHB diag-data. 67940ae5f69SGavin Shan */ 68040ae5f69SGavin Shan if (!(result & EEH_STATE_NOT_SUPPORT) && 68140ae5f69SGavin Shan !(result & EEH_STATE_UNAVAILABLE) && 68240ae5f69SGavin Shan !(result & EEH_STATE_MMIO_ACTIVE) && 68340ae5f69SGavin Shan !(result & EEH_STATE_DMA_ACTIVE) && 68440ae5f69SGavin Shan !(pe->state & EEH_PE_ISOLATED)) { 68540ae5f69SGavin Shan if (phb->freeze_pe) 68640ae5f69SGavin Shan phb->freeze_pe(phb, pe->addr); 68740ae5f69SGavin Shan 68840ae5f69SGavin Shan eeh_pe_state_mark(pe, EEH_PE_ISOLATED); 68940ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 69040ae5f69SGavin Shan 69140ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 69240ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 69340ae5f69SGavin Shan } 69440ae5f69SGavin Shan 69540ae5f69SGavin Shan return result; 69640ae5f69SGavin Shan } 69740ae5f69SGavin Shan 69829310e5eSGavin Shan /** 69901f3bfb7SGavin Shan * pnv_eeh_get_state - Retrieve PE state 70029310e5eSGavin Shan * @pe: EEH PE 70129310e5eSGavin Shan * @delay: delay while PE state is temporarily unavailable 70229310e5eSGavin Shan * 70329310e5eSGavin Shan * Retrieve the state of the specified PE. For IODA-compitable 70429310e5eSGavin Shan * platform, it should be retrieved from IODA table. Therefore, 70529310e5eSGavin Shan * we prefer passing down to hardware implementation to handle 70629310e5eSGavin Shan * it. 70729310e5eSGavin Shan */ 70801f3bfb7SGavin Shan static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 70929310e5eSGavin Shan { 71040ae5f69SGavin Shan int ret; 71129310e5eSGavin Shan 71240ae5f69SGavin Shan if (pe->type & EEH_PE_PHB) 71340ae5f69SGavin Shan ret = pnv_eeh_get_phb_state(pe); 71440ae5f69SGavin Shan else 71540ae5f69SGavin Shan ret = pnv_eeh_get_pe_state(pe); 71640ae5f69SGavin Shan 71740ae5f69SGavin Shan if (!delay) 71840ae5f69SGavin Shan return ret; 71929310e5eSGavin Shan 72029310e5eSGavin Shan /* 72129310e5eSGavin Shan * If the PE state is temporarily unavailable, 72229310e5eSGavin Shan * to inform the EEH core delay for default 72329310e5eSGavin Shan * period (1 second) 72429310e5eSGavin Shan */ 72529310e5eSGavin Shan *delay = 0; 72629310e5eSGavin Shan if (ret & EEH_STATE_UNAVAILABLE) 72729310e5eSGavin Shan *delay = 1000; 72829310e5eSGavin Shan 72929310e5eSGavin Shan return ret; 73029310e5eSGavin Shan } 73129310e5eSGavin Shan 732cadf364dSGavin Shan static s64 pnv_eeh_phb_poll(struct pnv_phb *phb) 733cadf364dSGavin Shan { 734cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 735cadf364dSGavin Shan 736cadf364dSGavin Shan while (1) { 737cadf364dSGavin Shan rc = opal_pci_poll(phb->opal_id); 738cadf364dSGavin Shan if (rc <= 0) 739cadf364dSGavin Shan break; 740cadf364dSGavin Shan 741cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 742cadf364dSGavin Shan udelay(1000 * rc); 743cadf364dSGavin Shan else 744cadf364dSGavin Shan msleep(rc); 745cadf364dSGavin Shan } 746cadf364dSGavin Shan 747cadf364dSGavin Shan return rc; 748cadf364dSGavin Shan } 749cadf364dSGavin Shan 750cadf364dSGavin Shan int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 751cadf364dSGavin Shan { 752cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 753cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 754cadf364dSGavin Shan 755cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 756cadf364dSGavin Shan __func__, hose->global_number, option); 757cadf364dSGavin Shan 758cadf364dSGavin Shan /* Issue PHB complete reset request */ 759cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL || 760cadf364dSGavin Shan option == EEH_RESET_HOT) 761cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 762cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 763cadf364dSGavin Shan OPAL_ASSERT_RESET); 764cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 765cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 766cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 767cadf364dSGavin Shan OPAL_DEASSERT_RESET); 768cadf364dSGavin Shan if (rc < 0) 769cadf364dSGavin Shan goto out; 770cadf364dSGavin Shan 771cadf364dSGavin Shan /* 772cadf364dSGavin Shan * Poll state of the PHB until the request is done 773cadf364dSGavin Shan * successfully. The PHB reset is usually PHB complete 774cadf364dSGavin Shan * reset followed by hot reset on root bus. So we also 775cadf364dSGavin Shan * need the PCI bus settlement delay. 776cadf364dSGavin Shan */ 777cadf364dSGavin Shan rc = pnv_eeh_phb_poll(phb); 778cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) { 779cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 780cadf364dSGavin Shan udelay(1000 * EEH_PE_RST_SETTLE_TIME); 781cadf364dSGavin Shan else 782cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 783cadf364dSGavin Shan } 784cadf364dSGavin Shan out: 785cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 786cadf364dSGavin Shan return -EIO; 787cadf364dSGavin Shan 788cadf364dSGavin Shan return 0; 789cadf364dSGavin Shan } 790cadf364dSGavin Shan 791cadf364dSGavin Shan static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 792cadf364dSGavin Shan { 793cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 794cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 795cadf364dSGavin Shan 796cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 797cadf364dSGavin Shan __func__, hose->global_number, option); 798cadf364dSGavin Shan 799cadf364dSGavin Shan /* 800cadf364dSGavin Shan * During the reset deassert time, we needn't care 801cadf364dSGavin Shan * the reset scope because the firmware does nothing 802cadf364dSGavin Shan * for fundamental or hot reset during deassert phase. 803cadf364dSGavin Shan */ 804cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL) 805cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 806cadf364dSGavin Shan OPAL_RESET_PCI_FUNDAMENTAL, 807cadf364dSGavin Shan OPAL_ASSERT_RESET); 808cadf364dSGavin Shan else if (option == EEH_RESET_HOT) 809cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 810cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 811cadf364dSGavin Shan OPAL_ASSERT_RESET); 812cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 813cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 814cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 815cadf364dSGavin Shan OPAL_DEASSERT_RESET); 816cadf364dSGavin Shan if (rc < 0) 817cadf364dSGavin Shan goto out; 818cadf364dSGavin Shan 819cadf364dSGavin Shan /* Poll state of the PHB until the request is done */ 820cadf364dSGavin Shan rc = pnv_eeh_phb_poll(phb); 821cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) 822cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 823cadf364dSGavin Shan out: 824cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 825cadf364dSGavin Shan return -EIO; 826cadf364dSGavin Shan 827cadf364dSGavin Shan return 0; 828cadf364dSGavin Shan } 829cadf364dSGavin Shan 830cadf364dSGavin Shan static int pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 831cadf364dSGavin Shan { 8320bd78587SGavin Shan struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 8330bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 834cadf364dSGavin Shan int aer = edev ? edev->aer_cap : 0; 835cadf364dSGavin Shan u32 ctrl; 836cadf364dSGavin Shan 837cadf364dSGavin Shan pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 838cadf364dSGavin Shan __func__, pci_domain_nr(dev->bus), 839cadf364dSGavin Shan dev->bus->number, option); 840cadf364dSGavin Shan 841cadf364dSGavin Shan switch (option) { 842cadf364dSGavin Shan case EEH_RESET_FUNDAMENTAL: 843cadf364dSGavin Shan case EEH_RESET_HOT: 844cadf364dSGavin Shan /* Don't report linkDown event */ 845cadf364dSGavin Shan if (aer) { 8460bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 847cadf364dSGavin Shan 4, &ctrl); 848cadf364dSGavin Shan ctrl |= PCI_ERR_UNC_SURPDN; 8490bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 850cadf364dSGavin Shan 4, ctrl); 851cadf364dSGavin Shan } 852cadf364dSGavin Shan 8530bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 854cadf364dSGavin Shan ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 8550bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 856cadf364dSGavin Shan 857cadf364dSGavin Shan msleep(EEH_PE_RST_HOLD_TIME); 858cadf364dSGavin Shan break; 859cadf364dSGavin Shan case EEH_RESET_DEACTIVATE: 8600bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 861cadf364dSGavin Shan ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 8620bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 863cadf364dSGavin Shan 864cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 865cadf364dSGavin Shan 866cadf364dSGavin Shan /* Continue reporting linkDown event */ 867cadf364dSGavin Shan if (aer) { 8680bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 869cadf364dSGavin Shan 4, &ctrl); 870cadf364dSGavin Shan ctrl &= ~PCI_ERR_UNC_SURPDN; 8710bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 872cadf364dSGavin Shan 4, ctrl); 873cadf364dSGavin Shan } 874cadf364dSGavin Shan 875cadf364dSGavin Shan break; 876cadf364dSGavin Shan } 877cadf364dSGavin Shan 878cadf364dSGavin Shan return 0; 879cadf364dSGavin Shan } 880cadf364dSGavin Shan 881cadf364dSGavin Shan void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 882cadf364dSGavin Shan { 883cadf364dSGavin Shan struct pci_controller *hose; 884cadf364dSGavin Shan 885cadf364dSGavin Shan if (pci_is_root_bus(dev->bus)) { 886cadf364dSGavin Shan hose = pci_bus_to_host(dev->bus); 887cadf364dSGavin Shan pnv_eeh_root_reset(hose, EEH_RESET_HOT); 888cadf364dSGavin Shan pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 889cadf364dSGavin Shan } else { 890cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 891cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 892cadf364dSGavin Shan } 893cadf364dSGavin Shan } 894cadf364dSGavin Shan 89529310e5eSGavin Shan /** 89601f3bfb7SGavin Shan * pnv_eeh_reset - Reset the specified PE 89729310e5eSGavin Shan * @pe: EEH PE 89829310e5eSGavin Shan * @option: reset option 89929310e5eSGavin Shan * 900cadf364dSGavin Shan * Do reset on the indicated PE. For PCI bus sensitive PE, 901cadf364dSGavin Shan * we need to reset the parent p2p bridge. The PHB has to 902cadf364dSGavin Shan * be reinitialized if the p2p bridge is root bridge. For 903cadf364dSGavin Shan * PCI device sensitive PE, we will try to reset the device 904cadf364dSGavin Shan * through FLR. For now, we don't have OPAL APIs to do HARD 905cadf364dSGavin Shan * reset yet, so all reset would be SOFT (HOT) reset. 90629310e5eSGavin Shan */ 90701f3bfb7SGavin Shan static int pnv_eeh_reset(struct eeh_pe *pe, int option) 90829310e5eSGavin Shan { 90929310e5eSGavin Shan struct pci_controller *hose = pe->phb; 910cadf364dSGavin Shan struct pci_bus *bus; 911cadf364dSGavin Shan int ret; 91229310e5eSGavin Shan 913cadf364dSGavin Shan /* 914cadf364dSGavin Shan * For PHB reset, we always have complete reset. For those PEs whose 915cadf364dSGavin Shan * primary bus derived from root complex (root bus) or root port 916cadf364dSGavin Shan * (usually bus#1), we apply hot or fundamental reset on the root port. 917cadf364dSGavin Shan * For other PEs, we always have hot reset on the PE primary bus. 918cadf364dSGavin Shan * 919cadf364dSGavin Shan * Here, we have different design to pHyp, which always clear the 920cadf364dSGavin Shan * frozen state during PE reset. However, the good idea here from 921cadf364dSGavin Shan * benh is to keep frozen state before we get PE reset done completely 922cadf364dSGavin Shan * (until BAR restore). With the frozen state, HW drops illegal IO 923cadf364dSGavin Shan * or MMIO access, which can incur recrusive frozen PE during PE 924cadf364dSGavin Shan * reset. The side effect is that EEH core has to clear the frozen 925cadf364dSGavin Shan * state explicitly after BAR restore. 926cadf364dSGavin Shan */ 927cadf364dSGavin Shan if (pe->type & EEH_PE_PHB) { 928cadf364dSGavin Shan ret = pnv_eeh_phb_reset(hose, option); 929cadf364dSGavin Shan } else { 930cadf364dSGavin Shan struct pnv_phb *phb; 931cadf364dSGavin Shan s64 rc; 932cadf364dSGavin Shan 933cadf364dSGavin Shan /* 934cadf364dSGavin Shan * The frozen PE might be caused by PAPR error injection 935cadf364dSGavin Shan * registers, which are expected to be cleared after hitting 936cadf364dSGavin Shan * frozen PE as stated in the hardware spec. Unfortunately, 937cadf364dSGavin Shan * that's not true on P7IOC. So we have to clear it manually 938cadf364dSGavin Shan * to avoid recursive EEH errors during recovery. 939cadf364dSGavin Shan */ 940cadf364dSGavin Shan phb = hose->private_data; 941cadf364dSGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC && 942cadf364dSGavin Shan (option == EEH_RESET_HOT || 943cadf364dSGavin Shan option == EEH_RESET_FUNDAMENTAL)) { 944cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 945cadf364dSGavin Shan OPAL_RESET_PHB_ERROR, 946cadf364dSGavin Shan OPAL_ASSERT_RESET); 947cadf364dSGavin Shan if (rc != OPAL_SUCCESS) { 948cadf364dSGavin Shan pr_warn("%s: Failure %lld clearing " 949cadf364dSGavin Shan "error injection registers\n", 950cadf364dSGavin Shan __func__, rc); 951cadf364dSGavin Shan return -EIO; 952cadf364dSGavin Shan } 953cadf364dSGavin Shan } 954cadf364dSGavin Shan 955cadf364dSGavin Shan bus = eeh_pe_bus_get(pe); 956cadf364dSGavin Shan if (pci_is_root_bus(bus) || 957cadf364dSGavin Shan pci_is_root_bus(bus->parent)) 958cadf364dSGavin Shan ret = pnv_eeh_root_reset(hose, option); 959cadf364dSGavin Shan else 960cadf364dSGavin Shan ret = pnv_eeh_bridge_reset(bus->self, option); 961cadf364dSGavin Shan } 96229310e5eSGavin Shan 96329310e5eSGavin Shan return ret; 96429310e5eSGavin Shan } 96529310e5eSGavin Shan 96629310e5eSGavin Shan /** 96701f3bfb7SGavin Shan * pnv_eeh_wait_state - Wait for PE state 96829310e5eSGavin Shan * @pe: EEH PE 9692ac3990cSWei Yang * @max_wait: maximal period in millisecond 97029310e5eSGavin Shan * 97129310e5eSGavin Shan * Wait for the state of associated PE. It might take some time 97229310e5eSGavin Shan * to retrieve the PE's state. 97329310e5eSGavin Shan */ 97401f3bfb7SGavin Shan static int pnv_eeh_wait_state(struct eeh_pe *pe, int max_wait) 97529310e5eSGavin Shan { 97629310e5eSGavin Shan int ret; 97729310e5eSGavin Shan int mwait; 97829310e5eSGavin Shan 97929310e5eSGavin Shan while (1) { 98001f3bfb7SGavin Shan ret = pnv_eeh_get_state(pe, &mwait); 98129310e5eSGavin Shan 98229310e5eSGavin Shan /* 98329310e5eSGavin Shan * If the PE's state is temporarily unavailable, 98429310e5eSGavin Shan * we have to wait for the specified time. Otherwise, 98529310e5eSGavin Shan * the PE's state will be returned immediately. 98629310e5eSGavin Shan */ 98729310e5eSGavin Shan if (ret != EEH_STATE_UNAVAILABLE) 98829310e5eSGavin Shan return ret; 98929310e5eSGavin Shan 99029310e5eSGavin Shan if (max_wait <= 0) { 9910dae2743SGavin Shan pr_warn("%s: Timeout getting PE#%x's state (%d)\n", 99229310e5eSGavin Shan __func__, pe->addr, max_wait); 99329310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 99429310e5eSGavin Shan } 99529310e5eSGavin Shan 996e17866d5SWei Yang max_wait -= mwait; 99729310e5eSGavin Shan msleep(mwait); 99829310e5eSGavin Shan } 99929310e5eSGavin Shan 100029310e5eSGavin Shan return EEH_STATE_NOT_SUPPORT; 100129310e5eSGavin Shan } 100229310e5eSGavin Shan 100329310e5eSGavin Shan /** 100401f3bfb7SGavin Shan * pnv_eeh_get_log - Retrieve error log 100529310e5eSGavin Shan * @pe: EEH PE 100629310e5eSGavin Shan * @severity: temporary or permanent error log 100729310e5eSGavin Shan * @drv_log: driver log to be combined with retrieved error log 100829310e5eSGavin Shan * @len: length of driver log 100929310e5eSGavin Shan * 101029310e5eSGavin Shan * Retrieve the temporary or permanent error from the PE. 101129310e5eSGavin Shan */ 101201f3bfb7SGavin Shan static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 101329310e5eSGavin Shan char *drv_log, unsigned long len) 101429310e5eSGavin Shan { 101595edcdeaSGavin Shan if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 101695edcdeaSGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 101729310e5eSGavin Shan 101895edcdeaSGavin Shan return 0; 101929310e5eSGavin Shan } 102029310e5eSGavin Shan 102129310e5eSGavin Shan /** 102201f3bfb7SGavin Shan * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 102329310e5eSGavin Shan * @pe: EEH PE 102429310e5eSGavin Shan * 102529310e5eSGavin Shan * The function will be called to reconfigure the bridges included 102629310e5eSGavin Shan * in the specified PE so that the mulfunctional PE would be recovered 102729310e5eSGavin Shan * again. 102829310e5eSGavin Shan */ 102901f3bfb7SGavin Shan static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 103029310e5eSGavin Shan { 1031bbe170edSGavin Shan return 0; 103229310e5eSGavin Shan } 103329310e5eSGavin Shan 103429310e5eSGavin Shan /** 103501f3bfb7SGavin Shan * pnv_pe_err_inject - Inject specified error to the indicated PE 1036131c123aSGavin Shan * @pe: the indicated PE 1037131c123aSGavin Shan * @type: error type 1038131c123aSGavin Shan * @func: specific error type 1039131c123aSGavin Shan * @addr: address 1040131c123aSGavin Shan * @mask: address mask 1041131c123aSGavin Shan * 1042131c123aSGavin Shan * The routine is called to inject specified error, which is 1043131c123aSGavin Shan * determined by @type and @func, to the indicated PE for 1044131c123aSGavin Shan * testing purpose. 1045131c123aSGavin Shan */ 104601f3bfb7SGavin Shan static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1047131c123aSGavin Shan unsigned long addr, unsigned long mask) 1048131c123aSGavin Shan { 1049131c123aSGavin Shan struct pci_controller *hose = pe->phb; 1050131c123aSGavin Shan struct pnv_phb *phb = hose->private_data; 1051fa646c3cSGavin Shan s64 rc; 1052131c123aSGavin Shan 1053fa646c3cSGavin Shan if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1054fa646c3cSGavin Shan type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1055fa646c3cSGavin Shan pr_warn("%s: Invalid error type %d\n", 1056fa646c3cSGavin Shan __func__, type); 1057fa646c3cSGavin Shan return -ERANGE; 1058fa646c3cSGavin Shan } 1059131c123aSGavin Shan 1060fa646c3cSGavin Shan if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1061fa646c3cSGavin Shan func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1062fa646c3cSGavin Shan pr_warn("%s: Invalid error function %d\n", 1063fa646c3cSGavin Shan __func__, func); 1064fa646c3cSGavin Shan return -ERANGE; 1065fa646c3cSGavin Shan } 1066fa646c3cSGavin Shan 1067fa646c3cSGavin Shan /* Firmware supports error injection ? */ 1068fa646c3cSGavin Shan if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1069fa646c3cSGavin Shan pr_warn("%s: Firmware doesn't support error injection\n", 1070fa646c3cSGavin Shan __func__); 1071fa646c3cSGavin Shan return -ENXIO; 1072fa646c3cSGavin Shan } 1073fa646c3cSGavin Shan 1074fa646c3cSGavin Shan /* Do error injection */ 1075fa646c3cSGavin Shan rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1076fa646c3cSGavin Shan type, func, addr, mask); 1077fa646c3cSGavin Shan if (rc != OPAL_SUCCESS) { 1078fa646c3cSGavin Shan pr_warn("%s: Failure %lld injecting error " 1079fa646c3cSGavin Shan "%d-%d to PHB#%x-PE#%x\n", 1080fa646c3cSGavin Shan __func__, rc, type, func, 1081fa646c3cSGavin Shan hose->global_number, pe->addr); 1082fa646c3cSGavin Shan return -EIO; 1083fa646c3cSGavin Shan } 1084fa646c3cSGavin Shan 1085fa646c3cSGavin Shan return 0; 1086131c123aSGavin Shan } 1087131c123aSGavin Shan 10880bd78587SGavin Shan static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1089d2cfbcd7SGavin Shan { 10900bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1091d2cfbcd7SGavin Shan 1092d2cfbcd7SGavin Shan if (!edev || !edev->pe) 1093d2cfbcd7SGavin Shan return false; 1094d2cfbcd7SGavin Shan 1095d2cfbcd7SGavin Shan if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1096d2cfbcd7SGavin Shan return true; 1097d2cfbcd7SGavin Shan 1098d2cfbcd7SGavin Shan return false; 1099d2cfbcd7SGavin Shan } 1100d2cfbcd7SGavin Shan 11010bd78587SGavin Shan static int pnv_eeh_read_config(struct pci_dn *pdn, 1102d2cfbcd7SGavin Shan int where, int size, u32 *val) 1103d2cfbcd7SGavin Shan { 11043532a741SGavin Shan if (!pdn) 11053532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 11063532a741SGavin Shan 11070bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) { 1108d2cfbcd7SGavin Shan *val = 0xFFFFFFFF; 1109d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1110d2cfbcd7SGavin Shan } 1111d2cfbcd7SGavin Shan 11123532a741SGavin Shan return pnv_pci_cfg_read(pdn, where, size, val); 1113d2cfbcd7SGavin Shan } 1114d2cfbcd7SGavin Shan 11150bd78587SGavin Shan static int pnv_eeh_write_config(struct pci_dn *pdn, 1116d2cfbcd7SGavin Shan int where, int size, u32 val) 1117d2cfbcd7SGavin Shan { 11183532a741SGavin Shan if (!pdn) 11193532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 11203532a741SGavin Shan 11210bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) 1122d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1123d2cfbcd7SGavin Shan 11243532a741SGavin Shan return pnv_pci_cfg_write(pdn, where, size, val); 1125d2cfbcd7SGavin Shan } 1126d2cfbcd7SGavin Shan 11272a485ad7SGavin Shan static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 11282a485ad7SGavin Shan { 11292a485ad7SGavin Shan /* GEM */ 11302a485ad7SGavin Shan if (data->gemXfir || data->gemRfir || 11312a485ad7SGavin Shan data->gemRirqfir || data->gemMask || data->gemRwof) 11322a485ad7SGavin Shan pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 11332a485ad7SGavin Shan be64_to_cpu(data->gemXfir), 11342a485ad7SGavin Shan be64_to_cpu(data->gemRfir), 11352a485ad7SGavin Shan be64_to_cpu(data->gemRirqfir), 11362a485ad7SGavin Shan be64_to_cpu(data->gemMask), 11372a485ad7SGavin Shan be64_to_cpu(data->gemRwof)); 11382a485ad7SGavin Shan 11392a485ad7SGavin Shan /* LEM */ 11402a485ad7SGavin Shan if (data->lemFir || data->lemErrMask || 11412a485ad7SGavin Shan data->lemAction0 || data->lemAction1 || data->lemWof) 11422a485ad7SGavin Shan pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 11432a485ad7SGavin Shan be64_to_cpu(data->lemFir), 11442a485ad7SGavin Shan be64_to_cpu(data->lemErrMask), 11452a485ad7SGavin Shan be64_to_cpu(data->lemAction0), 11462a485ad7SGavin Shan be64_to_cpu(data->lemAction1), 11472a485ad7SGavin Shan be64_to_cpu(data->lemWof)); 11482a485ad7SGavin Shan } 11492a485ad7SGavin Shan 11502a485ad7SGavin Shan static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 11512a485ad7SGavin Shan { 11522a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 11532a485ad7SGavin Shan struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag; 11542a485ad7SGavin Shan long rc; 11552a485ad7SGavin Shan 11562a485ad7SGavin Shan rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 11572a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 11582a485ad7SGavin Shan pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 11592a485ad7SGavin Shan __func__, phb->hub_id, rc); 11602a485ad7SGavin Shan return; 11612a485ad7SGavin Shan } 11622a485ad7SGavin Shan 11632a485ad7SGavin Shan switch (data->type) { 11642a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_RGC: 11652a485ad7SGavin Shan pr_info("P7IOC diag-data for RGC\n\n"); 11662a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 11672a485ad7SGavin Shan if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 11682a485ad7SGavin Shan pr_info(" RGC: %016llx %016llx\n", 11692a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcStatus), 11702a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcLdcp)); 11712a485ad7SGavin Shan break; 11722a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_BI: 11732a485ad7SGavin Shan pr_info("P7IOC diag-data for BI %s\n\n", 11742a485ad7SGavin Shan data->bi.biDownbound ? "Downbound" : "Upbound"); 11752a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 11762a485ad7SGavin Shan if (data->bi.biLdcp0 || data->bi.biLdcp1 || 11772a485ad7SGavin Shan data->bi.biLdcp2 || data->bi.biFenceStatus) 11782a485ad7SGavin Shan pr_info(" BI: %016llx %016llx %016llx %016llx\n", 11792a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp0), 11802a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp1), 11812a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp2), 11822a485ad7SGavin Shan be64_to_cpu(data->bi.biFenceStatus)); 11832a485ad7SGavin Shan break; 11842a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_CI: 11852a485ad7SGavin Shan pr_info("P7IOC diag-data for CI Port %d\n\n", 11862a485ad7SGavin Shan data->ci.ciPort); 11872a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 11882a485ad7SGavin Shan if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 11892a485ad7SGavin Shan pr_info(" CI: %016llx %016llx\n", 11902a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortStatus), 11912a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortLdcp)); 11922a485ad7SGavin Shan break; 11932a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_MISC: 11942a485ad7SGavin Shan pr_info("P7IOC diag-data for MISC\n\n"); 11952a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 11962a485ad7SGavin Shan break; 11972a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_I2C: 11982a485ad7SGavin Shan pr_info("P7IOC diag-data for I2C\n\n"); 11992a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 12002a485ad7SGavin Shan break; 12012a485ad7SGavin Shan default: 12022a485ad7SGavin Shan pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 12032a485ad7SGavin Shan __func__, phb->hub_id, data->type); 12042a485ad7SGavin Shan } 12052a485ad7SGavin Shan } 12062a485ad7SGavin Shan 12072a485ad7SGavin Shan static int pnv_eeh_get_pe(struct pci_controller *hose, 12082a485ad7SGavin Shan u16 pe_no, struct eeh_pe **pe) 12092a485ad7SGavin Shan { 12102a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 12112a485ad7SGavin Shan struct pnv_ioda_pe *pnv_pe; 12122a485ad7SGavin Shan struct eeh_pe *dev_pe; 12132a485ad7SGavin Shan struct eeh_dev edev; 12142a485ad7SGavin Shan 12152a485ad7SGavin Shan /* 12162a485ad7SGavin Shan * If PHB supports compound PE, to fetch 12172a485ad7SGavin Shan * the master PE because slave PE is invisible 12182a485ad7SGavin Shan * to EEH core. 12192a485ad7SGavin Shan */ 12202a485ad7SGavin Shan pnv_pe = &phb->ioda.pe_array[pe_no]; 12212a485ad7SGavin Shan if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 12222a485ad7SGavin Shan pnv_pe = pnv_pe->master; 12232a485ad7SGavin Shan WARN_ON(!pnv_pe || 12242a485ad7SGavin Shan !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 12252a485ad7SGavin Shan pe_no = pnv_pe->pe_number; 12262a485ad7SGavin Shan } 12272a485ad7SGavin Shan 12282a485ad7SGavin Shan /* Find the PE according to PE# */ 12292a485ad7SGavin Shan memset(&edev, 0, sizeof(struct eeh_dev)); 12302a485ad7SGavin Shan edev.phb = hose; 12312a485ad7SGavin Shan edev.pe_config_addr = pe_no; 12322a485ad7SGavin Shan dev_pe = eeh_pe_get(&edev); 12332a485ad7SGavin Shan if (!dev_pe) 12342a485ad7SGavin Shan return -EEXIST; 12352a485ad7SGavin Shan 12362a485ad7SGavin Shan /* Freeze the (compound) PE */ 12372a485ad7SGavin Shan *pe = dev_pe; 12382a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 12392a485ad7SGavin Shan phb->freeze_pe(phb, pe_no); 12402a485ad7SGavin Shan 12412a485ad7SGavin Shan /* 12422a485ad7SGavin Shan * At this point, we're sure the (compound) PE should 12432a485ad7SGavin Shan * have been frozen. However, we still need poke until 12442a485ad7SGavin Shan * hitting the frozen PE on top level. 12452a485ad7SGavin Shan */ 12462a485ad7SGavin Shan dev_pe = dev_pe->parent; 12472a485ad7SGavin Shan while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 12482a485ad7SGavin Shan int ret; 12492a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | 12502a485ad7SGavin Shan EEH_STATE_DMA_ACTIVE); 12512a485ad7SGavin Shan 12522a485ad7SGavin Shan ret = eeh_ops->get_state(dev_pe, NULL); 12532a485ad7SGavin Shan if (ret <= 0 || (ret & active_flags) == active_flags) { 12542a485ad7SGavin Shan dev_pe = dev_pe->parent; 12552a485ad7SGavin Shan continue; 12562a485ad7SGavin Shan } 12572a485ad7SGavin Shan 12582a485ad7SGavin Shan /* Frozen parent PE */ 12592a485ad7SGavin Shan *pe = dev_pe; 12602a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 12612a485ad7SGavin Shan phb->freeze_pe(phb, dev_pe->addr); 12622a485ad7SGavin Shan 12632a485ad7SGavin Shan /* Next one */ 12642a485ad7SGavin Shan dev_pe = dev_pe->parent; 12652a485ad7SGavin Shan } 12662a485ad7SGavin Shan 12672a485ad7SGavin Shan return 0; 12682a485ad7SGavin Shan } 12692a485ad7SGavin Shan 1270131c123aSGavin Shan /** 127101f3bfb7SGavin Shan * pnv_eeh_next_error - Retrieve next EEH error to handle 127229310e5eSGavin Shan * @pe: Affected PE 127329310e5eSGavin Shan * 12742a485ad7SGavin Shan * The function is expected to be called by EEH core while it gets 12752a485ad7SGavin Shan * special EEH event (without binding PE). The function calls to 12762a485ad7SGavin Shan * OPAL APIs for next error to handle. The informational error is 12772a485ad7SGavin Shan * handled internally by platform. However, the dead IOC, dead PHB, 12782a485ad7SGavin Shan * fenced PHB and frozen PE should be handled by EEH core eventually. 127929310e5eSGavin Shan */ 128001f3bfb7SGavin Shan static int pnv_eeh_next_error(struct eeh_pe **pe) 128129310e5eSGavin Shan { 128229310e5eSGavin Shan struct pci_controller *hose; 12832a485ad7SGavin Shan struct pnv_phb *phb; 12842a485ad7SGavin Shan struct eeh_pe *phb_pe, *parent_pe; 12852a485ad7SGavin Shan __be64 frozen_pe_no; 12862a485ad7SGavin Shan __be16 err_type, severity; 12872a485ad7SGavin Shan int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE); 12882a485ad7SGavin Shan long rc; 12892a485ad7SGavin Shan int state, ret = EEH_NEXT_ERR_NONE; 12902a485ad7SGavin Shan 12912a485ad7SGavin Shan /* 129279231448SAlistair Popple * While running here, it's safe to purge the event queue. The 129379231448SAlistair Popple * event should still be masked. 12942a485ad7SGavin Shan */ 12952a485ad7SGavin Shan eeh_remove_event(NULL, false); 129629310e5eSGavin Shan 129729310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 12982a485ad7SGavin Shan /* 12992a485ad7SGavin Shan * If the subordinate PCI buses of the PHB has been 13002a485ad7SGavin Shan * removed or is exactly under error recovery, we 13012a485ad7SGavin Shan * needn't take care of it any more. 13022a485ad7SGavin Shan */ 130329310e5eSGavin Shan phb = hose->private_data; 13042a485ad7SGavin Shan phb_pe = eeh_phb_pe_get(hose); 13052a485ad7SGavin Shan if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 13062a485ad7SGavin Shan continue; 13072a485ad7SGavin Shan 13082a485ad7SGavin Shan rc = opal_pci_next_error(phb->opal_id, 13092a485ad7SGavin Shan &frozen_pe_no, &err_type, &severity); 13102a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 13112a485ad7SGavin Shan pr_devel("%s: Invalid return value on " 13122a485ad7SGavin Shan "PHB#%x (0x%lx) from opal_pci_next_error", 13132a485ad7SGavin Shan __func__, hose->global_number, rc); 13142a485ad7SGavin Shan continue; 13152a485ad7SGavin Shan } 13162a485ad7SGavin Shan 13172a485ad7SGavin Shan /* If the PHB doesn't have error, stop processing */ 13182a485ad7SGavin Shan if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 13192a485ad7SGavin Shan be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 13202a485ad7SGavin Shan pr_devel("%s: No error found on PHB#%x\n", 13212a485ad7SGavin Shan __func__, hose->global_number); 13222a485ad7SGavin Shan continue; 13232a485ad7SGavin Shan } 13242a485ad7SGavin Shan 13252a485ad7SGavin Shan /* 13262a485ad7SGavin Shan * Processing the error. We're expecting the error with 13272a485ad7SGavin Shan * highest priority reported upon multiple errors on the 13282a485ad7SGavin Shan * specific PHB. 13292a485ad7SGavin Shan */ 13302a485ad7SGavin Shan pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 13312a485ad7SGavin Shan __func__, be16_to_cpu(err_type), 13322a485ad7SGavin Shan be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 13332a485ad7SGavin Shan hose->global_number); 13342a485ad7SGavin Shan switch (be16_to_cpu(err_type)) { 13352a485ad7SGavin Shan case OPAL_EEH_IOC_ERROR: 13362a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 13372a485ad7SGavin Shan pr_err("EEH: dead IOC detected\n"); 13382a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_IOC; 13392a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 13402a485ad7SGavin Shan pr_info("EEH: IOC informative error " 13412a485ad7SGavin Shan "detected\n"); 13422a485ad7SGavin Shan pnv_eeh_get_and_dump_hub_diag(hose); 13432a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 13442a485ad7SGavin Shan } 13452a485ad7SGavin Shan 13462a485ad7SGavin Shan break; 13472a485ad7SGavin Shan case OPAL_EEH_PHB_ERROR: 13482a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 13492a485ad7SGavin Shan *pe = phb_pe; 13502a485ad7SGavin Shan pr_err("EEH: dead PHB#%x detected, " 13512a485ad7SGavin Shan "location: %s\n", 13522a485ad7SGavin Shan hose->global_number, 13532a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 13542a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_PHB; 13552a485ad7SGavin Shan } else if (be16_to_cpu(severity) == 13562a485ad7SGavin Shan OPAL_EEH_SEV_PHB_FENCED) { 13572a485ad7SGavin Shan *pe = phb_pe; 13582a485ad7SGavin Shan pr_err("EEH: Fenced PHB#%x detected, " 13592a485ad7SGavin Shan "location: %s\n", 13602a485ad7SGavin Shan hose->global_number, 13612a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 13622a485ad7SGavin Shan ret = EEH_NEXT_ERR_FENCED_PHB; 13632a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 13642a485ad7SGavin Shan pr_info("EEH: PHB#%x informative error " 13652a485ad7SGavin Shan "detected, location: %s\n", 13662a485ad7SGavin Shan hose->global_number, 13672a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 13682a485ad7SGavin Shan pnv_eeh_get_phb_diag(phb_pe); 13692a485ad7SGavin Shan pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 13702a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 13712a485ad7SGavin Shan } 13722a485ad7SGavin Shan 13732a485ad7SGavin Shan break; 13742a485ad7SGavin Shan case OPAL_EEH_PE_ERROR: 13752a485ad7SGavin Shan /* 13762a485ad7SGavin Shan * If we can't find the corresponding PE, we 13772a485ad7SGavin Shan * just try to unfreeze. 13782a485ad7SGavin Shan */ 13792a485ad7SGavin Shan if (pnv_eeh_get_pe(hose, 13802a485ad7SGavin Shan be64_to_cpu(frozen_pe_no), pe)) { 13812a485ad7SGavin Shan pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 13820f36db77SGavin Shan hose->global_number, be64_to_cpu(frozen_pe_no)); 13832a485ad7SGavin Shan pr_info("EEH: PHB location: %s\n", 13842a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 138579cd9520SGavin Shan 138679cd9520SGavin Shan /* Dump PHB diag-data */ 138779cd9520SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, 138879cd9520SGavin Shan phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE); 138979cd9520SGavin Shan if (rc == OPAL_SUCCESS) 139079cd9520SGavin Shan pnv_pci_dump_phb_diag_data(hose, 139179cd9520SGavin Shan phb->diag.blob); 139279cd9520SGavin Shan 139379cd9520SGavin Shan /* Try best to clear it */ 13942a485ad7SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 13952a485ad7SGavin Shan frozen_pe_no, 13962a485ad7SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 13972a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 13982a485ad7SGavin Shan } else if ((*pe)->state & EEH_PE_ISOLATED || 13992a485ad7SGavin Shan eeh_pe_passed(*pe)) { 14002a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 14012a485ad7SGavin Shan } else { 14022a485ad7SGavin Shan pr_err("EEH: Frozen PE#%x " 14032a485ad7SGavin Shan "on PHB#%x detected\n", 14042a485ad7SGavin Shan (*pe)->addr, 14052a485ad7SGavin Shan (*pe)->phb->global_number); 14062a485ad7SGavin Shan pr_err("EEH: PE location: %s, " 14072a485ad7SGavin Shan "PHB location: %s\n", 14082a485ad7SGavin Shan eeh_pe_loc_get(*pe), 14092a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14102a485ad7SGavin Shan ret = EEH_NEXT_ERR_FROZEN_PE; 14112a485ad7SGavin Shan } 14122a485ad7SGavin Shan 14132a485ad7SGavin Shan break; 14142a485ad7SGavin Shan default: 14152a485ad7SGavin Shan pr_warn("%s: Unexpected error type %d\n", 14162a485ad7SGavin Shan __func__, be16_to_cpu(err_type)); 14172a485ad7SGavin Shan } 14182a485ad7SGavin Shan 14192a485ad7SGavin Shan /* 14202a485ad7SGavin Shan * EEH core will try recover from fenced PHB or 14212a485ad7SGavin Shan * frozen PE. In the time for frozen PE, EEH core 14222a485ad7SGavin Shan * enable IO path for that before collecting logs, 14232a485ad7SGavin Shan * but it ruins the site. So we have to dump the 14242a485ad7SGavin Shan * log in advance here. 14252a485ad7SGavin Shan */ 14262a485ad7SGavin Shan if ((ret == EEH_NEXT_ERR_FROZEN_PE || 14272a485ad7SGavin Shan ret == EEH_NEXT_ERR_FENCED_PHB) && 14282a485ad7SGavin Shan !((*pe)->state & EEH_PE_ISOLATED)) { 14292a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 14302a485ad7SGavin Shan pnv_eeh_get_phb_diag(*pe); 14312a485ad7SGavin Shan 14322a485ad7SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 14332a485ad7SGavin Shan pnv_pci_dump_phb_diag_data((*pe)->phb, 14342a485ad7SGavin Shan (*pe)->data); 14352a485ad7SGavin Shan } 14362a485ad7SGavin Shan 14372a485ad7SGavin Shan /* 14382a485ad7SGavin Shan * We probably have the frozen parent PE out there and 14392a485ad7SGavin Shan * we need have to handle frozen parent PE firstly. 14402a485ad7SGavin Shan */ 14412a485ad7SGavin Shan if (ret == EEH_NEXT_ERR_FROZEN_PE) { 14422a485ad7SGavin Shan parent_pe = (*pe)->parent; 14432a485ad7SGavin Shan while (parent_pe) { 14442a485ad7SGavin Shan /* Hit the ceiling ? */ 14452a485ad7SGavin Shan if (parent_pe->type & EEH_PE_PHB) 14462a485ad7SGavin Shan break; 14472a485ad7SGavin Shan 14482a485ad7SGavin Shan /* Frozen parent PE ? */ 14492a485ad7SGavin Shan state = eeh_ops->get_state(parent_pe, NULL); 14502a485ad7SGavin Shan if (state > 0 && 14512a485ad7SGavin Shan (state & active_flags) != active_flags) 14522a485ad7SGavin Shan *pe = parent_pe; 14532a485ad7SGavin Shan 14542a485ad7SGavin Shan /* Next parent level */ 14552a485ad7SGavin Shan parent_pe = parent_pe->parent; 14562a485ad7SGavin Shan } 14572a485ad7SGavin Shan 14582a485ad7SGavin Shan /* We possibly migrate to another PE */ 14592a485ad7SGavin Shan eeh_pe_state_mark(*pe, EEH_PE_ISOLATED); 14602a485ad7SGavin Shan } 14612a485ad7SGavin Shan 14622a485ad7SGavin Shan /* 14632a485ad7SGavin Shan * If we have no errors on the specific PHB or only 14642a485ad7SGavin Shan * informative error there, we continue poking it. 14652a485ad7SGavin Shan * Otherwise, we need actions to be taken by upper 14662a485ad7SGavin Shan * layer. 14672a485ad7SGavin Shan */ 14682a485ad7SGavin Shan if (ret > EEH_NEXT_ERR_INF) 146929310e5eSGavin Shan break; 147029310e5eSGavin Shan } 147129310e5eSGavin Shan 147279231448SAlistair Popple /* Unmask the event */ 1473b8d65e96SAlistair Popple if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 147479231448SAlistair Popple enable_irq(eeh_event_irq); 147579231448SAlistair Popple 14762a485ad7SGavin Shan return ret; 147729310e5eSGavin Shan } 147829310e5eSGavin Shan 14790bd78587SGavin Shan static int pnv_eeh_restore_config(struct pci_dn *pdn) 14809be3beccSGavin Shan { 14810bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 14829be3beccSGavin Shan struct pnv_phb *phb; 14839be3beccSGavin Shan s64 ret; 14849be3beccSGavin Shan 14859be3beccSGavin Shan if (!edev) 14869be3beccSGavin Shan return -EEXIST; 14879be3beccSGavin Shan 14889be3beccSGavin Shan phb = edev->phb->private_data; 14899be3beccSGavin Shan ret = opal_pci_reinit(phb->opal_id, 14909be3beccSGavin Shan OPAL_REINIT_PCI_DEV, edev->config_addr); 14919be3beccSGavin Shan if (ret) { 14929be3beccSGavin Shan pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 14939be3beccSGavin Shan __func__, edev->config_addr, ret); 14949be3beccSGavin Shan return -EIO; 14959be3beccSGavin Shan } 14969be3beccSGavin Shan 14979be3beccSGavin Shan return 0; 14989be3beccSGavin Shan } 14999be3beccSGavin Shan 150001f3bfb7SGavin Shan static struct eeh_ops pnv_eeh_ops = { 150129310e5eSGavin Shan .name = "powernv", 150201f3bfb7SGavin Shan .init = pnv_eeh_init, 150301f3bfb7SGavin Shan .post_init = pnv_eeh_post_init, 1504ff57b454SGavin Shan .probe = pnv_eeh_probe, 150501f3bfb7SGavin Shan .set_option = pnv_eeh_set_option, 150601f3bfb7SGavin Shan .get_pe_addr = pnv_eeh_get_pe_addr, 150701f3bfb7SGavin Shan .get_state = pnv_eeh_get_state, 150801f3bfb7SGavin Shan .reset = pnv_eeh_reset, 150901f3bfb7SGavin Shan .wait_state = pnv_eeh_wait_state, 151001f3bfb7SGavin Shan .get_log = pnv_eeh_get_log, 151101f3bfb7SGavin Shan .configure_bridge = pnv_eeh_configure_bridge, 151201f3bfb7SGavin Shan .err_inject = pnv_eeh_err_inject, 151301f3bfb7SGavin Shan .read_config = pnv_eeh_read_config, 151401f3bfb7SGavin Shan .write_config = pnv_eeh_write_config, 151501f3bfb7SGavin Shan .next_error = pnv_eeh_next_error, 151601f3bfb7SGavin Shan .restore_config = pnv_eeh_restore_config 151729310e5eSGavin Shan }; 151829310e5eSGavin Shan 151929310e5eSGavin Shan /** 152029310e5eSGavin Shan * eeh_powernv_init - Register platform dependent EEH operations 152129310e5eSGavin Shan * 152229310e5eSGavin Shan * EEH initialization on powernv platform. This function should be 152329310e5eSGavin Shan * called before any EEH related functions. 152429310e5eSGavin Shan */ 152529310e5eSGavin Shan static int __init eeh_powernv_init(void) 152629310e5eSGavin Shan { 152729310e5eSGavin Shan int ret = -EINVAL; 152829310e5eSGavin Shan 1529bb593c00SGavin Shan eeh_set_pe_aux_size(PNV_PCI_DIAG_BUF_SIZE); 153001f3bfb7SGavin Shan ret = eeh_ops_register(&pnv_eeh_ops); 153129310e5eSGavin Shan if (!ret) 153229310e5eSGavin Shan pr_info("EEH: PowerNV platform initialized\n"); 153329310e5eSGavin Shan else 153429310e5eSGavin Shan pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 153529310e5eSGavin Shan 153629310e5eSGavin Shan return ret; 153729310e5eSGavin Shan } 1538b14726c5SMichael Ellerman machine_early_initcall(powernv, eeh_powernv_init); 1539