12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 229310e5eSGavin Shan /* 329310e5eSGavin Shan * The file intends to implement the platform dependent EEH operations on 429310e5eSGavin Shan * powernv platform. Actually, the powernv was created in order to fully 529310e5eSGavin Shan * hypervisor support. 629310e5eSGavin Shan * 729310e5eSGavin Shan * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 829310e5eSGavin Shan */ 929310e5eSGavin Shan 1029310e5eSGavin Shan #include <linux/atomic.h> 114cf17445SGavin Shan #include <linux/debugfs.h> 1229310e5eSGavin Shan #include <linux/delay.h> 1329310e5eSGavin Shan #include <linux/export.h> 1429310e5eSGavin Shan #include <linux/init.h> 1579231448SAlistair Popple #include <linux/interrupt.h> 1629310e5eSGavin Shan #include <linux/list.h> 1729310e5eSGavin Shan #include <linux/msi.h> 1829310e5eSGavin Shan #include <linux/of.h> 1929310e5eSGavin Shan #include <linux/pci.h> 2029310e5eSGavin Shan #include <linux/proc_fs.h> 2129310e5eSGavin Shan #include <linux/rbtree.h> 2229310e5eSGavin Shan #include <linux/sched.h> 2329310e5eSGavin Shan #include <linux/seq_file.h> 2429310e5eSGavin Shan #include <linux/spinlock.h> 2529310e5eSGavin Shan 2629310e5eSGavin Shan #include <asm/eeh.h> 2729310e5eSGavin Shan #include <asm/eeh_event.h> 2829310e5eSGavin Shan #include <asm/firmware.h> 2929310e5eSGavin Shan #include <asm/io.h> 3029310e5eSGavin Shan #include <asm/iommu.h> 3129310e5eSGavin Shan #include <asm/machdep.h> 3229310e5eSGavin Shan #include <asm/msi_bitmap.h> 3329310e5eSGavin Shan #include <asm/opal.h> 3429310e5eSGavin Shan #include <asm/ppc-pci.h> 359c0e1ecbSGavin Shan #include <asm/pnv-pci.h> 3629310e5eSGavin Shan 3729310e5eSGavin Shan #include "powernv.h" 3829310e5eSGavin Shan #include "pci.h" 3929310e5eSGavin Shan 4079231448SAlistair Popple static int eeh_event_irq = -EINVAL; 414cf17445SGavin Shan 42988fc3baSBryant G. Ly void pnv_pcibios_bus_add_device(struct pci_dev *pdev) 43988fc3baSBryant G. Ly { 44988fc3baSBryant G. Ly struct pci_dn *pdn = pci_get_pdn(pdev); 45988fc3baSBryant G. Ly 46988fc3baSBryant G. Ly if (!pdev->is_virtfn) 47988fc3baSBryant G. Ly return; 48988fc3baSBryant G. Ly 49988fc3baSBryant G. Ly /* 50988fc3baSBryant G. Ly * The following operations will fail if VF's sysfs files 51988fc3baSBryant G. Ly * aren't created or its resources aren't finalized. 52988fc3baSBryant G. Ly */ 53988fc3baSBryant G. Ly eeh_add_device_early(pdn); 54988fc3baSBryant G. Ly eeh_add_device_late(pdev); 55988fc3baSBryant G. Ly eeh_sysfs_add_device(pdev); 56988fc3baSBryant G. Ly } 57988fc3baSBryant G. Ly 5801f3bfb7SGavin Shan static int pnv_eeh_init(void) 5929310e5eSGavin Shan { 60dc561fb9SGavin Shan struct pci_controller *hose; 61dc561fb9SGavin Shan struct pnv_phb *phb; 625cb1f8fdSRussell Currey int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 63dc561fb9SGavin Shan 64e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 65e4d54f71SStewart Smith pr_warn("%s: OPAL is required !\n", 660dae2743SGavin Shan __func__); 6729310e5eSGavin Shan return -EINVAL; 6829310e5eSGavin Shan } 6929310e5eSGavin Shan 7005b1721dSGavin Shan /* Set probe mode */ 7105b1721dSGavin Shan eeh_add_flag(EEH_PROBE_MODE_DEV); 7229310e5eSGavin Shan 73dc561fb9SGavin Shan /* 74dc561fb9SGavin Shan * P7IOC blocks PCI config access to frozen PE, but PHB3 75dc561fb9SGavin Shan * doesn't do that. So we have to selectively enable I/O 76dc561fb9SGavin Shan * prior to collecting error log. 77dc561fb9SGavin Shan */ 78dc561fb9SGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 79dc561fb9SGavin Shan phb = hose->private_data; 80dc561fb9SGavin Shan 81dc561fb9SGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC) 82dc561fb9SGavin Shan eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 832aa5cf9eSGavin Shan 845cb1f8fdSRussell Currey if (phb->diag_data_size > max_diag_size) 855cb1f8fdSRussell Currey max_diag_size = phb->diag_data_size; 865cb1f8fdSRussell Currey 872aa5cf9eSGavin Shan /* 882aa5cf9eSGavin Shan * PE#0 should be regarded as valid by EEH core 892aa5cf9eSGavin Shan * if it's not the reserved one. Currently, we 90608fb9c2SGavin Shan * have the reserved PE#255 and PE#127 for PHB3 912aa5cf9eSGavin Shan * and P7IOC separately. So we should regard 92608fb9c2SGavin Shan * PE#0 as valid for PHB3 and P7IOC. 932aa5cf9eSGavin Shan */ 9492b8f137SGavin Shan if (phb->ioda.reserved_pe_idx != 0) 952aa5cf9eSGavin Shan eeh_add_flag(EEH_VALID_PE_ZERO); 962aa5cf9eSGavin Shan 97dc561fb9SGavin Shan break; 98dc561fb9SGavin Shan } 99dc561fb9SGavin Shan 1005cb1f8fdSRussell Currey eeh_set_pe_aux_size(max_diag_size); 101988fc3baSBryant G. Ly ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device; 1025cb1f8fdSRussell Currey 10329310e5eSGavin Shan return 0; 10429310e5eSGavin Shan } 10529310e5eSGavin Shan 10679231448SAlistair Popple static irqreturn_t pnv_eeh_event(int irq, void *data) 1074cf17445SGavin Shan { 1084cf17445SGavin Shan /* 10979231448SAlistair Popple * We simply send a special EEH event if EEH has been 11079231448SAlistair Popple * enabled. We don't care about EEH events until we've 11179231448SAlistair Popple * finished processing the outstanding ones. Event processing 11279231448SAlistair Popple * gets unmasked in next_error() if EEH is enabled. 1134cf17445SGavin Shan */ 11479231448SAlistair Popple disable_irq_nosync(irq); 1154cf17445SGavin Shan 1164cf17445SGavin Shan if (eeh_enabled()) 1174cf17445SGavin Shan eeh_send_failure_event(NULL); 1184cf17445SGavin Shan 11979231448SAlistair Popple return IRQ_HANDLED; 1204cf17445SGavin Shan } 1214cf17445SGavin Shan 1224cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 1234cf17445SGavin Shan static ssize_t pnv_eeh_ei_write(struct file *filp, 1244cf17445SGavin Shan const char __user *user_buf, 1254cf17445SGavin Shan size_t count, loff_t *ppos) 1264cf17445SGavin Shan { 1274cf17445SGavin Shan struct pci_controller *hose = filp->private_data; 1284cf17445SGavin Shan struct eeh_pe *pe; 1294cf17445SGavin Shan int pe_no, type, func; 1304cf17445SGavin Shan unsigned long addr, mask; 1314cf17445SGavin Shan char buf[50]; 1324cf17445SGavin Shan int ret; 1334cf17445SGavin Shan 1344cf17445SGavin Shan if (!eeh_ops || !eeh_ops->err_inject) 1354cf17445SGavin Shan return -ENXIO; 1364cf17445SGavin Shan 1374cf17445SGavin Shan /* Copy over argument buffer */ 1384cf17445SGavin Shan ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 1394cf17445SGavin Shan if (!ret) 1404cf17445SGavin Shan return -EFAULT; 1414cf17445SGavin Shan 1424cf17445SGavin Shan /* Retrieve parameters */ 1434cf17445SGavin Shan ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 1444cf17445SGavin Shan &pe_no, &type, &func, &addr, &mask); 1454cf17445SGavin Shan if (ret != 5) 1464cf17445SGavin Shan return -EINVAL; 1474cf17445SGavin Shan 1484cf17445SGavin Shan /* Retrieve PE */ 1498bae6a23SAlexey Kardashevskiy pe = eeh_pe_get(hose, pe_no, 0); 1504cf17445SGavin Shan if (!pe) 1514cf17445SGavin Shan return -ENODEV; 1524cf17445SGavin Shan 1534cf17445SGavin Shan /* Do error injection */ 1544cf17445SGavin Shan ret = eeh_ops->err_inject(pe, type, func, addr, mask); 1554cf17445SGavin Shan return ret < 0 ? ret : count; 1564cf17445SGavin Shan } 1574cf17445SGavin Shan 1584cf17445SGavin Shan static const struct file_operations pnv_eeh_ei_fops = { 1594cf17445SGavin Shan .open = simple_open, 1604cf17445SGavin Shan .llseek = no_llseek, 1614cf17445SGavin Shan .write = pnv_eeh_ei_write, 1624cf17445SGavin Shan }; 1634cf17445SGavin Shan 1644cf17445SGavin Shan static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 1654cf17445SGavin Shan { 1664cf17445SGavin Shan struct pci_controller *hose = data; 1674cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1684cf17445SGavin Shan 1694cf17445SGavin Shan out_be64(phb->regs + offset, val); 1704cf17445SGavin Shan return 0; 1714cf17445SGavin Shan } 1724cf17445SGavin Shan 1734cf17445SGavin Shan static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 1744cf17445SGavin Shan { 1754cf17445SGavin Shan struct pci_controller *hose = data; 1764cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1774cf17445SGavin Shan 1784cf17445SGavin Shan *val = in_be64(phb->regs + offset); 1794cf17445SGavin Shan return 0; 1804cf17445SGavin Shan } 1814cf17445SGavin Shan 182ccc9662dSGavin Shan #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 183ccc9662dSGavin Shan static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 184ccc9662dSGavin Shan { \ 185ccc9662dSGavin Shan return pnv_eeh_dbgfs_set(data, reg, val); \ 186ccc9662dSGavin Shan } \ 187ccc9662dSGavin Shan \ 188ccc9662dSGavin Shan static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 189ccc9662dSGavin Shan { \ 190ccc9662dSGavin Shan return pnv_eeh_dbgfs_get(data, reg, val); \ 191ccc9662dSGavin Shan } \ 192ccc9662dSGavin Shan \ 193ccc9662dSGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 194ccc9662dSGavin Shan pnv_eeh_dbgfs_get_##name, \ 195ccc9662dSGavin Shan pnv_eeh_dbgfs_set_##name, \ 196ccc9662dSGavin Shan "0x%llx\n") 1974cf17445SGavin Shan 198ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 199ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 200ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 2014cf17445SGavin Shan 2024cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 2034cf17445SGavin Shan 20429310e5eSGavin Shan /** 20501f3bfb7SGavin Shan * pnv_eeh_post_init - EEH platform dependent post initialization 20629310e5eSGavin Shan * 20729310e5eSGavin Shan * EEH platform dependent post initialization on powernv. When 20829310e5eSGavin Shan * the function is called, the EEH PEs and devices should have 20929310e5eSGavin Shan * been built. If the I/O cache staff has been built, EEH is 21029310e5eSGavin Shan * ready to supply service. 21129310e5eSGavin Shan */ 212b9fde58dSBenjamin Herrenschmidt int pnv_eeh_post_init(void) 21329310e5eSGavin Shan { 21429310e5eSGavin Shan struct pci_controller *hose; 21529310e5eSGavin Shan struct pnv_phb *phb; 21629310e5eSGavin Shan int ret = 0; 21729310e5eSGavin Shan 218b9fde58dSBenjamin Herrenschmidt /* Probe devices & build address cache */ 219b9fde58dSBenjamin Herrenschmidt eeh_probe_devices(); 220b9fde58dSBenjamin Herrenschmidt eeh_addr_cache_build(); 221b9fde58dSBenjamin Herrenschmidt 2224cf17445SGavin Shan /* Register OPAL event notifier */ 22379231448SAlistair Popple eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 22479231448SAlistair Popple if (eeh_event_irq < 0) { 22579231448SAlistair Popple pr_err("%s: Can't register OPAL event interrupt (%d)\n", 22679231448SAlistair Popple __func__, eeh_event_irq); 22779231448SAlistair Popple return eeh_event_irq; 22879231448SAlistair Popple } 22979231448SAlistair Popple 23079231448SAlistair Popple ret = request_irq(eeh_event_irq, pnv_eeh_event, 23179231448SAlistair Popple IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 23279231448SAlistair Popple if (ret < 0) { 23379231448SAlistair Popple irq_dispose_mapping(eeh_event_irq); 23479231448SAlistair Popple pr_err("%s: Can't request OPAL event interrupt (%d)\n", 23579231448SAlistair Popple __func__, eeh_event_irq); 2364cf17445SGavin Shan return ret; 2374cf17445SGavin Shan } 2384cf17445SGavin Shan 23979231448SAlistair Popple if (!eeh_enabled()) 24079231448SAlistair Popple disable_irq(eeh_event_irq); 24179231448SAlistair Popple 24229310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 24329310e5eSGavin Shan phb = hose->private_data; 24429310e5eSGavin Shan 2454cf17445SGavin Shan /* 2464cf17445SGavin Shan * If EEH is enabled, we're going to rely on that. 2474cf17445SGavin Shan * Otherwise, we restore to conventional mechanism 2484cf17445SGavin Shan * to clear frozen PE during PCI config access. 2494cf17445SGavin Shan */ 2504cf17445SGavin Shan if (eeh_enabled()) 2514cf17445SGavin Shan phb->flags |= PNV_PHB_FLAG_EEH; 2524cf17445SGavin Shan else 2534cf17445SGavin Shan phb->flags &= ~PNV_PHB_FLAG_EEH; 2544cf17445SGavin Shan 2554cf17445SGavin Shan /* Create debugfs entries */ 2564cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 2574cf17445SGavin Shan if (phb->has_dbgfs || !phb->dbgfs) 2584cf17445SGavin Shan continue; 2594cf17445SGavin Shan 2604cf17445SGavin Shan phb->has_dbgfs = 1; 2614cf17445SGavin Shan debugfs_create_file("err_injct", 0200, 2624cf17445SGavin Shan phb->dbgfs, hose, 2634cf17445SGavin Shan &pnv_eeh_ei_fops); 2644cf17445SGavin Shan 2654cf17445SGavin Shan debugfs_create_file("err_injct_outbound", 0600, 2664cf17445SGavin Shan phb->dbgfs, hose, 267ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_outb); 2684cf17445SGavin Shan debugfs_create_file("err_injct_inboundA", 0600, 2694cf17445SGavin Shan phb->dbgfs, hose, 270ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbA); 2714cf17445SGavin Shan debugfs_create_file("err_injct_inboundB", 0600, 2724cf17445SGavin Shan phb->dbgfs, hose, 273ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbB); 2744cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 27529310e5eSGavin Shan } 2764cf17445SGavin Shan 27729310e5eSGavin Shan return ret; 27829310e5eSGavin Shan } 27929310e5eSGavin Shan 2804d6186caSGavin Shan static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 281ff57b454SGavin Shan { 2824d6186caSGavin Shan int pos = PCI_CAPABILITY_LIST; 2834d6186caSGavin Shan int cnt = 48; /* Maximal number of capabilities */ 2844d6186caSGavin Shan u32 status, id; 285ff57b454SGavin Shan 286ff57b454SGavin Shan if (!pdn) 287ff57b454SGavin Shan return 0; 288ff57b454SGavin Shan 2894d6186caSGavin Shan /* Check if the device supports capabilities */ 290ff57b454SGavin Shan pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 291ff57b454SGavin Shan if (!(status & PCI_STATUS_CAP_LIST)) 292ff57b454SGavin Shan return 0; 293ff57b454SGavin Shan 294ff57b454SGavin Shan while (cnt--) { 295ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos, 1, &pos); 296ff57b454SGavin Shan if (pos < 0x40) 297ff57b454SGavin Shan break; 298ff57b454SGavin Shan 299ff57b454SGavin Shan pos &= ~3; 300ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 301ff57b454SGavin Shan if (id == 0xff) 302ff57b454SGavin Shan break; 303ff57b454SGavin Shan 304ff57b454SGavin Shan /* Found */ 305ff57b454SGavin Shan if (id == cap) 306ff57b454SGavin Shan return pos; 307ff57b454SGavin Shan 308ff57b454SGavin Shan /* Next one */ 309ff57b454SGavin Shan pos += PCI_CAP_LIST_NEXT; 310ff57b454SGavin Shan } 311ff57b454SGavin Shan 312ff57b454SGavin Shan return 0; 313ff57b454SGavin Shan } 314ff57b454SGavin Shan 315ff57b454SGavin Shan static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 316ff57b454SGavin Shan { 317ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 318ff57b454SGavin Shan u32 header; 319ff57b454SGavin Shan int pos = 256, ttl = (4096 - 256) / 8; 320ff57b454SGavin Shan 321ff57b454SGavin Shan if (!edev || !edev->pcie_cap) 322ff57b454SGavin Shan return 0; 323ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 324ff57b454SGavin Shan return 0; 325ff57b454SGavin Shan else if (!header) 326ff57b454SGavin Shan return 0; 327ff57b454SGavin Shan 328ff57b454SGavin Shan while (ttl-- > 0) { 329ff57b454SGavin Shan if (PCI_EXT_CAP_ID(header) == cap && pos) 330ff57b454SGavin Shan return pos; 331ff57b454SGavin Shan 332ff57b454SGavin Shan pos = PCI_EXT_CAP_NEXT(header); 333ff57b454SGavin Shan if (pos < 256) 334ff57b454SGavin Shan break; 335ff57b454SGavin Shan 336ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 337ff57b454SGavin Shan break; 338ff57b454SGavin Shan } 339ff57b454SGavin Shan 340ff57b454SGavin Shan return 0; 341ff57b454SGavin Shan } 342ff57b454SGavin Shan 34329310e5eSGavin Shan /** 344ff57b454SGavin Shan * pnv_eeh_probe - Do probe on PCI device 345ff57b454SGavin Shan * @pdn: PCI device node 346ff57b454SGavin Shan * @data: unused 34729310e5eSGavin Shan * 34829310e5eSGavin Shan * When EEH module is installed during system boot, all PCI devices 34929310e5eSGavin Shan * are checked one by one to see if it supports EEH. The function 35029310e5eSGavin Shan * is introduced for the purpose. By default, EEH has been enabled 35129310e5eSGavin Shan * on all PCI devices. That's to say, we only need do necessary 35229310e5eSGavin Shan * initialization on the corresponding eeh device and create PE 35329310e5eSGavin Shan * accordingly. 35429310e5eSGavin Shan * 35529310e5eSGavin Shan * It's notable that's unsafe to retrieve the EEH device through 35629310e5eSGavin Shan * the corresponding PCI device. During the PCI device hotplug, which 35729310e5eSGavin Shan * was possiblly triggered by EEH core, the binding between EEH device 35829310e5eSGavin Shan * and the PCI device isn't built yet. 35929310e5eSGavin Shan */ 360ff57b454SGavin Shan static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 36129310e5eSGavin Shan { 362ff57b454SGavin Shan struct pci_controller *hose = pdn->phb; 36329310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 364ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 365ff57b454SGavin Shan uint32_t pcie_flags; 366dadcd6d6SMike Qiu int ret; 367405b33a7SAlexey Kardashevskiy int config_addr = (pdn->busno << 8) | (pdn->devfn); 36829310e5eSGavin Shan 36929310e5eSGavin Shan /* 37029310e5eSGavin Shan * When probing the root bridge, which doesn't have any 37129310e5eSGavin Shan * subordinate PCI devices. We don't have OF node for 37229310e5eSGavin Shan * the root bridge. So it's not reasonable to continue 37329310e5eSGavin Shan * the probing. 37429310e5eSGavin Shan */ 375ff57b454SGavin Shan if (!edev || edev->pe) 376ff57b454SGavin Shan return NULL; 37729310e5eSGavin Shan 37829310e5eSGavin Shan /* Skip for PCI-ISA bridge */ 379ff57b454SGavin Shan if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 380ff57b454SGavin Shan return NULL; 38129310e5eSGavin Shan 38229310e5eSGavin Shan /* Initialize eeh device */ 383ff57b454SGavin Shan edev->class_code = pdn->class_code; 384ab55d218SGavin Shan edev->mode &= 0xFFFFFF00; 385ff57b454SGavin Shan edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 386ff57b454SGavin Shan edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 3879312bc5bSWei Yang edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 388ff57b454SGavin Shan edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 389ff57b454SGavin Shan if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 3904b83bd45SGavin Shan edev->mode |= EEH_DEV_BRIDGE; 391ff57b454SGavin Shan if (edev->pcie_cap) { 392ff57b454SGavin Shan pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 393ff57b454SGavin Shan 2, &pcie_flags); 394ff57b454SGavin Shan pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 395ff57b454SGavin Shan if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 3964b83bd45SGavin Shan edev->mode |= EEH_DEV_ROOT_PORT; 397ff57b454SGavin Shan else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 3984b83bd45SGavin Shan edev->mode |= EEH_DEV_DS_PORT; 399ff57b454SGavin Shan } 4004b83bd45SGavin Shan } 4014b83bd45SGavin Shan 402405b33a7SAlexey Kardashevskiy edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; 40329310e5eSGavin Shan 40429310e5eSGavin Shan /* Create PE */ 405dadcd6d6SMike Qiu ret = eeh_add_to_parent_pe(edev); 406dadcd6d6SMike Qiu if (ret) { 4071f52f176SRussell Currey pr_warn("%s: Can't add PCI dev %04x:%02x:%02x.%01x to parent PE (%x)\n", 408ff57b454SGavin Shan __func__, hose->global_number, pdn->busno, 409ff57b454SGavin Shan PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn), ret); 410ff57b454SGavin Shan return NULL; 411dadcd6d6SMike Qiu } 412dadcd6d6SMike Qiu 413dadcd6d6SMike Qiu /* 414b6541db1SGavin Shan * If the PE contains any one of following adapters, the 415b6541db1SGavin Shan * PCI config space can't be accessed when dumping EEH log. 416b6541db1SGavin Shan * Otherwise, we will run into fenced PHB caused by shortage 417b6541db1SGavin Shan * of outbound credits in the adapter. The PCI config access 418b6541db1SGavin Shan * should be blocked until PE reset. MMIO access is dropped 419b6541db1SGavin Shan * by hardware certainly. In order to drop PCI config requests, 420b6541db1SGavin Shan * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 421b6541db1SGavin Shan * will be checked in the backend for PE state retrival. If 422b6541db1SGavin Shan * the PE becomes frozen for the first time and the flag has 423b6541db1SGavin Shan * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 424b6541db1SGavin Shan * that PE to block its config space. 425b6541db1SGavin Shan * 426c374ed27SGavin Shan * Broadcom BCM5718 2-ports NICs (14e4:1656) 427b6541db1SGavin Shan * Broadcom Austin 4-ports NICs (14e4:1657) 428353169acSGavin Shan * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 429179ea48bSGavin Shan * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 430b6541db1SGavin Shan */ 431ff57b454SGavin Shan if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 432c374ed27SGavin Shan pdn->device_id == 0x1656) || 433c374ed27SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 434ff57b454SGavin Shan pdn->device_id == 0x1657) || 435ff57b454SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 436353169acSGavin Shan pdn->device_id == 0x168a) || 437353169acSGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 438ff57b454SGavin Shan pdn->device_id == 0x168e)) 439b6541db1SGavin Shan edev->pe->state |= EEH_PE_CFG_RESTRICTED; 440b6541db1SGavin Shan 441b6541db1SGavin Shan /* 442dadcd6d6SMike Qiu * Cache the PE primary bus, which can't be fetched when 443dadcd6d6SMike Qiu * full hotplug is in progress. In that case, all child 444dadcd6d6SMike Qiu * PCI devices of the PE are expected to be removed prior 445dadcd6d6SMike Qiu * to PE reset. 446dadcd6d6SMike Qiu */ 44705ba75f8SGavin Shan if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 448ff57b454SGavin Shan edev->pe->bus = pci_find_bus(hose->global_number, 449ff57b454SGavin Shan pdn->busno); 45005ba75f8SGavin Shan if (edev->pe->bus) 45105ba75f8SGavin Shan edev->pe->state |= EEH_PE_PRI_BUS; 45205ba75f8SGavin Shan } 45329310e5eSGavin Shan 45429310e5eSGavin Shan /* 45529310e5eSGavin Shan * Enable EEH explicitly so that we will do EEH check 45629310e5eSGavin Shan * while accessing I/O stuff 45729310e5eSGavin Shan */ 45805b1721dSGavin Shan eeh_add_flag(EEH_ENABLED); 45929310e5eSGavin Shan 46029310e5eSGavin Shan /* Save memory bars */ 46129310e5eSGavin Shan eeh_save_bars(edev); 46229310e5eSGavin Shan 463ff57b454SGavin Shan return NULL; 46429310e5eSGavin Shan } 46529310e5eSGavin Shan 46629310e5eSGavin Shan /** 46701f3bfb7SGavin Shan * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 46829310e5eSGavin Shan * @pe: EEH PE 46929310e5eSGavin Shan * @option: operation to be issued 47029310e5eSGavin Shan * 47129310e5eSGavin Shan * The function is used to control the EEH functionality globally. 47229310e5eSGavin Shan * Currently, following options are support according to PAPR: 47329310e5eSGavin Shan * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 47429310e5eSGavin Shan */ 47501f3bfb7SGavin Shan static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 47629310e5eSGavin Shan { 47729310e5eSGavin Shan struct pci_controller *hose = pe->phb; 47829310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 4797e3e4f8dSGavin Shan bool freeze_pe = false; 480f9433718SGavin Shan int opt; 4817e3e4f8dSGavin Shan s64 rc; 48229310e5eSGavin Shan 4837e3e4f8dSGavin Shan switch (option) { 4847e3e4f8dSGavin Shan case EEH_OPT_DISABLE: 4857e3e4f8dSGavin Shan return -EPERM; 4867e3e4f8dSGavin Shan case EEH_OPT_ENABLE: 4877e3e4f8dSGavin Shan return 0; 4887e3e4f8dSGavin Shan case EEH_OPT_THAW_MMIO: 4897e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 4907e3e4f8dSGavin Shan break; 4917e3e4f8dSGavin Shan case EEH_OPT_THAW_DMA: 4927e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 4937e3e4f8dSGavin Shan break; 4947e3e4f8dSGavin Shan case EEH_OPT_FREEZE_PE: 4957e3e4f8dSGavin Shan freeze_pe = true; 4967e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 4977e3e4f8dSGavin Shan break; 4987e3e4f8dSGavin Shan default: 4997e3e4f8dSGavin Shan pr_warn("%s: Invalid option %d\n", __func__, option); 5007e3e4f8dSGavin Shan return -EINVAL; 5017e3e4f8dSGavin Shan } 5027e3e4f8dSGavin Shan 503f9433718SGavin Shan /* Freeze master and slave PEs if PHB supports compound PEs */ 5047e3e4f8dSGavin Shan if (freeze_pe) { 5057e3e4f8dSGavin Shan if (phb->freeze_pe) { 5067e3e4f8dSGavin Shan phb->freeze_pe(phb, pe->addr); 507f9433718SGavin Shan return 0; 5087e3e4f8dSGavin Shan } 50929310e5eSGavin Shan 510f9433718SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 511f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 512f9433718SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 513f9433718SGavin Shan __func__, rc, phb->hose->global_number, 514f9433718SGavin Shan pe->addr); 515f9433718SGavin Shan return -EIO; 516f9433718SGavin Shan } 517f9433718SGavin Shan 518f9433718SGavin Shan return 0; 519f9433718SGavin Shan } 520f9433718SGavin Shan 521f9433718SGavin Shan /* Unfreeze master and slave PEs if PHB supports */ 522f9433718SGavin Shan if (phb->unfreeze_pe) 523f9433718SGavin Shan return phb->unfreeze_pe(phb, pe->addr, opt); 524f9433718SGavin Shan 525f9433718SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 526f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 527f9433718SGavin Shan pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 528f9433718SGavin Shan __func__, rc, option, phb->hose->global_number, 529f9433718SGavin Shan pe->addr); 530f9433718SGavin Shan return -EIO; 531f9433718SGavin Shan } 532f9433718SGavin Shan 533f9433718SGavin Shan return 0; 53429310e5eSGavin Shan } 53529310e5eSGavin Shan 53629310e5eSGavin Shan /** 53701f3bfb7SGavin Shan * pnv_eeh_get_pe_addr - Retrieve PE address 53829310e5eSGavin Shan * @pe: EEH PE 53929310e5eSGavin Shan * 54029310e5eSGavin Shan * Retrieve the PE address according to the given tranditional 54129310e5eSGavin Shan * PCI BDF (Bus/Device/Function) address. 54229310e5eSGavin Shan */ 54301f3bfb7SGavin Shan static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 54429310e5eSGavin Shan { 54529310e5eSGavin Shan return pe->addr; 54629310e5eSGavin Shan } 54729310e5eSGavin Shan 54840ae5f69SGavin Shan static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 54940ae5f69SGavin Shan { 55040ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 55140ae5f69SGavin Shan s64 rc; 55240ae5f69SGavin Shan 55340ae5f69SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 5545cb1f8fdSRussell Currey phb->diag_data_size); 55540ae5f69SGavin Shan if (rc != OPAL_SUCCESS) 55640ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 55740ae5f69SGavin Shan __func__, rc, pe->phb->global_number); 55840ae5f69SGavin Shan } 55940ae5f69SGavin Shan 56040ae5f69SGavin Shan static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 56140ae5f69SGavin Shan { 56240ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 563c2057701SAlexey Kardashevskiy u8 fstate = 0; 564c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 56540ae5f69SGavin Shan s64 rc; 56640ae5f69SGavin Shan int result = 0; 56740ae5f69SGavin Shan 56840ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 56940ae5f69SGavin Shan pe->addr, 57040ae5f69SGavin Shan &fstate, 57140ae5f69SGavin Shan &pcierr, 57240ae5f69SGavin Shan NULL); 57340ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 57440ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x state\n", 57540ae5f69SGavin Shan __func__, rc, phb->hose->global_number); 57640ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 57740ae5f69SGavin Shan } 57840ae5f69SGavin Shan 57940ae5f69SGavin Shan /* 58040ae5f69SGavin Shan * Check PHB state. If the PHB is frozen for the 58140ae5f69SGavin Shan * first time, to dump the PHB diag-data. 58240ae5f69SGavin Shan */ 58340ae5f69SGavin Shan if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 58440ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 58540ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 58640ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 58740ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 58840ae5f69SGavin Shan } else if (!(pe->state & EEH_PE_ISOLATED)) { 589e762bb89SSam Bobroff eeh_pe_mark_isolated(pe); 59040ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 59140ae5f69SGavin Shan 59240ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 59340ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 59440ae5f69SGavin Shan } 59540ae5f69SGavin Shan 59640ae5f69SGavin Shan return result; 59740ae5f69SGavin Shan } 59840ae5f69SGavin Shan 59940ae5f69SGavin Shan static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 60040ae5f69SGavin Shan { 60140ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 602c2057701SAlexey Kardashevskiy u8 fstate = 0; 603c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 60440ae5f69SGavin Shan s64 rc; 60540ae5f69SGavin Shan int result; 60640ae5f69SGavin Shan 60740ae5f69SGavin Shan /* 60840ae5f69SGavin Shan * We don't clobber hardware frozen state until PE 60940ae5f69SGavin Shan * reset is completed. In order to keep EEH core 61040ae5f69SGavin Shan * moving forward, we have to return operational 61140ae5f69SGavin Shan * state during PE reset. 61240ae5f69SGavin Shan */ 61340ae5f69SGavin Shan if (pe->state & EEH_PE_RESET) { 61440ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 61540ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 61640ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 61740ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 61840ae5f69SGavin Shan return result; 61940ae5f69SGavin Shan } 62040ae5f69SGavin Shan 62140ae5f69SGavin Shan /* 62240ae5f69SGavin Shan * Fetch PE state from hardware. If the PHB 62340ae5f69SGavin Shan * supports compound PE, let it handle that. 62440ae5f69SGavin Shan */ 62540ae5f69SGavin Shan if (phb->get_pe_state) { 62640ae5f69SGavin Shan fstate = phb->get_pe_state(phb, pe->addr); 62740ae5f69SGavin Shan } else { 62840ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 62940ae5f69SGavin Shan pe->addr, 63040ae5f69SGavin Shan &fstate, 63140ae5f69SGavin Shan &pcierr, 63240ae5f69SGavin Shan NULL); 63340ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 63440ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 63540ae5f69SGavin Shan __func__, rc, phb->hose->global_number, 63640ae5f69SGavin Shan pe->addr); 63740ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 63840ae5f69SGavin Shan } 63940ae5f69SGavin Shan } 64040ae5f69SGavin Shan 64140ae5f69SGavin Shan /* Figure out state */ 64240ae5f69SGavin Shan switch (fstate) { 64340ae5f69SGavin Shan case OPAL_EEH_STOPPED_NOT_FROZEN: 64440ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 64540ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 64640ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 64740ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 64840ae5f69SGavin Shan break; 64940ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_FREEZE: 65040ae5f69SGavin Shan result = (EEH_STATE_DMA_ACTIVE | 65140ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 65240ae5f69SGavin Shan break; 65340ae5f69SGavin Shan case OPAL_EEH_STOPPED_DMA_FREEZE: 65440ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 65540ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED); 65640ae5f69SGavin Shan break; 65740ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 65840ae5f69SGavin Shan result = 0; 65940ae5f69SGavin Shan break; 66040ae5f69SGavin Shan case OPAL_EEH_STOPPED_RESET: 66140ae5f69SGavin Shan result = EEH_STATE_RESET_ACTIVE; 66240ae5f69SGavin Shan break; 66340ae5f69SGavin Shan case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 66440ae5f69SGavin Shan result = EEH_STATE_UNAVAILABLE; 66540ae5f69SGavin Shan break; 66640ae5f69SGavin Shan case OPAL_EEH_STOPPED_PERM_UNAVAIL: 66740ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 66840ae5f69SGavin Shan break; 66940ae5f69SGavin Shan default: 67040ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 67140ae5f69SGavin Shan pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 67240ae5f69SGavin Shan __func__, phb->hose->global_number, 67340ae5f69SGavin Shan pe->addr, fstate); 67440ae5f69SGavin Shan } 67540ae5f69SGavin Shan 67640ae5f69SGavin Shan /* 67740ae5f69SGavin Shan * If PHB supports compound PE, to freeze all 67840ae5f69SGavin Shan * slave PEs for consistency. 67940ae5f69SGavin Shan * 68040ae5f69SGavin Shan * If the PE is switching to frozen state for the 68140ae5f69SGavin Shan * first time, to dump the PHB diag-data. 68240ae5f69SGavin Shan */ 68340ae5f69SGavin Shan if (!(result & EEH_STATE_NOT_SUPPORT) && 68440ae5f69SGavin Shan !(result & EEH_STATE_UNAVAILABLE) && 68540ae5f69SGavin Shan !(result & EEH_STATE_MMIO_ACTIVE) && 68640ae5f69SGavin Shan !(result & EEH_STATE_DMA_ACTIVE) && 68740ae5f69SGavin Shan !(pe->state & EEH_PE_ISOLATED)) { 68840ae5f69SGavin Shan if (phb->freeze_pe) 68940ae5f69SGavin Shan phb->freeze_pe(phb, pe->addr); 69040ae5f69SGavin Shan 691e762bb89SSam Bobroff eeh_pe_mark_isolated(pe); 69240ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 69340ae5f69SGavin Shan 69440ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 69540ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 69640ae5f69SGavin Shan } 69740ae5f69SGavin Shan 69840ae5f69SGavin Shan return result; 69940ae5f69SGavin Shan } 70040ae5f69SGavin Shan 70129310e5eSGavin Shan /** 70201f3bfb7SGavin Shan * pnv_eeh_get_state - Retrieve PE state 70329310e5eSGavin Shan * @pe: EEH PE 70429310e5eSGavin Shan * @delay: delay while PE state is temporarily unavailable 70529310e5eSGavin Shan * 70629310e5eSGavin Shan * Retrieve the state of the specified PE. For IODA-compitable 70729310e5eSGavin Shan * platform, it should be retrieved from IODA table. Therefore, 70829310e5eSGavin Shan * we prefer passing down to hardware implementation to handle 70929310e5eSGavin Shan * it. 71029310e5eSGavin Shan */ 71101f3bfb7SGavin Shan static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 71229310e5eSGavin Shan { 71340ae5f69SGavin Shan int ret; 71429310e5eSGavin Shan 71540ae5f69SGavin Shan if (pe->type & EEH_PE_PHB) 71640ae5f69SGavin Shan ret = pnv_eeh_get_phb_state(pe); 71740ae5f69SGavin Shan else 71840ae5f69SGavin Shan ret = pnv_eeh_get_pe_state(pe); 71940ae5f69SGavin Shan 72040ae5f69SGavin Shan if (!delay) 72140ae5f69SGavin Shan return ret; 72229310e5eSGavin Shan 72329310e5eSGavin Shan /* 72429310e5eSGavin Shan * If the PE state is temporarily unavailable, 72529310e5eSGavin Shan * to inform the EEH core delay for default 72629310e5eSGavin Shan * period (1 second) 72729310e5eSGavin Shan */ 72829310e5eSGavin Shan *delay = 0; 72929310e5eSGavin Shan if (ret & EEH_STATE_UNAVAILABLE) 73029310e5eSGavin Shan *delay = 1000; 73129310e5eSGavin Shan 73229310e5eSGavin Shan return ret; 73329310e5eSGavin Shan } 73429310e5eSGavin Shan 735ebe22531SGavin Shan static s64 pnv_eeh_poll(unsigned long id) 736cadf364dSGavin Shan { 737cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 738cadf364dSGavin Shan 739cadf364dSGavin Shan while (1) { 740ebe22531SGavin Shan rc = opal_pci_poll(id); 741cadf364dSGavin Shan if (rc <= 0) 742cadf364dSGavin Shan break; 743cadf364dSGavin Shan 744cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 745cadf364dSGavin Shan udelay(1000 * rc); 746cadf364dSGavin Shan else 747cadf364dSGavin Shan msleep(rc); 748cadf364dSGavin Shan } 749cadf364dSGavin Shan 750cadf364dSGavin Shan return rc; 751cadf364dSGavin Shan } 752cadf364dSGavin Shan 753cadf364dSGavin Shan int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 754cadf364dSGavin Shan { 755cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 756cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 757cadf364dSGavin Shan 758cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 759cadf364dSGavin Shan __func__, hose->global_number, option); 760cadf364dSGavin Shan 761cadf364dSGavin Shan /* Issue PHB complete reset request */ 762cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL || 763cadf364dSGavin Shan option == EEH_RESET_HOT) 764cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 765cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 766cadf364dSGavin Shan OPAL_ASSERT_RESET); 767cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 768cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 769cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 770cadf364dSGavin Shan OPAL_DEASSERT_RESET); 771cadf364dSGavin Shan if (rc < 0) 772cadf364dSGavin Shan goto out; 773cadf364dSGavin Shan 774cadf364dSGavin Shan /* 775cadf364dSGavin Shan * Poll state of the PHB until the request is done 776cadf364dSGavin Shan * successfully. The PHB reset is usually PHB complete 777cadf364dSGavin Shan * reset followed by hot reset on root bus. So we also 778cadf364dSGavin Shan * need the PCI bus settlement delay. 779cadf364dSGavin Shan */ 780fbce44d0SGavin Shan if (rc > 0) 781ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 782cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) { 783cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 784cadf364dSGavin Shan udelay(1000 * EEH_PE_RST_SETTLE_TIME); 785cadf364dSGavin Shan else 786cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 787cadf364dSGavin Shan } 788cadf364dSGavin Shan out: 789cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 790cadf364dSGavin Shan return -EIO; 791cadf364dSGavin Shan 792cadf364dSGavin Shan return 0; 793cadf364dSGavin Shan } 794cadf364dSGavin Shan 795cadf364dSGavin Shan static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 796cadf364dSGavin Shan { 797cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 798cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 799cadf364dSGavin Shan 800cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 801cadf364dSGavin Shan __func__, hose->global_number, option); 802cadf364dSGavin Shan 803cadf364dSGavin Shan /* 804cadf364dSGavin Shan * During the reset deassert time, we needn't care 805cadf364dSGavin Shan * the reset scope because the firmware does nothing 806cadf364dSGavin Shan * for fundamental or hot reset during deassert phase. 807cadf364dSGavin Shan */ 808cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL) 809cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 810cadf364dSGavin Shan OPAL_RESET_PCI_FUNDAMENTAL, 811cadf364dSGavin Shan OPAL_ASSERT_RESET); 812cadf364dSGavin Shan else if (option == EEH_RESET_HOT) 813cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 814cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 815cadf364dSGavin Shan OPAL_ASSERT_RESET); 816cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 817cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 818cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 819cadf364dSGavin Shan OPAL_DEASSERT_RESET); 820cadf364dSGavin Shan if (rc < 0) 821cadf364dSGavin Shan goto out; 822cadf364dSGavin Shan 823cadf364dSGavin Shan /* Poll state of the PHB until the request is done */ 824fbce44d0SGavin Shan if (rc > 0) 825ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 826cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) 827cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 828cadf364dSGavin Shan out: 829cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 830cadf364dSGavin Shan return -EIO; 831cadf364dSGavin Shan 832cadf364dSGavin Shan return 0; 833cadf364dSGavin Shan } 834cadf364dSGavin Shan 8359c0e1ecbSGavin Shan static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 836cadf364dSGavin Shan { 8370bd78587SGavin Shan struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 8380bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 839cadf364dSGavin Shan int aer = edev ? edev->aer_cap : 0; 840cadf364dSGavin Shan u32 ctrl; 841cadf364dSGavin Shan 842cadf364dSGavin Shan pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 843cadf364dSGavin Shan __func__, pci_domain_nr(dev->bus), 844cadf364dSGavin Shan dev->bus->number, option); 845cadf364dSGavin Shan 846cadf364dSGavin Shan switch (option) { 847cadf364dSGavin Shan case EEH_RESET_FUNDAMENTAL: 848cadf364dSGavin Shan case EEH_RESET_HOT: 849cadf364dSGavin Shan /* Don't report linkDown event */ 850cadf364dSGavin Shan if (aer) { 8510bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 852cadf364dSGavin Shan 4, &ctrl); 853cadf364dSGavin Shan ctrl |= PCI_ERR_UNC_SURPDN; 8540bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 855cadf364dSGavin Shan 4, ctrl); 856cadf364dSGavin Shan } 857cadf364dSGavin Shan 8580bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 859cadf364dSGavin Shan ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 8600bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 861cadf364dSGavin Shan 862cadf364dSGavin Shan msleep(EEH_PE_RST_HOLD_TIME); 863cadf364dSGavin Shan break; 864cadf364dSGavin Shan case EEH_RESET_DEACTIVATE: 8650bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 866cadf364dSGavin Shan ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 8670bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 868cadf364dSGavin Shan 869cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 870cadf364dSGavin Shan 871cadf364dSGavin Shan /* Continue reporting linkDown event */ 872cadf364dSGavin Shan if (aer) { 8730bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 874cadf364dSGavin Shan 4, &ctrl); 875cadf364dSGavin Shan ctrl &= ~PCI_ERR_UNC_SURPDN; 8760bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 877cadf364dSGavin Shan 4, ctrl); 878cadf364dSGavin Shan } 879cadf364dSGavin Shan 880cadf364dSGavin Shan break; 881cadf364dSGavin Shan } 882cadf364dSGavin Shan 883cadf364dSGavin Shan return 0; 884cadf364dSGavin Shan } 885cadf364dSGavin Shan 8869c0e1ecbSGavin Shan static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 8879c0e1ecbSGavin Shan { 8889c0e1ecbSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 8899c0e1ecbSGavin Shan struct pnv_phb *phb = hose->private_data; 8909c0e1ecbSGavin Shan struct device_node *dn = pci_device_to_OF_node(pdev); 8919c0e1ecbSGavin Shan uint64_t id = PCI_SLOT_ID(phb->opal_id, 8929c0e1ecbSGavin Shan (pdev->bus->number << 8) | pdev->devfn); 8939c0e1ecbSGavin Shan uint8_t scope; 8949c0e1ecbSGavin Shan int64_t rc; 8959c0e1ecbSGavin Shan 8969c0e1ecbSGavin Shan /* Hot reset to the bus if firmware cannot handle */ 8979c0e1ecbSGavin Shan if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 8989c0e1ecbSGavin Shan return __pnv_eeh_bridge_reset(pdev, option); 8999c0e1ecbSGavin Shan 9009c0e1ecbSGavin Shan switch (option) { 9019c0e1ecbSGavin Shan case EEH_RESET_FUNDAMENTAL: 9029c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_FUNDAMENTAL; 9039c0e1ecbSGavin Shan break; 9049c0e1ecbSGavin Shan case EEH_RESET_HOT: 9059c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_HOT; 9069c0e1ecbSGavin Shan break; 9079c0e1ecbSGavin Shan case EEH_RESET_DEACTIVATE: 9089c0e1ecbSGavin Shan return 0; 9099c0e1ecbSGavin Shan default: 9109c0e1ecbSGavin Shan dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 9119c0e1ecbSGavin Shan __func__, option); 9129c0e1ecbSGavin Shan return -EINVAL; 9139c0e1ecbSGavin Shan } 9149c0e1ecbSGavin Shan 9159c0e1ecbSGavin Shan rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 9169c0e1ecbSGavin Shan if (rc <= OPAL_SUCCESS) 9179c0e1ecbSGavin Shan goto out; 9189c0e1ecbSGavin Shan 9199c0e1ecbSGavin Shan rc = pnv_eeh_poll(id); 9209c0e1ecbSGavin Shan out: 9219c0e1ecbSGavin Shan return (rc == OPAL_SUCCESS) ? 0 : -EIO; 9229c0e1ecbSGavin Shan } 9239c0e1ecbSGavin Shan 924cadf364dSGavin Shan void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 925cadf364dSGavin Shan { 926848912e5SMichael Ellerman struct pci_controller *hose; 927848912e5SMichael Ellerman 928848912e5SMichael Ellerman if (pci_is_root_bus(dev->bus)) { 929848912e5SMichael Ellerman hose = pci_bus_to_host(dev->bus); 930848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_HOT); 931848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 932848912e5SMichael Ellerman } else { 933cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 934cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 935cadf364dSGavin Shan } 936848912e5SMichael Ellerman } 937cadf364dSGavin Shan 9389312bc5bSWei Yang static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 9399312bc5bSWei Yang int pos, u16 mask) 9409312bc5bSWei Yang { 9419312bc5bSWei Yang int i, status = 0; 9429312bc5bSWei Yang 9439312bc5bSWei Yang /* Wait for Transaction Pending bit to be cleared */ 9449312bc5bSWei Yang for (i = 0; i < 4; i++) { 9459312bc5bSWei Yang eeh_ops->read_config(pdn, pos, 2, &status); 9469312bc5bSWei Yang if (!(status & mask)) 9479312bc5bSWei Yang return; 9489312bc5bSWei Yang 9499312bc5bSWei Yang msleep((1 << i) * 100); 9509312bc5bSWei Yang } 9519312bc5bSWei Yang 9529312bc5bSWei Yang pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 9539312bc5bSWei Yang __func__, type, 95469672bd7SAlexey Kardashevskiy pdn->phb->global_number, pdn->busno, 9559312bc5bSWei Yang PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 9569312bc5bSWei Yang } 9579312bc5bSWei Yang 9589312bc5bSWei Yang static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 9599312bc5bSWei Yang { 9609312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9619312bc5bSWei Yang u32 reg = 0; 9629312bc5bSWei Yang 9639312bc5bSWei Yang if (WARN_ON(!edev->pcie_cap)) 9649312bc5bSWei Yang return -ENOTTY; 9659312bc5bSWei Yang 9669312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 9679312bc5bSWei Yang if (!(reg & PCI_EXP_DEVCAP_FLR)) 9689312bc5bSWei Yang return -ENOTTY; 9699312bc5bSWei Yang 9709312bc5bSWei Yang switch (option) { 9719312bc5bSWei Yang case EEH_RESET_HOT: 9729312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 9739312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "", 9749312bc5bSWei Yang edev->pcie_cap + PCI_EXP_DEVSTA, 9759312bc5bSWei Yang PCI_EXP_DEVSTA_TRPND); 9769312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9779312bc5bSWei Yang 4, ®); 9789312bc5bSWei Yang reg |= PCI_EXP_DEVCTL_BCR_FLR; 9799312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9809312bc5bSWei Yang 4, reg); 9819312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 9829312bc5bSWei Yang break; 9839312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 9849312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9859312bc5bSWei Yang 4, ®); 9869312bc5bSWei Yang reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 9879312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9889312bc5bSWei Yang 4, reg); 9899312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 9909312bc5bSWei Yang break; 9919312bc5bSWei Yang } 9929312bc5bSWei Yang 9939312bc5bSWei Yang return 0; 9949312bc5bSWei Yang } 9959312bc5bSWei Yang 9969312bc5bSWei Yang static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 9979312bc5bSWei Yang { 9989312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9999312bc5bSWei Yang u32 cap = 0; 10009312bc5bSWei Yang 10019312bc5bSWei Yang if (WARN_ON(!edev->af_cap)) 10029312bc5bSWei Yang return -ENOTTY; 10039312bc5bSWei Yang 10049312bc5bSWei Yang eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 10059312bc5bSWei Yang if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 10069312bc5bSWei Yang return -ENOTTY; 10079312bc5bSWei Yang 10089312bc5bSWei Yang switch (option) { 10099312bc5bSWei Yang case EEH_RESET_HOT: 10109312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 10119312bc5bSWei Yang /* 10129312bc5bSWei Yang * Wait for Transaction Pending bit to clear. A word-aligned 10139312bc5bSWei Yang * test is used, so we use the conrol offset rather than status 10149312bc5bSWei Yang * and shift the test bit to match. 10159312bc5bSWei Yang */ 10169312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "AF", 10179312bc5bSWei Yang edev->af_cap + PCI_AF_CTRL, 10189312bc5bSWei Yang PCI_AF_STATUS_TP << 8); 10199312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 10209312bc5bSWei Yang 1, PCI_AF_CTRL_FLR); 10219312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 10229312bc5bSWei Yang break; 10239312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 10249312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 10259312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 10269312bc5bSWei Yang break; 10279312bc5bSWei Yang } 10289312bc5bSWei Yang 10299312bc5bSWei Yang return 0; 10309312bc5bSWei Yang } 10319312bc5bSWei Yang 10329312bc5bSWei Yang static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 10339312bc5bSWei Yang { 10349312bc5bSWei Yang struct eeh_dev *edev; 10359312bc5bSWei Yang struct pci_dn *pdn; 10369312bc5bSWei Yang int ret; 10379312bc5bSWei Yang 10389312bc5bSWei Yang /* The VF PE should have only one child device */ 103980e65b00SSam Bobroff edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); 10409312bc5bSWei Yang pdn = eeh_dev_to_pdn(edev); 10419312bc5bSWei Yang if (!pdn) 10429312bc5bSWei Yang return -ENXIO; 10439312bc5bSWei Yang 10449312bc5bSWei Yang ret = pnv_eeh_do_flr(pdn, option); 10459312bc5bSWei Yang if (!ret) 10469312bc5bSWei Yang return ret; 10479312bc5bSWei Yang 10489312bc5bSWei Yang return pnv_eeh_do_af_flr(pdn, option); 10499312bc5bSWei Yang } 10509312bc5bSWei Yang 105129310e5eSGavin Shan /** 105201f3bfb7SGavin Shan * pnv_eeh_reset - Reset the specified PE 105329310e5eSGavin Shan * @pe: EEH PE 105429310e5eSGavin Shan * @option: reset option 105529310e5eSGavin Shan * 1056cadf364dSGavin Shan * Do reset on the indicated PE. For PCI bus sensitive PE, 1057cadf364dSGavin Shan * we need to reset the parent p2p bridge. The PHB has to 1058cadf364dSGavin Shan * be reinitialized if the p2p bridge is root bridge. For 1059cadf364dSGavin Shan * PCI device sensitive PE, we will try to reset the device 1060cadf364dSGavin Shan * through FLR. For now, we don't have OPAL APIs to do HARD 1061cadf364dSGavin Shan * reset yet, so all reset would be SOFT (HOT) reset. 106229310e5eSGavin Shan */ 106301f3bfb7SGavin Shan static int pnv_eeh_reset(struct eeh_pe *pe, int option) 106429310e5eSGavin Shan { 106529310e5eSGavin Shan struct pci_controller *hose = pe->phb; 10664fad4943SGavin Shan struct pnv_phb *phb; 1067cadf364dSGavin Shan struct pci_bus *bus; 10684fad4943SGavin Shan int64_t rc; 106929310e5eSGavin Shan 1070cadf364dSGavin Shan /* 1071cadf364dSGavin Shan * For PHB reset, we always have complete reset. For those PEs whose 1072cadf364dSGavin Shan * primary bus derived from root complex (root bus) or root port 1073cadf364dSGavin Shan * (usually bus#1), we apply hot or fundamental reset on the root port. 1074cadf364dSGavin Shan * For other PEs, we always have hot reset on the PE primary bus. 1075cadf364dSGavin Shan * 1076cadf364dSGavin Shan * Here, we have different design to pHyp, which always clear the 1077cadf364dSGavin Shan * frozen state during PE reset. However, the good idea here from 1078cadf364dSGavin Shan * benh is to keep frozen state before we get PE reset done completely 1079cadf364dSGavin Shan * (until BAR restore). With the frozen state, HW drops illegal IO 1080cadf364dSGavin Shan * or MMIO access, which can incur recrusive frozen PE during PE 1081cadf364dSGavin Shan * reset. The side effect is that EEH core has to clear the frozen 1082cadf364dSGavin Shan * state explicitly after BAR restore. 1083cadf364dSGavin Shan */ 10844fad4943SGavin Shan if (pe->type & EEH_PE_PHB) 10854fad4943SGavin Shan return pnv_eeh_phb_reset(hose, option); 1086cadf364dSGavin Shan 1087cadf364dSGavin Shan /* 1088cadf364dSGavin Shan * The frozen PE might be caused by PAPR error injection 1089cadf364dSGavin Shan * registers, which are expected to be cleared after hitting 1090cadf364dSGavin Shan * frozen PE as stated in the hardware spec. Unfortunately, 1091cadf364dSGavin Shan * that's not true on P7IOC. So we have to clear it manually 1092cadf364dSGavin Shan * to avoid recursive EEH errors during recovery. 1093cadf364dSGavin Shan */ 1094cadf364dSGavin Shan phb = hose->private_data; 1095cadf364dSGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC && 1096cadf364dSGavin Shan (option == EEH_RESET_HOT || 1097cadf364dSGavin Shan option == EEH_RESET_FUNDAMENTAL)) { 1098cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 1099cadf364dSGavin Shan OPAL_RESET_PHB_ERROR, 1100cadf364dSGavin Shan OPAL_ASSERT_RESET); 1101cadf364dSGavin Shan if (rc != OPAL_SUCCESS) { 11024fad4943SGavin Shan pr_warn("%s: Failure %lld clearing error injection registers\n", 1103cadf364dSGavin Shan __func__, rc); 1104cadf364dSGavin Shan return -EIO; 1105cadf364dSGavin Shan } 1106cadf364dSGavin Shan } 1107cadf364dSGavin Shan 1108e98ddb77SRussell Currey if (pe->type & EEH_PE_VF) 1109e98ddb77SRussell Currey return pnv_eeh_reset_vf_pe(pe, option); 1110e98ddb77SRussell Currey 1111cadf364dSGavin Shan bus = eeh_pe_bus_get(pe); 111204fec21cSRussell Currey if (!bus) { 11131f52f176SRussell Currey pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 111404fec21cSRussell Currey __func__, pe->phb->global_number, pe->addr); 111504fec21cSRussell Currey return -EIO; 111604fec21cSRussell Currey } 111729310e5eSGavin Shan 1118b7da1230SAndrew Donnellan /* 1119b7da1230SAndrew Donnellan * If dealing with the root bus (or the bus underneath the 1120b7da1230SAndrew Donnellan * root port), we reset the bus underneath the root port. 1121b7da1230SAndrew Donnellan * 1122b7da1230SAndrew Donnellan * The cxl driver depends on this behaviour for bi-modal card 1123b7da1230SAndrew Donnellan * switching. 1124b7da1230SAndrew Donnellan */ 11254fad4943SGavin Shan if (pci_is_root_bus(bus) || 11264fad4943SGavin Shan pci_is_root_bus(bus->parent)) 11274fad4943SGavin Shan return pnv_eeh_root_reset(hose, option); 11284fad4943SGavin Shan 11294fad4943SGavin Shan return pnv_eeh_bridge_reset(bus->self, option); 113029310e5eSGavin Shan } 113129310e5eSGavin Shan 113229310e5eSGavin Shan /** 113301f3bfb7SGavin Shan * pnv_eeh_get_log - Retrieve error log 113429310e5eSGavin Shan * @pe: EEH PE 113529310e5eSGavin Shan * @severity: temporary or permanent error log 113629310e5eSGavin Shan * @drv_log: driver log to be combined with retrieved error log 113729310e5eSGavin Shan * @len: length of driver log 113829310e5eSGavin Shan * 113929310e5eSGavin Shan * Retrieve the temporary or permanent error from the PE. 114029310e5eSGavin Shan */ 114101f3bfb7SGavin Shan static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 114229310e5eSGavin Shan char *drv_log, unsigned long len) 114329310e5eSGavin Shan { 114495edcdeaSGavin Shan if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 114595edcdeaSGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 114629310e5eSGavin Shan 114795edcdeaSGavin Shan return 0; 114829310e5eSGavin Shan } 114929310e5eSGavin Shan 115029310e5eSGavin Shan /** 115101f3bfb7SGavin Shan * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 115229310e5eSGavin Shan * @pe: EEH PE 115329310e5eSGavin Shan * 115429310e5eSGavin Shan * The function will be called to reconfigure the bridges included 115529310e5eSGavin Shan * in the specified PE so that the mulfunctional PE would be recovered 115629310e5eSGavin Shan * again. 115729310e5eSGavin Shan */ 115801f3bfb7SGavin Shan static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 115929310e5eSGavin Shan { 1160bbe170edSGavin Shan return 0; 116129310e5eSGavin Shan } 116229310e5eSGavin Shan 116329310e5eSGavin Shan /** 116401f3bfb7SGavin Shan * pnv_pe_err_inject - Inject specified error to the indicated PE 1165131c123aSGavin Shan * @pe: the indicated PE 1166131c123aSGavin Shan * @type: error type 1167131c123aSGavin Shan * @func: specific error type 1168131c123aSGavin Shan * @addr: address 1169131c123aSGavin Shan * @mask: address mask 1170131c123aSGavin Shan * 1171131c123aSGavin Shan * The routine is called to inject specified error, which is 1172131c123aSGavin Shan * determined by @type and @func, to the indicated PE for 1173131c123aSGavin Shan * testing purpose. 1174131c123aSGavin Shan */ 117501f3bfb7SGavin Shan static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1176131c123aSGavin Shan unsigned long addr, unsigned long mask) 1177131c123aSGavin Shan { 1178131c123aSGavin Shan struct pci_controller *hose = pe->phb; 1179131c123aSGavin Shan struct pnv_phb *phb = hose->private_data; 1180fa646c3cSGavin Shan s64 rc; 1181131c123aSGavin Shan 1182fa646c3cSGavin Shan if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1183fa646c3cSGavin Shan type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1184fa646c3cSGavin Shan pr_warn("%s: Invalid error type %d\n", 1185fa646c3cSGavin Shan __func__, type); 1186fa646c3cSGavin Shan return -ERANGE; 1187fa646c3cSGavin Shan } 1188131c123aSGavin Shan 1189fa646c3cSGavin Shan if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1190fa646c3cSGavin Shan func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1191fa646c3cSGavin Shan pr_warn("%s: Invalid error function %d\n", 1192fa646c3cSGavin Shan __func__, func); 1193fa646c3cSGavin Shan return -ERANGE; 1194fa646c3cSGavin Shan } 1195fa646c3cSGavin Shan 1196fa646c3cSGavin Shan /* Firmware supports error injection ? */ 1197fa646c3cSGavin Shan if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1198fa646c3cSGavin Shan pr_warn("%s: Firmware doesn't support error injection\n", 1199fa646c3cSGavin Shan __func__); 1200fa646c3cSGavin Shan return -ENXIO; 1201fa646c3cSGavin Shan } 1202fa646c3cSGavin Shan 1203fa646c3cSGavin Shan /* Do error injection */ 1204fa646c3cSGavin Shan rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1205fa646c3cSGavin Shan type, func, addr, mask); 1206fa646c3cSGavin Shan if (rc != OPAL_SUCCESS) { 1207fa646c3cSGavin Shan pr_warn("%s: Failure %lld injecting error " 1208fa646c3cSGavin Shan "%d-%d to PHB#%x-PE#%x\n", 1209fa646c3cSGavin Shan __func__, rc, type, func, 1210fa646c3cSGavin Shan hose->global_number, pe->addr); 1211fa646c3cSGavin Shan return -EIO; 1212fa646c3cSGavin Shan } 1213fa646c3cSGavin Shan 1214fa646c3cSGavin Shan return 0; 1215131c123aSGavin Shan } 1216131c123aSGavin Shan 12170bd78587SGavin Shan static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1218d2cfbcd7SGavin Shan { 12190bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1220d2cfbcd7SGavin Shan 1221d2cfbcd7SGavin Shan if (!edev || !edev->pe) 1222d2cfbcd7SGavin Shan return false; 1223d2cfbcd7SGavin Shan 12249312bc5bSWei Yang /* 12259312bc5bSWei Yang * We will issue FLR or AF FLR to all VFs, which are contained 12269312bc5bSWei Yang * in VF PE. It relies on the EEH PCI config accessors. So we 12279312bc5bSWei Yang * can't block them during the window. 12289312bc5bSWei Yang */ 12299312bc5bSWei Yang if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 12309312bc5bSWei Yang return false; 12319312bc5bSWei Yang 1232d2cfbcd7SGavin Shan if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1233d2cfbcd7SGavin Shan return true; 1234d2cfbcd7SGavin Shan 1235d2cfbcd7SGavin Shan return false; 1236d2cfbcd7SGavin Shan } 1237d2cfbcd7SGavin Shan 12380bd78587SGavin Shan static int pnv_eeh_read_config(struct pci_dn *pdn, 1239d2cfbcd7SGavin Shan int where, int size, u32 *val) 1240d2cfbcd7SGavin Shan { 12413532a741SGavin Shan if (!pdn) 12423532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12433532a741SGavin Shan 12440bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) { 1245d2cfbcd7SGavin Shan *val = 0xFFFFFFFF; 1246d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1247d2cfbcd7SGavin Shan } 1248d2cfbcd7SGavin Shan 12493532a741SGavin Shan return pnv_pci_cfg_read(pdn, where, size, val); 1250d2cfbcd7SGavin Shan } 1251d2cfbcd7SGavin Shan 12520bd78587SGavin Shan static int pnv_eeh_write_config(struct pci_dn *pdn, 1253d2cfbcd7SGavin Shan int where, int size, u32 val) 1254d2cfbcd7SGavin Shan { 12553532a741SGavin Shan if (!pdn) 12563532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12573532a741SGavin Shan 12580bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) 1259d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1260d2cfbcd7SGavin Shan 12613532a741SGavin Shan return pnv_pci_cfg_write(pdn, where, size, val); 1262d2cfbcd7SGavin Shan } 1263d2cfbcd7SGavin Shan 12642a485ad7SGavin Shan static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 12652a485ad7SGavin Shan { 12662a485ad7SGavin Shan /* GEM */ 12672a485ad7SGavin Shan if (data->gemXfir || data->gemRfir || 12682a485ad7SGavin Shan data->gemRirqfir || data->gemMask || data->gemRwof) 12692a485ad7SGavin Shan pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 12702a485ad7SGavin Shan be64_to_cpu(data->gemXfir), 12712a485ad7SGavin Shan be64_to_cpu(data->gemRfir), 12722a485ad7SGavin Shan be64_to_cpu(data->gemRirqfir), 12732a485ad7SGavin Shan be64_to_cpu(data->gemMask), 12742a485ad7SGavin Shan be64_to_cpu(data->gemRwof)); 12752a485ad7SGavin Shan 12762a485ad7SGavin Shan /* LEM */ 12772a485ad7SGavin Shan if (data->lemFir || data->lemErrMask || 12782a485ad7SGavin Shan data->lemAction0 || data->lemAction1 || data->lemWof) 12792a485ad7SGavin Shan pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 12802a485ad7SGavin Shan be64_to_cpu(data->lemFir), 12812a485ad7SGavin Shan be64_to_cpu(data->lemErrMask), 12822a485ad7SGavin Shan be64_to_cpu(data->lemAction0), 12832a485ad7SGavin Shan be64_to_cpu(data->lemAction1), 12842a485ad7SGavin Shan be64_to_cpu(data->lemWof)); 12852a485ad7SGavin Shan } 12862a485ad7SGavin Shan 12872a485ad7SGavin Shan static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 12882a485ad7SGavin Shan { 12892a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 12905cb1f8fdSRussell Currey struct OpalIoP7IOCErrorData *data = 12915cb1f8fdSRussell Currey (struct OpalIoP7IOCErrorData*)phb->diag_data; 12922a485ad7SGavin Shan long rc; 12932a485ad7SGavin Shan 12942a485ad7SGavin Shan rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 12952a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 12962a485ad7SGavin Shan pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 12972a485ad7SGavin Shan __func__, phb->hub_id, rc); 12982a485ad7SGavin Shan return; 12992a485ad7SGavin Shan } 13002a485ad7SGavin Shan 1301a7032132SGavin Shan switch (be16_to_cpu(data->type)) { 13022a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_RGC: 13032a485ad7SGavin Shan pr_info("P7IOC diag-data for RGC\n\n"); 13042a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13052a485ad7SGavin Shan if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 13062a485ad7SGavin Shan pr_info(" RGC: %016llx %016llx\n", 13072a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcStatus), 13082a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcLdcp)); 13092a485ad7SGavin Shan break; 13102a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_BI: 13112a485ad7SGavin Shan pr_info("P7IOC diag-data for BI %s\n\n", 13122a485ad7SGavin Shan data->bi.biDownbound ? "Downbound" : "Upbound"); 13132a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13142a485ad7SGavin Shan if (data->bi.biLdcp0 || data->bi.biLdcp1 || 13152a485ad7SGavin Shan data->bi.biLdcp2 || data->bi.biFenceStatus) 13162a485ad7SGavin Shan pr_info(" BI: %016llx %016llx %016llx %016llx\n", 13172a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp0), 13182a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp1), 13192a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp2), 13202a485ad7SGavin Shan be64_to_cpu(data->bi.biFenceStatus)); 13212a485ad7SGavin Shan break; 13222a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_CI: 13232a485ad7SGavin Shan pr_info("P7IOC diag-data for CI Port %d\n\n", 13242a485ad7SGavin Shan data->ci.ciPort); 13252a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13262a485ad7SGavin Shan if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 13272a485ad7SGavin Shan pr_info(" CI: %016llx %016llx\n", 13282a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortStatus), 13292a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortLdcp)); 13302a485ad7SGavin Shan break; 13312a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_MISC: 13322a485ad7SGavin Shan pr_info("P7IOC diag-data for MISC\n\n"); 13332a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13342a485ad7SGavin Shan break; 13352a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_I2C: 13362a485ad7SGavin Shan pr_info("P7IOC diag-data for I2C\n\n"); 13372a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13382a485ad7SGavin Shan break; 13392a485ad7SGavin Shan default: 13402a485ad7SGavin Shan pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 13412a485ad7SGavin Shan __func__, phb->hub_id, data->type); 13422a485ad7SGavin Shan } 13432a485ad7SGavin Shan } 13442a485ad7SGavin Shan 13452a485ad7SGavin Shan static int pnv_eeh_get_pe(struct pci_controller *hose, 13462a485ad7SGavin Shan u16 pe_no, struct eeh_pe **pe) 13472a485ad7SGavin Shan { 13482a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 13492a485ad7SGavin Shan struct pnv_ioda_pe *pnv_pe; 13502a485ad7SGavin Shan struct eeh_pe *dev_pe; 13512a485ad7SGavin Shan 13522a485ad7SGavin Shan /* 13532a485ad7SGavin Shan * If PHB supports compound PE, to fetch 13542a485ad7SGavin Shan * the master PE because slave PE is invisible 13552a485ad7SGavin Shan * to EEH core. 13562a485ad7SGavin Shan */ 13572a485ad7SGavin Shan pnv_pe = &phb->ioda.pe_array[pe_no]; 13582a485ad7SGavin Shan if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 13592a485ad7SGavin Shan pnv_pe = pnv_pe->master; 13602a485ad7SGavin Shan WARN_ON(!pnv_pe || 13612a485ad7SGavin Shan !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 13622a485ad7SGavin Shan pe_no = pnv_pe->pe_number; 13632a485ad7SGavin Shan } 13642a485ad7SGavin Shan 13652a485ad7SGavin Shan /* Find the PE according to PE# */ 13668bae6a23SAlexey Kardashevskiy dev_pe = eeh_pe_get(hose, pe_no, 0); 13672a485ad7SGavin Shan if (!dev_pe) 13682a485ad7SGavin Shan return -EEXIST; 13692a485ad7SGavin Shan 13702a485ad7SGavin Shan /* Freeze the (compound) PE */ 13712a485ad7SGavin Shan *pe = dev_pe; 13722a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 13732a485ad7SGavin Shan phb->freeze_pe(phb, pe_no); 13742a485ad7SGavin Shan 13752a485ad7SGavin Shan /* 13762a485ad7SGavin Shan * At this point, we're sure the (compound) PE should 13772a485ad7SGavin Shan * have been frozen. However, we still need poke until 13782a485ad7SGavin Shan * hitting the frozen PE on top level. 13792a485ad7SGavin Shan */ 13802a485ad7SGavin Shan dev_pe = dev_pe->parent; 13812a485ad7SGavin Shan while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 13822a485ad7SGavin Shan int ret; 13832a485ad7SGavin Shan ret = eeh_ops->get_state(dev_pe, NULL); 138434a286a4SSam Bobroff if (ret <= 0 || eeh_state_active(ret)) { 13852a485ad7SGavin Shan dev_pe = dev_pe->parent; 13862a485ad7SGavin Shan continue; 13872a485ad7SGavin Shan } 13882a485ad7SGavin Shan 13892a485ad7SGavin Shan /* Frozen parent PE */ 13902a485ad7SGavin Shan *pe = dev_pe; 13912a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 13922a485ad7SGavin Shan phb->freeze_pe(phb, dev_pe->addr); 13932a485ad7SGavin Shan 13942a485ad7SGavin Shan /* Next one */ 13952a485ad7SGavin Shan dev_pe = dev_pe->parent; 13962a485ad7SGavin Shan } 13972a485ad7SGavin Shan 13982a485ad7SGavin Shan return 0; 13992a485ad7SGavin Shan } 14002a485ad7SGavin Shan 1401131c123aSGavin Shan /** 140201f3bfb7SGavin Shan * pnv_eeh_next_error - Retrieve next EEH error to handle 140329310e5eSGavin Shan * @pe: Affected PE 140429310e5eSGavin Shan * 14052a485ad7SGavin Shan * The function is expected to be called by EEH core while it gets 14062a485ad7SGavin Shan * special EEH event (without binding PE). The function calls to 14072a485ad7SGavin Shan * OPAL APIs for next error to handle. The informational error is 14082a485ad7SGavin Shan * handled internally by platform. However, the dead IOC, dead PHB, 14092a485ad7SGavin Shan * fenced PHB and frozen PE should be handled by EEH core eventually. 141029310e5eSGavin Shan */ 141101f3bfb7SGavin Shan static int pnv_eeh_next_error(struct eeh_pe **pe) 141229310e5eSGavin Shan { 141329310e5eSGavin Shan struct pci_controller *hose; 14142a485ad7SGavin Shan struct pnv_phb *phb; 14152a485ad7SGavin Shan struct eeh_pe *phb_pe, *parent_pe; 14162a485ad7SGavin Shan __be64 frozen_pe_no; 14172a485ad7SGavin Shan __be16 err_type, severity; 14182a485ad7SGavin Shan long rc; 14192a485ad7SGavin Shan int state, ret = EEH_NEXT_ERR_NONE; 14202a485ad7SGavin Shan 14212a485ad7SGavin Shan /* 142279231448SAlistair Popple * While running here, it's safe to purge the event queue. The 142379231448SAlistair Popple * event should still be masked. 14242a485ad7SGavin Shan */ 14252a485ad7SGavin Shan eeh_remove_event(NULL, false); 142629310e5eSGavin Shan 142729310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 14282a485ad7SGavin Shan /* 14292a485ad7SGavin Shan * If the subordinate PCI buses of the PHB has been 14302a485ad7SGavin Shan * removed or is exactly under error recovery, we 14312a485ad7SGavin Shan * needn't take care of it any more. 14322a485ad7SGavin Shan */ 143329310e5eSGavin Shan phb = hose->private_data; 14342a485ad7SGavin Shan phb_pe = eeh_phb_pe_get(hose); 14352a485ad7SGavin Shan if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 14362a485ad7SGavin Shan continue; 14372a485ad7SGavin Shan 14382a485ad7SGavin Shan rc = opal_pci_next_error(phb->opal_id, 14392a485ad7SGavin Shan &frozen_pe_no, &err_type, &severity); 14402a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 14412a485ad7SGavin Shan pr_devel("%s: Invalid return value on " 14422a485ad7SGavin Shan "PHB#%x (0x%lx) from opal_pci_next_error", 14432a485ad7SGavin Shan __func__, hose->global_number, rc); 14442a485ad7SGavin Shan continue; 14452a485ad7SGavin Shan } 14462a485ad7SGavin Shan 14472a485ad7SGavin Shan /* If the PHB doesn't have error, stop processing */ 14482a485ad7SGavin Shan if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 14492a485ad7SGavin Shan be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 14502a485ad7SGavin Shan pr_devel("%s: No error found on PHB#%x\n", 14512a485ad7SGavin Shan __func__, hose->global_number); 14522a485ad7SGavin Shan continue; 14532a485ad7SGavin Shan } 14542a485ad7SGavin Shan 14552a485ad7SGavin Shan /* 14562a485ad7SGavin Shan * Processing the error. We're expecting the error with 14572a485ad7SGavin Shan * highest priority reported upon multiple errors on the 14582a485ad7SGavin Shan * specific PHB. 14592a485ad7SGavin Shan */ 14602a485ad7SGavin Shan pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 14612a485ad7SGavin Shan __func__, be16_to_cpu(err_type), 14622a485ad7SGavin Shan be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 14632a485ad7SGavin Shan hose->global_number); 14642a485ad7SGavin Shan switch (be16_to_cpu(err_type)) { 14652a485ad7SGavin Shan case OPAL_EEH_IOC_ERROR: 14662a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 14672a485ad7SGavin Shan pr_err("EEH: dead IOC detected\n"); 14682a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_IOC; 14692a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 14702a485ad7SGavin Shan pr_info("EEH: IOC informative error " 14712a485ad7SGavin Shan "detected\n"); 14722a485ad7SGavin Shan pnv_eeh_get_and_dump_hub_diag(hose); 14732a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 14742a485ad7SGavin Shan } 14752a485ad7SGavin Shan 14762a485ad7SGavin Shan break; 14772a485ad7SGavin Shan case OPAL_EEH_PHB_ERROR: 14782a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 14792a485ad7SGavin Shan *pe = phb_pe; 14802a485ad7SGavin Shan pr_err("EEH: dead PHB#%x detected, " 14812a485ad7SGavin Shan "location: %s\n", 14822a485ad7SGavin Shan hose->global_number, 14832a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14842a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_PHB; 14852a485ad7SGavin Shan } else if (be16_to_cpu(severity) == 14862a485ad7SGavin Shan OPAL_EEH_SEV_PHB_FENCED) { 14872a485ad7SGavin Shan *pe = phb_pe; 14882a485ad7SGavin Shan pr_err("EEH: Fenced PHB#%x detected, " 14892a485ad7SGavin Shan "location: %s\n", 14902a485ad7SGavin Shan hose->global_number, 14912a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14922a485ad7SGavin Shan ret = EEH_NEXT_ERR_FENCED_PHB; 14932a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 14942a485ad7SGavin Shan pr_info("EEH: PHB#%x informative error " 14952a485ad7SGavin Shan "detected, location: %s\n", 14962a485ad7SGavin Shan hose->global_number, 14972a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14982a485ad7SGavin Shan pnv_eeh_get_phb_diag(phb_pe); 14992a485ad7SGavin Shan pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 15002a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15012a485ad7SGavin Shan } 15022a485ad7SGavin Shan 15032a485ad7SGavin Shan break; 15042a485ad7SGavin Shan case OPAL_EEH_PE_ERROR: 15052a485ad7SGavin Shan /* 15062a485ad7SGavin Shan * If we can't find the corresponding PE, we 15072a485ad7SGavin Shan * just try to unfreeze. 15082a485ad7SGavin Shan */ 15092a485ad7SGavin Shan if (pnv_eeh_get_pe(hose, 15102a485ad7SGavin Shan be64_to_cpu(frozen_pe_no), pe)) { 15112a485ad7SGavin Shan pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 15120f36db77SGavin Shan hose->global_number, be64_to_cpu(frozen_pe_no)); 15132a485ad7SGavin Shan pr_info("EEH: PHB location: %s\n", 15142a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 151579cd9520SGavin Shan 151679cd9520SGavin Shan /* Dump PHB diag-data */ 151779cd9520SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, 15185cb1f8fdSRussell Currey phb->diag_data, phb->diag_data_size); 151979cd9520SGavin Shan if (rc == OPAL_SUCCESS) 152079cd9520SGavin Shan pnv_pci_dump_phb_diag_data(hose, 15215cb1f8fdSRussell Currey phb->diag_data); 152279cd9520SGavin Shan 152379cd9520SGavin Shan /* Try best to clear it */ 15242a485ad7SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 1525d63e51b3SGavin Shan be64_to_cpu(frozen_pe_no), 15262a485ad7SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 15272a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15282a485ad7SGavin Shan } else if ((*pe)->state & EEH_PE_ISOLATED || 15292a485ad7SGavin Shan eeh_pe_passed(*pe)) { 15302a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15312a485ad7SGavin Shan } else { 15322a485ad7SGavin Shan pr_err("EEH: Frozen PE#%x " 15332a485ad7SGavin Shan "on PHB#%x detected\n", 15342a485ad7SGavin Shan (*pe)->addr, 15352a485ad7SGavin Shan (*pe)->phb->global_number); 15362a485ad7SGavin Shan pr_err("EEH: PE location: %s, " 15372a485ad7SGavin Shan "PHB location: %s\n", 15382a485ad7SGavin Shan eeh_pe_loc_get(*pe), 15392a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15402a485ad7SGavin Shan ret = EEH_NEXT_ERR_FROZEN_PE; 15412a485ad7SGavin Shan } 15422a485ad7SGavin Shan 15432a485ad7SGavin Shan break; 15442a485ad7SGavin Shan default: 15452a485ad7SGavin Shan pr_warn("%s: Unexpected error type %d\n", 15462a485ad7SGavin Shan __func__, be16_to_cpu(err_type)); 15472a485ad7SGavin Shan } 15482a485ad7SGavin Shan 15492a485ad7SGavin Shan /* 15502a485ad7SGavin Shan * EEH core will try recover from fenced PHB or 15512a485ad7SGavin Shan * frozen PE. In the time for frozen PE, EEH core 15522a485ad7SGavin Shan * enable IO path for that before collecting logs, 15532a485ad7SGavin Shan * but it ruins the site. So we have to dump the 15542a485ad7SGavin Shan * log in advance here. 15552a485ad7SGavin Shan */ 15562a485ad7SGavin Shan if ((ret == EEH_NEXT_ERR_FROZEN_PE || 15572a485ad7SGavin Shan ret == EEH_NEXT_ERR_FENCED_PHB) && 15582a485ad7SGavin Shan !((*pe)->state & EEH_PE_ISOLATED)) { 1559e762bb89SSam Bobroff eeh_pe_mark_isolated(*pe); 15602a485ad7SGavin Shan pnv_eeh_get_phb_diag(*pe); 15612a485ad7SGavin Shan 15622a485ad7SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 15632a485ad7SGavin Shan pnv_pci_dump_phb_diag_data((*pe)->phb, 15642a485ad7SGavin Shan (*pe)->data); 15652a485ad7SGavin Shan } 15662a485ad7SGavin Shan 15672a485ad7SGavin Shan /* 15682a485ad7SGavin Shan * We probably have the frozen parent PE out there and 15692a485ad7SGavin Shan * we need have to handle frozen parent PE firstly. 15702a485ad7SGavin Shan */ 15712a485ad7SGavin Shan if (ret == EEH_NEXT_ERR_FROZEN_PE) { 15722a485ad7SGavin Shan parent_pe = (*pe)->parent; 15732a485ad7SGavin Shan while (parent_pe) { 15742a485ad7SGavin Shan /* Hit the ceiling ? */ 15752a485ad7SGavin Shan if (parent_pe->type & EEH_PE_PHB) 15762a485ad7SGavin Shan break; 15772a485ad7SGavin Shan 15782a485ad7SGavin Shan /* Frozen parent PE ? */ 15792a485ad7SGavin Shan state = eeh_ops->get_state(parent_pe, NULL); 158034a286a4SSam Bobroff if (state > 0 && !eeh_state_active(state)) 15812a485ad7SGavin Shan *pe = parent_pe; 15822a485ad7SGavin Shan 15832a485ad7SGavin Shan /* Next parent level */ 15842a485ad7SGavin Shan parent_pe = parent_pe->parent; 15852a485ad7SGavin Shan } 15862a485ad7SGavin Shan 15872a485ad7SGavin Shan /* We possibly migrate to another PE */ 1588e762bb89SSam Bobroff eeh_pe_mark_isolated(*pe); 15892a485ad7SGavin Shan } 15902a485ad7SGavin Shan 15912a485ad7SGavin Shan /* 15922a485ad7SGavin Shan * If we have no errors on the specific PHB or only 15932a485ad7SGavin Shan * informative error there, we continue poking it. 15942a485ad7SGavin Shan * Otherwise, we need actions to be taken by upper 15952a485ad7SGavin Shan * layer. 15962a485ad7SGavin Shan */ 15972a485ad7SGavin Shan if (ret > EEH_NEXT_ERR_INF) 159829310e5eSGavin Shan break; 159929310e5eSGavin Shan } 160029310e5eSGavin Shan 160179231448SAlistair Popple /* Unmask the event */ 1602b8d65e96SAlistair Popple if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 160379231448SAlistair Popple enable_irq(eeh_event_irq); 160479231448SAlistair Popple 16052a485ad7SGavin Shan return ret; 160629310e5eSGavin Shan } 160729310e5eSGavin Shan 16080bd78587SGavin Shan static int pnv_eeh_restore_config(struct pci_dn *pdn) 16099be3beccSGavin Shan { 16100bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 16119be3beccSGavin Shan struct pnv_phb *phb; 161264ba3dc7SBryant G. Ly s64 ret = 0; 1613405b33a7SAlexey Kardashevskiy int config_addr = (pdn->busno << 8) | (pdn->devfn); 16149be3beccSGavin Shan 16159be3beccSGavin Shan if (!edev) 16169be3beccSGavin Shan return -EEXIST; 16179be3beccSGavin Shan 16180dc2830eSWei Yang /* 16190dc2830eSWei Yang * We have to restore the PCI config space after reset since the 16200dc2830eSWei Yang * firmware can't see SRIOV VFs. 16210dc2830eSWei Yang * 16220dc2830eSWei Yang * FIXME: The MPS, error routing rules, timeout setting are worthy 16230dc2830eSWei Yang * to be exported by firmware in extendible way. 16240dc2830eSWei Yang */ 16250dc2830eSWei Yang if (edev->physfn) { 162664ba3dc7SBryant G. Ly ret = eeh_restore_vf_config(pdn); 16270dc2830eSWei Yang } else { 162869672bd7SAlexey Kardashevskiy phb = pdn->phb->private_data; 16299be3beccSGavin Shan ret = opal_pci_reinit(phb->opal_id, 1630405b33a7SAlexey Kardashevskiy OPAL_REINIT_PCI_DEV, config_addr); 16310dc2830eSWei Yang } 16320dc2830eSWei Yang 16339be3beccSGavin Shan if (ret) { 16349be3beccSGavin Shan pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 1635405b33a7SAlexey Kardashevskiy __func__, config_addr, ret); 16369be3beccSGavin Shan return -EIO; 16379be3beccSGavin Shan } 16389be3beccSGavin Shan 163964ba3dc7SBryant G. Ly return ret; 16409be3beccSGavin Shan } 16419be3beccSGavin Shan 164201f3bfb7SGavin Shan static struct eeh_ops pnv_eeh_ops = { 164329310e5eSGavin Shan .name = "powernv", 164401f3bfb7SGavin Shan .init = pnv_eeh_init, 1645ff57b454SGavin Shan .probe = pnv_eeh_probe, 164601f3bfb7SGavin Shan .set_option = pnv_eeh_set_option, 164701f3bfb7SGavin Shan .get_pe_addr = pnv_eeh_get_pe_addr, 164801f3bfb7SGavin Shan .get_state = pnv_eeh_get_state, 164901f3bfb7SGavin Shan .reset = pnv_eeh_reset, 165001f3bfb7SGavin Shan .get_log = pnv_eeh_get_log, 165101f3bfb7SGavin Shan .configure_bridge = pnv_eeh_configure_bridge, 165201f3bfb7SGavin Shan .err_inject = pnv_eeh_err_inject, 165301f3bfb7SGavin Shan .read_config = pnv_eeh_read_config, 165401f3bfb7SGavin Shan .write_config = pnv_eeh_write_config, 165501f3bfb7SGavin Shan .next_error = pnv_eeh_next_error, 165667923cfcSBryant G. Ly .restore_config = pnv_eeh_restore_config, 165767923cfcSBryant G. Ly .notify_resume = NULL 165829310e5eSGavin Shan }; 165929310e5eSGavin Shan 16600dc2830eSWei Yang #ifdef CONFIG_PCI_IOV 16610dc2830eSWei Yang static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 16620dc2830eSWei Yang { 16630dc2830eSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 16640dc2830eSWei Yang int parent_mps; 16650dc2830eSWei Yang 16660dc2830eSWei Yang if (!pdev->is_virtfn) 16670dc2830eSWei Yang return; 16680dc2830eSWei Yang 16690dc2830eSWei Yang /* Synchronize MPS for VF and PF */ 16700dc2830eSWei Yang parent_mps = pcie_get_mps(pdev->physfn); 16710dc2830eSWei Yang if ((128 << pdev->pcie_mpss) >= parent_mps) 16720dc2830eSWei Yang pcie_set_mps(pdev, parent_mps); 16730dc2830eSWei Yang pdn->mps = pcie_get_mps(pdev); 16740dc2830eSWei Yang } 16750dc2830eSWei Yang DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 16760dc2830eSWei Yang #endif /* CONFIG_PCI_IOV */ 16770dc2830eSWei Yang 167829310e5eSGavin Shan /** 167929310e5eSGavin Shan * eeh_powernv_init - Register platform dependent EEH operations 168029310e5eSGavin Shan * 168129310e5eSGavin Shan * EEH initialization on powernv platform. This function should be 168229310e5eSGavin Shan * called before any EEH related functions. 168329310e5eSGavin Shan */ 168429310e5eSGavin Shan static int __init eeh_powernv_init(void) 168529310e5eSGavin Shan { 168629310e5eSGavin Shan int ret = -EINVAL; 168729310e5eSGavin Shan 168801f3bfb7SGavin Shan ret = eeh_ops_register(&pnv_eeh_ops); 168929310e5eSGavin Shan if (!ret) 169029310e5eSGavin Shan pr_info("EEH: PowerNV platform initialized\n"); 169129310e5eSGavin Shan else 169229310e5eSGavin Shan pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 169329310e5eSGavin Shan 169429310e5eSGavin Shan return ret; 169529310e5eSGavin Shan } 1696b14726c5SMichael Ellerman machine_early_initcall(powernv, eeh_powernv_init); 1697