12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 229310e5eSGavin Shan /* 341732bdcSStewart Smith * PowerNV Platform dependent EEH operations 429310e5eSGavin Shan * 529310e5eSGavin Shan * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013. 629310e5eSGavin Shan */ 729310e5eSGavin Shan 829310e5eSGavin Shan #include <linux/atomic.h> 94cf17445SGavin Shan #include <linux/debugfs.h> 1029310e5eSGavin Shan #include <linux/delay.h> 1129310e5eSGavin Shan #include <linux/export.h> 1229310e5eSGavin Shan #include <linux/init.h> 1379231448SAlistair Popple #include <linux/interrupt.h> 1429310e5eSGavin Shan #include <linux/list.h> 1529310e5eSGavin Shan #include <linux/msi.h> 1629310e5eSGavin Shan #include <linux/of.h> 1729310e5eSGavin Shan #include <linux/pci.h> 1829310e5eSGavin Shan #include <linux/proc_fs.h> 1929310e5eSGavin Shan #include <linux/rbtree.h> 2029310e5eSGavin Shan #include <linux/sched.h> 2129310e5eSGavin Shan #include <linux/seq_file.h> 2229310e5eSGavin Shan #include <linux/spinlock.h> 2329310e5eSGavin Shan 2429310e5eSGavin Shan #include <asm/eeh.h> 2529310e5eSGavin Shan #include <asm/eeh_event.h> 2629310e5eSGavin Shan #include <asm/firmware.h> 2729310e5eSGavin Shan #include <asm/io.h> 2829310e5eSGavin Shan #include <asm/iommu.h> 2929310e5eSGavin Shan #include <asm/machdep.h> 3029310e5eSGavin Shan #include <asm/msi_bitmap.h> 3129310e5eSGavin Shan #include <asm/opal.h> 3229310e5eSGavin Shan #include <asm/ppc-pci.h> 339c0e1ecbSGavin Shan #include <asm/pnv-pci.h> 3429310e5eSGavin Shan 3529310e5eSGavin Shan #include "powernv.h" 3629310e5eSGavin Shan #include "pci.h" 3729310e5eSGavin Shan 3879231448SAlistair Popple static int eeh_event_irq = -EINVAL; 394cf17445SGavin Shan 40988fc3baSBryant G. Ly void pnv_pcibios_bus_add_device(struct pci_dev *pdev) 41988fc3baSBryant G. Ly { 42988fc3baSBryant G. Ly struct pci_dn *pdn = pci_get_pdn(pdev); 43988fc3baSBryant G. Ly 44b905f8cdSSam Bobroff if (eeh_has_flag(EEH_FORCE_DISABLED)) 45988fc3baSBryant G. Ly return; 46988fc3baSBryant G. Ly 471ff8f36fSSam Bobroff dev_dbg(&pdev->dev, "EEH: Setting up device\n"); 48988fc3baSBryant G. Ly eeh_add_device_early(pdn); 49988fc3baSBryant G. Ly eeh_add_device_late(pdev); 50988fc3baSBryant G. Ly eeh_sysfs_add_device(pdev); 51988fc3baSBryant G. Ly } 52988fc3baSBryant G. Ly 5301f3bfb7SGavin Shan static int pnv_eeh_init(void) 5429310e5eSGavin Shan { 55dc561fb9SGavin Shan struct pci_controller *hose; 56dc561fb9SGavin Shan struct pnv_phb *phb; 575cb1f8fdSRussell Currey int max_diag_size = PNV_PCI_DIAG_BUF_SIZE; 58dc561fb9SGavin Shan 59e4d54f71SStewart Smith if (!firmware_has_feature(FW_FEATURE_OPAL)) { 60e4d54f71SStewart Smith pr_warn("%s: OPAL is required !\n", 610dae2743SGavin Shan __func__); 6229310e5eSGavin Shan return -EINVAL; 6329310e5eSGavin Shan } 6429310e5eSGavin Shan 6505b1721dSGavin Shan /* Set probe mode */ 6605b1721dSGavin Shan eeh_add_flag(EEH_PROBE_MODE_DEV); 6729310e5eSGavin Shan 68dc561fb9SGavin Shan /* 69dc561fb9SGavin Shan * P7IOC blocks PCI config access to frozen PE, but PHB3 70dc561fb9SGavin Shan * doesn't do that. So we have to selectively enable I/O 71dc561fb9SGavin Shan * prior to collecting error log. 72dc561fb9SGavin Shan */ 73dc561fb9SGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 74dc561fb9SGavin Shan phb = hose->private_data; 75dc561fb9SGavin Shan 76dc561fb9SGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC) 77dc561fb9SGavin Shan eeh_add_flag(EEH_ENABLE_IO_FOR_LOG); 782aa5cf9eSGavin Shan 795cb1f8fdSRussell Currey if (phb->diag_data_size > max_diag_size) 805cb1f8fdSRussell Currey max_diag_size = phb->diag_data_size; 815cb1f8fdSRussell Currey 822aa5cf9eSGavin Shan /* 832aa5cf9eSGavin Shan * PE#0 should be regarded as valid by EEH core 842aa5cf9eSGavin Shan * if it's not the reserved one. Currently, we 85608fb9c2SGavin Shan * have the reserved PE#255 and PE#127 for PHB3 862aa5cf9eSGavin Shan * and P7IOC separately. So we should regard 87608fb9c2SGavin Shan * PE#0 as valid for PHB3 and P7IOC. 882aa5cf9eSGavin Shan */ 8992b8f137SGavin Shan if (phb->ioda.reserved_pe_idx != 0) 902aa5cf9eSGavin Shan eeh_add_flag(EEH_VALID_PE_ZERO); 912aa5cf9eSGavin Shan 92dc561fb9SGavin Shan break; 93dc561fb9SGavin Shan } 94dc561fb9SGavin Shan 955cb1f8fdSRussell Currey eeh_set_pe_aux_size(max_diag_size); 96988fc3baSBryant G. Ly ppc_md.pcibios_bus_add_device = pnv_pcibios_bus_add_device; 975cb1f8fdSRussell Currey 9829310e5eSGavin Shan return 0; 9929310e5eSGavin Shan } 10029310e5eSGavin Shan 10179231448SAlistair Popple static irqreturn_t pnv_eeh_event(int irq, void *data) 1024cf17445SGavin Shan { 1034cf17445SGavin Shan /* 10479231448SAlistair Popple * We simply send a special EEH event if EEH has been 10579231448SAlistair Popple * enabled. We don't care about EEH events until we've 10679231448SAlistair Popple * finished processing the outstanding ones. Event processing 10779231448SAlistair Popple * gets unmasked in next_error() if EEH is enabled. 1084cf17445SGavin Shan */ 10979231448SAlistair Popple disable_irq_nosync(irq); 1104cf17445SGavin Shan 1114cf17445SGavin Shan if (eeh_enabled()) 1124cf17445SGavin Shan eeh_send_failure_event(NULL); 1134cf17445SGavin Shan 11479231448SAlistair Popple return IRQ_HANDLED; 1154cf17445SGavin Shan } 1164cf17445SGavin Shan 1174cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 1184cf17445SGavin Shan static ssize_t pnv_eeh_ei_write(struct file *filp, 1194cf17445SGavin Shan const char __user *user_buf, 1204cf17445SGavin Shan size_t count, loff_t *ppos) 1214cf17445SGavin Shan { 1224cf17445SGavin Shan struct pci_controller *hose = filp->private_data; 1234cf17445SGavin Shan struct eeh_pe *pe; 1244cf17445SGavin Shan int pe_no, type, func; 1254cf17445SGavin Shan unsigned long addr, mask; 1264cf17445SGavin Shan char buf[50]; 1274cf17445SGavin Shan int ret; 1284cf17445SGavin Shan 1294cf17445SGavin Shan if (!eeh_ops || !eeh_ops->err_inject) 1304cf17445SGavin Shan return -ENXIO; 1314cf17445SGavin Shan 1324cf17445SGavin Shan /* Copy over argument buffer */ 1334cf17445SGavin Shan ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count); 1344cf17445SGavin Shan if (!ret) 1354cf17445SGavin Shan return -EFAULT; 1364cf17445SGavin Shan 1374cf17445SGavin Shan /* Retrieve parameters */ 1384cf17445SGavin Shan ret = sscanf(buf, "%x:%x:%x:%lx:%lx", 1394cf17445SGavin Shan &pe_no, &type, &func, &addr, &mask); 1404cf17445SGavin Shan if (ret != 5) 1414cf17445SGavin Shan return -EINVAL; 1424cf17445SGavin Shan 1434cf17445SGavin Shan /* Retrieve PE */ 1448bae6a23SAlexey Kardashevskiy pe = eeh_pe_get(hose, pe_no, 0); 1454cf17445SGavin Shan if (!pe) 1464cf17445SGavin Shan return -ENODEV; 1474cf17445SGavin Shan 1484cf17445SGavin Shan /* Do error injection */ 1494cf17445SGavin Shan ret = eeh_ops->err_inject(pe, type, func, addr, mask); 1504cf17445SGavin Shan return ret < 0 ? ret : count; 1514cf17445SGavin Shan } 1524cf17445SGavin Shan 1534cf17445SGavin Shan static const struct file_operations pnv_eeh_ei_fops = { 1544cf17445SGavin Shan .open = simple_open, 1554cf17445SGavin Shan .llseek = no_llseek, 1564cf17445SGavin Shan .write = pnv_eeh_ei_write, 1574cf17445SGavin Shan }; 1584cf17445SGavin Shan 1594cf17445SGavin Shan static int pnv_eeh_dbgfs_set(void *data, int offset, u64 val) 1604cf17445SGavin Shan { 1614cf17445SGavin Shan struct pci_controller *hose = data; 1624cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1634cf17445SGavin Shan 1644cf17445SGavin Shan out_be64(phb->regs + offset, val); 1654cf17445SGavin Shan return 0; 1664cf17445SGavin Shan } 1674cf17445SGavin Shan 1684cf17445SGavin Shan static int pnv_eeh_dbgfs_get(void *data, int offset, u64 *val) 1694cf17445SGavin Shan { 1704cf17445SGavin Shan struct pci_controller *hose = data; 1714cf17445SGavin Shan struct pnv_phb *phb = hose->private_data; 1724cf17445SGavin Shan 1734cf17445SGavin Shan *val = in_be64(phb->regs + offset); 1744cf17445SGavin Shan return 0; 1754cf17445SGavin Shan } 1764cf17445SGavin Shan 177ccc9662dSGavin Shan #define PNV_EEH_DBGFS_ENTRY(name, reg) \ 178ccc9662dSGavin Shan static int pnv_eeh_dbgfs_set_##name(void *data, u64 val) \ 179ccc9662dSGavin Shan { \ 180ccc9662dSGavin Shan return pnv_eeh_dbgfs_set(data, reg, val); \ 181ccc9662dSGavin Shan } \ 182ccc9662dSGavin Shan \ 183ccc9662dSGavin Shan static int pnv_eeh_dbgfs_get_##name(void *data, u64 *val) \ 184ccc9662dSGavin Shan { \ 185ccc9662dSGavin Shan return pnv_eeh_dbgfs_get(data, reg, val); \ 186ccc9662dSGavin Shan } \ 187ccc9662dSGavin Shan \ 188ccc9662dSGavin Shan DEFINE_SIMPLE_ATTRIBUTE(pnv_eeh_dbgfs_ops_##name, \ 189ccc9662dSGavin Shan pnv_eeh_dbgfs_get_##name, \ 190ccc9662dSGavin Shan pnv_eeh_dbgfs_set_##name, \ 191ccc9662dSGavin Shan "0x%llx\n") 1924cf17445SGavin Shan 193ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(outb, 0xD10); 194ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbA, 0xD90); 195ccc9662dSGavin Shan PNV_EEH_DBGFS_ENTRY(inbB, 0xE10); 1964cf17445SGavin Shan 1974cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 1984cf17445SGavin Shan 199b905f8cdSSam Bobroff void pnv_eeh_enable_phbs(void) 200b905f8cdSSam Bobroff { 201b905f8cdSSam Bobroff struct pci_controller *hose; 202b905f8cdSSam Bobroff struct pnv_phb *phb; 203b905f8cdSSam Bobroff 204b905f8cdSSam Bobroff list_for_each_entry(hose, &hose_list, list_node) { 205b905f8cdSSam Bobroff phb = hose->private_data; 206b905f8cdSSam Bobroff /* 207b905f8cdSSam Bobroff * If EEH is enabled, we're going to rely on that. 208b905f8cdSSam Bobroff * Otherwise, we restore to conventional mechanism 209b905f8cdSSam Bobroff * to clear frozen PE during PCI config access. 210b905f8cdSSam Bobroff */ 211b905f8cdSSam Bobroff if (eeh_enabled()) 212b905f8cdSSam Bobroff phb->flags |= PNV_PHB_FLAG_EEH; 213b905f8cdSSam Bobroff else 214b905f8cdSSam Bobroff phb->flags &= ~PNV_PHB_FLAG_EEH; 215b905f8cdSSam Bobroff } 216b905f8cdSSam Bobroff } 217b905f8cdSSam Bobroff 21829310e5eSGavin Shan /** 21901f3bfb7SGavin Shan * pnv_eeh_post_init - EEH platform dependent post initialization 22029310e5eSGavin Shan * 22129310e5eSGavin Shan * EEH platform dependent post initialization on powernv. When 22229310e5eSGavin Shan * the function is called, the EEH PEs and devices should have 22329310e5eSGavin Shan * been built. If the I/O cache staff has been built, EEH is 22429310e5eSGavin Shan * ready to supply service. 22529310e5eSGavin Shan */ 226b9fde58dSBenjamin Herrenschmidt int pnv_eeh_post_init(void) 22729310e5eSGavin Shan { 22829310e5eSGavin Shan struct pci_controller *hose; 22929310e5eSGavin Shan struct pnv_phb *phb; 23029310e5eSGavin Shan int ret = 0; 23129310e5eSGavin Shan 232c44e4ccaSSam Bobroff eeh_show_enabled(); 233b9fde58dSBenjamin Herrenschmidt 2344cf17445SGavin Shan /* Register OPAL event notifier */ 23579231448SAlistair Popple eeh_event_irq = opal_event_request(ilog2(OPAL_EVENT_PCI_ERROR)); 23679231448SAlistair Popple if (eeh_event_irq < 0) { 23779231448SAlistair Popple pr_err("%s: Can't register OPAL event interrupt (%d)\n", 23879231448SAlistair Popple __func__, eeh_event_irq); 23979231448SAlistair Popple return eeh_event_irq; 24079231448SAlistair Popple } 24179231448SAlistair Popple 24279231448SAlistair Popple ret = request_irq(eeh_event_irq, pnv_eeh_event, 24379231448SAlistair Popple IRQ_TYPE_LEVEL_HIGH, "opal-eeh", NULL); 24479231448SAlistair Popple if (ret < 0) { 24579231448SAlistair Popple irq_dispose_mapping(eeh_event_irq); 24679231448SAlistair Popple pr_err("%s: Can't request OPAL event interrupt (%d)\n", 24779231448SAlistair Popple __func__, eeh_event_irq); 2484cf17445SGavin Shan return ret; 2494cf17445SGavin Shan } 2504cf17445SGavin Shan 25179231448SAlistair Popple if (!eeh_enabled()) 25279231448SAlistair Popple disable_irq(eeh_event_irq); 25379231448SAlistair Popple 254b905f8cdSSam Bobroff pnv_eeh_enable_phbs(); 255b905f8cdSSam Bobroff 25629310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 25729310e5eSGavin Shan phb = hose->private_data; 25829310e5eSGavin Shan 2594cf17445SGavin Shan /* Create debugfs entries */ 2604cf17445SGavin Shan #ifdef CONFIG_DEBUG_FS 2614cf17445SGavin Shan if (phb->has_dbgfs || !phb->dbgfs) 2624cf17445SGavin Shan continue; 2634cf17445SGavin Shan 2644cf17445SGavin Shan phb->has_dbgfs = 1; 2654cf17445SGavin Shan debugfs_create_file("err_injct", 0200, 2664cf17445SGavin Shan phb->dbgfs, hose, 2674cf17445SGavin Shan &pnv_eeh_ei_fops); 2684cf17445SGavin Shan 2694cf17445SGavin Shan debugfs_create_file("err_injct_outbound", 0600, 2704cf17445SGavin Shan phb->dbgfs, hose, 271ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_outb); 2724cf17445SGavin Shan debugfs_create_file("err_injct_inboundA", 0600, 2734cf17445SGavin Shan phb->dbgfs, hose, 274ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbA); 2754cf17445SGavin Shan debugfs_create_file("err_injct_inboundB", 0600, 2764cf17445SGavin Shan phb->dbgfs, hose, 277ccc9662dSGavin Shan &pnv_eeh_dbgfs_ops_inbB); 2784cf17445SGavin Shan #endif /* CONFIG_DEBUG_FS */ 27929310e5eSGavin Shan } 2804cf17445SGavin Shan 28129310e5eSGavin Shan return ret; 28229310e5eSGavin Shan } 28329310e5eSGavin Shan 2844d6186caSGavin Shan static int pnv_eeh_find_cap(struct pci_dn *pdn, int cap) 285ff57b454SGavin Shan { 2864d6186caSGavin Shan int pos = PCI_CAPABILITY_LIST; 2874d6186caSGavin Shan int cnt = 48; /* Maximal number of capabilities */ 2884d6186caSGavin Shan u32 status, id; 289ff57b454SGavin Shan 290ff57b454SGavin Shan if (!pdn) 291ff57b454SGavin Shan return 0; 292ff57b454SGavin Shan 2934d6186caSGavin Shan /* Check if the device supports capabilities */ 294ff57b454SGavin Shan pnv_pci_cfg_read(pdn, PCI_STATUS, 2, &status); 295ff57b454SGavin Shan if (!(status & PCI_STATUS_CAP_LIST)) 296ff57b454SGavin Shan return 0; 297ff57b454SGavin Shan 298ff57b454SGavin Shan while (cnt--) { 299ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos, 1, &pos); 300ff57b454SGavin Shan if (pos < 0x40) 301ff57b454SGavin Shan break; 302ff57b454SGavin Shan 303ff57b454SGavin Shan pos &= ~3; 304ff57b454SGavin Shan pnv_pci_cfg_read(pdn, pos + PCI_CAP_LIST_ID, 1, &id); 305ff57b454SGavin Shan if (id == 0xff) 306ff57b454SGavin Shan break; 307ff57b454SGavin Shan 308ff57b454SGavin Shan /* Found */ 309ff57b454SGavin Shan if (id == cap) 310ff57b454SGavin Shan return pos; 311ff57b454SGavin Shan 312ff57b454SGavin Shan /* Next one */ 313ff57b454SGavin Shan pos += PCI_CAP_LIST_NEXT; 314ff57b454SGavin Shan } 315ff57b454SGavin Shan 316ff57b454SGavin Shan return 0; 317ff57b454SGavin Shan } 318ff57b454SGavin Shan 319ff57b454SGavin Shan static int pnv_eeh_find_ecap(struct pci_dn *pdn, int cap) 320ff57b454SGavin Shan { 321ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 322ff57b454SGavin Shan u32 header; 323ff57b454SGavin Shan int pos = 256, ttl = (4096 - 256) / 8; 324ff57b454SGavin Shan 325ff57b454SGavin Shan if (!edev || !edev->pcie_cap) 326ff57b454SGavin Shan return 0; 327ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 328ff57b454SGavin Shan return 0; 329ff57b454SGavin Shan else if (!header) 330ff57b454SGavin Shan return 0; 331ff57b454SGavin Shan 332ff57b454SGavin Shan while (ttl-- > 0) { 333ff57b454SGavin Shan if (PCI_EXT_CAP_ID(header) == cap && pos) 334ff57b454SGavin Shan return pos; 335ff57b454SGavin Shan 336ff57b454SGavin Shan pos = PCI_EXT_CAP_NEXT(header); 337ff57b454SGavin Shan if (pos < 256) 338ff57b454SGavin Shan break; 339ff57b454SGavin Shan 340ff57b454SGavin Shan if (pnv_pci_cfg_read(pdn, pos, 4, &header) != PCIBIOS_SUCCESSFUL) 341ff57b454SGavin Shan break; 342ff57b454SGavin Shan } 343ff57b454SGavin Shan 344ff57b454SGavin Shan return 0; 345ff57b454SGavin Shan } 346ff57b454SGavin Shan 34729310e5eSGavin Shan /** 348ff57b454SGavin Shan * pnv_eeh_probe - Do probe on PCI device 349ff57b454SGavin Shan * @pdn: PCI device node 350ff57b454SGavin Shan * @data: unused 35129310e5eSGavin Shan * 35229310e5eSGavin Shan * When EEH module is installed during system boot, all PCI devices 35329310e5eSGavin Shan * are checked one by one to see if it supports EEH. The function 35429310e5eSGavin Shan * is introduced for the purpose. By default, EEH has been enabled 35529310e5eSGavin Shan * on all PCI devices. That's to say, we only need do necessary 35629310e5eSGavin Shan * initialization on the corresponding eeh device and create PE 35729310e5eSGavin Shan * accordingly. 35829310e5eSGavin Shan * 35929310e5eSGavin Shan * It's notable that's unsafe to retrieve the EEH device through 36029310e5eSGavin Shan * the corresponding PCI device. During the PCI device hotplug, which 36129310e5eSGavin Shan * was possiblly triggered by EEH core, the binding between EEH device 36229310e5eSGavin Shan * and the PCI device isn't built yet. 36329310e5eSGavin Shan */ 364ff57b454SGavin Shan static void *pnv_eeh_probe(struct pci_dn *pdn, void *data) 36529310e5eSGavin Shan { 366ff57b454SGavin Shan struct pci_controller *hose = pdn->phb; 36729310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 368ff57b454SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 369ff57b454SGavin Shan uint32_t pcie_flags; 370dadcd6d6SMike Qiu int ret; 371405b33a7SAlexey Kardashevskiy int config_addr = (pdn->busno << 8) | (pdn->devfn); 37229310e5eSGavin Shan 37329310e5eSGavin Shan /* 37429310e5eSGavin Shan * When probing the root bridge, which doesn't have any 37529310e5eSGavin Shan * subordinate PCI devices. We don't have OF node for 37629310e5eSGavin Shan * the root bridge. So it's not reasonable to continue 37729310e5eSGavin Shan * the probing. 37829310e5eSGavin Shan */ 379ff57b454SGavin Shan if (!edev || edev->pe) 380ff57b454SGavin Shan return NULL; 38129310e5eSGavin Shan 38229310e5eSGavin Shan /* Skip for PCI-ISA bridge */ 383ff57b454SGavin Shan if ((pdn->class_code >> 8) == PCI_CLASS_BRIDGE_ISA) 384ff57b454SGavin Shan return NULL; 38529310e5eSGavin Shan 3861ff8f36fSSam Bobroff eeh_edev_dbg(edev, "Probing device\n"); 3871ff8f36fSSam Bobroff 38829310e5eSGavin Shan /* Initialize eeh device */ 389ff57b454SGavin Shan edev->class_code = pdn->class_code; 390ab55d218SGavin Shan edev->mode &= 0xFFFFFF00; 391ff57b454SGavin Shan edev->pcix_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_PCIX); 392ff57b454SGavin Shan edev->pcie_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_EXP); 3939312bc5bSWei Yang edev->af_cap = pnv_eeh_find_cap(pdn, PCI_CAP_ID_AF); 394ff57b454SGavin Shan edev->aer_cap = pnv_eeh_find_ecap(pdn, PCI_EXT_CAP_ID_ERR); 395ff57b454SGavin Shan if ((edev->class_code >> 8) == PCI_CLASS_BRIDGE_PCI) { 3964b83bd45SGavin Shan edev->mode |= EEH_DEV_BRIDGE; 397ff57b454SGavin Shan if (edev->pcie_cap) { 398ff57b454SGavin Shan pnv_pci_cfg_read(pdn, edev->pcie_cap + PCI_EXP_FLAGS, 399ff57b454SGavin Shan 2, &pcie_flags); 400ff57b454SGavin Shan pcie_flags = (pcie_flags & PCI_EXP_FLAGS_TYPE) >> 4; 401ff57b454SGavin Shan if (pcie_flags == PCI_EXP_TYPE_ROOT_PORT) 4024b83bd45SGavin Shan edev->mode |= EEH_DEV_ROOT_PORT; 403ff57b454SGavin Shan else if (pcie_flags == PCI_EXP_TYPE_DOWNSTREAM) 4044b83bd45SGavin Shan edev->mode |= EEH_DEV_DS_PORT; 405ff57b454SGavin Shan } 4064b83bd45SGavin Shan } 4074b83bd45SGavin Shan 408405b33a7SAlexey Kardashevskiy edev->pe_config_addr = phb->ioda.pe_rmap[config_addr]; 40929310e5eSGavin Shan 41029310e5eSGavin Shan /* Create PE */ 411dadcd6d6SMike Qiu ret = eeh_add_to_parent_pe(edev); 412dadcd6d6SMike Qiu if (ret) { 4131ff8f36fSSam Bobroff eeh_edev_warn(edev, "Failed to add device to PE (code %d)\n", ret); 414ff57b454SGavin Shan return NULL; 415dadcd6d6SMike Qiu } 416dadcd6d6SMike Qiu 417dadcd6d6SMike Qiu /* 418b6541db1SGavin Shan * If the PE contains any one of following adapters, the 419b6541db1SGavin Shan * PCI config space can't be accessed when dumping EEH log. 420b6541db1SGavin Shan * Otherwise, we will run into fenced PHB caused by shortage 421b6541db1SGavin Shan * of outbound credits in the adapter. The PCI config access 422b6541db1SGavin Shan * should be blocked until PE reset. MMIO access is dropped 423b6541db1SGavin Shan * by hardware certainly. In order to drop PCI config requests, 424b6541db1SGavin Shan * one more flag (EEH_PE_CFG_RESTRICTED) is introduced, which 425b6541db1SGavin Shan * will be checked in the backend for PE state retrival. If 426b6541db1SGavin Shan * the PE becomes frozen for the first time and the flag has 427b6541db1SGavin Shan * been set for the PE, we will set EEH_PE_CFG_BLOCKED for 428b6541db1SGavin Shan * that PE to block its config space. 429b6541db1SGavin Shan * 430c374ed27SGavin Shan * Broadcom BCM5718 2-ports NICs (14e4:1656) 431b6541db1SGavin Shan * Broadcom Austin 4-ports NICs (14e4:1657) 432353169acSGavin Shan * Broadcom Shiner 4-ports 1G NICs (14e4:168a) 433179ea48bSGavin Shan * Broadcom Shiner 2-ports 10G NICs (14e4:168e) 434b6541db1SGavin Shan */ 435ff57b454SGavin Shan if ((pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 436c374ed27SGavin Shan pdn->device_id == 0x1656) || 437c374ed27SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 438ff57b454SGavin Shan pdn->device_id == 0x1657) || 439ff57b454SGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 440353169acSGavin Shan pdn->device_id == 0x168a) || 441353169acSGavin Shan (pdn->vendor_id == PCI_VENDOR_ID_BROADCOM && 442ff57b454SGavin Shan pdn->device_id == 0x168e)) 443b6541db1SGavin Shan edev->pe->state |= EEH_PE_CFG_RESTRICTED; 444b6541db1SGavin Shan 445b6541db1SGavin Shan /* 446dadcd6d6SMike Qiu * Cache the PE primary bus, which can't be fetched when 447dadcd6d6SMike Qiu * full hotplug is in progress. In that case, all child 448dadcd6d6SMike Qiu * PCI devices of the PE are expected to be removed prior 449dadcd6d6SMike Qiu * to PE reset. 450dadcd6d6SMike Qiu */ 45105ba75f8SGavin Shan if (!(edev->pe->state & EEH_PE_PRI_BUS)) { 452ff57b454SGavin Shan edev->pe->bus = pci_find_bus(hose->global_number, 453ff57b454SGavin Shan pdn->busno); 45405ba75f8SGavin Shan if (edev->pe->bus) 45505ba75f8SGavin Shan edev->pe->state |= EEH_PE_PRI_BUS; 45605ba75f8SGavin Shan } 45729310e5eSGavin Shan 45829310e5eSGavin Shan /* 45929310e5eSGavin Shan * Enable EEH explicitly so that we will do EEH check 46029310e5eSGavin Shan * while accessing I/O stuff 46129310e5eSGavin Shan */ 462b905f8cdSSam Bobroff if (!eeh_has_flag(EEH_ENABLED)) { 463b905f8cdSSam Bobroff enable_irq(eeh_event_irq); 464b905f8cdSSam Bobroff pnv_eeh_enable_phbs(); 46505b1721dSGavin Shan eeh_add_flag(EEH_ENABLED); 466b905f8cdSSam Bobroff } 46729310e5eSGavin Shan 46829310e5eSGavin Shan /* Save memory bars */ 46929310e5eSGavin Shan eeh_save_bars(edev); 47029310e5eSGavin Shan 4711ff8f36fSSam Bobroff eeh_edev_dbg(edev, "EEH enabled on device\n"); 472617082a4SSam Bobroff 473ff57b454SGavin Shan return NULL; 47429310e5eSGavin Shan } 47529310e5eSGavin Shan 47629310e5eSGavin Shan /** 47701f3bfb7SGavin Shan * pnv_eeh_set_option - Initialize EEH or MMIO/DMA reenable 47829310e5eSGavin Shan * @pe: EEH PE 47929310e5eSGavin Shan * @option: operation to be issued 48029310e5eSGavin Shan * 48129310e5eSGavin Shan * The function is used to control the EEH functionality globally. 48229310e5eSGavin Shan * Currently, following options are support according to PAPR: 48329310e5eSGavin Shan * Enable EEH, Disable EEH, Enable MMIO and Enable DMA 48429310e5eSGavin Shan */ 48501f3bfb7SGavin Shan static int pnv_eeh_set_option(struct eeh_pe *pe, int option) 48629310e5eSGavin Shan { 48729310e5eSGavin Shan struct pci_controller *hose = pe->phb; 48829310e5eSGavin Shan struct pnv_phb *phb = hose->private_data; 4897e3e4f8dSGavin Shan bool freeze_pe = false; 490f9433718SGavin Shan int opt; 4917e3e4f8dSGavin Shan s64 rc; 49229310e5eSGavin Shan 4937e3e4f8dSGavin Shan switch (option) { 4947e3e4f8dSGavin Shan case EEH_OPT_DISABLE: 4957e3e4f8dSGavin Shan return -EPERM; 4967e3e4f8dSGavin Shan case EEH_OPT_ENABLE: 4977e3e4f8dSGavin Shan return 0; 4987e3e4f8dSGavin Shan case EEH_OPT_THAW_MMIO: 4997e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO; 5007e3e4f8dSGavin Shan break; 5017e3e4f8dSGavin Shan case EEH_OPT_THAW_DMA: 5027e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_CLEAR_FREEZE_DMA; 5037e3e4f8dSGavin Shan break; 5047e3e4f8dSGavin Shan case EEH_OPT_FREEZE_PE: 5057e3e4f8dSGavin Shan freeze_pe = true; 5067e3e4f8dSGavin Shan opt = OPAL_EEH_ACTION_SET_FREEZE_ALL; 5077e3e4f8dSGavin Shan break; 5087e3e4f8dSGavin Shan default: 5097e3e4f8dSGavin Shan pr_warn("%s: Invalid option %d\n", __func__, option); 5107e3e4f8dSGavin Shan return -EINVAL; 5117e3e4f8dSGavin Shan } 5127e3e4f8dSGavin Shan 513f9433718SGavin Shan /* Freeze master and slave PEs if PHB supports compound PEs */ 5147e3e4f8dSGavin Shan if (freeze_pe) { 5157e3e4f8dSGavin Shan if (phb->freeze_pe) { 5167e3e4f8dSGavin Shan phb->freeze_pe(phb, pe->addr); 517f9433718SGavin Shan return 0; 5187e3e4f8dSGavin Shan } 51929310e5eSGavin Shan 520f9433718SGavin Shan rc = opal_pci_eeh_freeze_set(phb->opal_id, pe->addr, opt); 521f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 522f9433718SGavin Shan pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", 523f9433718SGavin Shan __func__, rc, phb->hose->global_number, 524f9433718SGavin Shan pe->addr); 525f9433718SGavin Shan return -EIO; 526f9433718SGavin Shan } 527f9433718SGavin Shan 528f9433718SGavin Shan return 0; 529f9433718SGavin Shan } 530f9433718SGavin Shan 531f9433718SGavin Shan /* Unfreeze master and slave PEs if PHB supports */ 532f9433718SGavin Shan if (phb->unfreeze_pe) 533f9433718SGavin Shan return phb->unfreeze_pe(phb, pe->addr, opt); 534f9433718SGavin Shan 535f9433718SGavin Shan rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe->addr, opt); 536f9433718SGavin Shan if (rc != OPAL_SUCCESS) { 537f9433718SGavin Shan pr_warn("%s: Failure %lld enable %d for PHB#%x-PE#%x\n", 538f9433718SGavin Shan __func__, rc, option, phb->hose->global_number, 539f9433718SGavin Shan pe->addr); 540f9433718SGavin Shan return -EIO; 541f9433718SGavin Shan } 542f9433718SGavin Shan 543f9433718SGavin Shan return 0; 54429310e5eSGavin Shan } 54529310e5eSGavin Shan 54629310e5eSGavin Shan /** 54701f3bfb7SGavin Shan * pnv_eeh_get_pe_addr - Retrieve PE address 54829310e5eSGavin Shan * @pe: EEH PE 54929310e5eSGavin Shan * 55029310e5eSGavin Shan * Retrieve the PE address according to the given tranditional 55129310e5eSGavin Shan * PCI BDF (Bus/Device/Function) address. 55229310e5eSGavin Shan */ 55301f3bfb7SGavin Shan static int pnv_eeh_get_pe_addr(struct eeh_pe *pe) 55429310e5eSGavin Shan { 55529310e5eSGavin Shan return pe->addr; 55629310e5eSGavin Shan } 55729310e5eSGavin Shan 55840ae5f69SGavin Shan static void pnv_eeh_get_phb_diag(struct eeh_pe *pe) 55940ae5f69SGavin Shan { 56040ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 56140ae5f69SGavin Shan s64 rc; 56240ae5f69SGavin Shan 56340ae5f69SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data, 5645cb1f8fdSRussell Currey phb->diag_data_size); 56540ae5f69SGavin Shan if (rc != OPAL_SUCCESS) 56640ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x diag-data\n", 56740ae5f69SGavin Shan __func__, rc, pe->phb->global_number); 56840ae5f69SGavin Shan } 56940ae5f69SGavin Shan 57040ae5f69SGavin Shan static int pnv_eeh_get_phb_state(struct eeh_pe *pe) 57140ae5f69SGavin Shan { 57240ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 573c2057701SAlexey Kardashevskiy u8 fstate = 0; 574c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 57540ae5f69SGavin Shan s64 rc; 57640ae5f69SGavin Shan int result = 0; 57740ae5f69SGavin Shan 57840ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 57940ae5f69SGavin Shan pe->addr, 58040ae5f69SGavin Shan &fstate, 58140ae5f69SGavin Shan &pcierr, 58240ae5f69SGavin Shan NULL); 58340ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 58440ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x state\n", 58540ae5f69SGavin Shan __func__, rc, phb->hose->global_number); 58640ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 58740ae5f69SGavin Shan } 58840ae5f69SGavin Shan 58940ae5f69SGavin Shan /* 59040ae5f69SGavin Shan * Check PHB state. If the PHB is frozen for the 59140ae5f69SGavin Shan * first time, to dump the PHB diag-data. 59240ae5f69SGavin Shan */ 59340ae5f69SGavin Shan if (be16_to_cpu(pcierr) != OPAL_EEH_PHB_ERROR) { 59440ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 59540ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 59640ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 59740ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 59840ae5f69SGavin Shan } else if (!(pe->state & EEH_PE_ISOLATED)) { 599e762bb89SSam Bobroff eeh_pe_mark_isolated(pe); 60040ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 60140ae5f69SGavin Shan 60240ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 60340ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 60440ae5f69SGavin Shan } 60540ae5f69SGavin Shan 60640ae5f69SGavin Shan return result; 60740ae5f69SGavin Shan } 60840ae5f69SGavin Shan 60940ae5f69SGavin Shan static int pnv_eeh_get_pe_state(struct eeh_pe *pe) 61040ae5f69SGavin Shan { 61140ae5f69SGavin Shan struct pnv_phb *phb = pe->phb->private_data; 612c2057701SAlexey Kardashevskiy u8 fstate = 0; 613c2057701SAlexey Kardashevskiy __be16 pcierr = 0; 61440ae5f69SGavin Shan s64 rc; 61540ae5f69SGavin Shan int result; 61640ae5f69SGavin Shan 61740ae5f69SGavin Shan /* 61840ae5f69SGavin Shan * We don't clobber hardware frozen state until PE 61940ae5f69SGavin Shan * reset is completed. In order to keep EEH core 62040ae5f69SGavin Shan * moving forward, we have to return operational 62140ae5f69SGavin Shan * state during PE reset. 62240ae5f69SGavin Shan */ 62340ae5f69SGavin Shan if (pe->state & EEH_PE_RESET) { 62440ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 62540ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 62640ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 62740ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 62840ae5f69SGavin Shan return result; 62940ae5f69SGavin Shan } 63040ae5f69SGavin Shan 63140ae5f69SGavin Shan /* 63240ae5f69SGavin Shan * Fetch PE state from hardware. If the PHB 63340ae5f69SGavin Shan * supports compound PE, let it handle that. 63440ae5f69SGavin Shan */ 63540ae5f69SGavin Shan if (phb->get_pe_state) { 63640ae5f69SGavin Shan fstate = phb->get_pe_state(phb, pe->addr); 63740ae5f69SGavin Shan } else { 63840ae5f69SGavin Shan rc = opal_pci_eeh_freeze_status(phb->opal_id, 63940ae5f69SGavin Shan pe->addr, 64040ae5f69SGavin Shan &fstate, 64140ae5f69SGavin Shan &pcierr, 64240ae5f69SGavin Shan NULL); 64340ae5f69SGavin Shan if (rc != OPAL_SUCCESS) { 64440ae5f69SGavin Shan pr_warn("%s: Failure %lld getting PHB#%x-PE%x state\n", 64540ae5f69SGavin Shan __func__, rc, phb->hose->global_number, 64640ae5f69SGavin Shan pe->addr); 64740ae5f69SGavin Shan return EEH_STATE_NOT_SUPPORT; 64840ae5f69SGavin Shan } 64940ae5f69SGavin Shan } 65040ae5f69SGavin Shan 65140ae5f69SGavin Shan /* Figure out state */ 65240ae5f69SGavin Shan switch (fstate) { 65340ae5f69SGavin Shan case OPAL_EEH_STOPPED_NOT_FROZEN: 65440ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 65540ae5f69SGavin Shan EEH_STATE_DMA_ACTIVE | 65640ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED | 65740ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 65840ae5f69SGavin Shan break; 65940ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_FREEZE: 66040ae5f69SGavin Shan result = (EEH_STATE_DMA_ACTIVE | 66140ae5f69SGavin Shan EEH_STATE_DMA_ENABLED); 66240ae5f69SGavin Shan break; 66340ae5f69SGavin Shan case OPAL_EEH_STOPPED_DMA_FREEZE: 66440ae5f69SGavin Shan result = (EEH_STATE_MMIO_ACTIVE | 66540ae5f69SGavin Shan EEH_STATE_MMIO_ENABLED); 66640ae5f69SGavin Shan break; 66740ae5f69SGavin Shan case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE: 66840ae5f69SGavin Shan result = 0; 66940ae5f69SGavin Shan break; 67040ae5f69SGavin Shan case OPAL_EEH_STOPPED_RESET: 67140ae5f69SGavin Shan result = EEH_STATE_RESET_ACTIVE; 67240ae5f69SGavin Shan break; 67340ae5f69SGavin Shan case OPAL_EEH_STOPPED_TEMP_UNAVAIL: 67440ae5f69SGavin Shan result = EEH_STATE_UNAVAILABLE; 67540ae5f69SGavin Shan break; 67640ae5f69SGavin Shan case OPAL_EEH_STOPPED_PERM_UNAVAIL: 67740ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 67840ae5f69SGavin Shan break; 67940ae5f69SGavin Shan default: 68040ae5f69SGavin Shan result = EEH_STATE_NOT_SUPPORT; 68140ae5f69SGavin Shan pr_warn("%s: Invalid PHB#%x-PE#%x state %x\n", 68240ae5f69SGavin Shan __func__, phb->hose->global_number, 68340ae5f69SGavin Shan pe->addr, fstate); 68440ae5f69SGavin Shan } 68540ae5f69SGavin Shan 68640ae5f69SGavin Shan /* 68740ae5f69SGavin Shan * If PHB supports compound PE, to freeze all 68840ae5f69SGavin Shan * slave PEs for consistency. 68940ae5f69SGavin Shan * 69040ae5f69SGavin Shan * If the PE is switching to frozen state for the 69140ae5f69SGavin Shan * first time, to dump the PHB diag-data. 69240ae5f69SGavin Shan */ 69340ae5f69SGavin Shan if (!(result & EEH_STATE_NOT_SUPPORT) && 69440ae5f69SGavin Shan !(result & EEH_STATE_UNAVAILABLE) && 69540ae5f69SGavin Shan !(result & EEH_STATE_MMIO_ACTIVE) && 69640ae5f69SGavin Shan !(result & EEH_STATE_DMA_ACTIVE) && 69740ae5f69SGavin Shan !(pe->state & EEH_PE_ISOLATED)) { 69840ae5f69SGavin Shan if (phb->freeze_pe) 69940ae5f69SGavin Shan phb->freeze_pe(phb, pe->addr); 70040ae5f69SGavin Shan 701e762bb89SSam Bobroff eeh_pe_mark_isolated(pe); 70240ae5f69SGavin Shan pnv_eeh_get_phb_diag(pe); 70340ae5f69SGavin Shan 70440ae5f69SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 70540ae5f69SGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 70640ae5f69SGavin Shan } 70740ae5f69SGavin Shan 70840ae5f69SGavin Shan return result; 70940ae5f69SGavin Shan } 71040ae5f69SGavin Shan 71129310e5eSGavin Shan /** 71201f3bfb7SGavin Shan * pnv_eeh_get_state - Retrieve PE state 71329310e5eSGavin Shan * @pe: EEH PE 71429310e5eSGavin Shan * @delay: delay while PE state is temporarily unavailable 71529310e5eSGavin Shan * 71629310e5eSGavin Shan * Retrieve the state of the specified PE. For IODA-compitable 71729310e5eSGavin Shan * platform, it should be retrieved from IODA table. Therefore, 71829310e5eSGavin Shan * we prefer passing down to hardware implementation to handle 71929310e5eSGavin Shan * it. 72029310e5eSGavin Shan */ 72101f3bfb7SGavin Shan static int pnv_eeh_get_state(struct eeh_pe *pe, int *delay) 72229310e5eSGavin Shan { 72340ae5f69SGavin Shan int ret; 72429310e5eSGavin Shan 72540ae5f69SGavin Shan if (pe->type & EEH_PE_PHB) 72640ae5f69SGavin Shan ret = pnv_eeh_get_phb_state(pe); 72740ae5f69SGavin Shan else 72840ae5f69SGavin Shan ret = pnv_eeh_get_pe_state(pe); 72940ae5f69SGavin Shan 73040ae5f69SGavin Shan if (!delay) 73140ae5f69SGavin Shan return ret; 73229310e5eSGavin Shan 73329310e5eSGavin Shan /* 73429310e5eSGavin Shan * If the PE state is temporarily unavailable, 73529310e5eSGavin Shan * to inform the EEH core delay for default 73629310e5eSGavin Shan * period (1 second) 73729310e5eSGavin Shan */ 73829310e5eSGavin Shan *delay = 0; 73929310e5eSGavin Shan if (ret & EEH_STATE_UNAVAILABLE) 74029310e5eSGavin Shan *delay = 1000; 74129310e5eSGavin Shan 74229310e5eSGavin Shan return ret; 74329310e5eSGavin Shan } 74429310e5eSGavin Shan 745ebe22531SGavin Shan static s64 pnv_eeh_poll(unsigned long id) 746cadf364dSGavin Shan { 747cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 748cadf364dSGavin Shan 749cadf364dSGavin Shan while (1) { 750ebe22531SGavin Shan rc = opal_pci_poll(id); 751cadf364dSGavin Shan if (rc <= 0) 752cadf364dSGavin Shan break; 753cadf364dSGavin Shan 754cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 755cadf364dSGavin Shan udelay(1000 * rc); 756cadf364dSGavin Shan else 757cadf364dSGavin Shan msleep(rc); 758cadf364dSGavin Shan } 759cadf364dSGavin Shan 760cadf364dSGavin Shan return rc; 761cadf364dSGavin Shan } 762cadf364dSGavin Shan 763cadf364dSGavin Shan int pnv_eeh_phb_reset(struct pci_controller *hose, int option) 764cadf364dSGavin Shan { 765cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 766cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 767cadf364dSGavin Shan 768cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 769cadf364dSGavin Shan __func__, hose->global_number, option); 770cadf364dSGavin Shan 771cadf364dSGavin Shan /* Issue PHB complete reset request */ 772cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL || 773cadf364dSGavin Shan option == EEH_RESET_HOT) 774cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 775cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 776cadf364dSGavin Shan OPAL_ASSERT_RESET); 777cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 778cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 779cadf364dSGavin Shan OPAL_RESET_PHB_COMPLETE, 780cadf364dSGavin Shan OPAL_DEASSERT_RESET); 781cadf364dSGavin Shan if (rc < 0) 782cadf364dSGavin Shan goto out; 783cadf364dSGavin Shan 784cadf364dSGavin Shan /* 785cadf364dSGavin Shan * Poll state of the PHB until the request is done 786cadf364dSGavin Shan * successfully. The PHB reset is usually PHB complete 787cadf364dSGavin Shan * reset followed by hot reset on root bus. So we also 788cadf364dSGavin Shan * need the PCI bus settlement delay. 789cadf364dSGavin Shan */ 790fbce44d0SGavin Shan if (rc > 0) 791ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 792cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) { 793cadf364dSGavin Shan if (system_state < SYSTEM_RUNNING) 794cadf364dSGavin Shan udelay(1000 * EEH_PE_RST_SETTLE_TIME); 795cadf364dSGavin Shan else 796cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 797cadf364dSGavin Shan } 798cadf364dSGavin Shan out: 799cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 800cadf364dSGavin Shan return -EIO; 801cadf364dSGavin Shan 802cadf364dSGavin Shan return 0; 803cadf364dSGavin Shan } 804cadf364dSGavin Shan 805cadf364dSGavin Shan static int pnv_eeh_root_reset(struct pci_controller *hose, int option) 806cadf364dSGavin Shan { 807cadf364dSGavin Shan struct pnv_phb *phb = hose->private_data; 808cadf364dSGavin Shan s64 rc = OPAL_HARDWARE; 809cadf364dSGavin Shan 810cadf364dSGavin Shan pr_debug("%s: Reset PHB#%x, option=%d\n", 811cadf364dSGavin Shan __func__, hose->global_number, option); 812cadf364dSGavin Shan 813cadf364dSGavin Shan /* 814cadf364dSGavin Shan * During the reset deassert time, we needn't care 815cadf364dSGavin Shan * the reset scope because the firmware does nothing 816cadf364dSGavin Shan * for fundamental or hot reset during deassert phase. 817cadf364dSGavin Shan */ 818cadf364dSGavin Shan if (option == EEH_RESET_FUNDAMENTAL) 819cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 820cadf364dSGavin Shan OPAL_RESET_PCI_FUNDAMENTAL, 821cadf364dSGavin Shan OPAL_ASSERT_RESET); 822cadf364dSGavin Shan else if (option == EEH_RESET_HOT) 823cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 824cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 825cadf364dSGavin Shan OPAL_ASSERT_RESET); 826cadf364dSGavin Shan else if (option == EEH_RESET_DEACTIVATE) 827cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 828cadf364dSGavin Shan OPAL_RESET_PCI_HOT, 829cadf364dSGavin Shan OPAL_DEASSERT_RESET); 830cadf364dSGavin Shan if (rc < 0) 831cadf364dSGavin Shan goto out; 832cadf364dSGavin Shan 833cadf364dSGavin Shan /* Poll state of the PHB until the request is done */ 834fbce44d0SGavin Shan if (rc > 0) 835ebe22531SGavin Shan rc = pnv_eeh_poll(phb->opal_id); 836cadf364dSGavin Shan if (option == EEH_RESET_DEACTIVATE) 837cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 838cadf364dSGavin Shan out: 839cadf364dSGavin Shan if (rc != OPAL_SUCCESS) 840cadf364dSGavin Shan return -EIO; 841cadf364dSGavin Shan 842cadf364dSGavin Shan return 0; 843cadf364dSGavin Shan } 844cadf364dSGavin Shan 8459c0e1ecbSGavin Shan static int __pnv_eeh_bridge_reset(struct pci_dev *dev, int option) 846cadf364dSGavin Shan { 8470bd78587SGavin Shan struct pci_dn *pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn); 8480bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 849cadf364dSGavin Shan int aer = edev ? edev->aer_cap : 0; 850cadf364dSGavin Shan u32 ctrl; 851cadf364dSGavin Shan 852cadf364dSGavin Shan pr_debug("%s: Reset PCI bus %04x:%02x with option %d\n", 853cadf364dSGavin Shan __func__, pci_domain_nr(dev->bus), 854cadf364dSGavin Shan dev->bus->number, option); 855cadf364dSGavin Shan 856cadf364dSGavin Shan switch (option) { 857cadf364dSGavin Shan case EEH_RESET_FUNDAMENTAL: 858cadf364dSGavin Shan case EEH_RESET_HOT: 859cadf364dSGavin Shan /* Don't report linkDown event */ 860cadf364dSGavin Shan if (aer) { 8610bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 862cadf364dSGavin Shan 4, &ctrl); 863cadf364dSGavin Shan ctrl |= PCI_ERR_UNC_SURPDN; 8640bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 865cadf364dSGavin Shan 4, ctrl); 866cadf364dSGavin Shan } 867cadf364dSGavin Shan 8680bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 869cadf364dSGavin Shan ctrl |= PCI_BRIDGE_CTL_BUS_RESET; 8700bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 871cadf364dSGavin Shan 872cadf364dSGavin Shan msleep(EEH_PE_RST_HOLD_TIME); 873cadf364dSGavin Shan break; 874cadf364dSGavin Shan case EEH_RESET_DEACTIVATE: 8750bd78587SGavin Shan eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &ctrl); 876cadf364dSGavin Shan ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; 8770bd78587SGavin Shan eeh_ops->write_config(pdn, PCI_BRIDGE_CONTROL, 2, ctrl); 878cadf364dSGavin Shan 879cadf364dSGavin Shan msleep(EEH_PE_RST_SETTLE_TIME); 880cadf364dSGavin Shan 881cadf364dSGavin Shan /* Continue reporting linkDown event */ 882cadf364dSGavin Shan if (aer) { 8830bd78587SGavin Shan eeh_ops->read_config(pdn, aer + PCI_ERR_UNCOR_MASK, 884cadf364dSGavin Shan 4, &ctrl); 885cadf364dSGavin Shan ctrl &= ~PCI_ERR_UNC_SURPDN; 8860bd78587SGavin Shan eeh_ops->write_config(pdn, aer + PCI_ERR_UNCOR_MASK, 887cadf364dSGavin Shan 4, ctrl); 888cadf364dSGavin Shan } 889cadf364dSGavin Shan 890cadf364dSGavin Shan break; 891cadf364dSGavin Shan } 892cadf364dSGavin Shan 893cadf364dSGavin Shan return 0; 894cadf364dSGavin Shan } 895cadf364dSGavin Shan 8969c0e1ecbSGavin Shan static int pnv_eeh_bridge_reset(struct pci_dev *pdev, int option) 8979c0e1ecbSGavin Shan { 8989c0e1ecbSGavin Shan struct pci_controller *hose = pci_bus_to_host(pdev->bus); 8999c0e1ecbSGavin Shan struct pnv_phb *phb = hose->private_data; 9009c0e1ecbSGavin Shan struct device_node *dn = pci_device_to_OF_node(pdev); 9019c0e1ecbSGavin Shan uint64_t id = PCI_SLOT_ID(phb->opal_id, 9029c0e1ecbSGavin Shan (pdev->bus->number << 8) | pdev->devfn); 9039c0e1ecbSGavin Shan uint8_t scope; 9049c0e1ecbSGavin Shan int64_t rc; 9059c0e1ecbSGavin Shan 9069c0e1ecbSGavin Shan /* Hot reset to the bus if firmware cannot handle */ 9079c0e1ecbSGavin Shan if (!dn || !of_get_property(dn, "ibm,reset-by-firmware", NULL)) 9089c0e1ecbSGavin Shan return __pnv_eeh_bridge_reset(pdev, option); 9099c0e1ecbSGavin Shan 9109c0e1ecbSGavin Shan switch (option) { 9119c0e1ecbSGavin Shan case EEH_RESET_FUNDAMENTAL: 9129c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_FUNDAMENTAL; 9139c0e1ecbSGavin Shan break; 9149c0e1ecbSGavin Shan case EEH_RESET_HOT: 9159c0e1ecbSGavin Shan scope = OPAL_RESET_PCI_HOT; 9169c0e1ecbSGavin Shan break; 9179c0e1ecbSGavin Shan case EEH_RESET_DEACTIVATE: 9189c0e1ecbSGavin Shan return 0; 9199c0e1ecbSGavin Shan default: 9209c0e1ecbSGavin Shan dev_dbg(&pdev->dev, "%s: Unsupported reset %d\n", 9219c0e1ecbSGavin Shan __func__, option); 9229c0e1ecbSGavin Shan return -EINVAL; 9239c0e1ecbSGavin Shan } 9249c0e1ecbSGavin Shan 9259c0e1ecbSGavin Shan rc = opal_pci_reset(id, scope, OPAL_ASSERT_RESET); 9269c0e1ecbSGavin Shan if (rc <= OPAL_SUCCESS) 9279c0e1ecbSGavin Shan goto out; 9289c0e1ecbSGavin Shan 9299c0e1ecbSGavin Shan rc = pnv_eeh_poll(id); 9309c0e1ecbSGavin Shan out: 9319c0e1ecbSGavin Shan return (rc == OPAL_SUCCESS) ? 0 : -EIO; 9329c0e1ecbSGavin Shan } 9339c0e1ecbSGavin Shan 934cadf364dSGavin Shan void pnv_pci_reset_secondary_bus(struct pci_dev *dev) 935cadf364dSGavin Shan { 936848912e5SMichael Ellerman struct pci_controller *hose; 937848912e5SMichael Ellerman 938848912e5SMichael Ellerman if (pci_is_root_bus(dev->bus)) { 939848912e5SMichael Ellerman hose = pci_bus_to_host(dev->bus); 940848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_HOT); 941848912e5SMichael Ellerman pnv_eeh_root_reset(hose, EEH_RESET_DEACTIVATE); 942848912e5SMichael Ellerman } else { 943cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_HOT); 944cadf364dSGavin Shan pnv_eeh_bridge_reset(dev, EEH_RESET_DEACTIVATE); 945cadf364dSGavin Shan } 946848912e5SMichael Ellerman } 947cadf364dSGavin Shan 9489312bc5bSWei Yang static void pnv_eeh_wait_for_pending(struct pci_dn *pdn, const char *type, 9499312bc5bSWei Yang int pos, u16 mask) 9509312bc5bSWei Yang { 9519312bc5bSWei Yang int i, status = 0; 9529312bc5bSWei Yang 9539312bc5bSWei Yang /* Wait for Transaction Pending bit to be cleared */ 9549312bc5bSWei Yang for (i = 0; i < 4; i++) { 9559312bc5bSWei Yang eeh_ops->read_config(pdn, pos, 2, &status); 9569312bc5bSWei Yang if (!(status & mask)) 9579312bc5bSWei Yang return; 9589312bc5bSWei Yang 9599312bc5bSWei Yang msleep((1 << i) * 100); 9609312bc5bSWei Yang } 9619312bc5bSWei Yang 9629312bc5bSWei Yang pr_warn("%s: Pending transaction while issuing %sFLR to %04x:%02x:%02x.%01x\n", 9639312bc5bSWei Yang __func__, type, 96469672bd7SAlexey Kardashevskiy pdn->phb->global_number, pdn->busno, 9659312bc5bSWei Yang PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn)); 9669312bc5bSWei Yang } 9679312bc5bSWei Yang 9689312bc5bSWei Yang static int pnv_eeh_do_flr(struct pci_dn *pdn, int option) 9699312bc5bSWei Yang { 9709312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 9719312bc5bSWei Yang u32 reg = 0; 9729312bc5bSWei Yang 9739312bc5bSWei Yang if (WARN_ON(!edev->pcie_cap)) 9749312bc5bSWei Yang return -ENOTTY; 9759312bc5bSWei Yang 9769312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP, 4, ®); 9779312bc5bSWei Yang if (!(reg & PCI_EXP_DEVCAP_FLR)) 9789312bc5bSWei Yang return -ENOTTY; 9799312bc5bSWei Yang 9809312bc5bSWei Yang switch (option) { 9819312bc5bSWei Yang case EEH_RESET_HOT: 9829312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 9839312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "", 9849312bc5bSWei Yang edev->pcie_cap + PCI_EXP_DEVSTA, 9859312bc5bSWei Yang PCI_EXP_DEVSTA_TRPND); 9869312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9879312bc5bSWei Yang 4, ®); 9889312bc5bSWei Yang reg |= PCI_EXP_DEVCTL_BCR_FLR; 9899312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9909312bc5bSWei Yang 4, reg); 9919312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 9929312bc5bSWei Yang break; 9939312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 9949312bc5bSWei Yang eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9959312bc5bSWei Yang 4, ®); 9969312bc5bSWei Yang reg &= ~PCI_EXP_DEVCTL_BCR_FLR; 9979312bc5bSWei Yang eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, 9989312bc5bSWei Yang 4, reg); 9999312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 10009312bc5bSWei Yang break; 10019312bc5bSWei Yang } 10029312bc5bSWei Yang 10039312bc5bSWei Yang return 0; 10049312bc5bSWei Yang } 10059312bc5bSWei Yang 10069312bc5bSWei Yang static int pnv_eeh_do_af_flr(struct pci_dn *pdn, int option) 10079312bc5bSWei Yang { 10089312bc5bSWei Yang struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 10099312bc5bSWei Yang u32 cap = 0; 10109312bc5bSWei Yang 10119312bc5bSWei Yang if (WARN_ON(!edev->af_cap)) 10129312bc5bSWei Yang return -ENOTTY; 10139312bc5bSWei Yang 10149312bc5bSWei Yang eeh_ops->read_config(pdn, edev->af_cap + PCI_AF_CAP, 1, &cap); 10159312bc5bSWei Yang if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR)) 10169312bc5bSWei Yang return -ENOTTY; 10179312bc5bSWei Yang 10189312bc5bSWei Yang switch (option) { 10199312bc5bSWei Yang case EEH_RESET_HOT: 10209312bc5bSWei Yang case EEH_RESET_FUNDAMENTAL: 10219312bc5bSWei Yang /* 10229312bc5bSWei Yang * Wait for Transaction Pending bit to clear. A word-aligned 10239312bc5bSWei Yang * test is used, so we use the conrol offset rather than status 10249312bc5bSWei Yang * and shift the test bit to match. 10259312bc5bSWei Yang */ 10269312bc5bSWei Yang pnv_eeh_wait_for_pending(pdn, "AF", 10279312bc5bSWei Yang edev->af_cap + PCI_AF_CTRL, 10289312bc5bSWei Yang PCI_AF_STATUS_TP << 8); 10299312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 10309312bc5bSWei Yang 1, PCI_AF_CTRL_FLR); 10319312bc5bSWei Yang msleep(EEH_PE_RST_HOLD_TIME); 10329312bc5bSWei Yang break; 10339312bc5bSWei Yang case EEH_RESET_DEACTIVATE: 10349312bc5bSWei Yang eeh_ops->write_config(pdn, edev->af_cap + PCI_AF_CTRL, 1, 0); 10359312bc5bSWei Yang msleep(EEH_PE_RST_SETTLE_TIME); 10369312bc5bSWei Yang break; 10379312bc5bSWei Yang } 10389312bc5bSWei Yang 10399312bc5bSWei Yang return 0; 10409312bc5bSWei Yang } 10419312bc5bSWei Yang 10429312bc5bSWei Yang static int pnv_eeh_reset_vf_pe(struct eeh_pe *pe, int option) 10439312bc5bSWei Yang { 10449312bc5bSWei Yang struct eeh_dev *edev; 10459312bc5bSWei Yang struct pci_dn *pdn; 10469312bc5bSWei Yang int ret; 10479312bc5bSWei Yang 10489312bc5bSWei Yang /* The VF PE should have only one child device */ 104980e65b00SSam Bobroff edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); 10509312bc5bSWei Yang pdn = eeh_dev_to_pdn(edev); 10519312bc5bSWei Yang if (!pdn) 10529312bc5bSWei Yang return -ENXIO; 10539312bc5bSWei Yang 10549312bc5bSWei Yang ret = pnv_eeh_do_flr(pdn, option); 10559312bc5bSWei Yang if (!ret) 10569312bc5bSWei Yang return ret; 10579312bc5bSWei Yang 10589312bc5bSWei Yang return pnv_eeh_do_af_flr(pdn, option); 10599312bc5bSWei Yang } 10609312bc5bSWei Yang 106129310e5eSGavin Shan /** 106201f3bfb7SGavin Shan * pnv_eeh_reset - Reset the specified PE 106329310e5eSGavin Shan * @pe: EEH PE 106429310e5eSGavin Shan * @option: reset option 106529310e5eSGavin Shan * 1066cadf364dSGavin Shan * Do reset on the indicated PE. For PCI bus sensitive PE, 1067cadf364dSGavin Shan * we need to reset the parent p2p bridge. The PHB has to 1068cadf364dSGavin Shan * be reinitialized if the p2p bridge is root bridge. For 1069cadf364dSGavin Shan * PCI device sensitive PE, we will try to reset the device 1070cadf364dSGavin Shan * through FLR. For now, we don't have OPAL APIs to do HARD 1071cadf364dSGavin Shan * reset yet, so all reset would be SOFT (HOT) reset. 107229310e5eSGavin Shan */ 107301f3bfb7SGavin Shan static int pnv_eeh_reset(struct eeh_pe *pe, int option) 107429310e5eSGavin Shan { 107529310e5eSGavin Shan struct pci_controller *hose = pe->phb; 10764fad4943SGavin Shan struct pnv_phb *phb; 1077cadf364dSGavin Shan struct pci_bus *bus; 10784fad4943SGavin Shan int64_t rc; 107929310e5eSGavin Shan 1080cadf364dSGavin Shan /* 1081cadf364dSGavin Shan * For PHB reset, we always have complete reset. For those PEs whose 1082cadf364dSGavin Shan * primary bus derived from root complex (root bus) or root port 1083cadf364dSGavin Shan * (usually bus#1), we apply hot or fundamental reset on the root port. 1084cadf364dSGavin Shan * For other PEs, we always have hot reset on the PE primary bus. 1085cadf364dSGavin Shan * 1086cadf364dSGavin Shan * Here, we have different design to pHyp, which always clear the 1087cadf364dSGavin Shan * frozen state during PE reset. However, the good idea here from 1088cadf364dSGavin Shan * benh is to keep frozen state before we get PE reset done completely 1089cadf364dSGavin Shan * (until BAR restore). With the frozen state, HW drops illegal IO 1090cadf364dSGavin Shan * or MMIO access, which can incur recrusive frozen PE during PE 1091cadf364dSGavin Shan * reset. The side effect is that EEH core has to clear the frozen 1092cadf364dSGavin Shan * state explicitly after BAR restore. 1093cadf364dSGavin Shan */ 10944fad4943SGavin Shan if (pe->type & EEH_PE_PHB) 10954fad4943SGavin Shan return pnv_eeh_phb_reset(hose, option); 1096cadf364dSGavin Shan 1097cadf364dSGavin Shan /* 1098cadf364dSGavin Shan * The frozen PE might be caused by PAPR error injection 1099cadf364dSGavin Shan * registers, which are expected to be cleared after hitting 1100cadf364dSGavin Shan * frozen PE as stated in the hardware spec. Unfortunately, 1101cadf364dSGavin Shan * that's not true on P7IOC. So we have to clear it manually 1102cadf364dSGavin Shan * to avoid recursive EEH errors during recovery. 1103cadf364dSGavin Shan */ 1104cadf364dSGavin Shan phb = hose->private_data; 1105cadf364dSGavin Shan if (phb->model == PNV_PHB_MODEL_P7IOC && 1106cadf364dSGavin Shan (option == EEH_RESET_HOT || 1107cadf364dSGavin Shan option == EEH_RESET_FUNDAMENTAL)) { 1108cadf364dSGavin Shan rc = opal_pci_reset(phb->opal_id, 1109cadf364dSGavin Shan OPAL_RESET_PHB_ERROR, 1110cadf364dSGavin Shan OPAL_ASSERT_RESET); 1111cadf364dSGavin Shan if (rc != OPAL_SUCCESS) { 11124fad4943SGavin Shan pr_warn("%s: Failure %lld clearing error injection registers\n", 1113cadf364dSGavin Shan __func__, rc); 1114cadf364dSGavin Shan return -EIO; 1115cadf364dSGavin Shan } 1116cadf364dSGavin Shan } 1117cadf364dSGavin Shan 1118e98ddb77SRussell Currey if (pe->type & EEH_PE_VF) 1119e98ddb77SRussell Currey return pnv_eeh_reset_vf_pe(pe, option); 1120e98ddb77SRussell Currey 1121cadf364dSGavin Shan bus = eeh_pe_bus_get(pe); 112204fec21cSRussell Currey if (!bus) { 11231f52f176SRussell Currey pr_err("%s: Cannot find PCI bus for PHB#%x-PE#%x\n", 112404fec21cSRussell Currey __func__, pe->phb->global_number, pe->addr); 112504fec21cSRussell Currey return -EIO; 112604fec21cSRussell Currey } 112729310e5eSGavin Shan 1128b7da1230SAndrew Donnellan /* 1129b7da1230SAndrew Donnellan * If dealing with the root bus (or the bus underneath the 1130b7da1230SAndrew Donnellan * root port), we reset the bus underneath the root port. 1131b7da1230SAndrew Donnellan * 1132b7da1230SAndrew Donnellan * The cxl driver depends on this behaviour for bi-modal card 1133b7da1230SAndrew Donnellan * switching. 1134b7da1230SAndrew Donnellan */ 11354fad4943SGavin Shan if (pci_is_root_bus(bus) || 11364fad4943SGavin Shan pci_is_root_bus(bus->parent)) 11374fad4943SGavin Shan return pnv_eeh_root_reset(hose, option); 11384fad4943SGavin Shan 11394fad4943SGavin Shan return pnv_eeh_bridge_reset(bus->self, option); 114029310e5eSGavin Shan } 114129310e5eSGavin Shan 114229310e5eSGavin Shan /** 114301f3bfb7SGavin Shan * pnv_eeh_get_log - Retrieve error log 114429310e5eSGavin Shan * @pe: EEH PE 114529310e5eSGavin Shan * @severity: temporary or permanent error log 114629310e5eSGavin Shan * @drv_log: driver log to be combined with retrieved error log 114729310e5eSGavin Shan * @len: length of driver log 114829310e5eSGavin Shan * 114929310e5eSGavin Shan * Retrieve the temporary or permanent error from the PE. 115029310e5eSGavin Shan */ 115101f3bfb7SGavin Shan static int pnv_eeh_get_log(struct eeh_pe *pe, int severity, 115229310e5eSGavin Shan char *drv_log, unsigned long len) 115329310e5eSGavin Shan { 115495edcdeaSGavin Shan if (!eeh_has_flag(EEH_EARLY_DUMP_LOG)) 115595edcdeaSGavin Shan pnv_pci_dump_phb_diag_data(pe->phb, pe->data); 115629310e5eSGavin Shan 115795edcdeaSGavin Shan return 0; 115829310e5eSGavin Shan } 115929310e5eSGavin Shan 116029310e5eSGavin Shan /** 116101f3bfb7SGavin Shan * pnv_eeh_configure_bridge - Configure PCI bridges in the indicated PE 116229310e5eSGavin Shan * @pe: EEH PE 116329310e5eSGavin Shan * 116429310e5eSGavin Shan * The function will be called to reconfigure the bridges included 116529310e5eSGavin Shan * in the specified PE so that the mulfunctional PE would be recovered 116629310e5eSGavin Shan * again. 116729310e5eSGavin Shan */ 116801f3bfb7SGavin Shan static int pnv_eeh_configure_bridge(struct eeh_pe *pe) 116929310e5eSGavin Shan { 1170bbe170edSGavin Shan return 0; 117129310e5eSGavin Shan } 117229310e5eSGavin Shan 117329310e5eSGavin Shan /** 117401f3bfb7SGavin Shan * pnv_pe_err_inject - Inject specified error to the indicated PE 1175131c123aSGavin Shan * @pe: the indicated PE 1176131c123aSGavin Shan * @type: error type 1177131c123aSGavin Shan * @func: specific error type 1178131c123aSGavin Shan * @addr: address 1179131c123aSGavin Shan * @mask: address mask 1180131c123aSGavin Shan * 1181131c123aSGavin Shan * The routine is called to inject specified error, which is 1182131c123aSGavin Shan * determined by @type and @func, to the indicated PE for 1183131c123aSGavin Shan * testing purpose. 1184131c123aSGavin Shan */ 118501f3bfb7SGavin Shan static int pnv_eeh_err_inject(struct eeh_pe *pe, int type, int func, 1186131c123aSGavin Shan unsigned long addr, unsigned long mask) 1187131c123aSGavin Shan { 1188131c123aSGavin Shan struct pci_controller *hose = pe->phb; 1189131c123aSGavin Shan struct pnv_phb *phb = hose->private_data; 1190fa646c3cSGavin Shan s64 rc; 1191131c123aSGavin Shan 1192fa646c3cSGavin Shan if (type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR && 1193fa646c3cSGavin Shan type != OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64) { 1194fa646c3cSGavin Shan pr_warn("%s: Invalid error type %d\n", 1195fa646c3cSGavin Shan __func__, type); 1196fa646c3cSGavin Shan return -ERANGE; 1197fa646c3cSGavin Shan } 1198131c123aSGavin Shan 1199fa646c3cSGavin Shan if (func < OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR || 1200fa646c3cSGavin Shan func > OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET) { 1201fa646c3cSGavin Shan pr_warn("%s: Invalid error function %d\n", 1202fa646c3cSGavin Shan __func__, func); 1203fa646c3cSGavin Shan return -ERANGE; 1204fa646c3cSGavin Shan } 1205fa646c3cSGavin Shan 1206fa646c3cSGavin Shan /* Firmware supports error injection ? */ 1207fa646c3cSGavin Shan if (!opal_check_token(OPAL_PCI_ERR_INJECT)) { 1208fa646c3cSGavin Shan pr_warn("%s: Firmware doesn't support error injection\n", 1209fa646c3cSGavin Shan __func__); 1210fa646c3cSGavin Shan return -ENXIO; 1211fa646c3cSGavin Shan } 1212fa646c3cSGavin Shan 1213fa646c3cSGavin Shan /* Do error injection */ 1214fa646c3cSGavin Shan rc = opal_pci_err_inject(phb->opal_id, pe->addr, 1215fa646c3cSGavin Shan type, func, addr, mask); 1216fa646c3cSGavin Shan if (rc != OPAL_SUCCESS) { 1217fa646c3cSGavin Shan pr_warn("%s: Failure %lld injecting error " 1218fa646c3cSGavin Shan "%d-%d to PHB#%x-PE#%x\n", 1219fa646c3cSGavin Shan __func__, rc, type, func, 1220fa646c3cSGavin Shan hose->global_number, pe->addr); 1221fa646c3cSGavin Shan return -EIO; 1222fa646c3cSGavin Shan } 1223fa646c3cSGavin Shan 1224fa646c3cSGavin Shan return 0; 1225131c123aSGavin Shan } 1226131c123aSGavin Shan 12270bd78587SGavin Shan static inline bool pnv_eeh_cfg_blocked(struct pci_dn *pdn) 1228d2cfbcd7SGavin Shan { 12290bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 1230d2cfbcd7SGavin Shan 1231d2cfbcd7SGavin Shan if (!edev || !edev->pe) 1232d2cfbcd7SGavin Shan return false; 1233d2cfbcd7SGavin Shan 12349312bc5bSWei Yang /* 12359312bc5bSWei Yang * We will issue FLR or AF FLR to all VFs, which are contained 12369312bc5bSWei Yang * in VF PE. It relies on the EEH PCI config accessors. So we 12379312bc5bSWei Yang * can't block them during the window. 12389312bc5bSWei Yang */ 12399312bc5bSWei Yang if (edev->physfn && (edev->pe->state & EEH_PE_RESET)) 12409312bc5bSWei Yang return false; 12419312bc5bSWei Yang 1242d2cfbcd7SGavin Shan if (edev->pe->state & EEH_PE_CFG_BLOCKED) 1243d2cfbcd7SGavin Shan return true; 1244d2cfbcd7SGavin Shan 1245d2cfbcd7SGavin Shan return false; 1246d2cfbcd7SGavin Shan } 1247d2cfbcd7SGavin Shan 12480bd78587SGavin Shan static int pnv_eeh_read_config(struct pci_dn *pdn, 1249d2cfbcd7SGavin Shan int where, int size, u32 *val) 1250d2cfbcd7SGavin Shan { 12513532a741SGavin Shan if (!pdn) 12523532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12533532a741SGavin Shan 12540bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) { 1255d2cfbcd7SGavin Shan *val = 0xFFFFFFFF; 1256d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1257d2cfbcd7SGavin Shan } 1258d2cfbcd7SGavin Shan 12593532a741SGavin Shan return pnv_pci_cfg_read(pdn, where, size, val); 1260d2cfbcd7SGavin Shan } 1261d2cfbcd7SGavin Shan 12620bd78587SGavin Shan static int pnv_eeh_write_config(struct pci_dn *pdn, 1263d2cfbcd7SGavin Shan int where, int size, u32 val) 1264d2cfbcd7SGavin Shan { 12653532a741SGavin Shan if (!pdn) 12663532a741SGavin Shan return PCIBIOS_DEVICE_NOT_FOUND; 12673532a741SGavin Shan 12680bd78587SGavin Shan if (pnv_eeh_cfg_blocked(pdn)) 1269d2cfbcd7SGavin Shan return PCIBIOS_SET_FAILED; 1270d2cfbcd7SGavin Shan 12713532a741SGavin Shan return pnv_pci_cfg_write(pdn, where, size, val); 1272d2cfbcd7SGavin Shan } 1273d2cfbcd7SGavin Shan 12742a485ad7SGavin Shan static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data) 12752a485ad7SGavin Shan { 12762a485ad7SGavin Shan /* GEM */ 12772a485ad7SGavin Shan if (data->gemXfir || data->gemRfir || 12782a485ad7SGavin Shan data->gemRirqfir || data->gemMask || data->gemRwof) 12792a485ad7SGavin Shan pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n", 12802a485ad7SGavin Shan be64_to_cpu(data->gemXfir), 12812a485ad7SGavin Shan be64_to_cpu(data->gemRfir), 12822a485ad7SGavin Shan be64_to_cpu(data->gemRirqfir), 12832a485ad7SGavin Shan be64_to_cpu(data->gemMask), 12842a485ad7SGavin Shan be64_to_cpu(data->gemRwof)); 12852a485ad7SGavin Shan 12862a485ad7SGavin Shan /* LEM */ 12872a485ad7SGavin Shan if (data->lemFir || data->lemErrMask || 12882a485ad7SGavin Shan data->lemAction0 || data->lemAction1 || data->lemWof) 12892a485ad7SGavin Shan pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n", 12902a485ad7SGavin Shan be64_to_cpu(data->lemFir), 12912a485ad7SGavin Shan be64_to_cpu(data->lemErrMask), 12922a485ad7SGavin Shan be64_to_cpu(data->lemAction0), 12932a485ad7SGavin Shan be64_to_cpu(data->lemAction1), 12942a485ad7SGavin Shan be64_to_cpu(data->lemWof)); 12952a485ad7SGavin Shan } 12962a485ad7SGavin Shan 12972a485ad7SGavin Shan static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose) 12982a485ad7SGavin Shan { 12992a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 13005cb1f8fdSRussell Currey struct OpalIoP7IOCErrorData *data = 13015cb1f8fdSRussell Currey (struct OpalIoP7IOCErrorData*)phb->diag_data; 13022a485ad7SGavin Shan long rc; 13032a485ad7SGavin Shan 13042a485ad7SGavin Shan rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data)); 13052a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 13062a485ad7SGavin Shan pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n", 13072a485ad7SGavin Shan __func__, phb->hub_id, rc); 13082a485ad7SGavin Shan return; 13092a485ad7SGavin Shan } 13102a485ad7SGavin Shan 1311a7032132SGavin Shan switch (be16_to_cpu(data->type)) { 13122a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_RGC: 13132a485ad7SGavin Shan pr_info("P7IOC diag-data for RGC\n\n"); 13142a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13152a485ad7SGavin Shan if (data->rgc.rgcStatus || data->rgc.rgcLdcp) 13162a485ad7SGavin Shan pr_info(" RGC: %016llx %016llx\n", 13172a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcStatus), 13182a485ad7SGavin Shan be64_to_cpu(data->rgc.rgcLdcp)); 13192a485ad7SGavin Shan break; 13202a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_BI: 13212a485ad7SGavin Shan pr_info("P7IOC diag-data for BI %s\n\n", 13222a485ad7SGavin Shan data->bi.biDownbound ? "Downbound" : "Upbound"); 13232a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13242a485ad7SGavin Shan if (data->bi.biLdcp0 || data->bi.biLdcp1 || 13252a485ad7SGavin Shan data->bi.biLdcp2 || data->bi.biFenceStatus) 13262a485ad7SGavin Shan pr_info(" BI: %016llx %016llx %016llx %016llx\n", 13272a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp0), 13282a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp1), 13292a485ad7SGavin Shan be64_to_cpu(data->bi.biLdcp2), 13302a485ad7SGavin Shan be64_to_cpu(data->bi.biFenceStatus)); 13312a485ad7SGavin Shan break; 13322a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_CI: 13332a485ad7SGavin Shan pr_info("P7IOC diag-data for CI Port %d\n\n", 13342a485ad7SGavin Shan data->ci.ciPort); 13352a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13362a485ad7SGavin Shan if (data->ci.ciPortStatus || data->ci.ciPortLdcp) 13372a485ad7SGavin Shan pr_info(" CI: %016llx %016llx\n", 13382a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortStatus), 13392a485ad7SGavin Shan be64_to_cpu(data->ci.ciPortLdcp)); 13402a485ad7SGavin Shan break; 13412a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_MISC: 13422a485ad7SGavin Shan pr_info("P7IOC diag-data for MISC\n\n"); 13432a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13442a485ad7SGavin Shan break; 13452a485ad7SGavin Shan case OPAL_P7IOC_DIAG_TYPE_I2C: 13462a485ad7SGavin Shan pr_info("P7IOC diag-data for I2C\n\n"); 13472a485ad7SGavin Shan pnv_eeh_dump_hub_diag_common(data); 13482a485ad7SGavin Shan break; 13492a485ad7SGavin Shan default: 13502a485ad7SGavin Shan pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n", 13512a485ad7SGavin Shan __func__, phb->hub_id, data->type); 13522a485ad7SGavin Shan } 13532a485ad7SGavin Shan } 13542a485ad7SGavin Shan 13552a485ad7SGavin Shan static int pnv_eeh_get_pe(struct pci_controller *hose, 13562a485ad7SGavin Shan u16 pe_no, struct eeh_pe **pe) 13572a485ad7SGavin Shan { 13582a485ad7SGavin Shan struct pnv_phb *phb = hose->private_data; 13592a485ad7SGavin Shan struct pnv_ioda_pe *pnv_pe; 13602a485ad7SGavin Shan struct eeh_pe *dev_pe; 13612a485ad7SGavin Shan 13622a485ad7SGavin Shan /* 13632a485ad7SGavin Shan * If PHB supports compound PE, to fetch 13642a485ad7SGavin Shan * the master PE because slave PE is invisible 13652a485ad7SGavin Shan * to EEH core. 13662a485ad7SGavin Shan */ 13672a485ad7SGavin Shan pnv_pe = &phb->ioda.pe_array[pe_no]; 13682a485ad7SGavin Shan if (pnv_pe->flags & PNV_IODA_PE_SLAVE) { 13692a485ad7SGavin Shan pnv_pe = pnv_pe->master; 13702a485ad7SGavin Shan WARN_ON(!pnv_pe || 13712a485ad7SGavin Shan !(pnv_pe->flags & PNV_IODA_PE_MASTER)); 13722a485ad7SGavin Shan pe_no = pnv_pe->pe_number; 13732a485ad7SGavin Shan } 13742a485ad7SGavin Shan 13752a485ad7SGavin Shan /* Find the PE according to PE# */ 13768bae6a23SAlexey Kardashevskiy dev_pe = eeh_pe_get(hose, pe_no, 0); 13772a485ad7SGavin Shan if (!dev_pe) 13782a485ad7SGavin Shan return -EEXIST; 13792a485ad7SGavin Shan 13802a485ad7SGavin Shan /* Freeze the (compound) PE */ 13812a485ad7SGavin Shan *pe = dev_pe; 13822a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 13832a485ad7SGavin Shan phb->freeze_pe(phb, pe_no); 13842a485ad7SGavin Shan 13852a485ad7SGavin Shan /* 13862a485ad7SGavin Shan * At this point, we're sure the (compound) PE should 13872a485ad7SGavin Shan * have been frozen. However, we still need poke until 13882a485ad7SGavin Shan * hitting the frozen PE on top level. 13892a485ad7SGavin Shan */ 13902a485ad7SGavin Shan dev_pe = dev_pe->parent; 13912a485ad7SGavin Shan while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) { 13922a485ad7SGavin Shan int ret; 13932a485ad7SGavin Shan ret = eeh_ops->get_state(dev_pe, NULL); 139434a286a4SSam Bobroff if (ret <= 0 || eeh_state_active(ret)) { 13952a485ad7SGavin Shan dev_pe = dev_pe->parent; 13962a485ad7SGavin Shan continue; 13972a485ad7SGavin Shan } 13982a485ad7SGavin Shan 13992a485ad7SGavin Shan /* Frozen parent PE */ 14002a485ad7SGavin Shan *pe = dev_pe; 14012a485ad7SGavin Shan if (!(dev_pe->state & EEH_PE_ISOLATED)) 14022a485ad7SGavin Shan phb->freeze_pe(phb, dev_pe->addr); 14032a485ad7SGavin Shan 14042a485ad7SGavin Shan /* Next one */ 14052a485ad7SGavin Shan dev_pe = dev_pe->parent; 14062a485ad7SGavin Shan } 14072a485ad7SGavin Shan 14082a485ad7SGavin Shan return 0; 14092a485ad7SGavin Shan } 14102a485ad7SGavin Shan 1411131c123aSGavin Shan /** 141201f3bfb7SGavin Shan * pnv_eeh_next_error - Retrieve next EEH error to handle 141329310e5eSGavin Shan * @pe: Affected PE 141429310e5eSGavin Shan * 14152a485ad7SGavin Shan * The function is expected to be called by EEH core while it gets 14162a485ad7SGavin Shan * special EEH event (without binding PE). The function calls to 14172a485ad7SGavin Shan * OPAL APIs for next error to handle. The informational error is 14182a485ad7SGavin Shan * handled internally by platform. However, the dead IOC, dead PHB, 14192a485ad7SGavin Shan * fenced PHB and frozen PE should be handled by EEH core eventually. 142029310e5eSGavin Shan */ 142101f3bfb7SGavin Shan static int pnv_eeh_next_error(struct eeh_pe **pe) 142229310e5eSGavin Shan { 142329310e5eSGavin Shan struct pci_controller *hose; 14242a485ad7SGavin Shan struct pnv_phb *phb; 14252a485ad7SGavin Shan struct eeh_pe *phb_pe, *parent_pe; 14262a485ad7SGavin Shan __be64 frozen_pe_no; 14272a485ad7SGavin Shan __be16 err_type, severity; 14282a485ad7SGavin Shan long rc; 14292a485ad7SGavin Shan int state, ret = EEH_NEXT_ERR_NONE; 14302a485ad7SGavin Shan 14312a485ad7SGavin Shan /* 143279231448SAlistair Popple * While running here, it's safe to purge the event queue. The 143379231448SAlistair Popple * event should still be masked. 14342a485ad7SGavin Shan */ 14352a485ad7SGavin Shan eeh_remove_event(NULL, false); 143629310e5eSGavin Shan 143729310e5eSGavin Shan list_for_each_entry(hose, &hose_list, list_node) { 14382a485ad7SGavin Shan /* 14392a485ad7SGavin Shan * If the subordinate PCI buses of the PHB has been 14402a485ad7SGavin Shan * removed or is exactly under error recovery, we 14412a485ad7SGavin Shan * needn't take care of it any more. 14422a485ad7SGavin Shan */ 144329310e5eSGavin Shan phb = hose->private_data; 14442a485ad7SGavin Shan phb_pe = eeh_phb_pe_get(hose); 14452a485ad7SGavin Shan if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED)) 14462a485ad7SGavin Shan continue; 14472a485ad7SGavin Shan 14482a485ad7SGavin Shan rc = opal_pci_next_error(phb->opal_id, 14492a485ad7SGavin Shan &frozen_pe_no, &err_type, &severity); 14502a485ad7SGavin Shan if (rc != OPAL_SUCCESS) { 14512a485ad7SGavin Shan pr_devel("%s: Invalid return value on " 14522a485ad7SGavin Shan "PHB#%x (0x%lx) from opal_pci_next_error", 14532a485ad7SGavin Shan __func__, hose->global_number, rc); 14542a485ad7SGavin Shan continue; 14552a485ad7SGavin Shan } 14562a485ad7SGavin Shan 14572a485ad7SGavin Shan /* If the PHB doesn't have error, stop processing */ 14582a485ad7SGavin Shan if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR || 14592a485ad7SGavin Shan be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) { 14602a485ad7SGavin Shan pr_devel("%s: No error found on PHB#%x\n", 14612a485ad7SGavin Shan __func__, hose->global_number); 14622a485ad7SGavin Shan continue; 14632a485ad7SGavin Shan } 14642a485ad7SGavin Shan 14652a485ad7SGavin Shan /* 14662a485ad7SGavin Shan * Processing the error. We're expecting the error with 14672a485ad7SGavin Shan * highest priority reported upon multiple errors on the 14682a485ad7SGavin Shan * specific PHB. 14692a485ad7SGavin Shan */ 14702a485ad7SGavin Shan pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n", 14712a485ad7SGavin Shan __func__, be16_to_cpu(err_type), 14722a485ad7SGavin Shan be16_to_cpu(severity), be64_to_cpu(frozen_pe_no), 14732a485ad7SGavin Shan hose->global_number); 14742a485ad7SGavin Shan switch (be16_to_cpu(err_type)) { 14752a485ad7SGavin Shan case OPAL_EEH_IOC_ERROR: 14762a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) { 14772a485ad7SGavin Shan pr_err("EEH: dead IOC detected\n"); 14782a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_IOC; 14792a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 14802a485ad7SGavin Shan pr_info("EEH: IOC informative error " 14812a485ad7SGavin Shan "detected\n"); 14822a485ad7SGavin Shan pnv_eeh_get_and_dump_hub_diag(hose); 14832a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 14842a485ad7SGavin Shan } 14852a485ad7SGavin Shan 14862a485ad7SGavin Shan break; 14872a485ad7SGavin Shan case OPAL_EEH_PHB_ERROR: 14882a485ad7SGavin Shan if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) { 14892a485ad7SGavin Shan *pe = phb_pe; 14902a485ad7SGavin Shan pr_err("EEH: dead PHB#%x detected, " 14912a485ad7SGavin Shan "location: %s\n", 14922a485ad7SGavin Shan hose->global_number, 14932a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 14942a485ad7SGavin Shan ret = EEH_NEXT_ERR_DEAD_PHB; 14952a485ad7SGavin Shan } else if (be16_to_cpu(severity) == 14962a485ad7SGavin Shan OPAL_EEH_SEV_PHB_FENCED) { 14972a485ad7SGavin Shan *pe = phb_pe; 14982a485ad7SGavin Shan pr_err("EEH: Fenced PHB#%x detected, " 14992a485ad7SGavin Shan "location: %s\n", 15002a485ad7SGavin Shan hose->global_number, 15012a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15022a485ad7SGavin Shan ret = EEH_NEXT_ERR_FENCED_PHB; 15032a485ad7SGavin Shan } else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) { 15042a485ad7SGavin Shan pr_info("EEH: PHB#%x informative error " 15052a485ad7SGavin Shan "detected, location: %s\n", 15062a485ad7SGavin Shan hose->global_number, 15072a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15082a485ad7SGavin Shan pnv_eeh_get_phb_diag(phb_pe); 15092a485ad7SGavin Shan pnv_pci_dump_phb_diag_data(hose, phb_pe->data); 15102a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15112a485ad7SGavin Shan } 15122a485ad7SGavin Shan 15132a485ad7SGavin Shan break; 15142a485ad7SGavin Shan case OPAL_EEH_PE_ERROR: 15152a485ad7SGavin Shan /* 15162a485ad7SGavin Shan * If we can't find the corresponding PE, we 15172a485ad7SGavin Shan * just try to unfreeze. 15182a485ad7SGavin Shan */ 15192a485ad7SGavin Shan if (pnv_eeh_get_pe(hose, 15202a485ad7SGavin Shan be64_to_cpu(frozen_pe_no), pe)) { 15212a485ad7SGavin Shan pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n", 15220f36db77SGavin Shan hose->global_number, be64_to_cpu(frozen_pe_no)); 15232a485ad7SGavin Shan pr_info("EEH: PHB location: %s\n", 15242a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 152579cd9520SGavin Shan 152679cd9520SGavin Shan /* Dump PHB diag-data */ 152779cd9520SGavin Shan rc = opal_pci_get_phb_diag_data2(phb->opal_id, 15285cb1f8fdSRussell Currey phb->diag_data, phb->diag_data_size); 152979cd9520SGavin Shan if (rc == OPAL_SUCCESS) 153079cd9520SGavin Shan pnv_pci_dump_phb_diag_data(hose, 15315cb1f8fdSRussell Currey phb->diag_data); 153279cd9520SGavin Shan 153379cd9520SGavin Shan /* Try best to clear it */ 15342a485ad7SGavin Shan opal_pci_eeh_freeze_clear(phb->opal_id, 1535d63e51b3SGavin Shan be64_to_cpu(frozen_pe_no), 15362a485ad7SGavin Shan OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); 15372a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15382a485ad7SGavin Shan } else if ((*pe)->state & EEH_PE_ISOLATED || 15392a485ad7SGavin Shan eeh_pe_passed(*pe)) { 15402a485ad7SGavin Shan ret = EEH_NEXT_ERR_NONE; 15412a485ad7SGavin Shan } else { 15422a485ad7SGavin Shan pr_err("EEH: Frozen PE#%x " 15432a485ad7SGavin Shan "on PHB#%x detected\n", 15442a485ad7SGavin Shan (*pe)->addr, 15452a485ad7SGavin Shan (*pe)->phb->global_number); 15462a485ad7SGavin Shan pr_err("EEH: PE location: %s, " 15472a485ad7SGavin Shan "PHB location: %s\n", 15482a485ad7SGavin Shan eeh_pe_loc_get(*pe), 15492a485ad7SGavin Shan eeh_pe_loc_get(phb_pe)); 15502a485ad7SGavin Shan ret = EEH_NEXT_ERR_FROZEN_PE; 15512a485ad7SGavin Shan } 15522a485ad7SGavin Shan 15532a485ad7SGavin Shan break; 15542a485ad7SGavin Shan default: 15552a485ad7SGavin Shan pr_warn("%s: Unexpected error type %d\n", 15562a485ad7SGavin Shan __func__, be16_to_cpu(err_type)); 15572a485ad7SGavin Shan } 15582a485ad7SGavin Shan 15592a485ad7SGavin Shan /* 15602a485ad7SGavin Shan * EEH core will try recover from fenced PHB or 15612a485ad7SGavin Shan * frozen PE. In the time for frozen PE, EEH core 15622a485ad7SGavin Shan * enable IO path for that before collecting logs, 15632a485ad7SGavin Shan * but it ruins the site. So we have to dump the 15642a485ad7SGavin Shan * log in advance here. 15652a485ad7SGavin Shan */ 15662a485ad7SGavin Shan if ((ret == EEH_NEXT_ERR_FROZEN_PE || 15672a485ad7SGavin Shan ret == EEH_NEXT_ERR_FENCED_PHB) && 15682a485ad7SGavin Shan !((*pe)->state & EEH_PE_ISOLATED)) { 1569e762bb89SSam Bobroff eeh_pe_mark_isolated(*pe); 15702a485ad7SGavin Shan pnv_eeh_get_phb_diag(*pe); 15712a485ad7SGavin Shan 15722a485ad7SGavin Shan if (eeh_has_flag(EEH_EARLY_DUMP_LOG)) 15732a485ad7SGavin Shan pnv_pci_dump_phb_diag_data((*pe)->phb, 15742a485ad7SGavin Shan (*pe)->data); 15752a485ad7SGavin Shan } 15762a485ad7SGavin Shan 15772a485ad7SGavin Shan /* 15782a485ad7SGavin Shan * We probably have the frozen parent PE out there and 15792a485ad7SGavin Shan * we need have to handle frozen parent PE firstly. 15802a485ad7SGavin Shan */ 15812a485ad7SGavin Shan if (ret == EEH_NEXT_ERR_FROZEN_PE) { 15822a485ad7SGavin Shan parent_pe = (*pe)->parent; 15832a485ad7SGavin Shan while (parent_pe) { 15842a485ad7SGavin Shan /* Hit the ceiling ? */ 15852a485ad7SGavin Shan if (parent_pe->type & EEH_PE_PHB) 15862a485ad7SGavin Shan break; 15872a485ad7SGavin Shan 15882a485ad7SGavin Shan /* Frozen parent PE ? */ 15892a485ad7SGavin Shan state = eeh_ops->get_state(parent_pe, NULL); 159034a286a4SSam Bobroff if (state > 0 && !eeh_state_active(state)) 15912a485ad7SGavin Shan *pe = parent_pe; 15922a485ad7SGavin Shan 15932a485ad7SGavin Shan /* Next parent level */ 15942a485ad7SGavin Shan parent_pe = parent_pe->parent; 15952a485ad7SGavin Shan } 15962a485ad7SGavin Shan 15972a485ad7SGavin Shan /* We possibly migrate to another PE */ 1598e762bb89SSam Bobroff eeh_pe_mark_isolated(*pe); 15992a485ad7SGavin Shan } 16002a485ad7SGavin Shan 16012a485ad7SGavin Shan /* 16022a485ad7SGavin Shan * If we have no errors on the specific PHB or only 16032a485ad7SGavin Shan * informative error there, we continue poking it. 16042a485ad7SGavin Shan * Otherwise, we need actions to be taken by upper 16052a485ad7SGavin Shan * layer. 16062a485ad7SGavin Shan */ 16072a485ad7SGavin Shan if (ret > EEH_NEXT_ERR_INF) 160829310e5eSGavin Shan break; 160929310e5eSGavin Shan } 161029310e5eSGavin Shan 161179231448SAlistair Popple /* Unmask the event */ 1612b8d65e96SAlistair Popple if (ret == EEH_NEXT_ERR_NONE && eeh_enabled()) 161379231448SAlistair Popple enable_irq(eeh_event_irq); 161479231448SAlistair Popple 16152a485ad7SGavin Shan return ret; 161629310e5eSGavin Shan } 161729310e5eSGavin Shan 16180bd78587SGavin Shan static int pnv_eeh_restore_config(struct pci_dn *pdn) 16199be3beccSGavin Shan { 16200bd78587SGavin Shan struct eeh_dev *edev = pdn_to_eeh_dev(pdn); 16219be3beccSGavin Shan struct pnv_phb *phb; 162264ba3dc7SBryant G. Ly s64 ret = 0; 1623405b33a7SAlexey Kardashevskiy int config_addr = (pdn->busno << 8) | (pdn->devfn); 16249be3beccSGavin Shan 16259be3beccSGavin Shan if (!edev) 16269be3beccSGavin Shan return -EEXIST; 16279be3beccSGavin Shan 16280dc2830eSWei Yang /* 16290dc2830eSWei Yang * We have to restore the PCI config space after reset since the 16300dc2830eSWei Yang * firmware can't see SRIOV VFs. 16310dc2830eSWei Yang * 16320dc2830eSWei Yang * FIXME: The MPS, error routing rules, timeout setting are worthy 16330dc2830eSWei Yang * to be exported by firmware in extendible way. 16340dc2830eSWei Yang */ 16350dc2830eSWei Yang if (edev->physfn) { 163664ba3dc7SBryant G. Ly ret = eeh_restore_vf_config(pdn); 16370dc2830eSWei Yang } else { 163869672bd7SAlexey Kardashevskiy phb = pdn->phb->private_data; 16399be3beccSGavin Shan ret = opal_pci_reinit(phb->opal_id, 1640405b33a7SAlexey Kardashevskiy OPAL_REINIT_PCI_DEV, config_addr); 16410dc2830eSWei Yang } 16420dc2830eSWei Yang 16439be3beccSGavin Shan if (ret) { 16449be3beccSGavin Shan pr_warn("%s: Can't reinit PCI dev 0x%x (%lld)\n", 1645405b33a7SAlexey Kardashevskiy __func__, config_addr, ret); 16469be3beccSGavin Shan return -EIO; 16479be3beccSGavin Shan } 16489be3beccSGavin Shan 164964ba3dc7SBryant G. Ly return ret; 16509be3beccSGavin Shan } 16519be3beccSGavin Shan 165201f3bfb7SGavin Shan static struct eeh_ops pnv_eeh_ops = { 165329310e5eSGavin Shan .name = "powernv", 165401f3bfb7SGavin Shan .init = pnv_eeh_init, 1655ff57b454SGavin Shan .probe = pnv_eeh_probe, 165601f3bfb7SGavin Shan .set_option = pnv_eeh_set_option, 165701f3bfb7SGavin Shan .get_pe_addr = pnv_eeh_get_pe_addr, 165801f3bfb7SGavin Shan .get_state = pnv_eeh_get_state, 165901f3bfb7SGavin Shan .reset = pnv_eeh_reset, 166001f3bfb7SGavin Shan .get_log = pnv_eeh_get_log, 166101f3bfb7SGavin Shan .configure_bridge = pnv_eeh_configure_bridge, 166201f3bfb7SGavin Shan .err_inject = pnv_eeh_err_inject, 166301f3bfb7SGavin Shan .read_config = pnv_eeh_read_config, 166401f3bfb7SGavin Shan .write_config = pnv_eeh_write_config, 166501f3bfb7SGavin Shan .next_error = pnv_eeh_next_error, 166667923cfcSBryant G. Ly .restore_config = pnv_eeh_restore_config, 166767923cfcSBryant G. Ly .notify_resume = NULL 166829310e5eSGavin Shan }; 166929310e5eSGavin Shan 16700dc2830eSWei Yang #ifdef CONFIG_PCI_IOV 16710dc2830eSWei Yang static void pnv_pci_fixup_vf_mps(struct pci_dev *pdev) 16720dc2830eSWei Yang { 16730dc2830eSWei Yang struct pci_dn *pdn = pci_get_pdn(pdev); 16740dc2830eSWei Yang int parent_mps; 16750dc2830eSWei Yang 16760dc2830eSWei Yang if (!pdev->is_virtfn) 16770dc2830eSWei Yang return; 16780dc2830eSWei Yang 16790dc2830eSWei Yang /* Synchronize MPS for VF and PF */ 16800dc2830eSWei Yang parent_mps = pcie_get_mps(pdev->physfn); 16810dc2830eSWei Yang if ((128 << pdev->pcie_mpss) >= parent_mps) 16820dc2830eSWei Yang pcie_set_mps(pdev, parent_mps); 16830dc2830eSWei Yang pdn->mps = pcie_get_mps(pdev); 16840dc2830eSWei Yang } 16850dc2830eSWei Yang DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pnv_pci_fixup_vf_mps); 16860dc2830eSWei Yang #endif /* CONFIG_PCI_IOV */ 16870dc2830eSWei Yang 168829310e5eSGavin Shan /** 168929310e5eSGavin Shan * eeh_powernv_init - Register platform dependent EEH operations 169029310e5eSGavin Shan * 169129310e5eSGavin Shan * EEH initialization on powernv platform. This function should be 169229310e5eSGavin Shan * called before any EEH related functions. 169329310e5eSGavin Shan */ 169429310e5eSGavin Shan static int __init eeh_powernv_init(void) 169529310e5eSGavin Shan { 169629310e5eSGavin Shan int ret = -EINVAL; 169729310e5eSGavin Shan 169801f3bfb7SGavin Shan ret = eeh_ops_register(&pnv_eeh_ops); 169929310e5eSGavin Shan if (!ret) 170029310e5eSGavin Shan pr_info("EEH: PowerNV platform initialized\n"); 170129310e5eSGavin Shan else 170229310e5eSGavin Shan pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret); 170329310e5eSGavin Shan 170429310e5eSGavin Shan return ret; 170529310e5eSGavin Shan } 1706b14726c5SMichael Ellerman machine_early_initcall(powernv, eeh_powernv_init); 1707