1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * SMP support for power macintosh. 4 * 5 * We support both the old "powersurge" SMP architecture 6 * and the current Core99 (G4 PowerMac) machines. 7 * 8 * Note that we don't support the very first rev. of 9 * Apple/DayStar 2 CPUs board, the one with the funky 10 * watchdog. Hopefully, none of these should be there except 11 * maybe internally to Apple. I should probably still add some 12 * code to detect this card though and disable SMP. --BenH. 13 * 14 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net) 15 * and Ben Herrenschmidt <benh@kernel.crashing.org>. 16 * 17 * Support for DayStar quad CPU cards 18 * Copyright (C) XLR8, Inc. 1994-2000 19 */ 20 #include <linux/kernel.h> 21 #include <linux/sched.h> 22 #include <linux/sched/hotplug.h> 23 #include <linux/smp.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel_stat.h> 26 #include <linux/delay.h> 27 #include <linux/init.h> 28 #include <linux/spinlock.h> 29 #include <linux/errno.h> 30 #include <linux/hardirq.h> 31 #include <linux/cpu.h> 32 #include <linux/compiler.h> 33 34 #include <asm/ptrace.h> 35 #include <linux/atomic.h> 36 #include <asm/code-patching.h> 37 #include <asm/irq.h> 38 #include <asm/page.h> 39 #include <asm/pgtable.h> 40 #include <asm/sections.h> 41 #include <asm/io.h> 42 #include <asm/prom.h> 43 #include <asm/smp.h> 44 #include <asm/machdep.h> 45 #include <asm/pmac_feature.h> 46 #include <asm/time.h> 47 #include <asm/mpic.h> 48 #include <asm/cacheflush.h> 49 #include <asm/keylargo.h> 50 #include <asm/pmac_low_i2c.h> 51 #include <asm/pmac_pfunc.h> 52 53 #include "pmac.h" 54 55 #undef DEBUG 56 57 #ifdef DEBUG 58 #define DBG(fmt...) udbg_printf(fmt) 59 #else 60 #define DBG(fmt...) 61 #endif 62 63 extern void __secondary_start_pmac_0(void); 64 65 static void (*pmac_tb_freeze)(int freeze); 66 static u64 timebase; 67 static int tb_req; 68 69 #ifdef CONFIG_PPC_PMAC32_PSURGE 70 71 /* 72 * Powersurge (old powermac SMP) support. 73 */ 74 75 /* Addresses for powersurge registers */ 76 #define HAMMERHEAD_BASE 0xf8000000 77 #define HHEAD_CONFIG 0x90 78 #define HHEAD_SEC_INTR 0xc0 79 80 /* register for interrupting the primary processor on the powersurge */ 81 /* N.B. this is actually the ethernet ROM! */ 82 #define PSURGE_PRI_INTR 0xf3019000 83 84 /* register for storing the start address for the secondary processor */ 85 /* N.B. this is the PCI config space address register for the 1st bridge */ 86 #define PSURGE_START 0xf2800000 87 88 /* Daystar/XLR8 4-CPU card */ 89 #define PSURGE_QUAD_REG_ADDR 0xf8800000 90 91 #define PSURGE_QUAD_IRQ_SET 0 92 #define PSURGE_QUAD_IRQ_CLR 1 93 #define PSURGE_QUAD_IRQ_PRIMARY 2 94 #define PSURGE_QUAD_CKSTOP_CTL 3 95 #define PSURGE_QUAD_PRIMARY_ARB 4 96 #define PSURGE_QUAD_BOARD_ID 6 97 #define PSURGE_QUAD_WHICH_CPU 7 98 #define PSURGE_QUAD_CKSTOP_RDBK 8 99 #define PSURGE_QUAD_RESET_CTL 11 100 101 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v))) 102 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f) 103 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v))) 104 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) 105 106 /* virtual addresses for the above */ 107 static volatile u8 __iomem *hhead_base; 108 static volatile u8 __iomem *quad_base; 109 static volatile u32 __iomem *psurge_pri_intr; 110 static volatile u8 __iomem *psurge_sec_intr; 111 static volatile u32 __iomem *psurge_start; 112 113 /* values for psurge_type */ 114 #define PSURGE_NONE -1 115 #define PSURGE_DUAL 0 116 #define PSURGE_QUAD_OKEE 1 117 #define PSURGE_QUAD_COTTON 2 118 #define PSURGE_QUAD_ICEGRASS 3 119 120 /* what sort of powersurge board we have */ 121 static int psurge_type = PSURGE_NONE; 122 123 /* irq for secondary cpus to report */ 124 static struct irq_domain *psurge_host; 125 int psurge_secondary_virq; 126 127 /* 128 * Set and clear IPIs for powersurge. 129 */ 130 static inline void psurge_set_ipi(int cpu) 131 { 132 if (psurge_type == PSURGE_NONE) 133 return; 134 if (cpu == 0) 135 in_be32(psurge_pri_intr); 136 else if (psurge_type == PSURGE_DUAL) 137 out_8(psurge_sec_intr, 0); 138 else 139 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu); 140 } 141 142 static inline void psurge_clr_ipi(int cpu) 143 { 144 if (cpu > 0) { 145 switch(psurge_type) { 146 case PSURGE_DUAL: 147 out_8(psurge_sec_intr, ~0); 148 case PSURGE_NONE: 149 break; 150 default: 151 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu); 152 } 153 } 154 } 155 156 /* 157 * On powersurge (old SMP powermac architecture) we don't have 158 * separate IPIs for separate messages like openpic does. Instead 159 * use the generic demux helpers 160 * -- paulus. 161 */ 162 static irqreturn_t psurge_ipi_intr(int irq, void *d) 163 { 164 psurge_clr_ipi(smp_processor_id()); 165 smp_ipi_demux(); 166 167 return IRQ_HANDLED; 168 } 169 170 static void smp_psurge_cause_ipi(int cpu) 171 { 172 psurge_set_ipi(cpu); 173 } 174 175 static int psurge_host_map(struct irq_domain *h, unsigned int virq, 176 irq_hw_number_t hw) 177 { 178 irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_percpu_irq); 179 180 return 0; 181 } 182 183 static const struct irq_domain_ops psurge_host_ops = { 184 .map = psurge_host_map, 185 }; 186 187 static int psurge_secondary_ipi_init(void) 188 { 189 int rc = -ENOMEM; 190 191 psurge_host = irq_domain_add_nomap(NULL, ~0, &psurge_host_ops, NULL); 192 193 if (psurge_host) 194 psurge_secondary_virq = irq_create_direct_mapping(psurge_host); 195 196 if (psurge_secondary_virq) 197 rc = request_irq(psurge_secondary_virq, psurge_ipi_intr, 198 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL); 199 200 if (rc) 201 pr_err("Failed to setup secondary cpu IPI\n"); 202 203 return rc; 204 } 205 206 /* 207 * Determine a quad card presence. We read the board ID register, we 208 * force the data bus to change to something else, and we read it again. 209 * It it's stable, then the register probably exist (ugh !) 210 */ 211 static int __init psurge_quad_probe(void) 212 { 213 int type; 214 unsigned int i; 215 216 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID); 217 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS 218 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 219 return PSURGE_DUAL; 220 221 /* looks OK, try a slightly more rigorous test */ 222 /* bogus is not necessarily cacheline-aligned, 223 though I don't suppose that really matters. -- paulus */ 224 for (i = 0; i < 100; i++) { 225 volatile u32 bogus[8]; 226 bogus[(0+i)%8] = 0x00000000; 227 bogus[(1+i)%8] = 0x55555555; 228 bogus[(2+i)%8] = 0xFFFFFFFF; 229 bogus[(3+i)%8] = 0xAAAAAAAA; 230 bogus[(4+i)%8] = 0x33333333; 231 bogus[(5+i)%8] = 0xCCCCCCCC; 232 bogus[(6+i)%8] = 0xCCCCCCCC; 233 bogus[(7+i)%8] = 0x33333333; 234 wmb(); 235 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); 236 mb(); 237 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 238 return PSURGE_DUAL; 239 } 240 return type; 241 } 242 243 static void __init psurge_quad_init(void) 244 { 245 int procbits; 246 247 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); 248 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU); 249 if (psurge_type == PSURGE_QUAD_ICEGRASS) 250 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 251 else 252 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits); 253 mdelay(33); 254 out_8(psurge_sec_intr, ~0); 255 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits); 256 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 257 if (psurge_type != PSURGE_QUAD_ICEGRASS) 258 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits); 259 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits); 260 mdelay(33); 261 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits); 262 mdelay(33); 263 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits); 264 mdelay(33); 265 } 266 267 static void __init smp_psurge_probe(void) 268 { 269 int i, ncpus; 270 struct device_node *dn; 271 272 /* We don't do SMP on the PPC601 -- paulus */ 273 if (PVR_VER(mfspr(SPRN_PVR)) == 1) 274 return; 275 276 /* 277 * The powersurge cpu board can be used in the generation 278 * of powermacs that have a socket for an upgradeable cpu card, 279 * including the 7500, 8500, 9500, 9600. 280 * The device tree doesn't tell you if you have 2 cpus because 281 * OF doesn't know anything about the 2nd processor. 282 * Instead we look for magic bits in magic registers, 283 * in the hammerhead memory controller in the case of the 284 * dual-cpu powersurge board. -- paulus. 285 */ 286 dn = of_find_node_by_name(NULL, "hammerhead"); 287 if (dn == NULL) 288 return; 289 of_node_put(dn); 290 291 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); 292 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024); 293 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR; 294 295 psurge_type = psurge_quad_probe(); 296 if (psurge_type != PSURGE_DUAL) { 297 psurge_quad_init(); 298 /* All released cards using this HW design have 4 CPUs */ 299 ncpus = 4; 300 /* No sure how timebase sync works on those, let's use SW */ 301 smp_ops->give_timebase = smp_generic_give_timebase; 302 smp_ops->take_timebase = smp_generic_take_timebase; 303 } else { 304 iounmap(quad_base); 305 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { 306 /* not a dual-cpu card */ 307 iounmap(hhead_base); 308 psurge_type = PSURGE_NONE; 309 return; 310 } 311 ncpus = 2; 312 } 313 314 if (psurge_secondary_ipi_init()) 315 return; 316 317 psurge_start = ioremap(PSURGE_START, 4); 318 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); 319 320 /* This is necessary because OF doesn't know about the 321 * secondary cpu(s), and thus there aren't nodes in the 322 * device tree for them, and smp_setup_cpu_maps hasn't 323 * set their bits in cpu_present_mask. 324 */ 325 if (ncpus > NR_CPUS) 326 ncpus = NR_CPUS; 327 for (i = 1; i < ncpus ; ++i) 328 set_cpu_present(i, true); 329 330 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); 331 } 332 333 static int __init smp_psurge_kick_cpu(int nr) 334 { 335 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; 336 unsigned long a, flags; 337 int i, j; 338 339 /* Defining this here is evil ... but I prefer hiding that 340 * crap to avoid giving people ideas that they can do the 341 * same. 342 */ 343 extern volatile unsigned int cpu_callin_map[NR_CPUS]; 344 345 /* may need to flush here if secondary bats aren't setup */ 346 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) 347 asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); 348 asm volatile("sync"); 349 350 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); 351 352 /* This is going to freeze the timeebase, we disable interrupts */ 353 local_irq_save(flags); 354 355 out_be32(psurge_start, start); 356 mb(); 357 358 psurge_set_ipi(nr); 359 360 /* 361 * We can't use udelay here because the timebase is now frozen. 362 */ 363 for (i = 0; i < 2000; ++i) 364 asm volatile("nop" : : : "memory"); 365 psurge_clr_ipi(nr); 366 367 /* 368 * Also, because the timebase is frozen, we must not return to the 369 * caller which will try to do udelay's etc... Instead, we wait -here- 370 * for the CPU to callin. 371 */ 372 for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) { 373 for (j = 1; j < 10000; j++) 374 asm volatile("nop" : : : "memory"); 375 asm volatile("sync" : : : "memory"); 376 } 377 if (!cpu_callin_map[nr]) 378 goto stuck; 379 380 /* And we do the TB sync here too for standard dual CPU cards */ 381 if (psurge_type == PSURGE_DUAL) { 382 while(!tb_req) 383 barrier(); 384 tb_req = 0; 385 mb(); 386 timebase = get_tb(); 387 mb(); 388 while (timebase) 389 barrier(); 390 mb(); 391 } 392 stuck: 393 /* now interrupt the secondary, restarting both TBs */ 394 if (psurge_type == PSURGE_DUAL) 395 psurge_set_ipi(1); 396 397 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); 398 399 return 0; 400 } 401 402 static struct irqaction psurge_irqaction = { 403 .handler = psurge_ipi_intr, 404 .flags = IRQF_PERCPU | IRQF_NO_THREAD, 405 .name = "primary IPI", 406 }; 407 408 static void __init smp_psurge_setup_cpu(int cpu_nr) 409 { 410 if (cpu_nr != 0 || !psurge_start) 411 return; 412 413 /* reset the entry point so if we get another intr we won't 414 * try to startup again */ 415 out_be32(psurge_start, 0x100); 416 if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction)) 417 printk(KERN_ERR "Couldn't get primary IPI interrupt"); 418 } 419 420 void __init smp_psurge_take_timebase(void) 421 { 422 if (psurge_type != PSURGE_DUAL) 423 return; 424 425 tb_req = 1; 426 mb(); 427 while (!timebase) 428 barrier(); 429 mb(); 430 set_tb(timebase >> 32, timebase & 0xffffffff); 431 timebase = 0; 432 mb(); 433 set_dec(tb_ticks_per_jiffy/2); 434 } 435 436 void __init smp_psurge_give_timebase(void) 437 { 438 /* Nothing to do here */ 439 } 440 441 /* PowerSurge-style Macs */ 442 struct smp_ops_t psurge_smp_ops = { 443 .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */ 444 .cause_ipi = smp_psurge_cause_ipi, 445 .cause_nmi_ipi = NULL, 446 .probe = smp_psurge_probe, 447 .kick_cpu = smp_psurge_kick_cpu, 448 .setup_cpu = smp_psurge_setup_cpu, 449 .give_timebase = smp_psurge_give_timebase, 450 .take_timebase = smp_psurge_take_timebase, 451 }; 452 #endif /* CONFIG_PPC_PMAC32_PSURGE */ 453 454 /* 455 * Core 99 and later support 456 */ 457 458 459 static void smp_core99_give_timebase(void) 460 { 461 unsigned long flags; 462 463 local_irq_save(flags); 464 465 while(!tb_req) 466 barrier(); 467 tb_req = 0; 468 (*pmac_tb_freeze)(1); 469 mb(); 470 timebase = get_tb(); 471 mb(); 472 while (timebase) 473 barrier(); 474 mb(); 475 (*pmac_tb_freeze)(0); 476 mb(); 477 478 local_irq_restore(flags); 479 } 480 481 482 static void smp_core99_take_timebase(void) 483 { 484 unsigned long flags; 485 486 local_irq_save(flags); 487 488 tb_req = 1; 489 mb(); 490 while (!timebase) 491 barrier(); 492 mb(); 493 set_tb(timebase >> 32, timebase & 0xffffffff); 494 timebase = 0; 495 mb(); 496 497 local_irq_restore(flags); 498 } 499 500 #ifdef CONFIG_PPC64 501 /* 502 * G5s enable/disable the timebase via an i2c-connected clock chip. 503 */ 504 static struct pmac_i2c_bus *pmac_tb_clock_chip_host; 505 static u8 pmac_tb_pulsar_addr; 506 507 static void smp_core99_cypress_tb_freeze(int freeze) 508 { 509 u8 data; 510 int rc; 511 512 /* Strangely, the device-tree says address is 0xd2, but darwin 513 * accesses 0xd0 ... 514 */ 515 pmac_i2c_setmode(pmac_tb_clock_chip_host, 516 pmac_i2c_mode_combined); 517 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 518 0xd0 | pmac_i2c_read, 519 1, 0x81, &data, 1); 520 if (rc != 0) 521 goto bail; 522 523 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c); 524 525 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 526 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 527 0xd0 | pmac_i2c_write, 528 1, 0x81, &data, 1); 529 530 bail: 531 if (rc != 0) { 532 printk("Cypress Timebase %s rc: %d\n", 533 freeze ? "freeze" : "unfreeze", rc); 534 panic("Timebase freeze failed !\n"); 535 } 536 } 537 538 539 static void smp_core99_pulsar_tb_freeze(int freeze) 540 { 541 u8 data; 542 int rc; 543 544 pmac_i2c_setmode(pmac_tb_clock_chip_host, 545 pmac_i2c_mode_combined); 546 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 547 pmac_tb_pulsar_addr | pmac_i2c_read, 548 1, 0x2e, &data, 1); 549 if (rc != 0) 550 goto bail; 551 552 data = (data & 0x88) | (freeze ? 0x11 : 0x22); 553 554 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 555 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 556 pmac_tb_pulsar_addr | pmac_i2c_write, 557 1, 0x2e, &data, 1); 558 bail: 559 if (rc != 0) { 560 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n", 561 freeze ? "freeze" : "unfreeze", rc); 562 panic("Timebase freeze failed !\n"); 563 } 564 } 565 566 static void __init smp_core99_setup_i2c_hwsync(int ncpus) 567 { 568 struct device_node *cc = NULL; 569 struct device_node *p; 570 const char *name = NULL; 571 const u32 *reg; 572 int ok; 573 574 /* Look for the clock chip */ 575 for_each_node_by_name(cc, "i2c-hwclock") { 576 p = of_get_parent(cc); 577 ok = p && of_device_is_compatible(p, "uni-n-i2c"); 578 of_node_put(p); 579 if (!ok) 580 continue; 581 582 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc); 583 if (pmac_tb_clock_chip_host == NULL) 584 continue; 585 reg = of_get_property(cc, "reg", NULL); 586 if (reg == NULL) 587 continue; 588 switch (*reg) { 589 case 0xd2: 590 if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) { 591 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 592 pmac_tb_pulsar_addr = 0xd2; 593 name = "Pulsar"; 594 } else if (of_device_is_compatible(cc, "cy28508")) { 595 pmac_tb_freeze = smp_core99_cypress_tb_freeze; 596 name = "Cypress"; 597 } 598 break; 599 case 0xd4: 600 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 601 pmac_tb_pulsar_addr = 0xd4; 602 name = "Pulsar"; 603 break; 604 } 605 if (pmac_tb_freeze != NULL) 606 break; 607 } 608 if (pmac_tb_freeze != NULL) { 609 /* Open i2c bus for synchronous access */ 610 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) { 611 printk(KERN_ERR "Failed top open i2c bus for clock" 612 " sync, fallback to software sync !\n"); 613 goto no_i2c_sync; 614 } 615 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n", 616 name); 617 return; 618 } 619 no_i2c_sync: 620 pmac_tb_freeze = NULL; 621 pmac_tb_clock_chip_host = NULL; 622 } 623 624 625 626 /* 627 * Newer G5s uses a platform function 628 */ 629 630 static void smp_core99_pfunc_tb_freeze(int freeze) 631 { 632 struct device_node *cpus; 633 struct pmf_args args; 634 635 cpus = of_find_node_by_path("/cpus"); 636 BUG_ON(cpus == NULL); 637 args.count = 1; 638 args.u[0].v = !freeze; 639 pmf_call_function(cpus, "cpu-timebase", &args); 640 of_node_put(cpus); 641 } 642 643 #else /* CONFIG_PPC64 */ 644 645 /* 646 * SMP G4 use a GPIO to enable/disable the timebase. 647 */ 648 649 static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */ 650 651 static void smp_core99_gpio_tb_freeze(int freeze) 652 { 653 if (freeze) 654 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4); 655 else 656 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); 657 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); 658 } 659 660 661 #endif /* !CONFIG_PPC64 */ 662 663 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ 664 volatile static long int core99_l2_cache; 665 volatile static long int core99_l3_cache; 666 667 static void core99_init_caches(int cpu) 668 { 669 #ifndef CONFIG_PPC64 670 if (!cpu_has_feature(CPU_FTR_L2CR)) 671 return; 672 673 if (cpu == 0) { 674 core99_l2_cache = _get_L2CR(); 675 printk("CPU0: L2CR is %lx\n", core99_l2_cache); 676 } else { 677 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); 678 _set_L2CR(0); 679 _set_L2CR(core99_l2_cache); 680 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); 681 } 682 683 if (!cpu_has_feature(CPU_FTR_L3CR)) 684 return; 685 686 if (cpu == 0){ 687 core99_l3_cache = _get_L3CR(); 688 printk("CPU0: L3CR is %lx\n", core99_l3_cache); 689 } else { 690 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR()); 691 _set_L3CR(0); 692 _set_L3CR(core99_l3_cache); 693 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache); 694 } 695 #endif /* !CONFIG_PPC64 */ 696 } 697 698 static void __init smp_core99_setup(int ncpus) 699 { 700 #ifdef CONFIG_PPC64 701 702 /* i2c based HW sync on some G5s */ 703 if (of_machine_is_compatible("PowerMac7,2") || 704 of_machine_is_compatible("PowerMac7,3") || 705 of_machine_is_compatible("RackMac3,1")) 706 smp_core99_setup_i2c_hwsync(ncpus); 707 708 /* pfunc based HW sync on recent G5s */ 709 if (pmac_tb_freeze == NULL) { 710 struct device_node *cpus = 711 of_find_node_by_path("/cpus"); 712 if (cpus && 713 of_get_property(cpus, "platform-cpu-timebase", NULL)) { 714 pmac_tb_freeze = smp_core99_pfunc_tb_freeze; 715 printk(KERN_INFO "Processor timebase sync using" 716 " platform function\n"); 717 } 718 } 719 720 #else /* CONFIG_PPC64 */ 721 722 /* GPIO based HW sync on ppc32 Core99 */ 723 if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) { 724 struct device_node *cpu; 725 const u32 *tbprop = NULL; 726 727 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */ 728 cpu = of_find_node_by_type(NULL, "cpu"); 729 if (cpu != NULL) { 730 tbprop = of_get_property(cpu, "timebase-enable", NULL); 731 if (tbprop) 732 core99_tb_gpio = *tbprop; 733 of_node_put(cpu); 734 } 735 pmac_tb_freeze = smp_core99_gpio_tb_freeze; 736 printk(KERN_INFO "Processor timebase sync using" 737 " GPIO 0x%02x\n", core99_tb_gpio); 738 } 739 740 #endif /* CONFIG_PPC64 */ 741 742 /* No timebase sync, fallback to software */ 743 if (pmac_tb_freeze == NULL) { 744 smp_ops->give_timebase = smp_generic_give_timebase; 745 smp_ops->take_timebase = smp_generic_take_timebase; 746 printk(KERN_INFO "Processor timebase sync using software\n"); 747 } 748 749 #ifndef CONFIG_PPC64 750 { 751 int i; 752 753 /* XXX should get this from reg properties */ 754 for (i = 1; i < ncpus; ++i) 755 set_hard_smp_processor_id(i, i); 756 } 757 #endif 758 759 /* 32 bits SMP can't NAP */ 760 if (!of_machine_is_compatible("MacRISC4")) 761 powersave_nap = 0; 762 } 763 764 static void __init smp_core99_probe(void) 765 { 766 struct device_node *cpus; 767 int ncpus = 0; 768 769 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); 770 771 /* Count CPUs in the device-tree */ 772 for_each_node_by_type(cpus, "cpu") 773 ++ncpus; 774 775 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus); 776 777 /* Nothing more to do if less than 2 of them */ 778 if (ncpus <= 1) 779 return; 780 781 /* We need to perform some early initialisations before we can start 782 * setting up SMP as we are running before initcalls 783 */ 784 pmac_pfunc_base_install(); 785 pmac_i2c_init(); 786 787 /* Setup various bits like timebase sync method, ability to nap, ... */ 788 smp_core99_setup(ncpus); 789 790 /* Install IPIs */ 791 mpic_request_ipis(); 792 793 /* Collect l2cr and l3cr values from CPU 0 */ 794 core99_init_caches(0); 795 } 796 797 static int smp_core99_kick_cpu(int nr) 798 { 799 unsigned int save_vector; 800 unsigned long target, flags; 801 unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100); 802 803 if (nr < 0 || nr > 3) 804 return -ENOENT; 805 806 if (ppc_md.progress) 807 ppc_md.progress("smp_core99_kick_cpu", 0x346); 808 809 local_irq_save(flags); 810 811 /* Save reset vector */ 812 save_vector = *vector; 813 814 /* Setup fake reset vector that does 815 * b __secondary_start_pmac_0 + nr*8 816 */ 817 target = (unsigned long) __secondary_start_pmac_0 + nr * 8; 818 patch_branch(vector, target, BRANCH_SET_LINK); 819 820 /* Put some life in our friend */ 821 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); 822 823 /* FIXME: We wait a bit for the CPU to take the exception, I should 824 * instead wait for the entry code to set something for me. Well, 825 * ideally, all that crap will be done in prom.c and the CPU left 826 * in a RAM-based wait loop like CHRP. 827 */ 828 mdelay(1); 829 830 /* Restore our exception vector */ 831 patch_instruction(vector, save_vector); 832 833 local_irq_restore(flags); 834 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); 835 836 return 0; 837 } 838 839 static void smp_core99_setup_cpu(int cpu_nr) 840 { 841 /* Setup L2/L3 */ 842 if (cpu_nr != 0) 843 core99_init_caches(cpu_nr); 844 845 /* Setup openpic */ 846 mpic_setup_this_cpu(); 847 } 848 849 #ifdef CONFIG_PPC64 850 #ifdef CONFIG_HOTPLUG_CPU 851 static unsigned int smp_core99_host_open; 852 853 static int smp_core99_cpu_prepare(unsigned int cpu) 854 { 855 int rc; 856 857 /* Open i2c bus if it was used for tb sync */ 858 if (pmac_tb_clock_chip_host && !smp_core99_host_open) { 859 rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1); 860 if (rc) { 861 pr_err("Failed to open i2c bus for time sync\n"); 862 return notifier_from_errno(rc); 863 } 864 smp_core99_host_open = 1; 865 } 866 return 0; 867 } 868 869 static int smp_core99_cpu_online(unsigned int cpu) 870 { 871 /* Close i2c bus if it was used for tb sync */ 872 if (pmac_tb_clock_chip_host && smp_core99_host_open) { 873 pmac_i2c_close(pmac_tb_clock_chip_host); 874 smp_core99_host_open = 0; 875 } 876 return 0; 877 } 878 #endif /* CONFIG_HOTPLUG_CPU */ 879 880 static void __init smp_core99_bringup_done(void) 881 { 882 extern void g5_phy_disable_cpu1(void); 883 884 /* Close i2c bus if it was used for tb sync */ 885 if (pmac_tb_clock_chip_host) 886 pmac_i2c_close(pmac_tb_clock_chip_host); 887 888 /* If we didn't start the second CPU, we must take 889 * it off the bus. 890 */ 891 if (of_machine_is_compatible("MacRISC4") && 892 num_online_cpus() < 2) { 893 set_cpu_present(1, false); 894 g5_phy_disable_cpu1(); 895 } 896 #ifdef CONFIG_HOTPLUG_CPU 897 cpuhp_setup_state_nocalls(CPUHP_POWERPC_PMAC_PREPARE, 898 "powerpc/pmac:prepare", smp_core99_cpu_prepare, 899 NULL); 900 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "powerpc/pmac:online", 901 smp_core99_cpu_online, NULL); 902 #endif 903 904 if (ppc_md.progress) 905 ppc_md.progress("smp_core99_bringup_done", 0x349); 906 } 907 #endif /* CONFIG_PPC64 */ 908 909 #ifdef CONFIG_HOTPLUG_CPU 910 911 static int smp_core99_cpu_disable(void) 912 { 913 int rc = generic_cpu_disable(); 914 if (rc) 915 return rc; 916 917 mpic_cpu_set_priority(0xf); 918 919 return 0; 920 } 921 922 #ifdef CONFIG_PPC32 923 924 static void pmac_cpu_die(void) 925 { 926 int cpu = smp_processor_id(); 927 928 local_irq_disable(); 929 idle_task_exit(); 930 pr_debug("CPU%d offline\n", cpu); 931 generic_set_cpu_dead(cpu); 932 smp_wmb(); 933 mb(); 934 low_cpu_die(); 935 } 936 937 #else /* CONFIG_PPC32 */ 938 939 static void pmac_cpu_die(void) 940 { 941 int cpu = smp_processor_id(); 942 943 local_irq_disable(); 944 idle_task_exit(); 945 946 /* 947 * turn off as much as possible, we'll be 948 * kicked out as this will only be invoked 949 * on core99 platforms for now ... 950 */ 951 952 printk(KERN_INFO "CPU#%d offline\n", cpu); 953 generic_set_cpu_dead(cpu); 954 smp_wmb(); 955 956 /* 957 * Re-enable interrupts. The NAP code needs to enable them 958 * anyways, do it now so we deal with the case where one already 959 * happened while soft-disabled. 960 * We shouldn't get any external interrupts, only decrementer, and the 961 * decrementer handler is safe for use on offline CPUs 962 */ 963 local_irq_enable(); 964 965 while (1) { 966 /* let's not take timer interrupts too often ... */ 967 set_dec(0x7fffffff); 968 969 /* Enter NAP mode */ 970 power4_idle(); 971 } 972 } 973 974 #endif /* else CONFIG_PPC32 */ 975 #endif /* CONFIG_HOTPLUG_CPU */ 976 977 /* Core99 Macs (dual G4s and G5s) */ 978 static struct smp_ops_t core99_smp_ops = { 979 .message_pass = smp_mpic_message_pass, 980 .probe = smp_core99_probe, 981 #ifdef CONFIG_PPC64 982 .bringup_done = smp_core99_bringup_done, 983 #endif 984 .kick_cpu = smp_core99_kick_cpu, 985 .setup_cpu = smp_core99_setup_cpu, 986 .give_timebase = smp_core99_give_timebase, 987 .take_timebase = smp_core99_take_timebase, 988 #if defined(CONFIG_HOTPLUG_CPU) 989 .cpu_disable = smp_core99_cpu_disable, 990 .cpu_die = generic_cpu_die, 991 #endif 992 }; 993 994 void __init pmac_setup_smp(void) 995 { 996 struct device_node *np; 997 998 /* Check for Core99 */ 999 np = of_find_node_by_name(NULL, "uni-n"); 1000 if (!np) 1001 np = of_find_node_by_name(NULL, "u3"); 1002 if (!np) 1003 np = of_find_node_by_name(NULL, "u4"); 1004 if (np) { 1005 of_node_put(np); 1006 smp_ops = &core99_smp_ops; 1007 } 1008 #ifdef CONFIG_PPC_PMAC32_PSURGE 1009 else { 1010 /* We have to set bits in cpu_possible_mask here since the 1011 * secondary CPU(s) aren't in the device tree. Various 1012 * things won't be initialized for CPUs not in the possible 1013 * map, so we really need to fix it up here. 1014 */ 1015 int cpu; 1016 1017 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) 1018 set_cpu_possible(cpu, true); 1019 smp_ops = &psurge_smp_ops; 1020 } 1021 #endif /* CONFIG_PPC_PMAC32_PSURGE */ 1022 1023 #ifdef CONFIG_HOTPLUG_CPU 1024 ppc_md.cpu_die = pmac_cpu_die; 1025 #endif 1026 } 1027 1028 1029