1 /* 2 * SMP support for power macintosh. 3 * 4 * We support both the old "powersurge" SMP architecture 5 * and the current Core99 (G4 PowerMac) machines. 6 * 7 * Note that we don't support the very first rev. of 8 * Apple/DayStar 2 CPUs board, the one with the funky 9 * watchdog. Hopefully, none of these should be there except 10 * maybe internally to Apple. I should probably still add some 11 * code to detect this card though and disable SMP. --BenH. 12 * 13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net) 14 * and Ben Herrenschmidt <benh@kernel.crashing.org>. 15 * 16 * Support for DayStar quad CPU cards 17 * Copyright (C) XLR8, Inc. 1994-2000 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24 #include <linux/kernel.h> 25 #include <linux/sched.h> 26 #include <linux/sched/hotplug.h> 27 #include <linux/smp.h> 28 #include <linux/interrupt.h> 29 #include <linux/kernel_stat.h> 30 #include <linux/delay.h> 31 #include <linux/init.h> 32 #include <linux/spinlock.h> 33 #include <linux/errno.h> 34 #include <linux/hardirq.h> 35 #include <linux/cpu.h> 36 #include <linux/compiler.h> 37 38 #include <asm/ptrace.h> 39 #include <linux/atomic.h> 40 #include <asm/code-patching.h> 41 #include <asm/irq.h> 42 #include <asm/page.h> 43 #include <asm/pgtable.h> 44 #include <asm/sections.h> 45 #include <asm/io.h> 46 #include <asm/prom.h> 47 #include <asm/smp.h> 48 #include <asm/machdep.h> 49 #include <asm/pmac_feature.h> 50 #include <asm/time.h> 51 #include <asm/mpic.h> 52 #include <asm/cacheflush.h> 53 #include <asm/keylargo.h> 54 #include <asm/pmac_low_i2c.h> 55 #include <asm/pmac_pfunc.h> 56 57 #include "pmac.h" 58 59 #undef DEBUG 60 61 #ifdef DEBUG 62 #define DBG(fmt...) udbg_printf(fmt) 63 #else 64 #define DBG(fmt...) 65 #endif 66 67 extern void __secondary_start_pmac_0(void); 68 69 static void (*pmac_tb_freeze)(int freeze); 70 static u64 timebase; 71 static int tb_req; 72 73 #ifdef CONFIG_PPC_PMAC32_PSURGE 74 75 /* 76 * Powersurge (old powermac SMP) support. 77 */ 78 79 /* Addresses for powersurge registers */ 80 #define HAMMERHEAD_BASE 0xf8000000 81 #define HHEAD_CONFIG 0x90 82 #define HHEAD_SEC_INTR 0xc0 83 84 /* register for interrupting the primary processor on the powersurge */ 85 /* N.B. this is actually the ethernet ROM! */ 86 #define PSURGE_PRI_INTR 0xf3019000 87 88 /* register for storing the start address for the secondary processor */ 89 /* N.B. this is the PCI config space address register for the 1st bridge */ 90 #define PSURGE_START 0xf2800000 91 92 /* Daystar/XLR8 4-CPU card */ 93 #define PSURGE_QUAD_REG_ADDR 0xf8800000 94 95 #define PSURGE_QUAD_IRQ_SET 0 96 #define PSURGE_QUAD_IRQ_CLR 1 97 #define PSURGE_QUAD_IRQ_PRIMARY 2 98 #define PSURGE_QUAD_CKSTOP_CTL 3 99 #define PSURGE_QUAD_PRIMARY_ARB 4 100 #define PSURGE_QUAD_BOARD_ID 6 101 #define PSURGE_QUAD_WHICH_CPU 7 102 #define PSURGE_QUAD_CKSTOP_RDBK 8 103 #define PSURGE_QUAD_RESET_CTL 11 104 105 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v))) 106 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f) 107 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v))) 108 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) 109 110 /* virtual addresses for the above */ 111 static volatile u8 __iomem *hhead_base; 112 static volatile u8 __iomem *quad_base; 113 static volatile u32 __iomem *psurge_pri_intr; 114 static volatile u8 __iomem *psurge_sec_intr; 115 static volatile u32 __iomem *psurge_start; 116 117 /* values for psurge_type */ 118 #define PSURGE_NONE -1 119 #define PSURGE_DUAL 0 120 #define PSURGE_QUAD_OKEE 1 121 #define PSURGE_QUAD_COTTON 2 122 #define PSURGE_QUAD_ICEGRASS 3 123 124 /* what sort of powersurge board we have */ 125 static int psurge_type = PSURGE_NONE; 126 127 /* irq for secondary cpus to report */ 128 static struct irq_domain *psurge_host; 129 int psurge_secondary_virq; 130 131 /* 132 * Set and clear IPIs for powersurge. 133 */ 134 static inline void psurge_set_ipi(int cpu) 135 { 136 if (psurge_type == PSURGE_NONE) 137 return; 138 if (cpu == 0) 139 in_be32(psurge_pri_intr); 140 else if (psurge_type == PSURGE_DUAL) 141 out_8(psurge_sec_intr, 0); 142 else 143 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu); 144 } 145 146 static inline void psurge_clr_ipi(int cpu) 147 { 148 if (cpu > 0) { 149 switch(psurge_type) { 150 case PSURGE_DUAL: 151 out_8(psurge_sec_intr, ~0); 152 case PSURGE_NONE: 153 break; 154 default: 155 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu); 156 } 157 } 158 } 159 160 /* 161 * On powersurge (old SMP powermac architecture) we don't have 162 * separate IPIs for separate messages like openpic does. Instead 163 * use the generic demux helpers 164 * -- paulus. 165 */ 166 static irqreturn_t psurge_ipi_intr(int irq, void *d) 167 { 168 psurge_clr_ipi(smp_processor_id()); 169 smp_ipi_demux(); 170 171 return IRQ_HANDLED; 172 } 173 174 static void smp_psurge_cause_ipi(int cpu) 175 { 176 psurge_set_ipi(cpu); 177 } 178 179 static int psurge_host_map(struct irq_domain *h, unsigned int virq, 180 irq_hw_number_t hw) 181 { 182 irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_percpu_irq); 183 184 return 0; 185 } 186 187 static const struct irq_domain_ops psurge_host_ops = { 188 .map = psurge_host_map, 189 }; 190 191 static int psurge_secondary_ipi_init(void) 192 { 193 int rc = -ENOMEM; 194 195 psurge_host = irq_domain_add_nomap(NULL, ~0, &psurge_host_ops, NULL); 196 197 if (psurge_host) 198 psurge_secondary_virq = irq_create_direct_mapping(psurge_host); 199 200 if (psurge_secondary_virq) 201 rc = request_irq(psurge_secondary_virq, psurge_ipi_intr, 202 IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL); 203 204 if (rc) 205 pr_err("Failed to setup secondary cpu IPI\n"); 206 207 return rc; 208 } 209 210 /* 211 * Determine a quad card presence. We read the board ID register, we 212 * force the data bus to change to something else, and we read it again. 213 * It it's stable, then the register probably exist (ugh !) 214 */ 215 static int __init psurge_quad_probe(void) 216 { 217 int type; 218 unsigned int i; 219 220 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID); 221 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS 222 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 223 return PSURGE_DUAL; 224 225 /* looks OK, try a slightly more rigorous test */ 226 /* bogus is not necessarily cacheline-aligned, 227 though I don't suppose that really matters. -- paulus */ 228 for (i = 0; i < 100; i++) { 229 volatile u32 bogus[8]; 230 bogus[(0+i)%8] = 0x00000000; 231 bogus[(1+i)%8] = 0x55555555; 232 bogus[(2+i)%8] = 0xFFFFFFFF; 233 bogus[(3+i)%8] = 0xAAAAAAAA; 234 bogus[(4+i)%8] = 0x33333333; 235 bogus[(5+i)%8] = 0xCCCCCCCC; 236 bogus[(6+i)%8] = 0xCCCCCCCC; 237 bogus[(7+i)%8] = 0x33333333; 238 wmb(); 239 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); 240 mb(); 241 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 242 return PSURGE_DUAL; 243 } 244 return type; 245 } 246 247 static void __init psurge_quad_init(void) 248 { 249 int procbits; 250 251 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); 252 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU); 253 if (psurge_type == PSURGE_QUAD_ICEGRASS) 254 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 255 else 256 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits); 257 mdelay(33); 258 out_8(psurge_sec_intr, ~0); 259 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits); 260 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 261 if (psurge_type != PSURGE_QUAD_ICEGRASS) 262 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits); 263 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits); 264 mdelay(33); 265 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits); 266 mdelay(33); 267 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits); 268 mdelay(33); 269 } 270 271 static void __init smp_psurge_probe(void) 272 { 273 int i, ncpus; 274 struct device_node *dn; 275 276 /* We don't do SMP on the PPC601 -- paulus */ 277 if (PVR_VER(mfspr(SPRN_PVR)) == 1) 278 return; 279 280 /* 281 * The powersurge cpu board can be used in the generation 282 * of powermacs that have a socket for an upgradeable cpu card, 283 * including the 7500, 8500, 9500, 9600. 284 * The device tree doesn't tell you if you have 2 cpus because 285 * OF doesn't know anything about the 2nd processor. 286 * Instead we look for magic bits in magic registers, 287 * in the hammerhead memory controller in the case of the 288 * dual-cpu powersurge board. -- paulus. 289 */ 290 dn = of_find_node_by_name(NULL, "hammerhead"); 291 if (dn == NULL) 292 return; 293 of_node_put(dn); 294 295 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); 296 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024); 297 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR; 298 299 psurge_type = psurge_quad_probe(); 300 if (psurge_type != PSURGE_DUAL) { 301 psurge_quad_init(); 302 /* All released cards using this HW design have 4 CPUs */ 303 ncpus = 4; 304 /* No sure how timebase sync works on those, let's use SW */ 305 smp_ops->give_timebase = smp_generic_give_timebase; 306 smp_ops->take_timebase = smp_generic_take_timebase; 307 } else { 308 iounmap(quad_base); 309 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { 310 /* not a dual-cpu card */ 311 iounmap(hhead_base); 312 psurge_type = PSURGE_NONE; 313 return; 314 } 315 ncpus = 2; 316 } 317 318 if (psurge_secondary_ipi_init()) 319 return; 320 321 psurge_start = ioremap(PSURGE_START, 4); 322 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); 323 324 /* This is necessary because OF doesn't know about the 325 * secondary cpu(s), and thus there aren't nodes in the 326 * device tree for them, and smp_setup_cpu_maps hasn't 327 * set their bits in cpu_present_mask. 328 */ 329 if (ncpus > NR_CPUS) 330 ncpus = NR_CPUS; 331 for (i = 1; i < ncpus ; ++i) 332 set_cpu_present(i, true); 333 334 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); 335 } 336 337 static int __init smp_psurge_kick_cpu(int nr) 338 { 339 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; 340 unsigned long a, flags; 341 int i, j; 342 343 /* Defining this here is evil ... but I prefer hiding that 344 * crap to avoid giving people ideas that they can do the 345 * same. 346 */ 347 extern volatile unsigned int cpu_callin_map[NR_CPUS]; 348 349 /* may need to flush here if secondary bats aren't setup */ 350 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) 351 asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); 352 asm volatile("sync"); 353 354 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); 355 356 /* This is going to freeze the timeebase, we disable interrupts */ 357 local_irq_save(flags); 358 359 out_be32(psurge_start, start); 360 mb(); 361 362 psurge_set_ipi(nr); 363 364 /* 365 * We can't use udelay here because the timebase is now frozen. 366 */ 367 for (i = 0; i < 2000; ++i) 368 asm volatile("nop" : : : "memory"); 369 psurge_clr_ipi(nr); 370 371 /* 372 * Also, because the timebase is frozen, we must not return to the 373 * caller which will try to do udelay's etc... Instead, we wait -here- 374 * for the CPU to callin. 375 */ 376 for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) { 377 for (j = 1; j < 10000; j++) 378 asm volatile("nop" : : : "memory"); 379 asm volatile("sync" : : : "memory"); 380 } 381 if (!cpu_callin_map[nr]) 382 goto stuck; 383 384 /* And we do the TB sync here too for standard dual CPU cards */ 385 if (psurge_type == PSURGE_DUAL) { 386 while(!tb_req) 387 barrier(); 388 tb_req = 0; 389 mb(); 390 timebase = get_tb(); 391 mb(); 392 while (timebase) 393 barrier(); 394 mb(); 395 } 396 stuck: 397 /* now interrupt the secondary, restarting both TBs */ 398 if (psurge_type == PSURGE_DUAL) 399 psurge_set_ipi(1); 400 401 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); 402 403 return 0; 404 } 405 406 static struct irqaction psurge_irqaction = { 407 .handler = psurge_ipi_intr, 408 .flags = IRQF_PERCPU | IRQF_NO_THREAD, 409 .name = "primary IPI", 410 }; 411 412 static void __init smp_psurge_setup_cpu(int cpu_nr) 413 { 414 if (cpu_nr != 0 || !psurge_start) 415 return; 416 417 /* reset the entry point so if we get another intr we won't 418 * try to startup again */ 419 out_be32(psurge_start, 0x100); 420 if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction)) 421 printk(KERN_ERR "Couldn't get primary IPI interrupt"); 422 } 423 424 void __init smp_psurge_take_timebase(void) 425 { 426 if (psurge_type != PSURGE_DUAL) 427 return; 428 429 tb_req = 1; 430 mb(); 431 while (!timebase) 432 barrier(); 433 mb(); 434 set_tb(timebase >> 32, timebase & 0xffffffff); 435 timebase = 0; 436 mb(); 437 set_dec(tb_ticks_per_jiffy/2); 438 } 439 440 void __init smp_psurge_give_timebase(void) 441 { 442 /* Nothing to do here */ 443 } 444 445 /* PowerSurge-style Macs */ 446 struct smp_ops_t psurge_smp_ops = { 447 .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */ 448 .cause_ipi = smp_psurge_cause_ipi, 449 .cause_nmi_ipi = NULL, 450 .probe = smp_psurge_probe, 451 .kick_cpu = smp_psurge_kick_cpu, 452 .setup_cpu = smp_psurge_setup_cpu, 453 .give_timebase = smp_psurge_give_timebase, 454 .take_timebase = smp_psurge_take_timebase, 455 }; 456 #endif /* CONFIG_PPC_PMAC32_PSURGE */ 457 458 /* 459 * Core 99 and later support 460 */ 461 462 463 static void smp_core99_give_timebase(void) 464 { 465 unsigned long flags; 466 467 local_irq_save(flags); 468 469 while(!tb_req) 470 barrier(); 471 tb_req = 0; 472 (*pmac_tb_freeze)(1); 473 mb(); 474 timebase = get_tb(); 475 mb(); 476 while (timebase) 477 barrier(); 478 mb(); 479 (*pmac_tb_freeze)(0); 480 mb(); 481 482 local_irq_restore(flags); 483 } 484 485 486 static void smp_core99_take_timebase(void) 487 { 488 unsigned long flags; 489 490 local_irq_save(flags); 491 492 tb_req = 1; 493 mb(); 494 while (!timebase) 495 barrier(); 496 mb(); 497 set_tb(timebase >> 32, timebase & 0xffffffff); 498 timebase = 0; 499 mb(); 500 501 local_irq_restore(flags); 502 } 503 504 #ifdef CONFIG_PPC64 505 /* 506 * G5s enable/disable the timebase via an i2c-connected clock chip. 507 */ 508 static struct pmac_i2c_bus *pmac_tb_clock_chip_host; 509 static u8 pmac_tb_pulsar_addr; 510 511 static void smp_core99_cypress_tb_freeze(int freeze) 512 { 513 u8 data; 514 int rc; 515 516 /* Strangely, the device-tree says address is 0xd2, but darwin 517 * accesses 0xd0 ... 518 */ 519 pmac_i2c_setmode(pmac_tb_clock_chip_host, 520 pmac_i2c_mode_combined); 521 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 522 0xd0 | pmac_i2c_read, 523 1, 0x81, &data, 1); 524 if (rc != 0) 525 goto bail; 526 527 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c); 528 529 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 530 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 531 0xd0 | pmac_i2c_write, 532 1, 0x81, &data, 1); 533 534 bail: 535 if (rc != 0) { 536 printk("Cypress Timebase %s rc: %d\n", 537 freeze ? "freeze" : "unfreeze", rc); 538 panic("Timebase freeze failed !\n"); 539 } 540 } 541 542 543 static void smp_core99_pulsar_tb_freeze(int freeze) 544 { 545 u8 data; 546 int rc; 547 548 pmac_i2c_setmode(pmac_tb_clock_chip_host, 549 pmac_i2c_mode_combined); 550 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 551 pmac_tb_pulsar_addr | pmac_i2c_read, 552 1, 0x2e, &data, 1); 553 if (rc != 0) 554 goto bail; 555 556 data = (data & 0x88) | (freeze ? 0x11 : 0x22); 557 558 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 559 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 560 pmac_tb_pulsar_addr | pmac_i2c_write, 561 1, 0x2e, &data, 1); 562 bail: 563 if (rc != 0) { 564 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n", 565 freeze ? "freeze" : "unfreeze", rc); 566 panic("Timebase freeze failed !\n"); 567 } 568 } 569 570 static void __init smp_core99_setup_i2c_hwsync(int ncpus) 571 { 572 struct device_node *cc = NULL; 573 struct device_node *p; 574 const char *name = NULL; 575 const u32 *reg; 576 int ok; 577 578 /* Look for the clock chip */ 579 for_each_node_by_name(cc, "i2c-hwclock") { 580 p = of_get_parent(cc); 581 ok = p && of_device_is_compatible(p, "uni-n-i2c"); 582 of_node_put(p); 583 if (!ok) 584 continue; 585 586 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc); 587 if (pmac_tb_clock_chip_host == NULL) 588 continue; 589 reg = of_get_property(cc, "reg", NULL); 590 if (reg == NULL) 591 continue; 592 switch (*reg) { 593 case 0xd2: 594 if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) { 595 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 596 pmac_tb_pulsar_addr = 0xd2; 597 name = "Pulsar"; 598 } else if (of_device_is_compatible(cc, "cy28508")) { 599 pmac_tb_freeze = smp_core99_cypress_tb_freeze; 600 name = "Cypress"; 601 } 602 break; 603 case 0xd4: 604 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 605 pmac_tb_pulsar_addr = 0xd4; 606 name = "Pulsar"; 607 break; 608 } 609 if (pmac_tb_freeze != NULL) 610 break; 611 } 612 if (pmac_tb_freeze != NULL) { 613 /* Open i2c bus for synchronous access */ 614 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) { 615 printk(KERN_ERR "Failed top open i2c bus for clock" 616 " sync, fallback to software sync !\n"); 617 goto no_i2c_sync; 618 } 619 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n", 620 name); 621 return; 622 } 623 no_i2c_sync: 624 pmac_tb_freeze = NULL; 625 pmac_tb_clock_chip_host = NULL; 626 } 627 628 629 630 /* 631 * Newer G5s uses a platform function 632 */ 633 634 static void smp_core99_pfunc_tb_freeze(int freeze) 635 { 636 struct device_node *cpus; 637 struct pmf_args args; 638 639 cpus = of_find_node_by_path("/cpus"); 640 BUG_ON(cpus == NULL); 641 args.count = 1; 642 args.u[0].v = !freeze; 643 pmf_call_function(cpus, "cpu-timebase", &args); 644 of_node_put(cpus); 645 } 646 647 #else /* CONFIG_PPC64 */ 648 649 /* 650 * SMP G4 use a GPIO to enable/disable the timebase. 651 */ 652 653 static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */ 654 655 static void smp_core99_gpio_tb_freeze(int freeze) 656 { 657 if (freeze) 658 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4); 659 else 660 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); 661 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); 662 } 663 664 665 #endif /* !CONFIG_PPC64 */ 666 667 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ 668 volatile static long int core99_l2_cache; 669 volatile static long int core99_l3_cache; 670 671 static void core99_init_caches(int cpu) 672 { 673 #ifndef CONFIG_PPC64 674 if (!cpu_has_feature(CPU_FTR_L2CR)) 675 return; 676 677 if (cpu == 0) { 678 core99_l2_cache = _get_L2CR(); 679 printk("CPU0: L2CR is %lx\n", core99_l2_cache); 680 } else { 681 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); 682 _set_L2CR(0); 683 _set_L2CR(core99_l2_cache); 684 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); 685 } 686 687 if (!cpu_has_feature(CPU_FTR_L3CR)) 688 return; 689 690 if (cpu == 0){ 691 core99_l3_cache = _get_L3CR(); 692 printk("CPU0: L3CR is %lx\n", core99_l3_cache); 693 } else { 694 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR()); 695 _set_L3CR(0); 696 _set_L3CR(core99_l3_cache); 697 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache); 698 } 699 #endif /* !CONFIG_PPC64 */ 700 } 701 702 static void __init smp_core99_setup(int ncpus) 703 { 704 #ifdef CONFIG_PPC64 705 706 /* i2c based HW sync on some G5s */ 707 if (of_machine_is_compatible("PowerMac7,2") || 708 of_machine_is_compatible("PowerMac7,3") || 709 of_machine_is_compatible("RackMac3,1")) 710 smp_core99_setup_i2c_hwsync(ncpus); 711 712 /* pfunc based HW sync on recent G5s */ 713 if (pmac_tb_freeze == NULL) { 714 struct device_node *cpus = 715 of_find_node_by_path("/cpus"); 716 if (cpus && 717 of_get_property(cpus, "platform-cpu-timebase", NULL)) { 718 pmac_tb_freeze = smp_core99_pfunc_tb_freeze; 719 printk(KERN_INFO "Processor timebase sync using" 720 " platform function\n"); 721 } 722 } 723 724 #else /* CONFIG_PPC64 */ 725 726 /* GPIO based HW sync on ppc32 Core99 */ 727 if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) { 728 struct device_node *cpu; 729 const u32 *tbprop = NULL; 730 731 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */ 732 cpu = of_find_node_by_type(NULL, "cpu"); 733 if (cpu != NULL) { 734 tbprop = of_get_property(cpu, "timebase-enable", NULL); 735 if (tbprop) 736 core99_tb_gpio = *tbprop; 737 of_node_put(cpu); 738 } 739 pmac_tb_freeze = smp_core99_gpio_tb_freeze; 740 printk(KERN_INFO "Processor timebase sync using" 741 " GPIO 0x%02x\n", core99_tb_gpio); 742 } 743 744 #endif /* CONFIG_PPC64 */ 745 746 /* No timebase sync, fallback to software */ 747 if (pmac_tb_freeze == NULL) { 748 smp_ops->give_timebase = smp_generic_give_timebase; 749 smp_ops->take_timebase = smp_generic_take_timebase; 750 printk(KERN_INFO "Processor timebase sync using software\n"); 751 } 752 753 #ifndef CONFIG_PPC64 754 { 755 int i; 756 757 /* XXX should get this from reg properties */ 758 for (i = 1; i < ncpus; ++i) 759 set_hard_smp_processor_id(i, i); 760 } 761 #endif 762 763 /* 32 bits SMP can't NAP */ 764 if (!of_machine_is_compatible("MacRISC4")) 765 powersave_nap = 0; 766 } 767 768 static void __init smp_core99_probe(void) 769 { 770 struct device_node *cpus; 771 int ncpus = 0; 772 773 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); 774 775 /* Count CPUs in the device-tree */ 776 for_each_node_by_type(cpus, "cpu") 777 ++ncpus; 778 779 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus); 780 781 /* Nothing more to do if less than 2 of them */ 782 if (ncpus <= 1) 783 return; 784 785 /* We need to perform some early initialisations before we can start 786 * setting up SMP as we are running before initcalls 787 */ 788 pmac_pfunc_base_install(); 789 pmac_i2c_init(); 790 791 /* Setup various bits like timebase sync method, ability to nap, ... */ 792 smp_core99_setup(ncpus); 793 794 /* Install IPIs */ 795 mpic_request_ipis(); 796 797 /* Collect l2cr and l3cr values from CPU 0 */ 798 core99_init_caches(0); 799 } 800 801 static int smp_core99_kick_cpu(int nr) 802 { 803 unsigned int save_vector; 804 unsigned long target, flags; 805 unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100); 806 807 if (nr < 0 || nr > 3) 808 return -ENOENT; 809 810 if (ppc_md.progress) 811 ppc_md.progress("smp_core99_kick_cpu", 0x346); 812 813 local_irq_save(flags); 814 815 /* Save reset vector */ 816 save_vector = *vector; 817 818 /* Setup fake reset vector that does 819 * b __secondary_start_pmac_0 + nr*8 820 */ 821 target = (unsigned long) __secondary_start_pmac_0 + nr * 8; 822 patch_branch(vector, target, BRANCH_SET_LINK); 823 824 /* Put some life in our friend */ 825 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); 826 827 /* FIXME: We wait a bit for the CPU to take the exception, I should 828 * instead wait for the entry code to set something for me. Well, 829 * ideally, all that crap will be done in prom.c and the CPU left 830 * in a RAM-based wait loop like CHRP. 831 */ 832 mdelay(1); 833 834 /* Restore our exception vector */ 835 *vector = save_vector; 836 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); 837 838 local_irq_restore(flags); 839 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); 840 841 return 0; 842 } 843 844 static void smp_core99_setup_cpu(int cpu_nr) 845 { 846 /* Setup L2/L3 */ 847 if (cpu_nr != 0) 848 core99_init_caches(cpu_nr); 849 850 /* Setup openpic */ 851 mpic_setup_this_cpu(); 852 } 853 854 #ifdef CONFIG_PPC64 855 #ifdef CONFIG_HOTPLUG_CPU 856 static unsigned int smp_core99_host_open; 857 858 static int smp_core99_cpu_prepare(unsigned int cpu) 859 { 860 int rc; 861 862 /* Open i2c bus if it was used for tb sync */ 863 if (pmac_tb_clock_chip_host && !smp_core99_host_open) { 864 rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1); 865 if (rc) { 866 pr_err("Failed to open i2c bus for time sync\n"); 867 return notifier_from_errno(rc); 868 } 869 smp_core99_host_open = 1; 870 } 871 return 0; 872 } 873 874 static int smp_core99_cpu_online(unsigned int cpu) 875 { 876 /* Close i2c bus if it was used for tb sync */ 877 if (pmac_tb_clock_chip_host && smp_core99_host_open) { 878 pmac_i2c_close(pmac_tb_clock_chip_host); 879 smp_core99_host_open = 0; 880 } 881 return 0; 882 } 883 #endif /* CONFIG_HOTPLUG_CPU */ 884 885 static void __init smp_core99_bringup_done(void) 886 { 887 extern void g5_phy_disable_cpu1(void); 888 889 /* Close i2c bus if it was used for tb sync */ 890 if (pmac_tb_clock_chip_host) 891 pmac_i2c_close(pmac_tb_clock_chip_host); 892 893 /* If we didn't start the second CPU, we must take 894 * it off the bus. 895 */ 896 if (of_machine_is_compatible("MacRISC4") && 897 num_online_cpus() < 2) { 898 set_cpu_present(1, false); 899 g5_phy_disable_cpu1(); 900 } 901 #ifdef CONFIG_HOTPLUG_CPU 902 cpuhp_setup_state_nocalls(CPUHP_POWERPC_PMAC_PREPARE, 903 "powerpc/pmac:prepare", smp_core99_cpu_prepare, 904 NULL); 905 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "powerpc/pmac:online", 906 smp_core99_cpu_online, NULL); 907 #endif 908 909 if (ppc_md.progress) 910 ppc_md.progress("smp_core99_bringup_done", 0x349); 911 } 912 #endif /* CONFIG_PPC64 */ 913 914 #ifdef CONFIG_HOTPLUG_CPU 915 916 static int smp_core99_cpu_disable(void) 917 { 918 int rc = generic_cpu_disable(); 919 if (rc) 920 return rc; 921 922 mpic_cpu_set_priority(0xf); 923 924 return 0; 925 } 926 927 #ifdef CONFIG_PPC32 928 929 static void pmac_cpu_die(void) 930 { 931 int cpu = smp_processor_id(); 932 933 local_irq_disable(); 934 idle_task_exit(); 935 pr_debug("CPU%d offline\n", cpu); 936 generic_set_cpu_dead(cpu); 937 smp_wmb(); 938 mb(); 939 low_cpu_die(); 940 } 941 942 #else /* CONFIG_PPC32 */ 943 944 static void pmac_cpu_die(void) 945 { 946 int cpu = smp_processor_id(); 947 948 local_irq_disable(); 949 idle_task_exit(); 950 951 /* 952 * turn off as much as possible, we'll be 953 * kicked out as this will only be invoked 954 * on core99 platforms for now ... 955 */ 956 957 printk(KERN_INFO "CPU#%d offline\n", cpu); 958 generic_set_cpu_dead(cpu); 959 smp_wmb(); 960 961 /* 962 * Re-enable interrupts. The NAP code needs to enable them 963 * anyways, do it now so we deal with the case where one already 964 * happened while soft-disabled. 965 * We shouldn't get any external interrupts, only decrementer, and the 966 * decrementer handler is safe for use on offline CPUs 967 */ 968 local_irq_enable(); 969 970 while (1) { 971 /* let's not take timer interrupts too often ... */ 972 set_dec(0x7fffffff); 973 974 /* Enter NAP mode */ 975 power4_idle(); 976 } 977 } 978 979 #endif /* else CONFIG_PPC32 */ 980 #endif /* CONFIG_HOTPLUG_CPU */ 981 982 /* Core99 Macs (dual G4s and G5s) */ 983 static struct smp_ops_t core99_smp_ops = { 984 .message_pass = smp_mpic_message_pass, 985 .probe = smp_core99_probe, 986 #ifdef CONFIG_PPC64 987 .bringup_done = smp_core99_bringup_done, 988 #endif 989 .kick_cpu = smp_core99_kick_cpu, 990 .setup_cpu = smp_core99_setup_cpu, 991 .give_timebase = smp_core99_give_timebase, 992 .take_timebase = smp_core99_take_timebase, 993 #if defined(CONFIG_HOTPLUG_CPU) 994 .cpu_disable = smp_core99_cpu_disable, 995 .cpu_die = generic_cpu_die, 996 #endif 997 }; 998 999 void __init pmac_setup_smp(void) 1000 { 1001 struct device_node *np; 1002 1003 /* Check for Core99 */ 1004 np = of_find_node_by_name(NULL, "uni-n"); 1005 if (!np) 1006 np = of_find_node_by_name(NULL, "u3"); 1007 if (!np) 1008 np = of_find_node_by_name(NULL, "u4"); 1009 if (np) { 1010 of_node_put(np); 1011 smp_ops = &core99_smp_ops; 1012 } 1013 #ifdef CONFIG_PPC_PMAC32_PSURGE 1014 else { 1015 /* We have to set bits in cpu_possible_mask here since the 1016 * secondary CPU(s) aren't in the device tree. Various 1017 * things won't be initialized for CPUs not in the possible 1018 * map, so we really need to fix it up here. 1019 */ 1020 int cpu; 1021 1022 for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu) 1023 set_cpu_possible(cpu, true); 1024 smp_ops = &psurge_smp_ops; 1025 } 1026 #endif /* CONFIG_PPC_PMAC32_PSURGE */ 1027 1028 #ifdef CONFIG_HOTPLUG_CPU 1029 ppc_md.cpu_die = pmac_cpu_die; 1030 #endif 1031 } 1032 1033 1034