1 /* 2 * SMP support for power macintosh. 3 * 4 * We support both the old "powersurge" SMP architecture 5 * and the current Core99 (G4 PowerMac) machines. 6 * 7 * Note that we don't support the very first rev. of 8 * Apple/DayStar 2 CPUs board, the one with the funky 9 * watchdog. Hopefully, none of these should be there except 10 * maybe internally to Apple. I should probably still add some 11 * code to detect this card though and disable SMP. --BenH. 12 * 13 * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net) 14 * and Ben Herrenschmidt <benh@kernel.crashing.org>. 15 * 16 * Support for DayStar quad CPU cards 17 * Copyright (C) XLR8, Inc. 1994-2000 18 * 19 * This program is free software; you can redistribute it and/or 20 * modify it under the terms of the GNU General Public License 21 * as published by the Free Software Foundation; either version 22 * 2 of the License, or (at your option) any later version. 23 */ 24 #include <linux/kernel.h> 25 #include <linux/sched.h> 26 #include <linux/smp.h> 27 #include <linux/interrupt.h> 28 #include <linux/kernel_stat.h> 29 #include <linux/delay.h> 30 #include <linux/init.h> 31 #include <linux/spinlock.h> 32 #include <linux/errno.h> 33 #include <linux/hardirq.h> 34 #include <linux/cpu.h> 35 #include <linux/compiler.h> 36 37 #include <asm/ptrace.h> 38 #include <asm/atomic.h> 39 #include <asm/irq.h> 40 #include <asm/page.h> 41 #include <asm/pgtable.h> 42 #include <asm/sections.h> 43 #include <asm/io.h> 44 #include <asm/prom.h> 45 #include <asm/smp.h> 46 #include <asm/machdep.h> 47 #include <asm/pmac_feature.h> 48 #include <asm/time.h> 49 #include <asm/mpic.h> 50 #include <asm/cacheflush.h> 51 #include <asm/keylargo.h> 52 #include <asm/pmac_low_i2c.h> 53 #include <asm/pmac_pfunc.h> 54 55 #define DEBUG 56 57 #ifdef DEBUG 58 #define DBG(fmt...) udbg_printf(fmt) 59 #else 60 #define DBG(fmt...) 61 #endif 62 63 extern void __secondary_start_pmac_0(void); 64 extern int pmac_pfunc_base_install(void); 65 66 #ifdef CONFIG_PPC32 67 68 /* Sync flag for HW tb sync */ 69 static volatile int sec_tb_reset = 0; 70 71 /* 72 * Powersurge (old powermac SMP) support. 73 */ 74 75 /* Addresses for powersurge registers */ 76 #define HAMMERHEAD_BASE 0xf8000000 77 #define HHEAD_CONFIG 0x90 78 #define HHEAD_SEC_INTR 0xc0 79 80 /* register for interrupting the primary processor on the powersurge */ 81 /* N.B. this is actually the ethernet ROM! */ 82 #define PSURGE_PRI_INTR 0xf3019000 83 84 /* register for storing the start address for the secondary processor */ 85 /* N.B. this is the PCI config space address register for the 1st bridge */ 86 #define PSURGE_START 0xf2800000 87 88 /* Daystar/XLR8 4-CPU card */ 89 #define PSURGE_QUAD_REG_ADDR 0xf8800000 90 91 #define PSURGE_QUAD_IRQ_SET 0 92 #define PSURGE_QUAD_IRQ_CLR 1 93 #define PSURGE_QUAD_IRQ_PRIMARY 2 94 #define PSURGE_QUAD_CKSTOP_CTL 3 95 #define PSURGE_QUAD_PRIMARY_ARB 4 96 #define PSURGE_QUAD_BOARD_ID 6 97 #define PSURGE_QUAD_WHICH_CPU 7 98 #define PSURGE_QUAD_CKSTOP_RDBK 8 99 #define PSURGE_QUAD_RESET_CTL 11 100 101 #define PSURGE_QUAD_OUT(r, v) (out_8(quad_base + ((r) << 4) + 4, (v))) 102 #define PSURGE_QUAD_IN(r) (in_8(quad_base + ((r) << 4) + 4) & 0x0f) 103 #define PSURGE_QUAD_BIS(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v))) 104 #define PSURGE_QUAD_BIC(r, v) (PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v))) 105 106 /* virtual addresses for the above */ 107 static volatile u8 __iomem *hhead_base; 108 static volatile u8 __iomem *quad_base; 109 static volatile u32 __iomem *psurge_pri_intr; 110 static volatile u8 __iomem *psurge_sec_intr; 111 static volatile u32 __iomem *psurge_start; 112 113 /* values for psurge_type */ 114 #define PSURGE_NONE -1 115 #define PSURGE_DUAL 0 116 #define PSURGE_QUAD_OKEE 1 117 #define PSURGE_QUAD_COTTON 2 118 #define PSURGE_QUAD_ICEGRASS 3 119 120 /* what sort of powersurge board we have */ 121 static int psurge_type = PSURGE_NONE; 122 123 /* 124 * Set and clear IPIs for powersurge. 125 */ 126 static inline void psurge_set_ipi(int cpu) 127 { 128 if (psurge_type == PSURGE_NONE) 129 return; 130 if (cpu == 0) 131 in_be32(psurge_pri_intr); 132 else if (psurge_type == PSURGE_DUAL) 133 out_8(psurge_sec_intr, 0); 134 else 135 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu); 136 } 137 138 static inline void psurge_clr_ipi(int cpu) 139 { 140 if (cpu > 0) { 141 switch(psurge_type) { 142 case PSURGE_DUAL: 143 out_8(psurge_sec_intr, ~0); 144 case PSURGE_NONE: 145 break; 146 default: 147 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu); 148 } 149 } 150 } 151 152 /* 153 * On powersurge (old SMP powermac architecture) we don't have 154 * separate IPIs for separate messages like openpic does. Instead 155 * we have a bitmap for each processor, where a 1 bit means that 156 * the corresponding message is pending for that processor. 157 * Ideally each cpu's entry would be in a different cache line. 158 * -- paulus. 159 */ 160 static unsigned long psurge_smp_message[NR_CPUS]; 161 162 void psurge_smp_message_recv(void) 163 { 164 int cpu = smp_processor_id(); 165 int msg; 166 167 /* clear interrupt */ 168 psurge_clr_ipi(cpu); 169 170 if (num_online_cpus() < 2) 171 return; 172 173 /* make sure there is a message there */ 174 for (msg = 0; msg < 4; msg++) 175 if (test_and_clear_bit(msg, &psurge_smp_message[cpu])) 176 smp_message_recv(msg); 177 } 178 179 irqreturn_t psurge_primary_intr(int irq, void *d) 180 { 181 psurge_smp_message_recv(); 182 return IRQ_HANDLED; 183 } 184 185 static void smp_psurge_message_pass(int target, int msg) 186 { 187 int i; 188 189 if (num_online_cpus() < 2) 190 return; 191 192 for_each_online_cpu(i) { 193 if (target == MSG_ALL 194 || (target == MSG_ALL_BUT_SELF && i != smp_processor_id()) 195 || target == i) { 196 set_bit(msg, &psurge_smp_message[i]); 197 psurge_set_ipi(i); 198 } 199 } 200 } 201 202 /* 203 * Determine a quad card presence. We read the board ID register, we 204 * force the data bus to change to something else, and we read it again. 205 * It it's stable, then the register probably exist (ugh !) 206 */ 207 static int __init psurge_quad_probe(void) 208 { 209 int type; 210 unsigned int i; 211 212 type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID); 213 if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS 214 || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 215 return PSURGE_DUAL; 216 217 /* looks OK, try a slightly more rigorous test */ 218 /* bogus is not necessarily cacheline-aligned, 219 though I don't suppose that really matters. -- paulus */ 220 for (i = 0; i < 100; i++) { 221 volatile u32 bogus[8]; 222 bogus[(0+i)%8] = 0x00000000; 223 bogus[(1+i)%8] = 0x55555555; 224 bogus[(2+i)%8] = 0xFFFFFFFF; 225 bogus[(3+i)%8] = 0xAAAAAAAA; 226 bogus[(4+i)%8] = 0x33333333; 227 bogus[(5+i)%8] = 0xCCCCCCCC; 228 bogus[(6+i)%8] = 0xCCCCCCCC; 229 bogus[(7+i)%8] = 0x33333333; 230 wmb(); 231 asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory"); 232 mb(); 233 if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID)) 234 return PSURGE_DUAL; 235 } 236 return type; 237 } 238 239 static void __init psurge_quad_init(void) 240 { 241 int procbits; 242 243 if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351); 244 procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU); 245 if (psurge_type == PSURGE_QUAD_ICEGRASS) 246 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 247 else 248 PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits); 249 mdelay(33); 250 out_8(psurge_sec_intr, ~0); 251 PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits); 252 PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits); 253 if (psurge_type != PSURGE_QUAD_ICEGRASS) 254 PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits); 255 PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits); 256 mdelay(33); 257 PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits); 258 mdelay(33); 259 PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits); 260 mdelay(33); 261 } 262 263 static int __init smp_psurge_probe(void) 264 { 265 int i, ncpus; 266 struct device_node *dn; 267 268 /* We don't do SMP on the PPC601 -- paulus */ 269 if (PVR_VER(mfspr(SPRN_PVR)) == 1) 270 return 1; 271 272 /* 273 * The powersurge cpu board can be used in the generation 274 * of powermacs that have a socket for an upgradeable cpu card, 275 * including the 7500, 8500, 9500, 9600. 276 * The device tree doesn't tell you if you have 2 cpus because 277 * OF doesn't know anything about the 2nd processor. 278 * Instead we look for magic bits in magic registers, 279 * in the hammerhead memory controller in the case of the 280 * dual-cpu powersurge board. -- paulus. 281 */ 282 dn = of_find_node_by_name(NULL, "hammerhead"); 283 if (dn == NULL) 284 return 1; 285 of_node_put(dn); 286 287 hhead_base = ioremap(HAMMERHEAD_BASE, 0x800); 288 quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024); 289 psurge_sec_intr = hhead_base + HHEAD_SEC_INTR; 290 291 psurge_type = psurge_quad_probe(); 292 if (psurge_type != PSURGE_DUAL) { 293 psurge_quad_init(); 294 /* All released cards using this HW design have 4 CPUs */ 295 ncpus = 4; 296 } else { 297 iounmap(quad_base); 298 if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) { 299 /* not a dual-cpu card */ 300 iounmap(hhead_base); 301 psurge_type = PSURGE_NONE; 302 return 1; 303 } 304 ncpus = 2; 305 } 306 307 psurge_start = ioremap(PSURGE_START, 4); 308 psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4); 309 310 /* 311 * This is necessary because OF doesn't know about the 312 * secondary cpu(s), and thus there aren't nodes in the 313 * device tree for them, and smp_setup_cpu_maps hasn't 314 * set their bits in cpu_possible_map and cpu_present_map. 315 */ 316 if (ncpus > NR_CPUS) 317 ncpus = NR_CPUS; 318 for (i = 1; i < ncpus ; ++i) { 319 cpu_set(i, cpu_present_map); 320 set_hard_smp_processor_id(i, i); 321 } 322 323 if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352); 324 325 return ncpus; 326 } 327 328 static void __init smp_psurge_kick_cpu(int nr) 329 { 330 unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8; 331 unsigned long a; 332 int i; 333 334 /* may need to flush here if secondary bats aren't setup */ 335 for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32) 336 asm volatile("dcbf 0,%0" : : "r" (a) : "memory"); 337 asm volatile("sync"); 338 339 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353); 340 341 out_be32(psurge_start, start); 342 mb(); 343 344 psurge_set_ipi(nr); 345 /* 346 * We can't use udelay here because the timebase is now frozen. 347 */ 348 for (i = 0; i < 2000; ++i) 349 barrier(); 350 psurge_clr_ipi(nr); 351 352 if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354); 353 } 354 355 /* 356 * With the dual-cpu powersurge board, the decrementers and timebases 357 * of both cpus are frozen after the secondary cpu is started up, 358 * until we give the secondary cpu another interrupt. This routine 359 * uses this to get the timebases synchronized. 360 * -- paulus. 361 */ 362 static void __init psurge_dual_sync_tb(int cpu_nr) 363 { 364 int t; 365 366 set_dec(tb_ticks_per_jiffy); 367 /* XXX fixme */ 368 set_tb(0, 0); 369 370 if (cpu_nr > 0) { 371 mb(); 372 sec_tb_reset = 1; 373 return; 374 } 375 376 /* wait for the secondary to have reset its TB before proceeding */ 377 for (t = 10000000; t > 0 && !sec_tb_reset; --t) 378 ; 379 380 /* now interrupt the secondary, starting both TBs */ 381 psurge_set_ipi(1); 382 } 383 384 static struct irqaction psurge_irqaction = { 385 .handler = psurge_primary_intr, 386 .flags = IRQF_DISABLED, 387 .mask = CPU_MASK_NONE, 388 .name = "primary IPI", 389 }; 390 391 static void __init smp_psurge_setup_cpu(int cpu_nr) 392 { 393 394 if (cpu_nr == 0) { 395 /* If we failed to start the second CPU, we should still 396 * send it an IPI to start the timebase & DEC or we might 397 * have them stuck. 398 */ 399 if (num_online_cpus() < 2) { 400 if (psurge_type == PSURGE_DUAL) 401 psurge_set_ipi(1); 402 return; 403 } 404 /* reset the entry point so if we get another intr we won't 405 * try to startup again */ 406 out_be32(psurge_start, 0x100); 407 if (setup_irq(30, &psurge_irqaction)) 408 printk(KERN_ERR "Couldn't get primary IPI interrupt"); 409 } 410 411 if (psurge_type == PSURGE_DUAL) 412 psurge_dual_sync_tb(cpu_nr); 413 } 414 415 void __init smp_psurge_take_timebase(void) 416 { 417 /* Dummy implementation */ 418 } 419 420 void __init smp_psurge_give_timebase(void) 421 { 422 /* Dummy implementation */ 423 } 424 425 /* PowerSurge-style Macs */ 426 struct smp_ops_t psurge_smp_ops = { 427 .message_pass = smp_psurge_message_pass, 428 .probe = smp_psurge_probe, 429 .kick_cpu = smp_psurge_kick_cpu, 430 .setup_cpu = smp_psurge_setup_cpu, 431 .give_timebase = smp_psurge_give_timebase, 432 .take_timebase = smp_psurge_take_timebase, 433 }; 434 #endif /* CONFIG_PPC32 - actually powersurge support */ 435 436 /* 437 * Core 99 and later support 438 */ 439 440 static void (*pmac_tb_freeze)(int freeze); 441 static u64 timebase; 442 static int tb_req; 443 444 static void smp_core99_give_timebase(void) 445 { 446 unsigned long flags; 447 448 local_irq_save(flags); 449 450 while(!tb_req) 451 barrier(); 452 tb_req = 0; 453 (*pmac_tb_freeze)(1); 454 mb(); 455 timebase = get_tb(); 456 mb(); 457 while (timebase) 458 barrier(); 459 mb(); 460 (*pmac_tb_freeze)(0); 461 mb(); 462 463 local_irq_restore(flags); 464 } 465 466 467 static void __devinit smp_core99_take_timebase(void) 468 { 469 unsigned long flags; 470 471 local_irq_save(flags); 472 473 tb_req = 1; 474 mb(); 475 while (!timebase) 476 barrier(); 477 mb(); 478 set_tb(timebase >> 32, timebase & 0xffffffff); 479 timebase = 0; 480 mb(); 481 set_dec(tb_ticks_per_jiffy/2); 482 483 local_irq_restore(flags); 484 } 485 486 #ifdef CONFIG_PPC64 487 /* 488 * G5s enable/disable the timebase via an i2c-connected clock chip. 489 */ 490 static struct pmac_i2c_bus *pmac_tb_clock_chip_host; 491 static u8 pmac_tb_pulsar_addr; 492 493 static void smp_core99_cypress_tb_freeze(int freeze) 494 { 495 u8 data; 496 int rc; 497 498 /* Strangely, the device-tree says address is 0xd2, but darwin 499 * accesses 0xd0 ... 500 */ 501 pmac_i2c_setmode(pmac_tb_clock_chip_host, 502 pmac_i2c_mode_combined); 503 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 504 0xd0 | pmac_i2c_read, 505 1, 0x81, &data, 1); 506 if (rc != 0) 507 goto bail; 508 509 data = (data & 0xf3) | (freeze ? 0x00 : 0x0c); 510 511 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 512 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 513 0xd0 | pmac_i2c_write, 514 1, 0x81, &data, 1); 515 516 bail: 517 if (rc != 0) { 518 printk("Cypress Timebase %s rc: %d\n", 519 freeze ? "freeze" : "unfreeze", rc); 520 panic("Timebase freeze failed !\n"); 521 } 522 } 523 524 525 static void smp_core99_pulsar_tb_freeze(int freeze) 526 { 527 u8 data; 528 int rc; 529 530 pmac_i2c_setmode(pmac_tb_clock_chip_host, 531 pmac_i2c_mode_combined); 532 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 533 pmac_tb_pulsar_addr | pmac_i2c_read, 534 1, 0x2e, &data, 1); 535 if (rc != 0) 536 goto bail; 537 538 data = (data & 0x88) | (freeze ? 0x11 : 0x22); 539 540 pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub); 541 rc = pmac_i2c_xfer(pmac_tb_clock_chip_host, 542 pmac_tb_pulsar_addr | pmac_i2c_write, 543 1, 0x2e, &data, 1); 544 bail: 545 if (rc != 0) { 546 printk(KERN_ERR "Pulsar Timebase %s rc: %d\n", 547 freeze ? "freeze" : "unfreeze", rc); 548 panic("Timebase freeze failed !\n"); 549 } 550 } 551 552 static void __init smp_core99_setup_i2c_hwsync(int ncpus) 553 { 554 struct device_node *cc = NULL; 555 struct device_node *p; 556 const char *name = NULL; 557 const u32 *reg; 558 int ok; 559 560 /* Look for the clock chip */ 561 while ((cc = of_find_node_by_name(cc, "i2c-hwclock")) != NULL) { 562 p = of_get_parent(cc); 563 ok = p && of_device_is_compatible(p, "uni-n-i2c"); 564 of_node_put(p); 565 if (!ok) 566 continue; 567 568 pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc); 569 if (pmac_tb_clock_chip_host == NULL) 570 continue; 571 reg = of_get_property(cc, "reg", NULL); 572 if (reg == NULL) 573 continue; 574 switch (*reg) { 575 case 0xd2: 576 if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) { 577 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 578 pmac_tb_pulsar_addr = 0xd2; 579 name = "Pulsar"; 580 } else if (of_device_is_compatible(cc, "cy28508")) { 581 pmac_tb_freeze = smp_core99_cypress_tb_freeze; 582 name = "Cypress"; 583 } 584 break; 585 case 0xd4: 586 pmac_tb_freeze = smp_core99_pulsar_tb_freeze; 587 pmac_tb_pulsar_addr = 0xd4; 588 name = "Pulsar"; 589 break; 590 } 591 if (pmac_tb_freeze != NULL) 592 break; 593 } 594 if (pmac_tb_freeze != NULL) { 595 /* Open i2c bus for synchronous access */ 596 if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) { 597 printk(KERN_ERR "Failed top open i2c bus for clock" 598 " sync, fallback to software sync !\n"); 599 goto no_i2c_sync; 600 } 601 printk(KERN_INFO "Processor timebase sync using %s i2c clock\n", 602 name); 603 return; 604 } 605 no_i2c_sync: 606 pmac_tb_freeze = NULL; 607 pmac_tb_clock_chip_host = NULL; 608 } 609 610 611 612 /* 613 * Newer G5s uses a platform function 614 */ 615 616 static void smp_core99_pfunc_tb_freeze(int freeze) 617 { 618 struct device_node *cpus; 619 struct pmf_args args; 620 621 cpus = of_find_node_by_path("/cpus"); 622 BUG_ON(cpus == NULL); 623 args.count = 1; 624 args.u[0].v = !freeze; 625 pmf_call_function(cpus, "cpu-timebase", &args); 626 of_node_put(cpus); 627 } 628 629 #else /* CONFIG_PPC64 */ 630 631 /* 632 * SMP G4 use a GPIO to enable/disable the timebase. 633 */ 634 635 static unsigned int core99_tb_gpio; /* Timebase freeze GPIO */ 636 637 static void smp_core99_gpio_tb_freeze(int freeze) 638 { 639 if (freeze) 640 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4); 641 else 642 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0); 643 pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0); 644 } 645 646 647 #endif /* !CONFIG_PPC64 */ 648 649 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */ 650 volatile static long int core99_l2_cache; 651 volatile static long int core99_l3_cache; 652 653 static void __devinit core99_init_caches(int cpu) 654 { 655 #ifndef CONFIG_PPC64 656 if (!cpu_has_feature(CPU_FTR_L2CR)) 657 return; 658 659 if (cpu == 0) { 660 core99_l2_cache = _get_L2CR(); 661 printk("CPU0: L2CR is %lx\n", core99_l2_cache); 662 } else { 663 printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR()); 664 _set_L2CR(0); 665 _set_L2CR(core99_l2_cache); 666 printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache); 667 } 668 669 if (!cpu_has_feature(CPU_FTR_L3CR)) 670 return; 671 672 if (cpu == 0){ 673 core99_l3_cache = _get_L3CR(); 674 printk("CPU0: L3CR is %lx\n", core99_l3_cache); 675 } else { 676 printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR()); 677 _set_L3CR(0); 678 _set_L3CR(core99_l3_cache); 679 printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache); 680 } 681 #endif /* !CONFIG_PPC64 */ 682 } 683 684 static void __init smp_core99_setup(int ncpus) 685 { 686 #ifdef CONFIG_PPC64 687 688 /* i2c based HW sync on some G5s */ 689 if (machine_is_compatible("PowerMac7,2") || 690 machine_is_compatible("PowerMac7,3") || 691 machine_is_compatible("RackMac3,1")) 692 smp_core99_setup_i2c_hwsync(ncpus); 693 694 /* pfunc based HW sync on recent G5s */ 695 if (pmac_tb_freeze == NULL) { 696 struct device_node *cpus = 697 of_find_node_by_path("/cpus"); 698 if (cpus && 699 of_get_property(cpus, "platform-cpu-timebase", NULL)) { 700 pmac_tb_freeze = smp_core99_pfunc_tb_freeze; 701 printk(KERN_INFO "Processor timebase sync using" 702 " platform function\n"); 703 } 704 } 705 706 #else /* CONFIG_PPC64 */ 707 708 /* GPIO based HW sync on ppc32 Core99 */ 709 if (pmac_tb_freeze == NULL && !machine_is_compatible("MacRISC4")) { 710 struct device_node *cpu; 711 const u32 *tbprop = NULL; 712 713 core99_tb_gpio = KL_GPIO_TB_ENABLE; /* default value */ 714 cpu = of_find_node_by_type(NULL, "cpu"); 715 if (cpu != NULL) { 716 tbprop = of_get_property(cpu, "timebase-enable", NULL); 717 if (tbprop) 718 core99_tb_gpio = *tbprop; 719 of_node_put(cpu); 720 } 721 pmac_tb_freeze = smp_core99_gpio_tb_freeze; 722 printk(KERN_INFO "Processor timebase sync using" 723 " GPIO 0x%02x\n", core99_tb_gpio); 724 } 725 726 #endif /* CONFIG_PPC64 */ 727 728 /* No timebase sync, fallback to software */ 729 if (pmac_tb_freeze == NULL) { 730 smp_ops->give_timebase = smp_generic_give_timebase; 731 smp_ops->take_timebase = smp_generic_take_timebase; 732 printk(KERN_INFO "Processor timebase sync using software\n"); 733 } 734 735 #ifndef CONFIG_PPC64 736 { 737 int i; 738 739 /* XXX should get this from reg properties */ 740 for (i = 1; i < ncpus; ++i) 741 smp_hw_index[i] = i; 742 } 743 #endif 744 745 /* 32 bits SMP can't NAP */ 746 if (!machine_is_compatible("MacRISC4")) 747 powersave_nap = 0; 748 } 749 750 static int __init smp_core99_probe(void) 751 { 752 struct device_node *cpus; 753 int ncpus = 0; 754 755 if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345); 756 757 /* Count CPUs in the device-tree */ 758 for (cpus = NULL; (cpus = of_find_node_by_type(cpus, "cpu")) != NULL;) 759 ++ncpus; 760 761 printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus); 762 763 /* Nothing more to do if less than 2 of them */ 764 if (ncpus <= 1) 765 return 1; 766 767 /* We need to perform some early initialisations before we can start 768 * setting up SMP as we are running before initcalls 769 */ 770 pmac_pfunc_base_install(); 771 pmac_i2c_init(); 772 773 /* Setup various bits like timebase sync method, ability to nap, ... */ 774 smp_core99_setup(ncpus); 775 776 /* Install IPIs */ 777 mpic_request_ipis(); 778 779 /* Collect l2cr and l3cr values from CPU 0 */ 780 core99_init_caches(0); 781 782 return ncpus; 783 } 784 785 static void __devinit smp_core99_kick_cpu(int nr) 786 { 787 unsigned int save_vector; 788 unsigned long target, flags; 789 volatile unsigned int *vector 790 = ((volatile unsigned int *)(KERNELBASE+0x100)); 791 792 if (nr < 0 || nr > 3) 793 return; 794 795 if (ppc_md.progress) 796 ppc_md.progress("smp_core99_kick_cpu", 0x346); 797 798 local_irq_save(flags); 799 800 /* Save reset vector */ 801 save_vector = *vector; 802 803 /* Setup fake reset vector that does 804 * b __secondary_start_pmac_0 + nr*8 - KERNELBASE 805 */ 806 target = (unsigned long) __secondary_start_pmac_0 + nr * 8; 807 create_branch((unsigned long)vector, target, BRANCH_SET_LINK); 808 809 /* Put some life in our friend */ 810 pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0); 811 812 /* FIXME: We wait a bit for the CPU to take the exception, I should 813 * instead wait for the entry code to set something for me. Well, 814 * ideally, all that crap will be done in prom.c and the CPU left 815 * in a RAM-based wait loop like CHRP. 816 */ 817 mdelay(1); 818 819 /* Restore our exception vector */ 820 *vector = save_vector; 821 flush_icache_range((unsigned long) vector, (unsigned long) vector + 4); 822 823 local_irq_restore(flags); 824 if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347); 825 } 826 827 static void __devinit smp_core99_setup_cpu(int cpu_nr) 828 { 829 /* Setup L2/L3 */ 830 if (cpu_nr != 0) 831 core99_init_caches(cpu_nr); 832 833 /* Setup openpic */ 834 mpic_setup_this_cpu(); 835 836 if (cpu_nr == 0) { 837 #ifdef CONFIG_PPC64 838 extern void g5_phy_disable_cpu1(void); 839 840 /* Close i2c bus if it was used for tb sync */ 841 if (pmac_tb_clock_chip_host) { 842 pmac_i2c_close(pmac_tb_clock_chip_host); 843 pmac_tb_clock_chip_host = NULL; 844 } 845 846 /* If we didn't start the second CPU, we must take 847 * it off the bus 848 */ 849 if (machine_is_compatible("MacRISC4") && 850 num_online_cpus() < 2) 851 g5_phy_disable_cpu1(); 852 #endif /* CONFIG_PPC64 */ 853 854 if (ppc_md.progress) 855 ppc_md.progress("core99_setup_cpu 0 done", 0x349); 856 } 857 } 858 859 860 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32) 861 862 int smp_core99_cpu_disable(void) 863 { 864 cpu_clear(smp_processor_id(), cpu_online_map); 865 866 /* XXX reset cpu affinity here */ 867 mpic_cpu_set_priority(0xf); 868 asm volatile("mtdec %0" : : "r" (0x7fffffff)); 869 mb(); 870 udelay(20); 871 asm volatile("mtdec %0" : : "r" (0x7fffffff)); 872 return 0; 873 } 874 875 extern void low_cpu_die(void) __attribute__((noreturn)); /* in sleep.S */ 876 static int cpu_dead[NR_CPUS]; 877 878 void cpu_die(void) 879 { 880 local_irq_disable(); 881 cpu_dead[smp_processor_id()] = 1; 882 mb(); 883 low_cpu_die(); 884 } 885 886 void smp_core99_cpu_die(unsigned int cpu) 887 { 888 int timeout; 889 890 timeout = 1000; 891 while (!cpu_dead[cpu]) { 892 if (--timeout == 0) { 893 printk("CPU %u refused to die!\n", cpu); 894 break; 895 } 896 msleep(1); 897 } 898 cpu_dead[cpu] = 0; 899 } 900 901 #endif /* CONFIG_HOTPLUG_CPU && CONFIG_PP32 */ 902 903 /* Core99 Macs (dual G4s and G5s) */ 904 struct smp_ops_t core99_smp_ops = { 905 .message_pass = smp_mpic_message_pass, 906 .probe = smp_core99_probe, 907 .kick_cpu = smp_core99_kick_cpu, 908 .setup_cpu = smp_core99_setup_cpu, 909 .give_timebase = smp_core99_give_timebase, 910 .take_timebase = smp_core99_take_timebase, 911 #if defined(CONFIG_HOTPLUG_CPU) 912 # if defined(CONFIG_PPC32) 913 .cpu_disable = smp_core99_cpu_disable, 914 .cpu_die = smp_core99_cpu_die, 915 # endif 916 # if defined(CONFIG_PPC64) 917 .cpu_disable = generic_cpu_disable, 918 .cpu_die = generic_cpu_die, 919 /* intentionally do *NOT* assign cpu_enable, 920 * the generic code will use kick_cpu then! */ 921 # endif 922 #endif 923 }; 924