1 /*
2  * SMP support for power macintosh.
3  *
4  * We support both the old "powersurge" SMP architecture
5  * and the current Core99 (G4 PowerMac) machines.
6  *
7  * Note that we don't support the very first rev. of
8  * Apple/DayStar 2 CPUs board, the one with the funky
9  * watchdog. Hopefully, none of these should be there except
10  * maybe internally to Apple. I should probably still add some
11  * code to detect this card though and disable SMP. --BenH.
12  *
13  * Support Macintosh G4 SMP by Troy Benjegerdes (hozer@drgw.net)
14  * and Ben Herrenschmidt <benh@kernel.crashing.org>.
15  *
16  * Support for DayStar quad CPU cards
17  * Copyright (C) XLR8, Inc. 1994-2000
18  *
19  *  This program is free software; you can redistribute it and/or
20  *  modify it under the terms of the GNU General Public License
21  *  as published by the Free Software Foundation; either version
22  *  2 of the License, or (at your option) any later version.
23  */
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/sched/hotplug.h>
27 #include <linux/smp.h>
28 #include <linux/interrupt.h>
29 #include <linux/kernel_stat.h>
30 #include <linux/delay.h>
31 #include <linux/init.h>
32 #include <linux/spinlock.h>
33 #include <linux/errno.h>
34 #include <linux/hardirq.h>
35 #include <linux/cpu.h>
36 #include <linux/compiler.h>
37 
38 #include <asm/ptrace.h>
39 #include <linux/atomic.h>
40 #include <asm/code-patching.h>
41 #include <asm/irq.h>
42 #include <asm/page.h>
43 #include <asm/pgtable.h>
44 #include <asm/sections.h>
45 #include <asm/io.h>
46 #include <asm/prom.h>
47 #include <asm/smp.h>
48 #include <asm/machdep.h>
49 #include <asm/pmac_feature.h>
50 #include <asm/time.h>
51 #include <asm/mpic.h>
52 #include <asm/cacheflush.h>
53 #include <asm/keylargo.h>
54 #include <asm/pmac_low_i2c.h>
55 #include <asm/pmac_pfunc.h>
56 
57 #include "pmac.h"
58 
59 #undef DEBUG
60 
61 #ifdef DEBUG
62 #define DBG(fmt...) udbg_printf(fmt)
63 #else
64 #define DBG(fmt...)
65 #endif
66 
67 extern void __secondary_start_pmac_0(void);
68 extern int pmac_pfunc_base_install(void);
69 
70 static void (*pmac_tb_freeze)(int freeze);
71 static u64 timebase;
72 static int tb_req;
73 
74 #ifdef CONFIG_PPC_PMAC32_PSURGE
75 
76 /*
77  * Powersurge (old powermac SMP) support.
78  */
79 
80 /* Addresses for powersurge registers */
81 #define HAMMERHEAD_BASE		0xf8000000
82 #define HHEAD_CONFIG		0x90
83 #define HHEAD_SEC_INTR		0xc0
84 
85 /* register for interrupting the primary processor on the powersurge */
86 /* N.B. this is actually the ethernet ROM! */
87 #define PSURGE_PRI_INTR		0xf3019000
88 
89 /* register for storing the start address for the secondary processor */
90 /* N.B. this is the PCI config space address register for the 1st bridge */
91 #define PSURGE_START		0xf2800000
92 
93 /* Daystar/XLR8 4-CPU card */
94 #define PSURGE_QUAD_REG_ADDR	0xf8800000
95 
96 #define PSURGE_QUAD_IRQ_SET	0
97 #define PSURGE_QUAD_IRQ_CLR	1
98 #define PSURGE_QUAD_IRQ_PRIMARY	2
99 #define PSURGE_QUAD_CKSTOP_CTL	3
100 #define PSURGE_QUAD_PRIMARY_ARB	4
101 #define PSURGE_QUAD_BOARD_ID	6
102 #define PSURGE_QUAD_WHICH_CPU	7
103 #define PSURGE_QUAD_CKSTOP_RDBK	8
104 #define PSURGE_QUAD_RESET_CTL	11
105 
106 #define PSURGE_QUAD_OUT(r, v)	(out_8(quad_base + ((r) << 4) + 4, (v)))
107 #define PSURGE_QUAD_IN(r)	(in_8(quad_base + ((r) << 4) + 4) & 0x0f)
108 #define PSURGE_QUAD_BIS(r, v)	(PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) | (v)))
109 #define PSURGE_QUAD_BIC(r, v)	(PSURGE_QUAD_OUT((r), PSURGE_QUAD_IN(r) & ~(v)))
110 
111 /* virtual addresses for the above */
112 static volatile u8 __iomem *hhead_base;
113 static volatile u8 __iomem *quad_base;
114 static volatile u32 __iomem *psurge_pri_intr;
115 static volatile u8 __iomem *psurge_sec_intr;
116 static volatile u32 __iomem *psurge_start;
117 
118 /* values for psurge_type */
119 #define PSURGE_NONE		-1
120 #define PSURGE_DUAL		0
121 #define PSURGE_QUAD_OKEE	1
122 #define PSURGE_QUAD_COTTON	2
123 #define PSURGE_QUAD_ICEGRASS	3
124 
125 /* what sort of powersurge board we have */
126 static int psurge_type = PSURGE_NONE;
127 
128 /* irq for secondary cpus to report */
129 static struct irq_domain *psurge_host;
130 int psurge_secondary_virq;
131 
132 /*
133  * Set and clear IPIs for powersurge.
134  */
135 static inline void psurge_set_ipi(int cpu)
136 {
137 	if (psurge_type == PSURGE_NONE)
138 		return;
139 	if (cpu == 0)
140 		in_be32(psurge_pri_intr);
141 	else if (psurge_type == PSURGE_DUAL)
142 		out_8(psurge_sec_intr, 0);
143 	else
144 		PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_SET, 1 << cpu);
145 }
146 
147 static inline void psurge_clr_ipi(int cpu)
148 {
149 	if (cpu > 0) {
150 		switch(psurge_type) {
151 		case PSURGE_DUAL:
152 			out_8(psurge_sec_intr, ~0);
153 		case PSURGE_NONE:
154 			break;
155 		default:
156 			PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, 1 << cpu);
157 		}
158 	}
159 }
160 
161 /*
162  * On powersurge (old SMP powermac architecture) we don't have
163  * separate IPIs for separate messages like openpic does.  Instead
164  * use the generic demux helpers
165  *  -- paulus.
166  */
167 static irqreturn_t psurge_ipi_intr(int irq, void *d)
168 {
169 	psurge_clr_ipi(smp_processor_id());
170 	smp_ipi_demux();
171 
172 	return IRQ_HANDLED;
173 }
174 
175 static void smp_psurge_cause_ipi(int cpu)
176 {
177 	psurge_set_ipi(cpu);
178 }
179 
180 static int psurge_host_map(struct irq_domain *h, unsigned int virq,
181 			 irq_hw_number_t hw)
182 {
183 	irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_percpu_irq);
184 
185 	return 0;
186 }
187 
188 static const struct irq_domain_ops psurge_host_ops = {
189 	.map	= psurge_host_map,
190 };
191 
192 static int psurge_secondary_ipi_init(void)
193 {
194 	int rc = -ENOMEM;
195 
196 	psurge_host = irq_domain_add_nomap(NULL, ~0, &psurge_host_ops, NULL);
197 
198 	if (psurge_host)
199 		psurge_secondary_virq = irq_create_direct_mapping(psurge_host);
200 
201 	if (psurge_secondary_virq)
202 		rc = request_irq(psurge_secondary_virq, psurge_ipi_intr,
203 			IRQF_PERCPU | IRQF_NO_THREAD, "IPI", NULL);
204 
205 	if (rc)
206 		pr_err("Failed to setup secondary cpu IPI\n");
207 
208 	return rc;
209 }
210 
211 /*
212  * Determine a quad card presence. We read the board ID register, we
213  * force the data bus to change to something else, and we read it again.
214  * It it's stable, then the register probably exist (ugh !)
215  */
216 static int __init psurge_quad_probe(void)
217 {
218 	int type;
219 	unsigned int i;
220 
221 	type = PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID);
222 	if (type < PSURGE_QUAD_OKEE || type > PSURGE_QUAD_ICEGRASS
223 	    || type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
224 		return PSURGE_DUAL;
225 
226 	/* looks OK, try a slightly more rigorous test */
227 	/* bogus is not necessarily cacheline-aligned,
228 	   though I don't suppose that really matters.  -- paulus */
229 	for (i = 0; i < 100; i++) {
230 		volatile u32 bogus[8];
231 		bogus[(0+i)%8] = 0x00000000;
232 		bogus[(1+i)%8] = 0x55555555;
233 		bogus[(2+i)%8] = 0xFFFFFFFF;
234 		bogus[(3+i)%8] = 0xAAAAAAAA;
235 		bogus[(4+i)%8] = 0x33333333;
236 		bogus[(5+i)%8] = 0xCCCCCCCC;
237 		bogus[(6+i)%8] = 0xCCCCCCCC;
238 		bogus[(7+i)%8] = 0x33333333;
239 		wmb();
240 		asm volatile("dcbf 0,%0" : : "r" (bogus) : "memory");
241 		mb();
242 		if (type != PSURGE_QUAD_IN(PSURGE_QUAD_BOARD_ID))
243 			return PSURGE_DUAL;
244 	}
245 	return type;
246 }
247 
248 static void __init psurge_quad_init(void)
249 {
250 	int procbits;
251 
252 	if (ppc_md.progress) ppc_md.progress("psurge_quad_init", 0x351);
253 	procbits = ~PSURGE_QUAD_IN(PSURGE_QUAD_WHICH_CPU);
254 	if (psurge_type == PSURGE_QUAD_ICEGRASS)
255 		PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
256 	else
257 		PSURGE_QUAD_BIC(PSURGE_QUAD_CKSTOP_CTL, procbits);
258 	mdelay(33);
259 	out_8(psurge_sec_intr, ~0);
260 	PSURGE_QUAD_OUT(PSURGE_QUAD_IRQ_CLR, procbits);
261 	PSURGE_QUAD_BIS(PSURGE_QUAD_RESET_CTL, procbits);
262 	if (psurge_type != PSURGE_QUAD_ICEGRASS)
263 		PSURGE_QUAD_BIS(PSURGE_QUAD_CKSTOP_CTL, procbits);
264 	PSURGE_QUAD_BIC(PSURGE_QUAD_PRIMARY_ARB, procbits);
265 	mdelay(33);
266 	PSURGE_QUAD_BIC(PSURGE_QUAD_RESET_CTL, procbits);
267 	mdelay(33);
268 	PSURGE_QUAD_BIS(PSURGE_QUAD_PRIMARY_ARB, procbits);
269 	mdelay(33);
270 }
271 
272 static void __init smp_psurge_probe(void)
273 {
274 	int i, ncpus;
275 	struct device_node *dn;
276 
277 	/* We don't do SMP on the PPC601 -- paulus */
278 	if (PVR_VER(mfspr(SPRN_PVR)) == 1)
279 		return;
280 
281 	/*
282 	 * The powersurge cpu board can be used in the generation
283 	 * of powermacs that have a socket for an upgradeable cpu card,
284 	 * including the 7500, 8500, 9500, 9600.
285 	 * The device tree doesn't tell you if you have 2 cpus because
286 	 * OF doesn't know anything about the 2nd processor.
287 	 * Instead we look for magic bits in magic registers,
288 	 * in the hammerhead memory controller in the case of the
289 	 * dual-cpu powersurge board.  -- paulus.
290 	 */
291 	dn = of_find_node_by_name(NULL, "hammerhead");
292 	if (dn == NULL)
293 		return;
294 	of_node_put(dn);
295 
296 	hhead_base = ioremap(HAMMERHEAD_BASE, 0x800);
297 	quad_base = ioremap(PSURGE_QUAD_REG_ADDR, 1024);
298 	psurge_sec_intr = hhead_base + HHEAD_SEC_INTR;
299 
300 	psurge_type = psurge_quad_probe();
301 	if (psurge_type != PSURGE_DUAL) {
302 		psurge_quad_init();
303 		/* All released cards using this HW design have 4 CPUs */
304 		ncpus = 4;
305 		/* No sure how timebase sync works on those, let's use SW */
306 		smp_ops->give_timebase = smp_generic_give_timebase;
307 		smp_ops->take_timebase = smp_generic_take_timebase;
308 	} else {
309 		iounmap(quad_base);
310 		if ((in_8(hhead_base + HHEAD_CONFIG) & 0x02) == 0) {
311 			/* not a dual-cpu card */
312 			iounmap(hhead_base);
313 			psurge_type = PSURGE_NONE;
314 			return;
315 		}
316 		ncpus = 2;
317 	}
318 
319 	if (psurge_secondary_ipi_init())
320 		return;
321 
322 	psurge_start = ioremap(PSURGE_START, 4);
323 	psurge_pri_intr = ioremap(PSURGE_PRI_INTR, 4);
324 
325 	/* This is necessary because OF doesn't know about the
326 	 * secondary cpu(s), and thus there aren't nodes in the
327 	 * device tree for them, and smp_setup_cpu_maps hasn't
328 	 * set their bits in cpu_present_mask.
329 	 */
330 	if (ncpus > NR_CPUS)
331 		ncpus = NR_CPUS;
332 	for (i = 1; i < ncpus ; ++i)
333 		set_cpu_present(i, true);
334 
335 	if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);
336 }
337 
338 static int __init smp_psurge_kick_cpu(int nr)
339 {
340 	unsigned long start = __pa(__secondary_start_pmac_0) + nr * 8;
341 	unsigned long a, flags;
342 	int i, j;
343 
344 	/* Defining this here is evil ... but I prefer hiding that
345 	 * crap to avoid giving people ideas that they can do the
346 	 * same.
347 	 */
348 	extern volatile unsigned int cpu_callin_map[NR_CPUS];
349 
350 	/* may need to flush here if secondary bats aren't setup */
351 	for (a = KERNELBASE; a < KERNELBASE + 0x800000; a += 32)
352 		asm volatile("dcbf 0,%0" : : "r" (a) : "memory");
353 	asm volatile("sync");
354 
355 	if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu", 0x353);
356 
357 	/* This is going to freeze the timeebase, we disable interrupts */
358 	local_irq_save(flags);
359 
360 	out_be32(psurge_start, start);
361 	mb();
362 
363 	psurge_set_ipi(nr);
364 
365 	/*
366 	 * We can't use udelay here because the timebase is now frozen.
367 	 */
368 	for (i = 0; i < 2000; ++i)
369 		asm volatile("nop" : : : "memory");
370 	psurge_clr_ipi(nr);
371 
372 	/*
373 	 * Also, because the timebase is frozen, we must not return to the
374 	 * caller which will try to do udelay's etc... Instead, we wait -here-
375 	 * for the CPU to callin.
376 	 */
377 	for (i = 0; i < 100000 && !cpu_callin_map[nr]; ++i) {
378 		for (j = 1; j < 10000; j++)
379 			asm volatile("nop" : : : "memory");
380 		asm volatile("sync" : : : "memory");
381 	}
382 	if (!cpu_callin_map[nr])
383 		goto stuck;
384 
385 	/* And we do the TB sync here too for standard dual CPU cards */
386 	if (psurge_type == PSURGE_DUAL) {
387 		while(!tb_req)
388 			barrier();
389 		tb_req = 0;
390 		mb();
391 		timebase = get_tb();
392 		mb();
393 		while (timebase)
394 			barrier();
395 		mb();
396 	}
397  stuck:
398 	/* now interrupt the secondary, restarting both TBs */
399 	if (psurge_type == PSURGE_DUAL)
400 		psurge_set_ipi(1);
401 
402 	if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);
403 
404 	return 0;
405 }
406 
407 static struct irqaction psurge_irqaction = {
408 	.handler = psurge_ipi_intr,
409 	.flags = IRQF_PERCPU | IRQF_NO_THREAD,
410 	.name = "primary IPI",
411 };
412 
413 static void __init smp_psurge_setup_cpu(int cpu_nr)
414 {
415 	if (cpu_nr != 0 || !psurge_start)
416 		return;
417 
418 	/* reset the entry point so if we get another intr we won't
419 	 * try to startup again */
420 	out_be32(psurge_start, 0x100);
421 	if (setup_irq(irq_create_mapping(NULL, 30), &psurge_irqaction))
422 		printk(KERN_ERR "Couldn't get primary IPI interrupt");
423 }
424 
425 void __init smp_psurge_take_timebase(void)
426 {
427 	if (psurge_type != PSURGE_DUAL)
428 		return;
429 
430 	tb_req = 1;
431 	mb();
432 	while (!timebase)
433 		barrier();
434 	mb();
435 	set_tb(timebase >> 32, timebase & 0xffffffff);
436 	timebase = 0;
437 	mb();
438 	set_dec(tb_ticks_per_jiffy/2);
439 }
440 
441 void __init smp_psurge_give_timebase(void)
442 {
443 	/* Nothing to do here */
444 }
445 
446 /* PowerSurge-style Macs */
447 struct smp_ops_t psurge_smp_ops = {
448 	.message_pass	= NULL,	/* Use smp_muxed_ipi_message_pass */
449 	.cause_ipi	= smp_psurge_cause_ipi,
450 	.cause_nmi_ipi	= NULL,
451 	.probe		= smp_psurge_probe,
452 	.kick_cpu	= smp_psurge_kick_cpu,
453 	.setup_cpu	= smp_psurge_setup_cpu,
454 	.give_timebase	= smp_psurge_give_timebase,
455 	.take_timebase	= smp_psurge_take_timebase,
456 };
457 #endif /* CONFIG_PPC_PMAC32_PSURGE */
458 
459 /*
460  * Core 99 and later support
461  */
462 
463 
464 static void smp_core99_give_timebase(void)
465 {
466 	unsigned long flags;
467 
468 	local_irq_save(flags);
469 
470 	while(!tb_req)
471 		barrier();
472 	tb_req = 0;
473 	(*pmac_tb_freeze)(1);
474 	mb();
475 	timebase = get_tb();
476 	mb();
477 	while (timebase)
478 		barrier();
479 	mb();
480 	(*pmac_tb_freeze)(0);
481 	mb();
482 
483 	local_irq_restore(flags);
484 }
485 
486 
487 static void smp_core99_take_timebase(void)
488 {
489 	unsigned long flags;
490 
491 	local_irq_save(flags);
492 
493 	tb_req = 1;
494 	mb();
495 	while (!timebase)
496 		barrier();
497 	mb();
498 	set_tb(timebase >> 32, timebase & 0xffffffff);
499 	timebase = 0;
500 	mb();
501 
502 	local_irq_restore(flags);
503 }
504 
505 #ifdef CONFIG_PPC64
506 /*
507  * G5s enable/disable the timebase via an i2c-connected clock chip.
508  */
509 static struct pmac_i2c_bus *pmac_tb_clock_chip_host;
510 static u8 pmac_tb_pulsar_addr;
511 
512 static void smp_core99_cypress_tb_freeze(int freeze)
513 {
514 	u8 data;
515 	int rc;
516 
517 	/* Strangely, the device-tree says address is 0xd2, but darwin
518 	 * accesses 0xd0 ...
519 	 */
520 	pmac_i2c_setmode(pmac_tb_clock_chip_host,
521 			 pmac_i2c_mode_combined);
522 	rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
523 			   0xd0 | pmac_i2c_read,
524 			   1, 0x81, &data, 1);
525 	if (rc != 0)
526 		goto bail;
527 
528 	data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);
529 
530        	pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
531 	rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
532 			   0xd0 | pmac_i2c_write,
533 			   1, 0x81, &data, 1);
534 
535  bail:
536 	if (rc != 0) {
537 		printk("Cypress Timebase %s rc: %d\n",
538 		       freeze ? "freeze" : "unfreeze", rc);
539 		panic("Timebase freeze failed !\n");
540 	}
541 }
542 
543 
544 static void smp_core99_pulsar_tb_freeze(int freeze)
545 {
546 	u8 data;
547 	int rc;
548 
549 	pmac_i2c_setmode(pmac_tb_clock_chip_host,
550 			 pmac_i2c_mode_combined);
551 	rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
552 			   pmac_tb_pulsar_addr | pmac_i2c_read,
553 			   1, 0x2e, &data, 1);
554 	if (rc != 0)
555 		goto bail;
556 
557 	data = (data & 0x88) | (freeze ? 0x11 : 0x22);
558 
559 	pmac_i2c_setmode(pmac_tb_clock_chip_host, pmac_i2c_mode_stdsub);
560 	rc = pmac_i2c_xfer(pmac_tb_clock_chip_host,
561 			   pmac_tb_pulsar_addr | pmac_i2c_write,
562 			   1, 0x2e, &data, 1);
563  bail:
564 	if (rc != 0) {
565 		printk(KERN_ERR "Pulsar Timebase %s rc: %d\n",
566 		       freeze ? "freeze" : "unfreeze", rc);
567 		panic("Timebase freeze failed !\n");
568 	}
569 }
570 
571 static void __init smp_core99_setup_i2c_hwsync(int ncpus)
572 {
573 	struct device_node *cc = NULL;
574 	struct device_node *p;
575 	const char *name = NULL;
576 	const u32 *reg;
577 	int ok;
578 
579 	/* Look for the clock chip */
580 	for_each_node_by_name(cc, "i2c-hwclock") {
581 		p = of_get_parent(cc);
582 		ok = p && of_device_is_compatible(p, "uni-n-i2c");
583 		of_node_put(p);
584 		if (!ok)
585 			continue;
586 
587 		pmac_tb_clock_chip_host = pmac_i2c_find_bus(cc);
588 		if (pmac_tb_clock_chip_host == NULL)
589 			continue;
590 		reg = of_get_property(cc, "reg", NULL);
591 		if (reg == NULL)
592 			continue;
593 		switch (*reg) {
594 		case 0xd2:
595 			if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) {
596 				pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
597 				pmac_tb_pulsar_addr = 0xd2;
598 				name = "Pulsar";
599 			} else if (of_device_is_compatible(cc, "cy28508")) {
600 				pmac_tb_freeze = smp_core99_cypress_tb_freeze;
601 				name = "Cypress";
602 			}
603 			break;
604 		case 0xd4:
605 			pmac_tb_freeze = smp_core99_pulsar_tb_freeze;
606 			pmac_tb_pulsar_addr = 0xd4;
607 			name = "Pulsar";
608 			break;
609 		}
610 		if (pmac_tb_freeze != NULL)
611 			break;
612 	}
613 	if (pmac_tb_freeze != NULL) {
614 		/* Open i2c bus for synchronous access */
615 		if (pmac_i2c_open(pmac_tb_clock_chip_host, 1)) {
616 			printk(KERN_ERR "Failed top open i2c bus for clock"
617 			       " sync, fallback to software sync !\n");
618 			goto no_i2c_sync;
619 		}
620 		printk(KERN_INFO "Processor timebase sync using %s i2c clock\n",
621 		       name);
622 		return;
623 	}
624  no_i2c_sync:
625 	pmac_tb_freeze = NULL;
626 	pmac_tb_clock_chip_host = NULL;
627 }
628 
629 
630 
631 /*
632  * Newer G5s uses a platform function
633  */
634 
635 static void smp_core99_pfunc_tb_freeze(int freeze)
636 {
637 	struct device_node *cpus;
638 	struct pmf_args args;
639 
640 	cpus = of_find_node_by_path("/cpus");
641 	BUG_ON(cpus == NULL);
642 	args.count = 1;
643 	args.u[0].v = !freeze;
644 	pmf_call_function(cpus, "cpu-timebase", &args);
645 	of_node_put(cpus);
646 }
647 
648 #else /* CONFIG_PPC64 */
649 
650 /*
651  * SMP G4 use a GPIO to enable/disable the timebase.
652  */
653 
654 static unsigned int core99_tb_gpio;	/* Timebase freeze GPIO */
655 
656 static void smp_core99_gpio_tb_freeze(int freeze)
657 {
658 	if (freeze)
659 		pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 4);
660 	else
661 		pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, core99_tb_gpio, 0);
662 	pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, core99_tb_gpio, 0);
663 }
664 
665 
666 #endif /* !CONFIG_PPC64 */
667 
668 /* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
669 volatile static long int core99_l2_cache;
670 volatile static long int core99_l3_cache;
671 
672 static void core99_init_caches(int cpu)
673 {
674 #ifndef CONFIG_PPC64
675 	if (!cpu_has_feature(CPU_FTR_L2CR))
676 		return;
677 
678 	if (cpu == 0) {
679 		core99_l2_cache = _get_L2CR();
680 		printk("CPU0: L2CR is %lx\n", core99_l2_cache);
681 	} else {
682 		printk("CPU%d: L2CR was %lx\n", cpu, _get_L2CR());
683 		_set_L2CR(0);
684 		_set_L2CR(core99_l2_cache);
685 		printk("CPU%d: L2CR set to %lx\n", cpu, core99_l2_cache);
686 	}
687 
688 	if (!cpu_has_feature(CPU_FTR_L3CR))
689 		return;
690 
691 	if (cpu == 0){
692 		core99_l3_cache = _get_L3CR();
693 		printk("CPU0: L3CR is %lx\n", core99_l3_cache);
694 	} else {
695 		printk("CPU%d: L3CR was %lx\n", cpu, _get_L3CR());
696 		_set_L3CR(0);
697 		_set_L3CR(core99_l3_cache);
698 		printk("CPU%d: L3CR set to %lx\n", cpu, core99_l3_cache);
699 	}
700 #endif /* !CONFIG_PPC64 */
701 }
702 
703 static void __init smp_core99_setup(int ncpus)
704 {
705 #ifdef CONFIG_PPC64
706 
707 	/* i2c based HW sync on some G5s */
708 	if (of_machine_is_compatible("PowerMac7,2") ||
709 	    of_machine_is_compatible("PowerMac7,3") ||
710 	    of_machine_is_compatible("RackMac3,1"))
711 		smp_core99_setup_i2c_hwsync(ncpus);
712 
713 	/* pfunc based HW sync on recent G5s */
714 	if (pmac_tb_freeze == NULL) {
715 		struct device_node *cpus =
716 			of_find_node_by_path("/cpus");
717 		if (cpus &&
718 		    of_get_property(cpus, "platform-cpu-timebase", NULL)) {
719 			pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
720 			printk(KERN_INFO "Processor timebase sync using"
721 			       " platform function\n");
722 		}
723 	}
724 
725 #else /* CONFIG_PPC64 */
726 
727 	/* GPIO based HW sync on ppc32 Core99 */
728 	if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) {
729 		struct device_node *cpu;
730 		const u32 *tbprop = NULL;
731 
732 		core99_tb_gpio = KL_GPIO_TB_ENABLE;	/* default value */
733 		cpu = of_find_node_by_type(NULL, "cpu");
734 		if (cpu != NULL) {
735 			tbprop = of_get_property(cpu, "timebase-enable", NULL);
736 			if (tbprop)
737 				core99_tb_gpio = *tbprop;
738 			of_node_put(cpu);
739 		}
740 		pmac_tb_freeze = smp_core99_gpio_tb_freeze;
741 		printk(KERN_INFO "Processor timebase sync using"
742 		       " GPIO 0x%02x\n", core99_tb_gpio);
743 	}
744 
745 #endif /* CONFIG_PPC64 */
746 
747 	/* No timebase sync, fallback to software */
748 	if (pmac_tb_freeze == NULL) {
749 		smp_ops->give_timebase = smp_generic_give_timebase;
750 		smp_ops->take_timebase = smp_generic_take_timebase;
751 		printk(KERN_INFO "Processor timebase sync using software\n");
752 	}
753 
754 #ifndef CONFIG_PPC64
755 	{
756 		int i;
757 
758 		/* XXX should get this from reg properties */
759 		for (i = 1; i < ncpus; ++i)
760 			set_hard_smp_processor_id(i, i);
761 	}
762 #endif
763 
764 	/* 32 bits SMP can't NAP */
765 	if (!of_machine_is_compatible("MacRISC4"))
766 		powersave_nap = 0;
767 }
768 
769 static void __init smp_core99_probe(void)
770 {
771 	struct device_node *cpus;
772 	int ncpus = 0;
773 
774 	if (ppc_md.progress) ppc_md.progress("smp_core99_probe", 0x345);
775 
776 	/* Count CPUs in the device-tree */
777 	for_each_node_by_type(cpus, "cpu")
778 		++ncpus;
779 
780 	printk(KERN_INFO "PowerMac SMP probe found %d cpus\n", ncpus);
781 
782 	/* Nothing more to do if less than 2 of them */
783 	if (ncpus <= 1)
784 		return;
785 
786 	/* We need to perform some early initialisations before we can start
787 	 * setting up SMP as we are running before initcalls
788 	 */
789 	pmac_pfunc_base_install();
790 	pmac_i2c_init();
791 
792 	/* Setup various bits like timebase sync method, ability to nap, ... */
793 	smp_core99_setup(ncpus);
794 
795 	/* Install IPIs */
796 	mpic_request_ipis();
797 
798 	/* Collect l2cr and l3cr values from CPU 0 */
799 	core99_init_caches(0);
800 }
801 
802 static int smp_core99_kick_cpu(int nr)
803 {
804 	unsigned int save_vector;
805 	unsigned long target, flags;
806 	unsigned int *vector = (unsigned int *)(PAGE_OFFSET+0x100);
807 
808 	if (nr < 0 || nr > 3)
809 		return -ENOENT;
810 
811 	if (ppc_md.progress)
812 		ppc_md.progress("smp_core99_kick_cpu", 0x346);
813 
814 	local_irq_save(flags);
815 
816 	/* Save reset vector */
817 	save_vector = *vector;
818 
819 	/* Setup fake reset vector that does
820 	 *   b __secondary_start_pmac_0 + nr*8
821 	 */
822 	target = (unsigned long) __secondary_start_pmac_0 + nr * 8;
823 	patch_branch(vector, target, BRANCH_SET_LINK);
824 
825 	/* Put some life in our friend */
826 	pmac_call_feature(PMAC_FTR_RESET_CPU, NULL, nr, 0);
827 
828 	/* FIXME: We wait a bit for the CPU to take the exception, I should
829 	 * instead wait for the entry code to set something for me. Well,
830 	 * ideally, all that crap will be done in prom.c and the CPU left
831 	 * in a RAM-based wait loop like CHRP.
832 	 */
833 	mdelay(1);
834 
835 	/* Restore our exception vector */
836 	*vector = save_vector;
837 	flush_icache_range((unsigned long) vector, (unsigned long) vector + 4);
838 
839 	local_irq_restore(flags);
840 	if (ppc_md.progress) ppc_md.progress("smp_core99_kick_cpu done", 0x347);
841 
842 	return 0;
843 }
844 
845 static void smp_core99_setup_cpu(int cpu_nr)
846 {
847 	/* Setup L2/L3 */
848 	if (cpu_nr != 0)
849 		core99_init_caches(cpu_nr);
850 
851 	/* Setup openpic */
852 	mpic_setup_this_cpu();
853 }
854 
855 #ifdef CONFIG_PPC64
856 #ifdef CONFIG_HOTPLUG_CPU
857 static unsigned int smp_core99_host_open;
858 
859 static int smp_core99_cpu_prepare(unsigned int cpu)
860 {
861 	int rc;
862 
863 	/* Open i2c bus if it was used for tb sync */
864 	if (pmac_tb_clock_chip_host && !smp_core99_host_open) {
865 		rc = pmac_i2c_open(pmac_tb_clock_chip_host, 1);
866 		if (rc) {
867 			pr_err("Failed to open i2c bus for time sync\n");
868 			return notifier_from_errno(rc);
869 		}
870 		smp_core99_host_open = 1;
871 	}
872 	return 0;
873 }
874 
875 static int smp_core99_cpu_online(unsigned int cpu)
876 {
877 	/* Close i2c bus if it was used for tb sync */
878 	if (pmac_tb_clock_chip_host && smp_core99_host_open) {
879 		pmac_i2c_close(pmac_tb_clock_chip_host);
880 		smp_core99_host_open = 0;
881 	}
882 	return 0;
883 }
884 #endif /* CONFIG_HOTPLUG_CPU */
885 
886 static void __init smp_core99_bringup_done(void)
887 {
888 	extern void g5_phy_disable_cpu1(void);
889 
890 	/* Close i2c bus if it was used for tb sync */
891 	if (pmac_tb_clock_chip_host)
892 		pmac_i2c_close(pmac_tb_clock_chip_host);
893 
894 	/* If we didn't start the second CPU, we must take
895 	 * it off the bus.
896 	 */
897 	if (of_machine_is_compatible("MacRISC4") &&
898 	    num_online_cpus() < 2) {
899 		set_cpu_present(1, false);
900 		g5_phy_disable_cpu1();
901 	}
902 #ifdef CONFIG_HOTPLUG_CPU
903 	cpuhp_setup_state_nocalls(CPUHP_POWERPC_PMAC_PREPARE,
904 				  "powerpc/pmac:prepare", smp_core99_cpu_prepare,
905 				  NULL);
906 	cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "powerpc/pmac:online",
907 				  smp_core99_cpu_online, NULL);
908 #endif
909 
910 	if (ppc_md.progress)
911 		ppc_md.progress("smp_core99_bringup_done", 0x349);
912 }
913 #endif /* CONFIG_PPC64 */
914 
915 #ifdef CONFIG_HOTPLUG_CPU
916 
917 static int smp_core99_cpu_disable(void)
918 {
919 	int rc = generic_cpu_disable();
920 	if (rc)
921 		return rc;
922 
923 	mpic_cpu_set_priority(0xf);
924 
925 	return 0;
926 }
927 
928 #ifdef CONFIG_PPC32
929 
930 static void pmac_cpu_die(void)
931 {
932 	int cpu = smp_processor_id();
933 
934 	local_irq_disable();
935 	idle_task_exit();
936 	pr_debug("CPU%d offline\n", cpu);
937 	generic_set_cpu_dead(cpu);
938 	smp_wmb();
939 	mb();
940 	low_cpu_die();
941 }
942 
943 #else /* CONFIG_PPC32 */
944 
945 static void pmac_cpu_die(void)
946 {
947 	int cpu = smp_processor_id();
948 
949 	local_irq_disable();
950 	idle_task_exit();
951 
952 	/*
953 	 * turn off as much as possible, we'll be
954 	 * kicked out as this will only be invoked
955 	 * on core99 platforms for now ...
956 	 */
957 
958 	printk(KERN_INFO "CPU#%d offline\n", cpu);
959 	generic_set_cpu_dead(cpu);
960 	smp_wmb();
961 
962 	/*
963 	 * Re-enable interrupts. The NAP code needs to enable them
964 	 * anyways, do it now so we deal with the case where one already
965 	 * happened while soft-disabled.
966 	 * We shouldn't get any external interrupts, only decrementer, and the
967 	 * decrementer handler is safe for use on offline CPUs
968 	 */
969 	local_irq_enable();
970 
971 	while (1) {
972 		/* let's not take timer interrupts too often ... */
973 		set_dec(0x7fffffff);
974 
975 		/* Enter NAP mode */
976 		power4_idle();
977 	}
978 }
979 
980 #endif /* else CONFIG_PPC32 */
981 #endif /* CONFIG_HOTPLUG_CPU */
982 
983 /* Core99 Macs (dual G4s and G5s) */
984 static struct smp_ops_t core99_smp_ops = {
985 	.message_pass	= smp_mpic_message_pass,
986 	.probe		= smp_core99_probe,
987 #ifdef CONFIG_PPC64
988 	.bringup_done	= smp_core99_bringup_done,
989 #endif
990 	.kick_cpu	= smp_core99_kick_cpu,
991 	.setup_cpu	= smp_core99_setup_cpu,
992 	.give_timebase	= smp_core99_give_timebase,
993 	.take_timebase	= smp_core99_take_timebase,
994 #if defined(CONFIG_HOTPLUG_CPU)
995 	.cpu_disable	= smp_core99_cpu_disable,
996 	.cpu_die	= generic_cpu_die,
997 #endif
998 };
999 
1000 void __init pmac_setup_smp(void)
1001 {
1002 	struct device_node *np;
1003 
1004 	/* Check for Core99 */
1005 	np = of_find_node_by_name(NULL, "uni-n");
1006 	if (!np)
1007 		np = of_find_node_by_name(NULL, "u3");
1008 	if (!np)
1009 		np = of_find_node_by_name(NULL, "u4");
1010 	if (np) {
1011 		of_node_put(np);
1012 		smp_ops = &core99_smp_ops;
1013 	}
1014 #ifdef CONFIG_PPC_PMAC32_PSURGE
1015 	else {
1016 		/* We have to set bits in cpu_possible_mask here since the
1017 		 * secondary CPU(s) aren't in the device tree. Various
1018 		 * things won't be initialized for CPUs not in the possible
1019 		 * map, so we really need to fix it up here.
1020 		 */
1021 		int cpu;
1022 
1023 		for (cpu = 1; cpu < 4 && cpu < NR_CPUS; ++cpu)
1024 			set_cpu_possible(cpu, true);
1025 		smp_ops = &psurge_smp_ops;
1026 	}
1027 #endif /* CONFIG_PPC_PMAC32_PSURGE */
1028 
1029 #ifdef CONFIG_HOTPLUG_CPU
1030 	ppc_md.cpu_die = pmac_cpu_die;
1031 #endif
1032 }
1033 
1034 
1035