1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * This file contains sleep low-level functions for PowerBook G3.
4 *    Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org)
5 *    and Paul Mackerras (paulus@samba.org).
6 */
7
8#include <asm/processor.h>
9#include <asm/page.h>
10#include <asm/ppc_asm.h>
11#include <asm/cputable.h>
12#include <asm/cache.h>
13#include <asm/thread_info.h>
14#include <asm/asm-offsets.h>
15#include <asm/mmu.h>
16#include <asm/feature-fixups.h>
17
18#define MAGIC	0x4c617273	/* 'Lars' */
19
20/*
21 * Structure for storing CPU registers on the stack.
22 */
23#define SL_SP		0
24#define SL_PC		4
25#define SL_MSR		8
26#define SL_SDR1		0xc
27#define SL_SPRG0	0x10	/* 4 sprg's */
28#define SL_DBAT0	0x20
29#define SL_IBAT0	0x28
30#define SL_DBAT1	0x30
31#define SL_IBAT1	0x38
32#define SL_DBAT2	0x40
33#define SL_IBAT2	0x48
34#define SL_DBAT3	0x50
35#define SL_IBAT3	0x58
36#define SL_DBAT4	0x60
37#define SL_IBAT4	0x68
38#define SL_DBAT5	0x70
39#define SL_IBAT5	0x78
40#define SL_DBAT6	0x80
41#define SL_IBAT6	0x88
42#define SL_DBAT7	0x90
43#define SL_IBAT7	0x98
44#define SL_TB		0xa0
45#define SL_R2		0xa8
46#define SL_CR		0xac
47#define SL_R12		0xb0	/* r12 to r31 */
48#define SL_SIZE		(SL_R12 + 80)
49
50	.section .text
51	.align	5
52
53#if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || \
54    (defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32))
55
56/* This gets called by via-pmu.c late during the sleep process.
57 * The PMU was already send the sleep command and will shut us down
58 * soon. We need to save all that is needed and setup the wakeup
59 * vector that will be called by the ROM on wakeup
60 */
61_GLOBAL(low_sleep_handler)
62#ifndef CONFIG_PPC_BOOK3S_32
63	blr
64#else
65	mflr	r0
66	stw	r0,4(r1)
67	stwu	r1,-SL_SIZE(r1)
68	mfcr	r0
69	stw	r0,SL_CR(r1)
70	stw	r2,SL_R2(r1)
71	stmw	r12,SL_R12(r1)
72
73	/* Save MSR & SDR1 */
74	mfmsr	r4
75	stw	r4,SL_MSR(r1)
76	mfsdr1	r4
77	stw	r4,SL_SDR1(r1)
78
79	/* Get a stable timebase and save it */
801:	mftbu	r4
81	stw	r4,SL_TB(r1)
82	mftb	r5
83	stw	r5,SL_TB+4(r1)
84	mftbu	r3
85	cmpw	r3,r4
86	bne	1b
87
88	/* Save SPRGs */
89	mfsprg	r4,0
90	stw	r4,SL_SPRG0(r1)
91	mfsprg	r4,1
92	stw	r4,SL_SPRG0+4(r1)
93	mfsprg	r4,2
94	stw	r4,SL_SPRG0+8(r1)
95	mfsprg	r4,3
96	stw	r4,SL_SPRG0+12(r1)
97
98	/* Save BATs */
99	mfdbatu	r4,0
100	stw	r4,SL_DBAT0(r1)
101	mfdbatl	r4,0
102	stw	r4,SL_DBAT0+4(r1)
103	mfdbatu	r4,1
104	stw	r4,SL_DBAT1(r1)
105	mfdbatl	r4,1
106	stw	r4,SL_DBAT1+4(r1)
107	mfdbatu	r4,2
108	stw	r4,SL_DBAT2(r1)
109	mfdbatl	r4,2
110	stw	r4,SL_DBAT2+4(r1)
111	mfdbatu	r4,3
112	stw	r4,SL_DBAT3(r1)
113	mfdbatl	r4,3
114	stw	r4,SL_DBAT3+4(r1)
115	mfibatu	r4,0
116	stw	r4,SL_IBAT0(r1)
117	mfibatl	r4,0
118	stw	r4,SL_IBAT0+4(r1)
119	mfibatu	r4,1
120	stw	r4,SL_IBAT1(r1)
121	mfibatl	r4,1
122	stw	r4,SL_IBAT1+4(r1)
123	mfibatu	r4,2
124	stw	r4,SL_IBAT2(r1)
125	mfibatl	r4,2
126	stw	r4,SL_IBAT2+4(r1)
127	mfibatu	r4,3
128	stw	r4,SL_IBAT3(r1)
129	mfibatl	r4,3
130	stw	r4,SL_IBAT3+4(r1)
131
132BEGIN_MMU_FTR_SECTION
133	mfspr	r4,SPRN_DBAT4U
134	stw	r4,SL_DBAT4(r1)
135	mfspr	r4,SPRN_DBAT4L
136	stw	r4,SL_DBAT4+4(r1)
137	mfspr	r4,SPRN_DBAT5U
138	stw	r4,SL_DBAT5(r1)
139	mfspr	r4,SPRN_DBAT5L
140	stw	r4,SL_DBAT5+4(r1)
141	mfspr	r4,SPRN_DBAT6U
142	stw	r4,SL_DBAT6(r1)
143	mfspr	r4,SPRN_DBAT6L
144	stw	r4,SL_DBAT6+4(r1)
145	mfspr	r4,SPRN_DBAT7U
146	stw	r4,SL_DBAT7(r1)
147	mfspr	r4,SPRN_DBAT7L
148	stw	r4,SL_DBAT7+4(r1)
149	mfspr	r4,SPRN_IBAT4U
150	stw	r4,SL_IBAT4(r1)
151	mfspr	r4,SPRN_IBAT4L
152	stw	r4,SL_IBAT4+4(r1)
153	mfspr	r4,SPRN_IBAT5U
154	stw	r4,SL_IBAT5(r1)
155	mfspr	r4,SPRN_IBAT5L
156	stw	r4,SL_IBAT5+4(r1)
157	mfspr	r4,SPRN_IBAT6U
158	stw	r4,SL_IBAT6(r1)
159	mfspr	r4,SPRN_IBAT6L
160	stw	r4,SL_IBAT6+4(r1)
161	mfspr	r4,SPRN_IBAT7U
162	stw	r4,SL_IBAT7(r1)
163	mfspr	r4,SPRN_IBAT7L
164	stw	r4,SL_IBAT7+4(r1)
165END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
166
167	/* Backup various CPU config stuffs */
168	bl	__save_cpu_setup
169
170	/* The ROM can wake us up via 2 different vectors:
171	 *  - On wallstreet & lombard, we must write a magic
172	 *    value 'Lars' at address 4 and a pointer to a
173	 *    memory location containing the PC to resume from
174	 *    at address 0.
175	 *  - On Core99, we must store the wakeup vector at
176	 *    address 0x80 and eventually it's parameters
177	 *    at address 0x84. I've have some trouble with those
178	 *    parameters however and I no longer use them.
179	 */
180	lis	r5,grackle_wake_up@ha
181	addi	r5,r5,grackle_wake_up@l
182	tophys(r5,r5)
183	stw	r5,SL_PC(r1)
184	lis	r4,KERNELBASE@h
185	tophys(r5,r1)
186	addi	r5,r5,SL_PC
187	lis	r6,MAGIC@ha
188	addi	r6,r6,MAGIC@l
189	stw	r5,0(r4)
190	stw	r6,4(r4)
191	/* Setup stuffs at 0x80-0x84 for Core99 */
192	lis	r3,core99_wake_up@ha
193	addi	r3,r3,core99_wake_up@l
194	tophys(r3,r3)
195	stw	r3,0x80(r4)
196	stw	r5,0x84(r4)
197	/* Store a pointer to our backup storage into
198	 * a kernel global
199	 */
200	lis r3,sleep_storage@ha
201	addi r3,r3,sleep_storage@l
202	stw r5,0(r3)
203
204	.globl	low_cpu_die
205low_cpu_die:
206	/* Flush & disable all caches */
207	bl	flush_disable_caches
208
209	/* Turn off data relocation. */
210	mfmsr	r3		/* Save MSR in r7 */
211	rlwinm	r3,r3,0,28,26	/* Turn off DR bit */
212	sync
213	mtmsr	r3
214	isync
215
216BEGIN_FTR_SECTION
217	/* Flush any pending L2 data prefetches to work around HW bug */
218	sync
219	lis	r3,0xfff0
220	lwz	r0,0(r3)	/* perform cache-inhibited load to ROM */
221	sync			/* (caches are disabled at this point) */
222END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
223
224/*
225 * Set the HID0 and MSR for sleep.
226 */
227	mfspr	r2,SPRN_HID0
228	rlwinm	r2,r2,0,10,7	/* clear doze, nap */
229	oris	r2,r2,HID0_SLEEP@h
230	sync
231	isync
232	mtspr	SPRN_HID0,r2
233	sync
234
235/* This loop puts us back to sleep in case we have a spurrious
236 * wakeup so that the host bridge properly stays asleep. The
237 * CPU will be turned off, either after a known time (about 1
238 * second) on wallstreet & lombard, or as soon as the CPU enters
239 * SLEEP mode on core99
240 */
241	mfmsr	r2
242	oris	r2,r2,MSR_POW@h
2431:	sync
244	mtmsr	r2
245	isync
246	b	1b
247
248/*
249 * Here is the resume code.
250 */
251
252
253/*
254 * Core99 machines resume here
255 * r4 has the physical address of SL_PC(sp) (unused)
256 */
257_GLOBAL(core99_wake_up)
258	/* Make sure HID0 no longer contains any sleep bit and that data cache
259	 * is disabled
260	 */
261	mfspr	r3,SPRN_HID0
262	rlwinm	r3,r3,0,11,7		/* clear SLEEP, NAP, DOZE bits */
263	rlwinm	3,r3,0,18,15		/* clear DCE, ICE */
264	mtspr	SPRN_HID0,r3
265	sync
266	isync
267
268	/* sanitize MSR */
269	mfmsr	r3
270	ori	r3,r3,MSR_EE|MSR_IP
271	xori	r3,r3,MSR_EE|MSR_IP
272	sync
273	isync
274	mtmsr	r3
275	sync
276	isync
277
278	/* Recover sleep storage */
279	lis	r3,sleep_storage@ha
280	addi	r3,r3,sleep_storage@l
281	tophys(r3,r3)
282	lwz	r1,0(r3)
283
284	/* Pass thru to older resume code ... */
285/*
286 * Here is the resume code for older machines.
287 * r1 has the physical address of SL_PC(sp).
288 */
289
290grackle_wake_up:
291
292	/* Restore the kernel's segment registers before
293	 * we do any r1 memory access as we are not sure they
294	 * are in a sane state above the first 256Mb region
295	 */
296	li	r0,16		/* load up segment register values */
297	mtctr	r0		/* for context 0 */
298	lis	r3,0x2000	/* Ku = 1, VSID = 0 */
299	li	r4,0
3003:	mtsrin	r3,r4
301	addi	r3,r3,0x111	/* increment VSID */
302	addis	r4,r4,0x1000	/* address of next segment */
303	bdnz	3b
304	sync
305	isync
306
307	subi	r1,r1,SL_PC
308
309	/* Restore various CPU config stuffs */
310	bl	__restore_cpu_setup
311
312	/* Make sure all FPRs have been initialized */
313	bl	reloc_offset
314	bl	__init_fpu_registers
315
316	/* Invalidate & enable L1 cache, we don't care about
317	 * whatever the ROM may have tried to write to memory
318	 */
319	bl	__inval_enable_L1
320
321	/* Restore the BATs, and SDR1.  Then we can turn on the MMU. */
322	lwz	r4,SL_SDR1(r1)
323	mtsdr1	r4
324	lwz	r4,SL_SPRG0(r1)
325	mtsprg	0,r4
326	lwz	r4,SL_SPRG0+4(r1)
327	mtsprg	1,r4
328	lwz	r4,SL_SPRG0+8(r1)
329	mtsprg	2,r4
330	lwz	r4,SL_SPRG0+12(r1)
331	mtsprg	3,r4
332
333	lwz	r4,SL_DBAT0(r1)
334	mtdbatu	0,r4
335	lwz	r4,SL_DBAT0+4(r1)
336	mtdbatl	0,r4
337	lwz	r4,SL_DBAT1(r1)
338	mtdbatu	1,r4
339	lwz	r4,SL_DBAT1+4(r1)
340	mtdbatl	1,r4
341	lwz	r4,SL_DBAT2(r1)
342	mtdbatu	2,r4
343	lwz	r4,SL_DBAT2+4(r1)
344	mtdbatl	2,r4
345	lwz	r4,SL_DBAT3(r1)
346	mtdbatu	3,r4
347	lwz	r4,SL_DBAT3+4(r1)
348	mtdbatl	3,r4
349	lwz	r4,SL_IBAT0(r1)
350	mtibatu	0,r4
351	lwz	r4,SL_IBAT0+4(r1)
352	mtibatl	0,r4
353	lwz	r4,SL_IBAT1(r1)
354	mtibatu	1,r4
355	lwz	r4,SL_IBAT1+4(r1)
356	mtibatl	1,r4
357	lwz	r4,SL_IBAT2(r1)
358	mtibatu	2,r4
359	lwz	r4,SL_IBAT2+4(r1)
360	mtibatl	2,r4
361	lwz	r4,SL_IBAT3(r1)
362	mtibatu	3,r4
363	lwz	r4,SL_IBAT3+4(r1)
364	mtibatl	3,r4
365
366BEGIN_MMU_FTR_SECTION
367	lwz	r4,SL_DBAT4(r1)
368	mtspr	SPRN_DBAT4U,r4
369	lwz	r4,SL_DBAT4+4(r1)
370	mtspr	SPRN_DBAT4L,r4
371	lwz	r4,SL_DBAT5(r1)
372	mtspr	SPRN_DBAT5U,r4
373	lwz	r4,SL_DBAT5+4(r1)
374	mtspr	SPRN_DBAT5L,r4
375	lwz	r4,SL_DBAT6(r1)
376	mtspr	SPRN_DBAT6U,r4
377	lwz	r4,SL_DBAT6+4(r1)
378	mtspr	SPRN_DBAT6L,r4
379	lwz	r4,SL_DBAT7(r1)
380	mtspr	SPRN_DBAT7U,r4
381	lwz	r4,SL_DBAT7+4(r1)
382	mtspr	SPRN_DBAT7L,r4
383	lwz	r4,SL_IBAT4(r1)
384	mtspr	SPRN_IBAT4U,r4
385	lwz	r4,SL_IBAT4+4(r1)
386	mtspr	SPRN_IBAT4L,r4
387	lwz	r4,SL_IBAT5(r1)
388	mtspr	SPRN_IBAT5U,r4
389	lwz	r4,SL_IBAT5+4(r1)
390	mtspr	SPRN_IBAT5L,r4
391	lwz	r4,SL_IBAT6(r1)
392	mtspr	SPRN_IBAT6U,r4
393	lwz	r4,SL_IBAT6+4(r1)
394	mtspr	SPRN_IBAT6L,r4
395	lwz	r4,SL_IBAT7(r1)
396	mtspr	SPRN_IBAT7U,r4
397	lwz	r4,SL_IBAT7+4(r1)
398	mtspr	SPRN_IBAT7L,r4
399END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
400
401	/* Flush all TLBs */
402	lis	r4,0x1000
4031:	addic.	r4,r4,-0x1000
404	tlbie	r4
405	blt	1b
406	sync
407
408	/* restore the MSR and turn on the MMU */
409	lwz	r3,SL_MSR(r1)
410	bl	turn_on_mmu
411
412	/* get back the stack pointer */
413	tovirt(r1,r1)
414
415	/* Restore TB */
416	li	r3,0
417	mttbl	r3
418	lwz	r3,SL_TB(r1)
419	lwz	r4,SL_TB+4(r1)
420	mttbu	r3
421	mttbl	r4
422
423	/* Restore the callee-saved registers and return */
424	lwz	r0,SL_CR(r1)
425	mtcr	r0
426	lwz	r2,SL_R2(r1)
427	lmw	r12,SL_R12(r1)
428	addi	r1,r1,SL_SIZE
429	lwz	r0,4(r1)
430	mtlr	r0
431	blr
432
433turn_on_mmu:
434	mflr	r4
435	tovirt(r4,r4)
436	mtsrr0	r4
437	mtsrr1	r3
438	sync
439	isync
440	rfi
441
442#endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */
443
444	.section .data
445	.balign	L1_CACHE_BYTES
446sleep_storage:
447	.long 0
448	.balign	L1_CACHE_BYTES, 0
449
450#endif /* CONFIG_PPC_BOOK3S_32 */
451	.section .text
452