1 /*
2  *  Support for the interrupt controllers found on Power Macintosh,
3  *  currently Apple's "Grand Central" interrupt controller in all
4  *  it's incarnations. OpenPIC support used on newer machines is
5  *  in a separate file
6  *
7  *  Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8  *  Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
9  *                     IBM, Corp.
10  *
11  *  This program is free software; you can redistribute it and/or
12  *  modify it under the terms of the GNU General Public License
13  *  as published by the Free Software Foundation; either version
14  *  2 of the License, or (at your option) any later version.
15  *
16  */
17 
18 #include <linux/stddef.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/adb.h>
26 #include <linux/pmu.h>
27 
28 #include <asm/sections.h>
29 #include <asm/io.h>
30 #include <asm/smp.h>
31 #include <asm/prom.h>
32 #include <asm/pci-bridge.h>
33 #include <asm/time.h>
34 #include <asm/pmac_feature.h>
35 #include <asm/mpic.h>
36 #include <asm/xmon.h>
37 
38 #include "pmac.h"
39 
40 #ifdef CONFIG_PPC32
41 struct pmac_irq_hw {
42         unsigned int    event;
43         unsigned int    enable;
44         unsigned int    ack;
45         unsigned int    level;
46 };
47 
48 /* Workaround flags for 32bit powermac machines */
49 unsigned int of_irq_workarounds;
50 struct device_node *of_irq_dflt_pic;
51 
52 /* Default addresses */
53 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
54 
55 static int max_irqs;
56 static int max_real_irqs;
57 
58 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
59 
60 /* The max irq number this driver deals with is 128; see max_irqs */
61 static DECLARE_BITMAP(ppc_lost_interrupts, 128);
62 static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
63 static int pmac_irq_cascade = -1;
64 static struct irq_domain *pmac_pic_host;
65 
66 static void __pmac_retrigger(unsigned int irq_nr)
67 {
68 	if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
69 		__set_bit(irq_nr, ppc_lost_interrupts);
70 		irq_nr = pmac_irq_cascade;
71 		mb();
72 	}
73 	if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
74 		atomic_inc(&ppc_n_lost_interrupts);
75 		set_dec(1);
76 	}
77 }
78 
79 static void pmac_mask_and_ack_irq(struct irq_data *d)
80 {
81 	unsigned int src = irqd_to_hwirq(d);
82         unsigned long bit = 1UL << (src & 0x1f);
83         int i = src >> 5;
84         unsigned long flags;
85 
86 	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
87         __clear_bit(src, ppc_cached_irq_mask);
88         if (__test_and_clear_bit(src, ppc_lost_interrupts))
89                 atomic_dec(&ppc_n_lost_interrupts);
90         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
91         out_le32(&pmac_irq_hw[i]->ack, bit);
92         do {
93                 /* make sure ack gets to controller before we enable
94                    interrupts */
95                 mb();
96         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
97                 != (ppc_cached_irq_mask[i] & bit));
98 	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
99 }
100 
101 static void pmac_ack_irq(struct irq_data *d)
102 {
103 	unsigned int src = irqd_to_hwirq(d);
104         unsigned long bit = 1UL << (src & 0x1f);
105         int i = src >> 5;
106         unsigned long flags;
107 
108 	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
109 	if (__test_and_clear_bit(src, ppc_lost_interrupts))
110                 atomic_dec(&ppc_n_lost_interrupts);
111         out_le32(&pmac_irq_hw[i]->ack, bit);
112         (void)in_le32(&pmac_irq_hw[i]->ack);
113 	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
114 }
115 
116 static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
117 {
118         unsigned long bit = 1UL << (irq_nr & 0x1f);
119         int i = irq_nr >> 5;
120 
121         if ((unsigned)irq_nr >= max_irqs)
122                 return;
123 
124         /* enable unmasked interrupts */
125         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
126 
127         do {
128                 /* make sure mask gets to controller before we
129                    return to user */
130                 mb();
131         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
132                 != (ppc_cached_irq_mask[i] & bit));
133 
134         /*
135          * Unfortunately, setting the bit in the enable register
136          * when the device interrupt is already on *doesn't* set
137          * the bit in the flag register or request another interrupt.
138          */
139         if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
140 		__pmac_retrigger(irq_nr);
141 }
142 
143 /* When an irq gets requested for the first client, if it's an
144  * edge interrupt, we clear any previous one on the controller
145  */
146 static unsigned int pmac_startup_irq(struct irq_data *d)
147 {
148 	unsigned long flags;
149 	unsigned int src = irqd_to_hwirq(d);
150         unsigned long bit = 1UL << (src & 0x1f);
151         int i = src >> 5;
152 
153 	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
154 	if (!irqd_is_level_type(d))
155 		out_le32(&pmac_irq_hw[i]->ack, bit);
156         __set_bit(src, ppc_cached_irq_mask);
157         __pmac_set_irq_mask(src, 0);
158 	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
159 
160 	return 0;
161 }
162 
163 static void pmac_mask_irq(struct irq_data *d)
164 {
165 	unsigned long flags;
166 	unsigned int src = irqd_to_hwirq(d);
167 
168 	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
169         __clear_bit(src, ppc_cached_irq_mask);
170         __pmac_set_irq_mask(src, 1);
171 	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
172 }
173 
174 static void pmac_unmask_irq(struct irq_data *d)
175 {
176 	unsigned long flags;
177 	unsigned int src = irqd_to_hwirq(d);
178 
179 	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
180 	__set_bit(src, ppc_cached_irq_mask);
181         __pmac_set_irq_mask(src, 0);
182 	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
183 }
184 
185 static int pmac_retrigger(struct irq_data *d)
186 {
187 	unsigned long flags;
188 
189 	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
190 	__pmac_retrigger(irqd_to_hwirq(d));
191 	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
192 	return 1;
193 }
194 
195 static struct irq_chip pmac_pic = {
196 	.name		= "PMAC-PIC",
197 	.irq_startup	= pmac_startup_irq,
198 	.irq_mask	= pmac_mask_irq,
199 	.irq_ack	= pmac_ack_irq,
200 	.irq_mask_ack	= pmac_mask_and_ack_irq,
201 	.irq_unmask	= pmac_unmask_irq,
202 	.irq_retrigger	= pmac_retrigger,
203 };
204 
205 static irqreturn_t gatwick_action(int cpl, void *dev_id)
206 {
207 	unsigned long flags;
208 	int irq, bits;
209 	int rc = IRQ_NONE;
210 
211 	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
212 	for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
213 		int i = irq >> 5;
214 		bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
215 		bits |= in_le32(&pmac_irq_hw[i]->level);
216 		bits &= ppc_cached_irq_mask[i];
217 		if (bits == 0)
218 			continue;
219 		irq += __ilog2(bits);
220 		raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
221 		generic_handle_irq(irq);
222 		raw_spin_lock_irqsave(&pmac_pic_lock, flags);
223 		rc = IRQ_HANDLED;
224 	}
225 	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
226 	return rc;
227 }
228 
229 static unsigned int pmac_pic_get_irq(void)
230 {
231 	int irq;
232 	unsigned long bits = 0;
233 	unsigned long flags;
234 
235 #ifdef CONFIG_PPC_PMAC32_PSURGE
236 	/* IPI's are a hack on the powersurge -- Cort */
237 	if (smp_processor_id() != 0) {
238 		return  psurge_secondary_virq;
239         }
240 #endif /* CONFIG_PPC_PMAC32_PSURGE */
241 	raw_spin_lock_irqsave(&pmac_pic_lock, flags);
242 	for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
243 		int i = irq >> 5;
244 		bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
245 		bits |= in_le32(&pmac_irq_hw[i]->level);
246 		bits &= ppc_cached_irq_mask[i];
247 		if (bits == 0)
248 			continue;
249 		irq += __ilog2(bits);
250 		break;
251 	}
252 	raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
253 	if (unlikely(irq < 0))
254 		return NO_IRQ;
255 	return irq_linear_revmap(pmac_pic_host, irq);
256 }
257 
258 #ifdef CONFIG_XMON
259 static struct irqaction xmon_action = {
260 	.handler	= xmon_irq,
261 	.flags		= 0,
262 	.name		= "NMI - XMON"
263 };
264 #endif
265 
266 static struct irqaction gatwick_cascade_action = {
267 	.handler	= gatwick_action,
268 	.name		= "cascade",
269 };
270 
271 static int pmac_pic_host_match(struct irq_domain *h, struct device_node *node)
272 {
273 	/* We match all, we don't always have a node anyway */
274 	return 1;
275 }
276 
277 static int pmac_pic_host_map(struct irq_domain *h, unsigned int virq,
278 			     irq_hw_number_t hw)
279 {
280 	if (hw >= max_irqs)
281 		return -EINVAL;
282 
283 	/* Mark level interrupts, set delayed disable for edge ones and set
284 	 * handlers
285 	 */
286 	irq_set_status_flags(virq, IRQ_LEVEL);
287 	irq_set_chip_and_handler(virq, &pmac_pic, handle_level_irq);
288 	return 0;
289 }
290 
291 static const struct irq_domain_ops pmac_pic_host_ops = {
292 	.match = pmac_pic_host_match,
293 	.map = pmac_pic_host_map,
294 	.xlate = irq_domain_xlate_onecell,
295 };
296 
297 static void __init pmac_pic_probe_oldstyle(void)
298 {
299         int i;
300         struct device_node *master = NULL;
301 	struct device_node *slave = NULL;
302 	u8 __iomem *addr;
303 	struct resource r;
304 
305 	/* Set our get_irq function */
306 	ppc_md.get_irq = pmac_pic_get_irq;
307 
308 	/*
309 	 * Find the interrupt controller type & node
310 	 */
311 
312 	if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
313 		max_irqs = max_real_irqs = 32;
314 	} else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
315 		max_irqs = max_real_irqs = 32;
316 		/* We might have a second cascaded ohare */
317 		slave = of_find_node_by_name(NULL, "pci106b,7");
318 		if (slave)
319 			max_irqs = 64;
320 	} else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
321 		max_irqs = max_real_irqs = 64;
322 
323 		/* We might have a second cascaded heathrow */
324 		slave = of_find_node_by_name(master, "mac-io");
325 
326 		/* Check ordering of master & slave */
327 		if (of_device_is_compatible(master, "gatwick")) {
328 			struct device_node *tmp;
329 			BUG_ON(slave == NULL);
330 			tmp = master;
331 			master = slave;
332 			slave = tmp;
333 		}
334 
335 		/* We found a slave */
336 		if (slave)
337 			max_irqs = 128;
338 	}
339 	BUG_ON(master == NULL);
340 
341 	/*
342 	 * Allocate an irq host
343 	 */
344 	pmac_pic_host = irq_domain_add_linear(master, max_irqs,
345 					      &pmac_pic_host_ops, NULL);
346 	BUG_ON(pmac_pic_host == NULL);
347 	irq_set_default_host(pmac_pic_host);
348 
349 	/* Get addresses of first controller if we have a node for it */
350 	BUG_ON(of_address_to_resource(master, 0, &r));
351 
352 	/* Map interrupts of primary controller */
353 	addr = (u8 __iomem *) ioremap(r.start, 0x40);
354 	i = 0;
355 	pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
356 		(addr + 0x20);
357 	if (max_real_irqs > 32)
358 		pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
359 			(addr + 0x10);
360 	of_node_put(master);
361 
362 	printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n",
363 	       master->full_name, max_real_irqs);
364 
365 	/* Map interrupts of cascaded controller */
366 	if (slave && !of_address_to_resource(slave, 0, &r)) {
367 		addr = (u8 __iomem *)ioremap(r.start, 0x40);
368 		pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
369 			(addr + 0x20);
370 		if (max_irqs > 64)
371 			pmac_irq_hw[i++] =
372 				(volatile struct pmac_irq_hw __iomem *)
373 				(addr + 0x10);
374 		pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
375 
376 		printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs"
377 		       " cascade: %d\n", slave->full_name,
378 		       max_irqs - max_real_irqs, pmac_irq_cascade);
379 	}
380 	of_node_put(slave);
381 
382 	/* Disable all interrupts in all controllers */
383 	for (i = 0; i * 32 < max_irqs; ++i)
384 		out_le32(&pmac_irq_hw[i]->enable, 0);
385 
386 	/* Hookup cascade irq */
387 	if (slave && pmac_irq_cascade != NO_IRQ)
388 		setup_irq(pmac_irq_cascade, &gatwick_cascade_action);
389 
390 	printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
391 #ifdef CONFIG_XMON
392 	setup_irq(irq_create_mapping(NULL, 20), &xmon_action);
393 #endif
394 }
395 
396 int of_irq_parse_oldworld(struct device_node *device, int index,
397 			struct of_phandle_args *out_irq)
398 {
399 	const u32 *ints = NULL;
400 	int intlen;
401 
402 	/*
403 	 * Old machines just have a list of interrupt numbers
404 	 * and no interrupt-controller nodes. We also have dodgy
405 	 * cases where the APPL,interrupts property is completely
406 	 * missing behind pci-pci bridges and we have to get it
407 	 * from the parent (the bridge itself, as apple just wired
408 	 * everything together on these)
409 	 */
410 	while (device) {
411 		ints = of_get_property(device, "AAPL,interrupts", &intlen);
412 		if (ints != NULL)
413 			break;
414 		device = device->parent;
415 		if (device && strcmp(device->type, "pci") != 0)
416 			break;
417 	}
418 	if (ints == NULL)
419 		return -EINVAL;
420 	intlen /= sizeof(u32);
421 
422 	if (index >= intlen)
423 		return -EINVAL;
424 
425 	out_irq->np = NULL;
426 	out_irq->args[0] = ints[index];
427 	out_irq->args_count = 1;
428 
429 	return 0;
430 }
431 #endif /* CONFIG_PPC32 */
432 
433 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
434 {
435 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
436 	struct device_node* pswitch;
437 	int nmi_irq;
438 
439 	pswitch = of_find_node_by_name(NULL, "programmer-switch");
440 	if (pswitch) {
441 		nmi_irq = irq_of_parse_and_map(pswitch, 0);
442 		if (nmi_irq != NO_IRQ) {
443 			mpic_irq_set_priority(nmi_irq, 9);
444 			setup_irq(nmi_irq, &xmon_action);
445 		}
446 		of_node_put(pswitch);
447 	}
448 #endif	/* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
449 }
450 
451 static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
452 						int master)
453 {
454 	const char *name = master ? " MPIC 1   " : " MPIC 2   ";
455 	struct mpic *mpic;
456 	unsigned int flags = master ? 0 : MPIC_SECONDARY;
457 
458 	pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
459 
460 	if (of_get_property(np, "big-endian", NULL))
461 		flags |= MPIC_BIG_ENDIAN;
462 
463 	/* Primary Big Endian means HT interrupts. This is quite dodgy
464 	 * but works until I find a better way
465 	 */
466 	if (master && (flags & MPIC_BIG_ENDIAN))
467 		flags |= MPIC_U3_HT_IRQS;
468 
469 	mpic = mpic_alloc(np, 0, flags, 0, 0, name);
470 	if (mpic == NULL)
471 		return NULL;
472 
473 	mpic_init(mpic);
474 
475 	return mpic;
476  }
477 
478 static int __init pmac_pic_probe_mpic(void)
479 {
480 	struct mpic *mpic1, *mpic2;
481 	struct device_node *np, *master = NULL, *slave = NULL;
482 
483 	/* We can have up to 2 MPICs cascaded */
484 	for (np = NULL; (np = of_find_node_by_type(np, "open-pic"))
485 		     != NULL;) {
486 		if (master == NULL &&
487 		    of_get_property(np, "interrupts", NULL) == NULL)
488 			master = of_node_get(np);
489 		else if (slave == NULL)
490 			slave = of_node_get(np);
491 		if (master && slave)
492 			break;
493 	}
494 
495 	/* Check for bogus setups */
496 	if (master == NULL && slave != NULL) {
497 		master = slave;
498 		slave = NULL;
499 	}
500 
501 	/* Not found, default to good old pmac pic */
502 	if (master == NULL)
503 		return -ENODEV;
504 
505 	/* Set master handler */
506 	ppc_md.get_irq = mpic_get_irq;
507 
508 	/* Setup master */
509 	mpic1 = pmac_setup_one_mpic(master, 1);
510 	BUG_ON(mpic1 == NULL);
511 
512 	/* Install NMI if any */
513 	pmac_pic_setup_mpic_nmi(mpic1);
514 
515 	of_node_put(master);
516 
517 	/* Set up a cascaded controller, if present */
518 	if (slave) {
519 		mpic2 = pmac_setup_one_mpic(slave, 0);
520 		if (mpic2 == NULL)
521 			printk(KERN_ERR "Failed to setup slave MPIC\n");
522 		of_node_put(slave);
523 	}
524 
525 	return 0;
526 }
527 
528 
529 void __init pmac_pic_init(void)
530 {
531 	/* We configure the OF parsing based on our oldworld vs. newworld
532 	 * platform type and whether we were booted by BootX.
533 	 */
534 #ifdef CONFIG_PPC32
535 	if (!pmac_newworld)
536 		of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
537 	if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
538 		of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
539 
540 	/* If we don't have phandles on a newworld, then try to locate a
541 	 * default interrupt controller (happens when booting with BootX).
542 	 * We do a first match here, hopefully, that only ever happens on
543 	 * machines with one controller.
544 	 */
545 	if (pmac_newworld && (of_irq_workarounds & OF_IMAP_NO_PHANDLE)) {
546 		struct device_node *np;
547 
548 		for_each_node_with_property(np, "interrupt-controller") {
549 			/* Skip /chosen/interrupt-controller */
550 			if (strcmp(np->name, "chosen") == 0)
551 				continue;
552 			/* It seems like at least one person wants
553 			 * to use BootX on a machine with an AppleKiwi
554 			 * controller which happens to pretend to be an
555 			 * interrupt controller too. */
556 			if (strcmp(np->name, "AppleKiwi") == 0)
557 				continue;
558 			/* I think we found one ! */
559 			of_irq_dflt_pic = np;
560 			break;
561 		}
562 	}
563 #endif /* CONFIG_PPC32 */
564 
565 	/* We first try to detect Apple's new Core99 chipset, since mac-io
566 	 * is quite different on those machines and contains an IBM MPIC2.
567 	 */
568 	if (pmac_pic_probe_mpic() == 0)
569 		return;
570 
571 #ifdef CONFIG_PPC32
572 	pmac_pic_probe_oldstyle();
573 #endif
574 }
575 
576 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
577 /*
578  * These procedures are used in implementing sleep on the powerbooks.
579  * sleep_save_intrs() saves the states of all interrupt enables
580  * and disables all interrupts except for the nominated one.
581  * sleep_restore_intrs() restores the states of all interrupt enables.
582  */
583 unsigned long sleep_save_mask[2];
584 
585 /* This used to be passed by the PMU driver but that link got
586  * broken with the new driver model. We use this tweak for now...
587  * We really want to do things differently though...
588  */
589 static int pmacpic_find_viaint(void)
590 {
591 	int viaint = -1;
592 
593 #ifdef CONFIG_ADB_PMU
594 	struct device_node *np;
595 
596 	if (pmu_get_model() != PMU_OHARE_BASED)
597 		goto not_found;
598 	np = of_find_node_by_name(NULL, "via-pmu");
599 	if (np == NULL)
600 		goto not_found;
601 	viaint = irq_of_parse_and_map(np, 0);
602 
603 not_found:
604 #endif /* CONFIG_ADB_PMU */
605 	return viaint;
606 }
607 
608 static int pmacpic_suspend(void)
609 {
610 	int viaint = pmacpic_find_viaint();
611 
612 	sleep_save_mask[0] = ppc_cached_irq_mask[0];
613 	sleep_save_mask[1] = ppc_cached_irq_mask[1];
614 	ppc_cached_irq_mask[0] = 0;
615 	ppc_cached_irq_mask[1] = 0;
616 	if (viaint > 0)
617 		set_bit(viaint, ppc_cached_irq_mask);
618 	out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
619 	if (max_real_irqs > 32)
620 		out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
621 	(void)in_le32(&pmac_irq_hw[0]->event);
622 	/* make sure mask gets to controller before we return to caller */
623 	mb();
624         (void)in_le32(&pmac_irq_hw[0]->enable);
625 
626         return 0;
627 }
628 
629 static void pmacpic_resume(void)
630 {
631 	int i;
632 
633 	out_le32(&pmac_irq_hw[0]->enable, 0);
634 	if (max_real_irqs > 32)
635 		out_le32(&pmac_irq_hw[1]->enable, 0);
636 	mb();
637 	for (i = 0; i < max_real_irqs; ++i)
638 		if (test_bit(i, sleep_save_mask))
639 			pmac_unmask_irq(irq_get_irq_data(i));
640 }
641 
642 static struct syscore_ops pmacpic_syscore_ops = {
643 	.suspend	= pmacpic_suspend,
644 	.resume		= pmacpic_resume,
645 };
646 
647 static int __init init_pmacpic_syscore(void)
648 {
649 	if (pmac_irq_hw[0])
650 		register_syscore_ops(&pmacpic_syscore_ops);
651 	return 0;
652 }
653 
654 machine_subsys_initcall(powermac, init_pmacpic_syscore);
655 
656 #endif /* CONFIG_PM && CONFIG_PPC32 */
657