1 /*
2  *  Support for the interrupt controllers found on Power Macintosh,
3  *  currently Apple's "Grand Central" interrupt controller in all
4  *  it's incarnations. OpenPIC support used on newer machines is
5  *  in a separate file
6  *
7  *  Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
8  *  Copyright (C) 2005 Benjamin Herrenschmidt (benh@kernel.crashing.org)
9  *                     IBM, Corp.
10  *
11  *  This program is free software; you can redistribute it and/or
12  *  modify it under the terms of the GNU General Public License
13  *  as published by the Free Software Foundation; either version
14  *  2 of the License, or (at your option) any later version.
15  *
16  */
17 
18 #include <linux/stddef.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/pci.h>
23 #include <linux/interrupt.h>
24 #include <linux/sysdev.h>
25 #include <linux/adb.h>
26 #include <linux/pmu.h>
27 #include <linux/module.h>
28 
29 #include <asm/sections.h>
30 #include <asm/io.h>
31 #include <asm/smp.h>
32 #include <asm/prom.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/time.h>
35 #include <asm/pmac_feature.h>
36 #include <asm/mpic.h>
37 #include <asm/xmon.h>
38 
39 #include "pmac.h"
40 
41 #ifdef CONFIG_PPC32
42 struct pmac_irq_hw {
43         unsigned int    event;
44         unsigned int    enable;
45         unsigned int    ack;
46         unsigned int    level;
47 };
48 
49 /* Default addresses */
50 static volatile struct pmac_irq_hw __iomem *pmac_irq_hw[4];
51 
52 #define GC_LEVEL_MASK		0x3ff00000
53 #define OHARE_LEVEL_MASK	0x1ff00000
54 #define HEATHROW_LEVEL_MASK	0x1ff00000
55 
56 static int max_irqs;
57 static int max_real_irqs;
58 static u32 level_mask[4];
59 
60 static DEFINE_SPINLOCK(pmac_pic_lock);
61 
62 #define NR_MASK_WORDS	((NR_IRQS + 31) / 32)
63 static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
64 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
65 static int pmac_irq_cascade = -1;
66 static struct irq_host *pmac_pic_host;
67 
68 static void __pmac_retrigger(unsigned int irq_nr)
69 {
70 	if (irq_nr >= max_real_irqs && pmac_irq_cascade > 0) {
71 		__set_bit(irq_nr, ppc_lost_interrupts);
72 		irq_nr = pmac_irq_cascade;
73 		mb();
74 	}
75 	if (!__test_and_set_bit(irq_nr, ppc_lost_interrupts)) {
76 		atomic_inc(&ppc_n_lost_interrupts);
77 		set_dec(1);
78 	}
79 }
80 
81 static void pmac_mask_and_ack_irq(unsigned int virq)
82 {
83 	unsigned int src = irq_map[virq].hwirq;
84         unsigned long bit = 1UL << (src & 0x1f);
85         int i = src >> 5;
86         unsigned long flags;
87 
88 	spin_lock_irqsave(&pmac_pic_lock, flags);
89         __clear_bit(src, ppc_cached_irq_mask);
90         if (__test_and_clear_bit(src, ppc_lost_interrupts))
91                 atomic_dec(&ppc_n_lost_interrupts);
92         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
93         out_le32(&pmac_irq_hw[i]->ack, bit);
94         do {
95                 /* make sure ack gets to controller before we enable
96                    interrupts */
97                 mb();
98         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
99                 != (ppc_cached_irq_mask[i] & bit));
100 	spin_unlock_irqrestore(&pmac_pic_lock, flags);
101 }
102 
103 static void pmac_ack_irq(unsigned int virq)
104 {
105 	unsigned int src = irq_map[virq].hwirq;
106         unsigned long bit = 1UL << (src & 0x1f);
107         int i = src >> 5;
108         unsigned long flags;
109 
110   	spin_lock_irqsave(&pmac_pic_lock, flags);
111 	if (__test_and_clear_bit(src, ppc_lost_interrupts))
112                 atomic_dec(&ppc_n_lost_interrupts);
113         out_le32(&pmac_irq_hw[i]->ack, bit);
114         (void)in_le32(&pmac_irq_hw[i]->ack);
115 	spin_unlock_irqrestore(&pmac_pic_lock, flags);
116 }
117 
118 static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
119 {
120         unsigned long bit = 1UL << (irq_nr & 0x1f);
121         int i = irq_nr >> 5;
122 
123         if ((unsigned)irq_nr >= max_irqs)
124                 return;
125 
126         /* enable unmasked interrupts */
127         out_le32(&pmac_irq_hw[i]->enable, ppc_cached_irq_mask[i]);
128 
129         do {
130                 /* make sure mask gets to controller before we
131                    return to user */
132                 mb();
133         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
134                 != (ppc_cached_irq_mask[i] & bit));
135 
136         /*
137          * Unfortunately, setting the bit in the enable register
138          * when the device interrupt is already on *doesn't* set
139          * the bit in the flag register or request another interrupt.
140          */
141         if (bit & ppc_cached_irq_mask[i] & in_le32(&pmac_irq_hw[i]->level))
142 		__pmac_retrigger(irq_nr);
143 }
144 
145 /* When an irq gets requested for the first client, if it's an
146  * edge interrupt, we clear any previous one on the controller
147  */
148 static unsigned int pmac_startup_irq(unsigned int virq)
149 {
150 	unsigned long flags;
151 	unsigned int src = irq_map[virq].hwirq;
152         unsigned long bit = 1UL << (src & 0x1f);
153         int i = src >> 5;
154 
155   	spin_lock_irqsave(&pmac_pic_lock, flags);
156 	if ((irq_desc[virq].status & IRQ_LEVEL) == 0)
157 		out_le32(&pmac_irq_hw[i]->ack, bit);
158         __set_bit(src, ppc_cached_irq_mask);
159         __pmac_set_irq_mask(src, 0);
160   	spin_unlock_irqrestore(&pmac_pic_lock, flags);
161 
162 	return 0;
163 }
164 
165 static void pmac_mask_irq(unsigned int virq)
166 {
167 	unsigned long flags;
168 	unsigned int src = irq_map[virq].hwirq;
169 
170   	spin_lock_irqsave(&pmac_pic_lock, flags);
171         __clear_bit(src, ppc_cached_irq_mask);
172         __pmac_set_irq_mask(src, 1);
173   	spin_unlock_irqrestore(&pmac_pic_lock, flags);
174 }
175 
176 static void pmac_unmask_irq(unsigned int virq)
177 {
178 	unsigned long flags;
179 	unsigned int src = irq_map[virq].hwirq;
180 
181 	spin_lock_irqsave(&pmac_pic_lock, flags);
182 	__set_bit(src, ppc_cached_irq_mask);
183         __pmac_set_irq_mask(src, 0);
184   	spin_unlock_irqrestore(&pmac_pic_lock, flags);
185 }
186 
187 static int pmac_retrigger(unsigned int virq)
188 {
189 	unsigned long flags;
190 
191   	spin_lock_irqsave(&pmac_pic_lock, flags);
192 	__pmac_retrigger(irq_map[virq].hwirq);
193   	spin_unlock_irqrestore(&pmac_pic_lock, flags);
194 	return 1;
195 }
196 
197 static struct irq_chip pmac_pic = {
198 	.typename	= " PMAC-PIC ",
199 	.startup	= pmac_startup_irq,
200 	.mask		= pmac_mask_irq,
201 	.ack		= pmac_ack_irq,
202 	.mask_ack	= pmac_mask_and_ack_irq,
203 	.unmask		= pmac_unmask_irq,
204 	.retrigger	= pmac_retrigger,
205 };
206 
207 static irqreturn_t gatwick_action(int cpl, void *dev_id)
208 {
209 	unsigned long flags;
210 	int irq, bits;
211 	int rc = IRQ_NONE;
212 
213   	spin_lock_irqsave(&pmac_pic_lock, flags);
214 	for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
215 		int i = irq >> 5;
216 		bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
217 		/* We must read level interrupts from the level register */
218 		bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
219 		bits &= ppc_cached_irq_mask[i];
220 		if (bits == 0)
221 			continue;
222 		irq += __ilog2(bits);
223 		spin_unlock_irqrestore(&pmac_pic_lock, flags);
224 		__do_IRQ(irq);
225 		spin_lock_irqsave(&pmac_pic_lock, flags);
226 		rc = IRQ_HANDLED;
227 	}
228   	spin_unlock_irqrestore(&pmac_pic_lock, flags);
229 	return rc;
230 }
231 
232 static unsigned int pmac_pic_get_irq(void)
233 {
234 	int irq;
235 	unsigned long bits = 0;
236 	unsigned long flags;
237 
238 #ifdef CONFIG_SMP
239 	void psurge_smp_message_recv(void);
240 
241        	/* IPI's are a hack on the powersurge -- Cort */
242        	if ( smp_processor_id() != 0 ) {
243 		psurge_smp_message_recv();
244 		return NO_IRQ_IGNORE;	/* ignore, already handled */
245         }
246 #endif /* CONFIG_SMP */
247   	spin_lock_irqsave(&pmac_pic_lock, flags);
248 	for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
249 		int i = irq >> 5;
250 		bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
251 		/* We must read level interrupts from the level register */
252 		bits |= (in_le32(&pmac_irq_hw[i]->level) & level_mask[i]);
253 		bits &= ppc_cached_irq_mask[i];
254 		if (bits == 0)
255 			continue;
256 		irq += __ilog2(bits);
257 		break;
258 	}
259   	spin_unlock_irqrestore(&pmac_pic_lock, flags);
260 	if (unlikely(irq < 0))
261 		return NO_IRQ;
262 	return irq_linear_revmap(pmac_pic_host, irq);
263 }
264 
265 #ifdef CONFIG_XMON
266 static struct irqaction xmon_action = {
267 	.handler	= xmon_irq,
268 	.flags		= 0,
269 	.mask		= CPU_MASK_NONE,
270 	.name		= "NMI - XMON"
271 };
272 #endif
273 
274 static struct irqaction gatwick_cascade_action = {
275 	.handler	= gatwick_action,
276 	.flags		= IRQF_DISABLED,
277 	.mask		= CPU_MASK_NONE,
278 	.name		= "cascade",
279 };
280 
281 static int pmac_pic_host_match(struct irq_host *h, struct device_node *node)
282 {
283 	/* We match all, we don't always have a node anyway */
284 	return 1;
285 }
286 
287 static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
288 			     irq_hw_number_t hw)
289 {
290 	struct irq_desc *desc = get_irq_desc(virq);
291 	int level;
292 
293 	if (hw >= max_irqs)
294 		return -EINVAL;
295 
296 	/* Mark level interrupts, set delayed disable for edge ones and set
297 	 * handlers
298 	 */
299 	level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f)));
300 	if (level)
301 		desc->status |= IRQ_LEVEL;
302 	set_irq_chip_and_handler(virq, &pmac_pic, level ?
303 				 handle_level_irq : handle_edge_irq);
304 	return 0;
305 }
306 
307 static int pmac_pic_host_xlate(struct irq_host *h, struct device_node *ct,
308 			       u32 *intspec, unsigned int intsize,
309 			       irq_hw_number_t *out_hwirq,
310 			       unsigned int *out_flags)
311 
312 {
313 	*out_flags = IRQ_TYPE_NONE;
314 	*out_hwirq = *intspec;
315 	return 0;
316 }
317 
318 static struct irq_host_ops pmac_pic_host_ops = {
319 	.match = pmac_pic_host_match,
320 	.map = pmac_pic_host_map,
321 	.xlate = pmac_pic_host_xlate,
322 };
323 
324 static void __init pmac_pic_probe_oldstyle(void)
325 {
326         int i;
327         struct device_node *master = NULL;
328 	struct device_node *slave = NULL;
329 	u8 __iomem *addr;
330 	struct resource r;
331 
332 	/* Set our get_irq function */
333 	ppc_md.get_irq = pmac_pic_get_irq;
334 
335 	/*
336 	 * Find the interrupt controller type & node
337 	 */
338 
339 	if ((master = of_find_node_by_name(NULL, "gc")) != NULL) {
340 		max_irqs = max_real_irqs = 32;
341 		level_mask[0] = GC_LEVEL_MASK;
342 	} else if ((master = of_find_node_by_name(NULL, "ohare")) != NULL) {
343 		max_irqs = max_real_irqs = 32;
344 		level_mask[0] = OHARE_LEVEL_MASK;
345 
346 		/* We might have a second cascaded ohare */
347 		slave = of_find_node_by_name(NULL, "pci106b,7");
348 		if (slave) {
349 			max_irqs = 64;
350 			level_mask[1] = OHARE_LEVEL_MASK;
351 		}
352 	} else if ((master = of_find_node_by_name(NULL, "mac-io")) != NULL) {
353 		max_irqs = max_real_irqs = 64;
354 		level_mask[0] = HEATHROW_LEVEL_MASK;
355 		level_mask[1] = 0;
356 
357 		/* We might have a second cascaded heathrow */
358 		slave = of_find_node_by_name(master, "mac-io");
359 
360 		/* Check ordering of master & slave */
361 		if (of_device_is_compatible(master, "gatwick")) {
362 			struct device_node *tmp;
363 			BUG_ON(slave == NULL);
364 			tmp = master;
365 			master = slave;
366 			slave = tmp;
367 		}
368 
369 		/* We found a slave */
370 		if (slave) {
371 			max_irqs = 128;
372 			level_mask[2] = HEATHROW_LEVEL_MASK;
373 			level_mask[3] = 0;
374 		}
375 	}
376 	BUG_ON(master == NULL);
377 
378 	/*
379 	 * Allocate an irq host
380 	 */
381 	pmac_pic_host = irq_alloc_host(master, IRQ_HOST_MAP_LINEAR, max_irqs,
382 				       &pmac_pic_host_ops,
383 				       max_irqs);
384 	BUG_ON(pmac_pic_host == NULL);
385 	irq_set_default_host(pmac_pic_host);
386 
387 	/* Get addresses of first controller if we have a node for it */
388 	BUG_ON(of_address_to_resource(master, 0, &r));
389 
390 	/* Map interrupts of primary controller */
391 	addr = (u8 __iomem *) ioremap(r.start, 0x40);
392 	i = 0;
393 	pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
394 		(addr + 0x20);
395 	if (max_real_irqs > 32)
396 		pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
397 			(addr + 0x10);
398 	of_node_put(master);
399 
400 	printk(KERN_INFO "irq: Found primary Apple PIC %s for %d irqs\n",
401 	       master->full_name, max_real_irqs);
402 
403 	/* Map interrupts of cascaded controller */
404 	if (slave && !of_address_to_resource(slave, 0, &r)) {
405 		addr = (u8 __iomem *)ioremap(r.start, 0x40);
406 		pmac_irq_hw[i++] = (volatile struct pmac_irq_hw __iomem *)
407 			(addr + 0x20);
408 		if (max_irqs > 64)
409 			pmac_irq_hw[i++] =
410 				(volatile struct pmac_irq_hw __iomem *)
411 				(addr + 0x10);
412 		pmac_irq_cascade = irq_of_parse_and_map(slave, 0);
413 
414 		printk(KERN_INFO "irq: Found slave Apple PIC %s for %d irqs"
415 		       " cascade: %d\n", slave->full_name,
416 		       max_irqs - max_real_irqs, pmac_irq_cascade);
417 	}
418 	of_node_put(slave);
419 
420 	/* Disable all interrupts in all controllers */
421 	for (i = 0; i * 32 < max_irqs; ++i)
422 		out_le32(&pmac_irq_hw[i]->enable, 0);
423 
424 	/* Hookup cascade irq */
425 	if (slave && pmac_irq_cascade != NO_IRQ)
426 		setup_irq(pmac_irq_cascade, &gatwick_cascade_action);
427 
428 	printk(KERN_INFO "irq: System has %d possible interrupts\n", max_irqs);
429 #ifdef CONFIG_XMON
430 	setup_irq(irq_create_mapping(NULL, 20), &xmon_action);
431 #endif
432 }
433 #endif /* CONFIG_PPC32 */
434 
435 static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc)
436 {
437 	struct mpic *mpic = desc->handler_data;
438 
439 	unsigned int cascade_irq = mpic_get_one_irq(mpic);
440 	if (cascade_irq != NO_IRQ)
441 		generic_handle_irq(cascade_irq);
442 	desc->chip->eoi(irq);
443 }
444 
445 static void __init pmac_pic_setup_mpic_nmi(struct mpic *mpic)
446 {
447 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
448 	struct device_node* pswitch;
449 	int nmi_irq;
450 
451 	pswitch = of_find_node_by_name(NULL, "programmer-switch");
452 	if (pswitch) {
453 		nmi_irq = irq_of_parse_and_map(pswitch, 0);
454 		if (nmi_irq != NO_IRQ) {
455 			mpic_irq_set_priority(nmi_irq, 9);
456 			setup_irq(nmi_irq, &xmon_action);
457 		}
458 		of_node_put(pswitch);
459 	}
460 #endif	/* defined(CONFIG_XMON) && defined(CONFIG_PPC32) */
461 }
462 
463 static struct mpic * __init pmac_setup_one_mpic(struct device_node *np,
464 						int master)
465 {
466 	const char *name = master ? " MPIC 1   " : " MPIC 2   ";
467 	struct resource r;
468 	struct mpic *mpic;
469 	unsigned int flags = master ? MPIC_PRIMARY : 0;
470 	int rc;
471 
472 	rc = of_address_to_resource(np, 0, &r);
473 	if (rc)
474 		return NULL;
475 
476 	pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
477 
478 	flags |= MPIC_WANTS_RESET;
479 	if (of_get_property(np, "big-endian", NULL))
480 		flags |= MPIC_BIG_ENDIAN;
481 
482 	/* Primary Big Endian means HT interrupts. This is quite dodgy
483 	 * but works until I find a better way
484 	 */
485 	if (master && (flags & MPIC_BIG_ENDIAN))
486 		flags |= MPIC_U3_HT_IRQS;
487 
488 	mpic = mpic_alloc(np, r.start, flags, 0, 0, name);
489 	if (mpic == NULL)
490 		return NULL;
491 
492 	mpic_init(mpic);
493 
494 	return mpic;
495  }
496 
497 static int __init pmac_pic_probe_mpic(void)
498 {
499 	struct mpic *mpic1, *mpic2;
500 	struct device_node *np, *master = NULL, *slave = NULL;
501 	unsigned int cascade;
502 
503 	/* We can have up to 2 MPICs cascaded */
504 	for (np = NULL; (np = of_find_node_by_type(np, "open-pic"))
505 		     != NULL;) {
506 		if (master == NULL &&
507 		    of_get_property(np, "interrupts", NULL) == NULL)
508 			master = of_node_get(np);
509 		else if (slave == NULL)
510 			slave = of_node_get(np);
511 		if (master && slave)
512 			break;
513 	}
514 
515 	/* Check for bogus setups */
516 	if (master == NULL && slave != NULL) {
517 		master = slave;
518 		slave = NULL;
519 	}
520 
521 	/* Not found, default to good old pmac pic */
522 	if (master == NULL)
523 		return -ENODEV;
524 
525 	/* Set master handler */
526 	ppc_md.get_irq = mpic_get_irq;
527 
528 	/* Setup master */
529 	mpic1 = pmac_setup_one_mpic(master, 1);
530 	BUG_ON(mpic1 == NULL);
531 
532 	/* Install NMI if any */
533 	pmac_pic_setup_mpic_nmi(mpic1);
534 
535 	of_node_put(master);
536 
537 	/* No slave, let's go out */
538 	if (slave == NULL)
539 		return 0;
540 
541 	/* Get/Map slave interrupt */
542 	cascade = irq_of_parse_and_map(slave, 0);
543 	if (cascade == NO_IRQ) {
544 		printk(KERN_ERR "Failed to map cascade IRQ\n");
545 		return 0;
546 	}
547 
548 	mpic2 = pmac_setup_one_mpic(slave, 0);
549 	if (mpic2 == NULL) {
550 		printk(KERN_ERR "Failed to setup slave MPIC\n");
551 		of_node_put(slave);
552 		return 0;
553 	}
554 	set_irq_data(cascade, mpic2);
555 	set_irq_chained_handler(cascade, pmac_u3_cascade);
556 
557 	of_node_put(slave);
558 	return 0;
559 }
560 
561 
562 void __init pmac_pic_init(void)
563 {
564 	unsigned int flags = 0;
565 
566 	/* We configure the OF parsing based on our oldworld vs. newworld
567 	 * platform type and wether we were booted by BootX.
568 	 */
569 #ifdef CONFIG_PPC32
570 	if (!pmac_newworld)
571 		flags |= OF_IMAP_OLDWORLD_MAC;
572 	if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
573 		flags |= OF_IMAP_NO_PHANDLE;
574 #endif /* CONFIG_PPC_32 */
575 
576 	of_irq_map_init(flags);
577 
578 	/* We first try to detect Apple's new Core99 chipset, since mac-io
579 	 * is quite different on those machines and contains an IBM MPIC2.
580 	 */
581 	if (pmac_pic_probe_mpic() == 0)
582 		return;
583 
584 #ifdef CONFIG_PPC32
585 	pmac_pic_probe_oldstyle();
586 #endif
587 }
588 
589 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
590 /*
591  * These procedures are used in implementing sleep on the powerbooks.
592  * sleep_save_intrs() saves the states of all interrupt enables
593  * and disables all interrupts except for the nominated one.
594  * sleep_restore_intrs() restores the states of all interrupt enables.
595  */
596 unsigned long sleep_save_mask[2];
597 
598 /* This used to be passed by the PMU driver but that link got
599  * broken with the new driver model. We use this tweak for now...
600  * We really want to do things differently though...
601  */
602 static int pmacpic_find_viaint(void)
603 {
604 	int viaint = -1;
605 
606 #ifdef CONFIG_ADB_PMU
607 	struct device_node *np;
608 
609 	if (pmu_get_model() != PMU_OHARE_BASED)
610 		goto not_found;
611 	np = of_find_node_by_name(NULL, "via-pmu");
612 	if (np == NULL)
613 		goto not_found;
614 	viaint = irq_of_parse_and_map(np, 0);;
615 
616 not_found:
617 #endif /* CONFIG_ADB_PMU */
618 	return viaint;
619 }
620 
621 static int pmacpic_suspend(struct sys_device *sysdev, pm_message_t state)
622 {
623 	int viaint = pmacpic_find_viaint();
624 
625 	sleep_save_mask[0] = ppc_cached_irq_mask[0];
626 	sleep_save_mask[1] = ppc_cached_irq_mask[1];
627 	ppc_cached_irq_mask[0] = 0;
628 	ppc_cached_irq_mask[1] = 0;
629 	if (viaint > 0)
630 		set_bit(viaint, ppc_cached_irq_mask);
631 	out_le32(&pmac_irq_hw[0]->enable, ppc_cached_irq_mask[0]);
632 	if (max_real_irqs > 32)
633 		out_le32(&pmac_irq_hw[1]->enable, ppc_cached_irq_mask[1]);
634 	(void)in_le32(&pmac_irq_hw[0]->event);
635 	/* make sure mask gets to controller before we return to caller */
636 	mb();
637         (void)in_le32(&pmac_irq_hw[0]->enable);
638 
639         return 0;
640 }
641 
642 static int pmacpic_resume(struct sys_device *sysdev)
643 {
644 	int i;
645 
646 	out_le32(&pmac_irq_hw[0]->enable, 0);
647 	if (max_real_irqs > 32)
648 		out_le32(&pmac_irq_hw[1]->enable, 0);
649 	mb();
650 	for (i = 0; i < max_real_irqs; ++i)
651 		if (test_bit(i, sleep_save_mask))
652 			pmac_unmask_irq(i);
653 
654 	return 0;
655 }
656 
657 #endif /* CONFIG_PM && CONFIG_PPC32 */
658 
659 static struct sysdev_class pmacpic_sysclass = {
660 	.name = "pmac_pic",
661 };
662 
663 static struct sys_device device_pmacpic = {
664 	.id		= 0,
665 	.cls		= &pmacpic_sysclass,
666 };
667 
668 static struct sysdev_driver driver_pmacpic = {
669 #if defined(CONFIG_PM) && defined(CONFIG_PPC32)
670 	.suspend	= &pmacpic_suspend,
671 	.resume		= &pmacpic_resume,
672 #endif /* CONFIG_PM && CONFIG_PPC32 */
673 };
674 
675 static int __init init_pmacpic_sysfs(void)
676 {
677 #ifdef CONFIG_PPC32
678 	if (max_irqs == 0)
679 		return -ENODEV;
680 #endif
681 	printk(KERN_DEBUG "Registering pmac pic with sysfs...\n");
682 	sysdev_class_register(&pmacpic_sysclass);
683 	sysdev_register(&device_pmacpic);
684 	sysdev_driver_register(&pmacpic_sysclass, &driver_pmacpic);
685 	return 0;
686 }
687 machine_subsys_initcall(powermac, init_pmacpic_sysfs);
688 
689