1 /* 2 * Support for PCI bridges found on Power Macintoshes. 3 * 4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org) 5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/delay.h> 16 #include <linux/string.h> 17 #include <linux/init.h> 18 #include <linux/bootmem.h> 19 #include <linux/irq.h> 20 21 #include <asm/sections.h> 22 #include <asm/io.h> 23 #include <asm/prom.h> 24 #include <asm/pci-bridge.h> 25 #include <asm/machdep.h> 26 #include <asm/pmac_feature.h> 27 #include <asm/grackle.h> 28 #include <asm/ppc-pci.h> 29 30 #undef DEBUG 31 32 #ifdef DEBUG 33 #define DBG(x...) printk(x) 34 #else 35 #define DBG(x...) 36 #endif 37 38 /* XXX Could be per-controller, but I don't think we risk anything by 39 * assuming we won't have both UniNorth and Bandit */ 40 static int has_uninorth; 41 #ifdef CONFIG_PPC64 42 static struct pci_controller *u3_agp; 43 static struct pci_controller *u4_pcie; 44 static struct pci_controller *u3_ht; 45 #else 46 static int has_second_ohare; 47 #endif /* CONFIG_PPC64 */ 48 49 extern int pcibios_assign_bus_offset; 50 51 struct device_node *k2_skiplist[2]; 52 53 /* 54 * Magic constants for enabling cache coherency in the bandit/PSX bridge. 55 */ 56 #define BANDIT_DEVID_2 8 57 #define BANDIT_REVID 3 58 59 #define BANDIT_DEVNUM 11 60 #define BANDIT_MAGIC 0x50 61 #define BANDIT_COHERENT 0x40 62 63 static int __init fixup_one_level_bus_range(struct device_node *node, int higher) 64 { 65 for (; node != 0;node = node->sibling) { 66 const int * bus_range; 67 const unsigned int *class_code; 68 int len; 69 70 /* For PCI<->PCI bridges or CardBus bridges, we go down */ 71 class_code = of_get_property(node, "class-code", NULL); 72 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 73 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) 74 continue; 75 bus_range = of_get_property(node, "bus-range", &len); 76 if (bus_range != NULL && len > 2 * sizeof(int)) { 77 if (bus_range[1] > higher) 78 higher = bus_range[1]; 79 } 80 higher = fixup_one_level_bus_range(node->child, higher); 81 } 82 return higher; 83 } 84 85 /* This routine fixes the "bus-range" property of all bridges in the 86 * system since they tend to have their "last" member wrong on macs 87 * 88 * Note that the bus numbers manipulated here are OF bus numbers, they 89 * are not Linux bus numbers. 90 */ 91 static void __init fixup_bus_range(struct device_node *bridge) 92 { 93 int *bus_range, len; 94 struct property *prop; 95 96 /* Lookup the "bus-range" property for the hose */ 97 prop = of_find_property(bridge, "bus-range", &len); 98 if (prop == NULL || prop->length < 2 * sizeof(int)) 99 return; 100 101 bus_range = prop->value; 102 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); 103 } 104 105 /* 106 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. 107 * 108 * The "Bandit" version is present in all early PCI PowerMacs, 109 * and up to the first ones using Grackle. Some machines may 110 * have 2 bandit controllers (2 PCI busses). 111 * 112 * "Chaos" is used in some "Bandit"-type machines as a bridge 113 * for the separate display bus. It is accessed the same 114 * way as bandit, but cannot be probed for devices. It therefore 115 * has its own config access functions. 116 * 117 * The "UniNorth" version is present in all Core99 machines 118 * (iBook, G4, new IMacs, and all the recent Apple machines). 119 * It contains 3 controllers in one ASIC. 120 * 121 * The U3 is the bridge used on G5 machines. It contains an 122 * AGP bus which is dealt with the old UniNorth access routines 123 * and a HyperTransport bus which uses its own set of access 124 * functions. 125 */ 126 127 #define MACRISC_CFA0(devfn, off) \ 128 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \ 129 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 130 | (((unsigned int)(off)) & 0xFCUL)) 131 132 #define MACRISC_CFA1(bus, devfn, off) \ 133 ((((unsigned int)(bus)) << 16) \ 134 |(((unsigned int)(devfn)) << 8) \ 135 |(((unsigned int)(off)) & 0xFCUL) \ 136 |1UL) 137 138 static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose, 139 u8 bus, u8 dev_fn, u8 offset) 140 { 141 unsigned int caddr; 142 143 if (bus == hose->first_busno) { 144 if (dev_fn < (11 << 3)) 145 return NULL; 146 caddr = MACRISC_CFA0(dev_fn, offset); 147 } else 148 caddr = MACRISC_CFA1(bus, dev_fn, offset); 149 150 /* Uninorth will return garbage if we don't read back the value ! */ 151 do { 152 out_le32(hose->cfg_addr, caddr); 153 } while (in_le32(hose->cfg_addr) != caddr); 154 155 offset &= has_uninorth ? 0x07 : 0x03; 156 return hose->cfg_data + offset; 157 } 158 159 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, 160 int offset, int len, u32 *val) 161 { 162 struct pci_controller *hose; 163 volatile void __iomem *addr; 164 165 hose = pci_bus_to_host(bus); 166 if (hose == NULL) 167 return PCIBIOS_DEVICE_NOT_FOUND; 168 if (offset >= 0x100) 169 return PCIBIOS_BAD_REGISTER_NUMBER; 170 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 171 if (!addr) 172 return PCIBIOS_DEVICE_NOT_FOUND; 173 /* 174 * Note: the caller has already checked that offset is 175 * suitably aligned and that len is 1, 2 or 4. 176 */ 177 switch (len) { 178 case 1: 179 *val = in_8(addr); 180 break; 181 case 2: 182 *val = in_le16(addr); 183 break; 184 default: 185 *val = in_le32(addr); 186 break; 187 } 188 return PCIBIOS_SUCCESSFUL; 189 } 190 191 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, 192 int offset, int len, u32 val) 193 { 194 struct pci_controller *hose; 195 volatile void __iomem *addr; 196 197 hose = pci_bus_to_host(bus); 198 if (hose == NULL) 199 return PCIBIOS_DEVICE_NOT_FOUND; 200 if (offset >= 0x100) 201 return PCIBIOS_BAD_REGISTER_NUMBER; 202 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 203 if (!addr) 204 return PCIBIOS_DEVICE_NOT_FOUND; 205 /* 206 * Note: the caller has already checked that offset is 207 * suitably aligned and that len is 1, 2 or 4. 208 */ 209 switch (len) { 210 case 1: 211 out_8(addr, val); 212 (void) in_8(addr); 213 break; 214 case 2: 215 out_le16(addr, val); 216 (void) in_le16(addr); 217 break; 218 default: 219 out_le32(addr, val); 220 (void) in_le32(addr); 221 break; 222 } 223 return PCIBIOS_SUCCESSFUL; 224 } 225 226 static struct pci_ops macrisc_pci_ops = 227 { 228 macrisc_read_config, 229 macrisc_write_config 230 }; 231 232 #ifdef CONFIG_PPC32 233 /* 234 * Verify that a specific (bus, dev_fn) exists on chaos 235 */ 236 static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) 237 { 238 struct device_node *np; 239 const u32 *vendor, *device; 240 241 if (offset >= 0x100) 242 return PCIBIOS_BAD_REGISTER_NUMBER; 243 np = pci_busdev_to_OF_node(bus, devfn); 244 if (np == NULL) 245 return PCIBIOS_DEVICE_NOT_FOUND; 246 247 vendor = of_get_property(np, "vendor-id", NULL); 248 device = of_get_property(np, "device-id", NULL); 249 if (vendor == NULL || device == NULL) 250 return PCIBIOS_DEVICE_NOT_FOUND; 251 252 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) 253 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) 254 return PCIBIOS_BAD_REGISTER_NUMBER; 255 256 return PCIBIOS_SUCCESSFUL; 257 } 258 259 static int 260 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 261 int len, u32 *val) 262 { 263 int result = chaos_validate_dev(bus, devfn, offset); 264 if (result == PCIBIOS_BAD_REGISTER_NUMBER) 265 *val = ~0U; 266 if (result != PCIBIOS_SUCCESSFUL) 267 return result; 268 return macrisc_read_config(bus, devfn, offset, len, val); 269 } 270 271 static int 272 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 273 int len, u32 val) 274 { 275 int result = chaos_validate_dev(bus, devfn, offset); 276 if (result != PCIBIOS_SUCCESSFUL) 277 return result; 278 return macrisc_write_config(bus, devfn, offset, len, val); 279 } 280 281 static struct pci_ops chaos_pci_ops = 282 { 283 chaos_read_config, 284 chaos_write_config 285 }; 286 287 static void __init setup_chaos(struct pci_controller *hose, 288 struct resource *addr) 289 { 290 /* assume a `chaos' bridge */ 291 hose->ops = &chaos_pci_ops; 292 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 293 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 294 } 295 #endif /* CONFIG_PPC32 */ 296 297 #ifdef CONFIG_PPC64 298 /* 299 * These versions of U3 HyperTransport config space access ops do not 300 * implement self-view of the HT host yet 301 */ 302 303 /* 304 * This function deals with some "special cases" devices. 305 * 306 * 0 -> No special case 307 * 1 -> Skip the device but act as if the access was successfull 308 * (return 0xff's on reads, eventually, cache config space 309 * accesses in a later version) 310 * -1 -> Hide the device (unsuccessful acess) 311 */ 312 static int u3_ht_skip_device(struct pci_controller *hose, 313 struct pci_bus *bus, unsigned int devfn) 314 { 315 struct device_node *busdn, *dn; 316 int i; 317 318 /* We only allow config cycles to devices that are in OF device-tree 319 * as we are apparently having some weird things going on with some 320 * revs of K2 on recent G5s 321 */ 322 if (bus->self) 323 busdn = pci_device_to_OF_node(bus->self); 324 else 325 busdn = hose->arch_data; 326 for (dn = busdn->child; dn; dn = dn->sibling) 327 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn) 328 break; 329 if (dn == NULL) 330 return -1; 331 332 /* 333 * When a device in K2 is powered down, we die on config 334 * cycle accesses. Fix that here. 335 */ 336 for (i=0; i<2; i++) 337 if (k2_skiplist[i] == dn) 338 return 1; 339 340 return 0; 341 } 342 343 #define U3_HT_CFA0(devfn, off) \ 344 ((((unsigned int)devfn) << 8) | offset) 345 #define U3_HT_CFA1(bus, devfn, off) \ 346 (U3_HT_CFA0(devfn, off) \ 347 + (((unsigned int)bus) << 16) \ 348 + 0x01000000UL) 349 350 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose, 351 u8 bus, u8 devfn, u8 offset) 352 { 353 if (bus == hose->first_busno) { 354 /* For now, we don't self probe U3 HT bridge */ 355 if (PCI_SLOT(devfn) == 0) 356 return NULL; 357 return hose->cfg_data + U3_HT_CFA0(devfn, offset); 358 } else 359 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); 360 } 361 362 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 363 int offset, int len, u32 *val) 364 { 365 struct pci_controller *hose; 366 volatile void __iomem *addr; 367 368 hose = pci_bus_to_host(bus); 369 if (hose == NULL) 370 return PCIBIOS_DEVICE_NOT_FOUND; 371 if (offset >= 0x100) 372 return PCIBIOS_BAD_REGISTER_NUMBER; 373 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 374 if (!addr) 375 return PCIBIOS_DEVICE_NOT_FOUND; 376 377 switch (u3_ht_skip_device(hose, bus, devfn)) { 378 case 0: 379 break; 380 case 1: 381 switch (len) { 382 case 1: 383 *val = 0xff; break; 384 case 2: 385 *val = 0xffff; break; 386 default: 387 *val = 0xfffffffful; break; 388 } 389 return PCIBIOS_SUCCESSFUL; 390 default: 391 return PCIBIOS_DEVICE_NOT_FOUND; 392 } 393 394 /* 395 * Note: the caller has already checked that offset is 396 * suitably aligned and that len is 1, 2 or 4. 397 */ 398 switch (len) { 399 case 1: 400 *val = in_8(addr); 401 break; 402 case 2: 403 *val = in_le16(addr); 404 break; 405 default: 406 *val = in_le32(addr); 407 break; 408 } 409 return PCIBIOS_SUCCESSFUL; 410 } 411 412 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, 413 int offset, int len, u32 val) 414 { 415 struct pci_controller *hose; 416 volatile void __iomem *addr; 417 418 hose = pci_bus_to_host(bus); 419 if (hose == NULL) 420 return PCIBIOS_DEVICE_NOT_FOUND; 421 if (offset >= 0x100) 422 return PCIBIOS_BAD_REGISTER_NUMBER; 423 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 424 if (!addr) 425 return PCIBIOS_DEVICE_NOT_FOUND; 426 427 switch (u3_ht_skip_device(hose, bus, devfn)) { 428 case 0: 429 break; 430 case 1: 431 return PCIBIOS_SUCCESSFUL; 432 default: 433 return PCIBIOS_DEVICE_NOT_FOUND; 434 } 435 436 /* 437 * Note: the caller has already checked that offset is 438 * suitably aligned and that len is 1, 2 or 4. 439 */ 440 switch (len) { 441 case 1: 442 out_8(addr, val); 443 (void) in_8(addr); 444 break; 445 case 2: 446 out_le16(addr, val); 447 (void) in_le16(addr); 448 break; 449 default: 450 out_le32((u32 __iomem *)addr, val); 451 (void) in_le32(addr); 452 break; 453 } 454 return PCIBIOS_SUCCESSFUL; 455 } 456 457 static struct pci_ops u3_ht_pci_ops = 458 { 459 u3_ht_read_config, 460 u3_ht_write_config 461 }; 462 463 #define U4_PCIE_CFA0(devfn, off) \ 464 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \ 465 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 466 | ((((unsigned int)(off)) >> 8) << 28) \ 467 | (((unsigned int)(off)) & 0xfcU)) 468 469 #define U4_PCIE_CFA1(bus, devfn, off) \ 470 ((((unsigned int)(bus)) << 16) \ 471 |(((unsigned int)(devfn)) << 8) \ 472 | ((((unsigned int)(off)) >> 8) << 28) \ 473 |(((unsigned int)(off)) & 0xfcU) \ 474 |1UL) 475 476 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, 477 u8 bus, u8 dev_fn, int offset) 478 { 479 unsigned int caddr; 480 481 if (bus == hose->first_busno) { 482 caddr = U4_PCIE_CFA0(dev_fn, offset); 483 } else 484 caddr = U4_PCIE_CFA1(bus, dev_fn, offset); 485 486 /* Uninorth will return garbage if we don't read back the value ! */ 487 do { 488 out_le32(hose->cfg_addr, caddr); 489 } while (in_le32(hose->cfg_addr) != caddr); 490 491 offset &= 0x03; 492 return hose->cfg_data + offset; 493 } 494 495 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 496 int offset, int len, u32 *val) 497 { 498 struct pci_controller *hose; 499 volatile void __iomem *addr; 500 501 hose = pci_bus_to_host(bus); 502 if (hose == NULL) 503 return PCIBIOS_DEVICE_NOT_FOUND; 504 if (offset >= 0x1000) 505 return PCIBIOS_BAD_REGISTER_NUMBER; 506 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 507 if (!addr) 508 return PCIBIOS_DEVICE_NOT_FOUND; 509 /* 510 * Note: the caller has already checked that offset is 511 * suitably aligned and that len is 1, 2 or 4. 512 */ 513 switch (len) { 514 case 1: 515 *val = in_8(addr); 516 break; 517 case 2: 518 *val = in_le16(addr); 519 break; 520 default: 521 *val = in_le32(addr); 522 break; 523 } 524 return PCIBIOS_SUCCESSFUL; 525 } 526 527 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 528 int offset, int len, u32 val) 529 { 530 struct pci_controller *hose; 531 volatile void __iomem *addr; 532 533 hose = pci_bus_to_host(bus); 534 if (hose == NULL) 535 return PCIBIOS_DEVICE_NOT_FOUND; 536 if (offset >= 0x1000) 537 return PCIBIOS_BAD_REGISTER_NUMBER; 538 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 539 if (!addr) 540 return PCIBIOS_DEVICE_NOT_FOUND; 541 /* 542 * Note: the caller has already checked that offset is 543 * suitably aligned and that len is 1, 2 or 4. 544 */ 545 switch (len) { 546 case 1: 547 out_8(addr, val); 548 (void) in_8(addr); 549 break; 550 case 2: 551 out_le16(addr, val); 552 (void) in_le16(addr); 553 break; 554 default: 555 out_le32(addr, val); 556 (void) in_le32(addr); 557 break; 558 } 559 return PCIBIOS_SUCCESSFUL; 560 } 561 562 static struct pci_ops u4_pcie_pci_ops = 563 { 564 u4_pcie_read_config, 565 u4_pcie_write_config 566 }; 567 568 #endif /* CONFIG_PPC64 */ 569 570 #ifdef CONFIG_PPC32 571 /* 572 * For a bandit bridge, turn on cache coherency if necessary. 573 * N.B. we could clean this up using the hose ops directly. 574 */ 575 static void __init init_bandit(struct pci_controller *bp) 576 { 577 unsigned int vendev, magic; 578 int rev; 579 580 /* read the word at offset 0 in config space for device 11 */ 581 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); 582 udelay(2); 583 vendev = in_le32(bp->cfg_data); 584 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + 585 PCI_VENDOR_ID_APPLE) { 586 /* read the revision id */ 587 out_le32(bp->cfg_addr, 588 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); 589 udelay(2); 590 rev = in_8(bp->cfg_data); 591 if (rev != BANDIT_REVID) 592 printk(KERN_WARNING 593 "Unknown revision %d for bandit\n", rev); 594 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { 595 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); 596 return; 597 } 598 599 /* read the word at offset 0x50 */ 600 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); 601 udelay(2); 602 magic = in_le32(bp->cfg_data); 603 if ((magic & BANDIT_COHERENT) != 0) 604 return; 605 magic |= BANDIT_COHERENT; 606 udelay(2); 607 out_le32(bp->cfg_data, magic); 608 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); 609 } 610 611 /* 612 * Tweak the PCI-PCI bridge chip on the blue & white G3s. 613 */ 614 static void __init init_p2pbridge(void) 615 { 616 struct device_node *p2pbridge; 617 struct pci_controller* hose; 618 u8 bus, devfn; 619 u16 val; 620 621 /* XXX it would be better here to identify the specific 622 PCI-PCI bridge chip we have. */ 623 p2pbridge = of_find_node_by_name(NULL, "pci-bridge"); 624 if (p2pbridge == NULL 625 || p2pbridge->parent == NULL 626 || strcmp(p2pbridge->parent->name, "pci") != 0) 627 goto done; 628 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { 629 DBG("Can't find PCI infos for PCI<->PCI bridge\n"); 630 goto done; 631 } 632 /* Warning: At this point, we have not yet renumbered all busses. 633 * So we must use OF walking to find out hose 634 */ 635 hose = pci_find_hose_for_OF_device(p2pbridge); 636 if (!hose) { 637 DBG("Can't find hose for PCI<->PCI bridge\n"); 638 goto done; 639 } 640 if (early_read_config_word(hose, bus, devfn, 641 PCI_BRIDGE_CONTROL, &val) < 0) { 642 printk(KERN_ERR "init_p2pbridge: couldn't read bridge" 643 " control\n"); 644 goto done; 645 } 646 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; 647 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); 648 done: 649 of_node_put(p2pbridge); 650 } 651 652 static void __init init_second_ohare(void) 653 { 654 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7"); 655 unsigned char bus, devfn; 656 unsigned short cmd; 657 658 if (np == NULL) 659 return; 660 661 /* This must run before we initialize the PICs since the second 662 * ohare hosts a PIC that will be accessed there. 663 */ 664 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) { 665 struct pci_controller* hose = 666 pci_find_hose_for_OF_device(np); 667 if (!hose) { 668 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); 669 return; 670 } 671 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); 672 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 673 cmd &= ~PCI_COMMAND_IO; 674 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); 675 } 676 has_second_ohare = 1; 677 } 678 679 /* 680 * Some Apple desktop machines have a NEC PD720100A USB2 controller 681 * on the motherboard. Open Firmware, on these, will disable the 682 * EHCI part of it so it behaves like a pair of OHCI's. This fixup 683 * code re-enables it ;) 684 */ 685 static void __init fixup_nec_usb2(void) 686 { 687 struct device_node *nec; 688 689 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { 690 struct pci_controller *hose; 691 u32 data; 692 const u32 *prop; 693 u8 bus, devfn; 694 695 prop = of_get_property(nec, "vendor-id", NULL); 696 if (prop == NULL) 697 continue; 698 if (0x1033 != *prop) 699 continue; 700 prop = of_get_property(nec, "device-id", NULL); 701 if (prop == NULL) 702 continue; 703 if (0x0035 != *prop) 704 continue; 705 prop = of_get_property(nec, "reg", NULL); 706 if (prop == NULL) 707 continue; 708 devfn = (prop[0] >> 8) & 0xff; 709 bus = (prop[0] >> 16) & 0xff; 710 if (PCI_FUNC(devfn) != 0) 711 continue; 712 hose = pci_find_hose_for_OF_device(nec); 713 if (!hose) 714 continue; 715 early_read_config_dword(hose, bus, devfn, 0xe4, &data); 716 if (data & 1UL) { 717 printk("Found NEC PD720100A USB2 chip with disabled" 718 " EHCI, fixing up...\n"); 719 data &= ~1UL; 720 early_write_config_dword(hose, bus, devfn, 0xe4, data); 721 } 722 } 723 } 724 725 static void __init setup_bandit(struct pci_controller *hose, 726 struct resource *addr) 727 { 728 hose->ops = ¯isc_pci_ops; 729 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 730 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 731 init_bandit(hose); 732 } 733 734 static int __init setup_uninorth(struct pci_controller *hose, 735 struct resource *addr) 736 { 737 pci_assign_all_buses = 1; 738 has_uninorth = 1; 739 hose->ops = ¯isc_pci_ops; 740 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 741 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 742 /* We "know" that the bridge at f2000000 has the PCI slots. */ 743 return addr->start == 0xf2000000; 744 } 745 #endif /* CONFIG_PPC32 */ 746 747 #ifdef CONFIG_PPC64 748 static void __init setup_u3_agp(struct pci_controller* hose) 749 { 750 /* On G5, we move AGP up to high bus number so we don't need 751 * to reassign bus numbers for HT. If we ever have P2P bridges 752 * on AGP, we'll have to move pci_assign_all_busses to the 753 * pci_controller structure so we enable it for AGP and not for 754 * HT childs. 755 * We hard code the address because of the different size of 756 * the reg address cell, we shall fix that by killing struct 757 * reg_property and using some accessor functions instead 758 */ 759 hose->first_busno = 0xf0; 760 hose->last_busno = 0xff; 761 has_uninorth = 1; 762 hose->ops = ¯isc_pci_ops; 763 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 764 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 765 u3_agp = hose; 766 } 767 768 static void __init setup_u4_pcie(struct pci_controller* hose) 769 { 770 /* We currently only implement the "non-atomic" config space, to 771 * be optimised later. 772 */ 773 hose->ops = &u4_pcie_pci_ops; 774 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 775 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 776 777 /* The bus contains a bridge from root -> device, we need to 778 * make it visible on bus 0 so that we pick the right type 779 * of config cycles. If we didn't, we would have to force all 780 * config cycles to be type 1. So we override the "bus-range" 781 * property here 782 */ 783 hose->first_busno = 0x00; 784 hose->last_busno = 0xff; 785 u4_pcie = hose; 786 } 787 788 static void __init setup_u3_ht(struct pci_controller* hose) 789 { 790 struct device_node *np = (struct device_node *)hose->arch_data; 791 struct pci_controller *other = NULL; 792 int i, cur; 793 794 795 hose->ops = &u3_ht_pci_ops; 796 797 /* We hard code the address because of the different size of 798 * the reg address cell, we shall fix that by killing struct 799 * reg_property and using some accessor functions instead 800 */ 801 hose->cfg_data = ioremap(0xf2000000, 0x02000000); 802 803 /* 804 * /ht node doesn't expose a "ranges" property, so we "remove" 805 * regions that have been allocated to AGP. So far, this version of 806 * the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions 807 * to /ht. We need to fix that sooner or later by either parsing all 808 * child "ranges" properties or figuring out the U3 address space 809 * decoding logic and then read its configuration register (if any). 810 */ 811 hose->io_base_phys = 0xf4000000; 812 hose->pci_io_size = 0x00400000; 813 hose->io_resource.name = np->full_name; 814 hose->io_resource.start = 0; 815 hose->io_resource.end = 0x003fffff; 816 hose->io_resource.flags = IORESOURCE_IO; 817 hose->pci_mem_offset = 0; 818 hose->first_busno = 0; 819 hose->last_busno = 0xef; 820 hose->mem_resources[0].name = np->full_name; 821 hose->mem_resources[0].start = 0x80000000; 822 hose->mem_resources[0].end = 0xefffffff; 823 hose->mem_resources[0].flags = IORESOURCE_MEM; 824 825 u3_ht = hose; 826 827 if (u3_agp != NULL) 828 other = u3_agp; 829 else if (u4_pcie != NULL) 830 other = u4_pcie; 831 832 if (other == NULL) { 833 DBG("U3/4 has no AGP/PCIE, using full resource range\n"); 834 return; 835 } 836 837 /* Fixup bus range vs. PCIE */ 838 if (u4_pcie) 839 hose->last_busno = u4_pcie->first_busno - 1; 840 841 /* We "remove" the AGP resources from the resources allocated to HT, 842 * that is we create "holes". However, that code does assumptions 843 * that so far happen to be true (cross fingers...), typically that 844 * resources in the AGP node are properly ordered 845 */ 846 cur = 0; 847 for (i=0; i<3; i++) { 848 struct resource *res = &other->mem_resources[i]; 849 if (res->flags != IORESOURCE_MEM) 850 continue; 851 /* We don't care about "fine" resources */ 852 if (res->start >= 0xf0000000) 853 continue; 854 /* Check if it's just a matter of "shrinking" us in one 855 * direction 856 */ 857 if (hose->mem_resources[cur].start == res->start) { 858 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n", 859 cur, hose->mem_resources[cur].start, 860 res->end + 1); 861 hose->mem_resources[cur].start = res->end + 1; 862 continue; 863 } 864 if (hose->mem_resources[cur].end == res->end) { 865 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n", 866 cur, hose->mem_resources[cur].end, 867 res->start - 1); 868 hose->mem_resources[cur].end = res->start - 1; 869 continue; 870 } 871 /* No, it's not the case, we need a hole */ 872 if (cur == 2) { 873 /* not enough resources for a hole, we drop part 874 * of the range 875 */ 876 printk(KERN_WARNING "Running out of resources" 877 " for /ht host !\n"); 878 hose->mem_resources[cur].end = res->start - 1; 879 continue; 880 } 881 cur++; 882 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n", 883 cur-1, res->start - 1, cur, res->end + 1); 884 hose->mem_resources[cur].name = np->full_name; 885 hose->mem_resources[cur].flags = IORESOURCE_MEM; 886 hose->mem_resources[cur].start = res->end + 1; 887 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end; 888 hose->mem_resources[cur-1].end = res->start - 1; 889 } 890 } 891 #endif /* CONFIG_PPC64 */ 892 893 /* 894 * We assume that if we have a G3 powermac, we have one bridge called 895 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, 896 * if we have one or more bandit or chaos bridges, we don't have a MPC106. 897 */ 898 static int __init pmac_add_bridge(struct device_node *dev) 899 { 900 int len; 901 struct pci_controller *hose; 902 struct resource rsrc; 903 char *disp_name; 904 const int *bus_range; 905 int primary = 1, has_address = 0; 906 907 DBG("Adding PCI host bridge %s\n", dev->full_name); 908 909 /* Fetch host bridge registers address */ 910 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); 911 912 /* Get bus range if any */ 913 bus_range = of_get_property(dev, "bus-range", &len); 914 if (bus_range == NULL || len < 2 * sizeof(int)) { 915 printk(KERN_WARNING "Can't get bus-range for %s, assume" 916 " bus 0\n", dev->full_name); 917 } 918 919 hose = pcibios_alloc_controller(dev); 920 if (!hose) 921 return -ENOMEM; 922 hose->first_busno = bus_range ? bus_range[0] : 0; 923 hose->last_busno = bus_range ? bus_range[1] : 0xff; 924 925 disp_name = NULL; 926 927 /* 64 bits only bridges */ 928 #ifdef CONFIG_PPC64 929 if (of_device_is_compatible(dev, "u3-agp")) { 930 setup_u3_agp(hose); 931 disp_name = "U3-AGP"; 932 primary = 0; 933 } else if (of_device_is_compatible(dev, "u3-ht")) { 934 setup_u3_ht(hose); 935 disp_name = "U3-HT"; 936 primary = 1; 937 } else if (of_device_is_compatible(dev, "u4-pcie")) { 938 setup_u4_pcie(hose); 939 disp_name = "U4-PCIE"; 940 primary = 0; 941 } 942 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:" 943 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); 944 #endif /* CONFIG_PPC64 */ 945 946 /* 32 bits only bridges */ 947 #ifdef CONFIG_PPC32 948 if (of_device_is_compatible(dev, "uni-north")) { 949 primary = setup_uninorth(hose, &rsrc); 950 disp_name = "UniNorth"; 951 } else if (strcmp(dev->name, "pci") == 0) { 952 /* XXX assume this is a mpc106 (grackle) */ 953 setup_grackle(hose); 954 disp_name = "Grackle (MPC106)"; 955 } else if (strcmp(dev->name, "bandit") == 0) { 956 setup_bandit(hose, &rsrc); 957 disp_name = "Bandit"; 958 } else if (strcmp(dev->name, "chaos") == 0) { 959 setup_chaos(hose, &rsrc); 960 disp_name = "Chaos"; 961 primary = 0; 962 } 963 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. " 964 "Firmware bus number: %d->%d\n", 965 disp_name, (unsigned long long)rsrc.start, hose->first_busno, 966 hose->last_busno); 967 #endif /* CONFIG_PPC32 */ 968 969 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 970 hose, hose->cfg_addr, hose->cfg_data); 971 972 /* Interpret the "ranges" property */ 973 /* This also maps the I/O region and sets isa_io/mem_base */ 974 pci_process_bridge_OF_ranges(hose, dev, primary); 975 976 /* Fixup "bus-range" OF property */ 977 fixup_bus_range(dev); 978 979 return 0; 980 } 981 982 void __devinit pmac_pci_irq_fixup(struct pci_dev *dev) 983 { 984 #ifdef CONFIG_PPC32 985 /* Fixup interrupt for the modem/ethernet combo controller. 986 * on machines with a second ohare chip. 987 * The number in the device tree (27) is bogus (correct for 988 * the ethernet-only board but not the combo ethernet/modem 989 * board). The real interrupt is 28 on the second controller 990 * -> 28+32 = 60. 991 */ 992 if (has_second_ohare && 993 dev->vendor == PCI_VENDOR_ID_DEC && 994 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { 995 dev->irq = irq_create_mapping(NULL, 60); 996 set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); 997 } 998 #endif /* CONFIG_PPC32 */ 999 } 1000 1001 void __init pmac_pci_init(void) 1002 { 1003 struct device_node *np, *root; 1004 struct device_node *ht = NULL; 1005 1006 root = of_find_node_by_path("/"); 1007 if (root == NULL) { 1008 printk(KERN_CRIT "pmac_pci_init: can't find root " 1009 "of device tree\n"); 1010 return; 1011 } 1012 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { 1013 if (np->name == NULL) 1014 continue; 1015 if (strcmp(np->name, "bandit") == 0 1016 || strcmp(np->name, "chaos") == 0 1017 || strcmp(np->name, "pci") == 0) { 1018 if (pmac_add_bridge(np) == 0) 1019 of_node_get(np); 1020 } 1021 if (strcmp(np->name, "ht") == 0) { 1022 of_node_get(np); 1023 ht = np; 1024 } 1025 } 1026 of_node_put(root); 1027 1028 #ifdef CONFIG_PPC64 1029 /* Probe HT last as it relies on the agp resources to be already 1030 * setup 1031 */ 1032 if (ht && pmac_add_bridge(ht) != 0) 1033 of_node_put(ht); 1034 1035 /* Setup the linkage between OF nodes and PHBs */ 1036 pci_devs_phb_init(); 1037 1038 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We 1039 * assume there is no P2P bridge on the AGP bus, which should be a 1040 * safe assumptions for now. We should do something better in the 1041 * future though 1042 */ 1043 if (u3_agp) { 1044 struct device_node *np = u3_agp->arch_data; 1045 PCI_DN(np)->busno = 0xf0; 1046 for (np = np->child; np; np = np->sibling) 1047 PCI_DN(np)->busno = 0xf0; 1048 } 1049 /* pmac_check_ht_link(); */ 1050 1051 /* Tell pci.c to not use the common resource allocation mechanism */ 1052 pci_probe_only = 1; 1053 1054 #else /* CONFIG_PPC64 */ 1055 init_p2pbridge(); 1056 init_second_ohare(); 1057 fixup_nec_usb2(); 1058 1059 /* We are still having some issues with the Xserve G4, enabling 1060 * some offset between bus number and domains for now when we 1061 * assign all busses should help for now 1062 */ 1063 if (pci_assign_all_buses) 1064 pcibios_assign_bus_offset = 0x10; 1065 #endif 1066 } 1067 1068 int 1069 pmac_pci_enable_device_hook(struct pci_dev *dev, int initial) 1070 { 1071 struct device_node* node; 1072 int updatecfg = 0; 1073 int uninorth_child; 1074 1075 node = pci_device_to_OF_node(dev); 1076 1077 /* We don't want to enable USB controllers absent from the OF tree 1078 * (iBook second controller) 1079 */ 1080 if (dev->vendor == PCI_VENDOR_ID_APPLE 1081 && dev->class == PCI_CLASS_SERIAL_USB_OHCI 1082 && !node) { 1083 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", 1084 pci_name(dev)); 1085 return -EINVAL; 1086 } 1087 1088 if (!node) 1089 return 0; 1090 1091 uninorth_child = node->parent && 1092 of_device_is_compatible(node->parent, "uni-north"); 1093 1094 /* Firewire & GMAC were disabled after PCI probe, the driver is 1095 * claiming them, we must re-enable them now. 1096 */ 1097 if (uninorth_child && !strcmp(node->name, "firewire") && 1098 (of_device_is_compatible(node, "pci106b,18") || 1099 of_device_is_compatible(node, "pci106b,30") || 1100 of_device_is_compatible(node, "pci11c1,5811"))) { 1101 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); 1102 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); 1103 updatecfg = 1; 1104 } 1105 if (uninorth_child && !strcmp(node->name, "ethernet") && 1106 of_device_is_compatible(node, "gmac")) { 1107 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); 1108 updatecfg = 1; 1109 } 1110 1111 if (updatecfg) { 1112 u16 cmd; 1113 1114 /* 1115 * Make sure PCI is correctly configured 1116 * 1117 * We use old pci_bios versions of the function since, by 1118 * default, gmac is not powered up, and so will be absent 1119 * from the kernel initial PCI lookup. 1120 * 1121 * Should be replaced by 2.4 new PCI mechanisms and really 1122 * register the device. 1123 */ 1124 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1125 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 1126 | PCI_COMMAND_INVALIDATE; 1127 pci_write_config_word(dev, PCI_COMMAND, cmd); 1128 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); 1129 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 1130 L1_CACHE_BYTES >> 2); 1131 } 1132 1133 return 0; 1134 } 1135 1136 /* We power down some devices after they have been probed. They'll 1137 * be powered back on later on 1138 */ 1139 void __init pmac_pcibios_after_init(void) 1140 { 1141 struct device_node* nd; 1142 1143 #ifdef CONFIG_BLK_DEV_IDE 1144 struct pci_dev *dev = NULL; 1145 1146 /* OF fails to initialize IDE controllers on macs 1147 * (and maybe other machines) 1148 * 1149 * Ideally, this should be moved to the IDE layer, but we need 1150 * to check specifically with Andre Hedrick how to do it cleanly 1151 * since the common IDE code seem to care about the fact that the 1152 * BIOS may have disabled a controller. 1153 * 1154 * -- BenH 1155 */ 1156 for_each_pci_dev(dev) { 1157 if ((dev->class >> 16) != PCI_BASE_CLASS_STORAGE) 1158 continue; 1159 if (pci_enable_device(dev)) 1160 printk(KERN_WARNING 1161 "pci: Failed to enable %s\n", pci_name(dev)); 1162 } 1163 #endif /* CONFIG_BLK_DEV_IDE */ 1164 1165 for_each_node_by_name(nd, "firewire") { 1166 if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") || 1167 of_device_is_compatible(nd, "pci106b,30") || 1168 of_device_is_compatible(nd, "pci11c1,5811")) 1169 && of_device_is_compatible(nd->parent, "uni-north")) { 1170 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); 1171 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); 1172 } 1173 } 1174 of_node_put(nd); 1175 for_each_node_by_name(nd, "ethernet") { 1176 if (nd->parent && of_device_is_compatible(nd, "gmac") 1177 && of_device_is_compatible(nd->parent, "uni-north")) 1178 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); 1179 } 1180 of_node_put(nd); 1181 } 1182 1183 #ifdef CONFIG_PPC32 1184 void pmac_pci_fixup_cardbus(struct pci_dev* dev) 1185 { 1186 if (!machine_is(powermac)) 1187 return; 1188 /* 1189 * Fix the interrupt routing on the various cardbus bridges 1190 * used on powerbooks 1191 */ 1192 if (dev->vendor != PCI_VENDOR_ID_TI) 1193 return; 1194 if (dev->device == PCI_DEVICE_ID_TI_1130 || 1195 dev->device == PCI_DEVICE_ID_TI_1131) { 1196 u8 val; 1197 /* Enable PCI interrupt */ 1198 if (pci_read_config_byte(dev, 0x91, &val) == 0) 1199 pci_write_config_byte(dev, 0x91, val | 0x30); 1200 /* Disable ISA interrupt mode */ 1201 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1202 pci_write_config_byte(dev, 0x92, val & ~0x06); 1203 } 1204 if (dev->device == PCI_DEVICE_ID_TI_1210 || 1205 dev->device == PCI_DEVICE_ID_TI_1211 || 1206 dev->device == PCI_DEVICE_ID_TI_1410 || 1207 dev->device == PCI_DEVICE_ID_TI_1510) { 1208 u8 val; 1209 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA 1210 signal out the MFUNC0 pin */ 1211 if (pci_read_config_byte(dev, 0x8c, &val) == 0) 1212 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); 1213 /* Disable ISA interrupt mode */ 1214 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1215 pci_write_config_byte(dev, 0x92, val & ~0x06); 1216 } 1217 } 1218 1219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); 1220 1221 void pmac_pci_fixup_pciata(struct pci_dev* dev) 1222 { 1223 u8 progif = 0; 1224 1225 /* 1226 * On PowerMacs, we try to switch any PCI ATA controller to 1227 * fully native mode 1228 */ 1229 if (!machine_is(powermac)) 1230 return; 1231 1232 /* Some controllers don't have the class IDE */ 1233 if (dev->vendor == PCI_VENDOR_ID_PROMISE) 1234 switch(dev->device) { 1235 case PCI_DEVICE_ID_PROMISE_20246: 1236 case PCI_DEVICE_ID_PROMISE_20262: 1237 case PCI_DEVICE_ID_PROMISE_20263: 1238 case PCI_DEVICE_ID_PROMISE_20265: 1239 case PCI_DEVICE_ID_PROMISE_20267: 1240 case PCI_DEVICE_ID_PROMISE_20268: 1241 case PCI_DEVICE_ID_PROMISE_20269: 1242 case PCI_DEVICE_ID_PROMISE_20270: 1243 case PCI_DEVICE_ID_PROMISE_20271: 1244 case PCI_DEVICE_ID_PROMISE_20275: 1245 case PCI_DEVICE_ID_PROMISE_20276: 1246 case PCI_DEVICE_ID_PROMISE_20277: 1247 goto good; 1248 } 1249 /* Others, check PCI class */ 1250 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 1251 return; 1252 good: 1253 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1254 if ((progif & 5) != 5) { 1255 printk(KERN_INFO "Forcing PCI IDE into native mode: %s\n", 1256 pci_name(dev)); 1257 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); 1258 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || 1259 (progif & 5) != 5) 1260 printk(KERN_ERR "Rewrite of PROGIF failed !\n"); 1261 } 1262 } 1263 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); 1264 #endif 1265 1266 /* 1267 * Disable second function on K2-SATA, it's broken 1268 * and disable IO BARs on first one 1269 */ 1270 static void fixup_k2_sata(struct pci_dev* dev) 1271 { 1272 int i; 1273 u16 cmd; 1274 1275 if (PCI_FUNC(dev->devfn) > 0) { 1276 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1277 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1278 pci_write_config_word(dev, PCI_COMMAND, cmd); 1279 for (i = 0; i < 6; i++) { 1280 dev->resource[i].start = dev->resource[i].end = 0; 1281 dev->resource[i].flags = 0; 1282 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1283 0); 1284 } 1285 } else { 1286 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1287 cmd &= ~PCI_COMMAND_IO; 1288 pci_write_config_word(dev, PCI_COMMAND, cmd); 1289 for (i = 0; i < 5; i++) { 1290 dev->resource[i].start = dev->resource[i].end = 0; 1291 dev->resource[i].flags = 0; 1292 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1293 0); 1294 } 1295 } 1296 } 1297 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); 1298 1299