1 /* 2 * Support for PCI bridges found on Power Macintoshes. 3 * 4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org) 5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/delay.h> 16 #include <linux/string.h> 17 #include <linux/init.h> 18 #include <linux/irq.h> 19 #include <linux/of_pci.h> 20 21 #include <asm/sections.h> 22 #include <asm/io.h> 23 #include <asm/prom.h> 24 #include <asm/pci-bridge.h> 25 #include <asm/machdep.h> 26 #include <asm/pmac_feature.h> 27 #include <asm/grackle.h> 28 #include <asm/ppc-pci.h> 29 30 #undef DEBUG 31 32 #ifdef DEBUG 33 #define DBG(x...) printk(x) 34 #else 35 #define DBG(x...) 36 #endif 37 38 /* XXX Could be per-controller, but I don't think we risk anything by 39 * assuming we won't have both UniNorth and Bandit */ 40 static int has_uninorth; 41 #ifdef CONFIG_PPC64 42 static struct pci_controller *u3_agp; 43 #else 44 static int has_second_ohare; 45 #endif /* CONFIG_PPC64 */ 46 47 extern int pcibios_assign_bus_offset; 48 49 struct device_node *k2_skiplist[2]; 50 51 /* 52 * Magic constants for enabling cache coherency in the bandit/PSX bridge. 53 */ 54 #define BANDIT_DEVID_2 8 55 #define BANDIT_REVID 3 56 57 #define BANDIT_DEVNUM 11 58 #define BANDIT_MAGIC 0x50 59 #define BANDIT_COHERENT 0x40 60 61 static int __init fixup_one_level_bus_range(struct device_node *node, int higher) 62 { 63 for (; node != 0;node = node->sibling) { 64 const int * bus_range; 65 const unsigned int *class_code; 66 int len; 67 68 /* For PCI<->PCI bridges or CardBus bridges, we go down */ 69 class_code = of_get_property(node, "class-code", NULL); 70 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 71 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) 72 continue; 73 bus_range = of_get_property(node, "bus-range", &len); 74 if (bus_range != NULL && len > 2 * sizeof(int)) { 75 if (bus_range[1] > higher) 76 higher = bus_range[1]; 77 } 78 higher = fixup_one_level_bus_range(node->child, higher); 79 } 80 return higher; 81 } 82 83 /* This routine fixes the "bus-range" property of all bridges in the 84 * system since they tend to have their "last" member wrong on macs 85 * 86 * Note that the bus numbers manipulated here are OF bus numbers, they 87 * are not Linux bus numbers. 88 */ 89 static void __init fixup_bus_range(struct device_node *bridge) 90 { 91 int *bus_range, len; 92 struct property *prop; 93 94 /* Lookup the "bus-range" property for the hose */ 95 prop = of_find_property(bridge, "bus-range", &len); 96 if (prop == NULL || prop->length < 2 * sizeof(int)) 97 return; 98 99 bus_range = prop->value; 100 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); 101 } 102 103 /* 104 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. 105 * 106 * The "Bandit" version is present in all early PCI PowerMacs, 107 * and up to the first ones using Grackle. Some machines may 108 * have 2 bandit controllers (2 PCI busses). 109 * 110 * "Chaos" is used in some "Bandit"-type machines as a bridge 111 * for the separate display bus. It is accessed the same 112 * way as bandit, but cannot be probed for devices. It therefore 113 * has its own config access functions. 114 * 115 * The "UniNorth" version is present in all Core99 machines 116 * (iBook, G4, new IMacs, and all the recent Apple machines). 117 * It contains 3 controllers in one ASIC. 118 * 119 * The U3 is the bridge used on G5 machines. It contains an 120 * AGP bus which is dealt with the old UniNorth access routines 121 * and a HyperTransport bus which uses its own set of access 122 * functions. 123 */ 124 125 #define MACRISC_CFA0(devfn, off) \ 126 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \ 127 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 128 | (((unsigned int)(off)) & 0xFCUL)) 129 130 #define MACRISC_CFA1(bus, devfn, off) \ 131 ((((unsigned int)(bus)) << 16) \ 132 |(((unsigned int)(devfn)) << 8) \ 133 |(((unsigned int)(off)) & 0xFCUL) \ 134 |1UL) 135 136 static void __iomem *macrisc_cfg_map_bus(struct pci_bus *bus, 137 unsigned int dev_fn, 138 int offset) 139 { 140 unsigned int caddr; 141 struct pci_controller *hose; 142 143 hose = pci_bus_to_host(bus); 144 if (hose == NULL) 145 return NULL; 146 147 if (bus->number == hose->first_busno) { 148 if (dev_fn < (11 << 3)) 149 return NULL; 150 caddr = MACRISC_CFA0(dev_fn, offset); 151 } else 152 caddr = MACRISC_CFA1(bus->number, dev_fn, offset); 153 154 /* Uninorth will return garbage if we don't read back the value ! */ 155 do { 156 out_le32(hose->cfg_addr, caddr); 157 } while (in_le32(hose->cfg_addr) != caddr); 158 159 offset &= has_uninorth ? 0x07 : 0x03; 160 return hose->cfg_data + offset; 161 } 162 163 static struct pci_ops macrisc_pci_ops = 164 { 165 .map_bus = macrisc_cfg_map_bus, 166 .read = pci_generic_config_read, 167 .write = pci_generic_config_write, 168 }; 169 170 #ifdef CONFIG_PPC32 171 /* 172 * Verify that a specific (bus, dev_fn) exists on chaos 173 */ 174 static void __iomem *chaos_map_bus(struct pci_bus *bus, unsigned int devfn, 175 int offset) 176 { 177 struct device_node *np; 178 const u32 *vendor, *device; 179 180 if (offset >= 0x100) 181 return NULL; 182 np = of_pci_find_child_device(bus->dev.of_node, devfn); 183 if (np == NULL) 184 return NULL; 185 186 vendor = of_get_property(np, "vendor-id", NULL); 187 device = of_get_property(np, "device-id", NULL); 188 if (vendor == NULL || device == NULL) 189 return NULL; 190 191 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) 192 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) 193 return NULL; 194 195 return macrisc_cfg_map_bus(bus, devfn, offset); 196 } 197 198 static struct pci_ops chaos_pci_ops = 199 { 200 .map_bus = chaos_map_bus, 201 .read = pci_generic_config_read, 202 .write = pci_generic_config_write, 203 }; 204 205 static void __init setup_chaos(struct pci_controller *hose, 206 struct resource *addr) 207 { 208 /* assume a `chaos' bridge */ 209 hose->ops = &chaos_pci_ops; 210 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 211 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 212 } 213 #endif /* CONFIG_PPC32 */ 214 215 #ifdef CONFIG_PPC64 216 /* 217 * These versions of U3 HyperTransport config space access ops do not 218 * implement self-view of the HT host yet 219 */ 220 221 /* 222 * This function deals with some "special cases" devices. 223 * 224 * 0 -> No special case 225 * 1 -> Skip the device but act as if the access was successful 226 * (return 0xff's on reads, eventually, cache config space 227 * accesses in a later version) 228 * -1 -> Hide the device (unsuccessful access) 229 */ 230 static int u3_ht_skip_device(struct pci_controller *hose, 231 struct pci_bus *bus, unsigned int devfn) 232 { 233 struct device_node *busdn, *dn; 234 int i; 235 236 /* We only allow config cycles to devices that are in OF device-tree 237 * as we are apparently having some weird things going on with some 238 * revs of K2 on recent G5s, except for the host bridge itself, which 239 * is missing from the tree but we know we can probe. 240 */ 241 if (bus->self) 242 busdn = pci_device_to_OF_node(bus->self); 243 else if (devfn == 0) 244 return 0; 245 else 246 busdn = hose->dn; 247 for (dn = busdn->child; dn; dn = dn->sibling) 248 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn) 249 break; 250 if (dn == NULL) 251 return -1; 252 253 /* 254 * When a device in K2 is powered down, we die on config 255 * cycle accesses. Fix that here. 256 */ 257 for (i=0; i<2; i++) 258 if (k2_skiplist[i] == dn) 259 return 1; 260 261 return 0; 262 } 263 264 #define U3_HT_CFA0(devfn, off) \ 265 ((((unsigned int)devfn) << 8) | offset) 266 #define U3_HT_CFA1(bus, devfn, off) \ 267 (U3_HT_CFA0(devfn, off) \ 268 + (((unsigned int)bus) << 16) \ 269 + 0x01000000UL) 270 271 static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus, 272 u8 devfn, u8 offset, int *swap) 273 { 274 *swap = 1; 275 if (bus == hose->first_busno) { 276 if (devfn != 0) 277 return hose->cfg_data + U3_HT_CFA0(devfn, offset); 278 *swap = 0; 279 return ((void __iomem *)hose->cfg_addr) + (offset << 2); 280 } else 281 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); 282 } 283 284 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 285 int offset, int len, u32 *val) 286 { 287 struct pci_controller *hose; 288 void __iomem *addr; 289 int swap; 290 291 hose = pci_bus_to_host(bus); 292 if (hose == NULL) 293 return PCIBIOS_DEVICE_NOT_FOUND; 294 if (offset >= 0x100) 295 return PCIBIOS_BAD_REGISTER_NUMBER; 296 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); 297 if (!addr) 298 return PCIBIOS_DEVICE_NOT_FOUND; 299 300 switch (u3_ht_skip_device(hose, bus, devfn)) { 301 case 0: 302 break; 303 case 1: 304 switch (len) { 305 case 1: 306 *val = 0xff; break; 307 case 2: 308 *val = 0xffff; break; 309 default: 310 *val = 0xfffffffful; break; 311 } 312 return PCIBIOS_SUCCESSFUL; 313 default: 314 return PCIBIOS_DEVICE_NOT_FOUND; 315 } 316 317 /* 318 * Note: the caller has already checked that offset is 319 * suitably aligned and that len is 1, 2 or 4. 320 */ 321 switch (len) { 322 case 1: 323 *val = in_8(addr); 324 break; 325 case 2: 326 *val = swap ? in_le16(addr) : in_be16(addr); 327 break; 328 default: 329 *val = swap ? in_le32(addr) : in_be32(addr); 330 break; 331 } 332 return PCIBIOS_SUCCESSFUL; 333 } 334 335 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, 336 int offset, int len, u32 val) 337 { 338 struct pci_controller *hose; 339 void __iomem *addr; 340 int swap; 341 342 hose = pci_bus_to_host(bus); 343 if (hose == NULL) 344 return PCIBIOS_DEVICE_NOT_FOUND; 345 if (offset >= 0x100) 346 return PCIBIOS_BAD_REGISTER_NUMBER; 347 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); 348 if (!addr) 349 return PCIBIOS_DEVICE_NOT_FOUND; 350 351 switch (u3_ht_skip_device(hose, bus, devfn)) { 352 case 0: 353 break; 354 case 1: 355 return PCIBIOS_SUCCESSFUL; 356 default: 357 return PCIBIOS_DEVICE_NOT_FOUND; 358 } 359 360 /* 361 * Note: the caller has already checked that offset is 362 * suitably aligned and that len is 1, 2 or 4. 363 */ 364 switch (len) { 365 case 1: 366 out_8(addr, val); 367 break; 368 case 2: 369 swap ? out_le16(addr, val) : out_be16(addr, val); 370 break; 371 default: 372 swap ? out_le32(addr, val) : out_be32(addr, val); 373 break; 374 } 375 return PCIBIOS_SUCCESSFUL; 376 } 377 378 static struct pci_ops u3_ht_pci_ops = 379 { 380 .read = u3_ht_read_config, 381 .write = u3_ht_write_config, 382 }; 383 384 #define U4_PCIE_CFA0(devfn, off) \ 385 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \ 386 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 387 | ((((unsigned int)(off)) >> 8) << 28) \ 388 | (((unsigned int)(off)) & 0xfcU)) 389 390 #define U4_PCIE_CFA1(bus, devfn, off) \ 391 ((((unsigned int)(bus)) << 16) \ 392 |(((unsigned int)(devfn)) << 8) \ 393 | ((((unsigned int)(off)) >> 8) << 28) \ 394 |(((unsigned int)(off)) & 0xfcU) \ 395 |1UL) 396 397 static void __iomem *u4_pcie_cfg_map_bus(struct pci_bus *bus, 398 unsigned int dev_fn, 399 int offset) 400 { 401 struct pci_controller *hose; 402 unsigned int caddr; 403 404 if (offset >= 0x1000) 405 return NULL; 406 407 hose = pci_bus_to_host(bus); 408 if (!hose) 409 return NULL; 410 411 if (bus->number == hose->first_busno) { 412 caddr = U4_PCIE_CFA0(dev_fn, offset); 413 } else 414 caddr = U4_PCIE_CFA1(bus->number, dev_fn, offset); 415 416 /* Uninorth will return garbage if we don't read back the value ! */ 417 do { 418 out_le32(hose->cfg_addr, caddr); 419 } while (in_le32(hose->cfg_addr) != caddr); 420 421 offset &= 0x03; 422 return hose->cfg_data + offset; 423 } 424 425 static struct pci_ops u4_pcie_pci_ops = 426 { 427 .map_bus = u4_pcie_cfg_map_bus, 428 .read = pci_generic_config_read, 429 .write = pci_generic_config_write, 430 }; 431 432 static void pmac_pci_fixup_u4_of_node(struct pci_dev *dev) 433 { 434 /* Apple's device-tree "hides" the root complex virtual P2P bridge 435 * on U4. However, Linux sees it, causing the PCI <-> OF matching 436 * code to fail to properly match devices below it. This works around 437 * it by setting the node of the bridge to point to the PHB node, 438 * which is not entirely correct but fixes the matching code and 439 * doesn't break anything else. It's also the simplest possible fix. 440 */ 441 if (dev->dev.of_node == NULL) 442 dev->dev.of_node = pcibios_get_phb_of_node(dev->bus); 443 } 444 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, 0x5b, pmac_pci_fixup_u4_of_node); 445 446 #endif /* CONFIG_PPC64 */ 447 448 #ifdef CONFIG_PPC32 449 /* 450 * For a bandit bridge, turn on cache coherency if necessary. 451 * N.B. we could clean this up using the hose ops directly. 452 */ 453 static void __init init_bandit(struct pci_controller *bp) 454 { 455 unsigned int vendev, magic; 456 int rev; 457 458 /* read the word at offset 0 in config space for device 11 */ 459 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); 460 udelay(2); 461 vendev = in_le32(bp->cfg_data); 462 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + 463 PCI_VENDOR_ID_APPLE) { 464 /* read the revision id */ 465 out_le32(bp->cfg_addr, 466 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); 467 udelay(2); 468 rev = in_8(bp->cfg_data); 469 if (rev != BANDIT_REVID) 470 printk(KERN_WARNING 471 "Unknown revision %d for bandit\n", rev); 472 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { 473 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); 474 return; 475 } 476 477 /* read the word at offset 0x50 */ 478 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); 479 udelay(2); 480 magic = in_le32(bp->cfg_data); 481 if ((magic & BANDIT_COHERENT) != 0) 482 return; 483 magic |= BANDIT_COHERENT; 484 udelay(2); 485 out_le32(bp->cfg_data, magic); 486 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); 487 } 488 489 /* 490 * Tweak the PCI-PCI bridge chip on the blue & white G3s. 491 */ 492 static void __init init_p2pbridge(void) 493 { 494 struct device_node *p2pbridge; 495 struct pci_controller* hose; 496 u8 bus, devfn; 497 u16 val; 498 499 /* XXX it would be better here to identify the specific 500 PCI-PCI bridge chip we have. */ 501 p2pbridge = of_find_node_by_name(NULL, "pci-bridge"); 502 if (p2pbridge == NULL 503 || p2pbridge->parent == NULL 504 || strcmp(p2pbridge->parent->name, "pci") != 0) 505 goto done; 506 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { 507 DBG("Can't find PCI infos for PCI<->PCI bridge\n"); 508 goto done; 509 } 510 /* Warning: At this point, we have not yet renumbered all busses. 511 * So we must use OF walking to find out hose 512 */ 513 hose = pci_find_hose_for_OF_device(p2pbridge); 514 if (!hose) { 515 DBG("Can't find hose for PCI<->PCI bridge\n"); 516 goto done; 517 } 518 if (early_read_config_word(hose, bus, devfn, 519 PCI_BRIDGE_CONTROL, &val) < 0) { 520 printk(KERN_ERR "init_p2pbridge: couldn't read bridge" 521 " control\n"); 522 goto done; 523 } 524 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; 525 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); 526 done: 527 of_node_put(p2pbridge); 528 } 529 530 static void __init init_second_ohare(void) 531 { 532 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7"); 533 unsigned char bus, devfn; 534 unsigned short cmd; 535 536 if (np == NULL) 537 return; 538 539 /* This must run before we initialize the PICs since the second 540 * ohare hosts a PIC that will be accessed there. 541 */ 542 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) { 543 struct pci_controller* hose = 544 pci_find_hose_for_OF_device(np); 545 if (!hose) { 546 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); 547 of_node_put(np); 548 return; 549 } 550 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); 551 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 552 cmd &= ~PCI_COMMAND_IO; 553 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); 554 } 555 has_second_ohare = 1; 556 of_node_put(np); 557 } 558 559 /* 560 * Some Apple desktop machines have a NEC PD720100A USB2 controller 561 * on the motherboard. Open Firmware, on these, will disable the 562 * EHCI part of it so it behaves like a pair of OHCI's. This fixup 563 * code re-enables it ;) 564 */ 565 static void __init fixup_nec_usb2(void) 566 { 567 struct device_node *nec; 568 569 for_each_node_by_name(nec, "usb") { 570 struct pci_controller *hose; 571 u32 data; 572 const u32 *prop; 573 u8 bus, devfn; 574 575 prop = of_get_property(nec, "vendor-id", NULL); 576 if (prop == NULL) 577 continue; 578 if (0x1033 != *prop) 579 continue; 580 prop = of_get_property(nec, "device-id", NULL); 581 if (prop == NULL) 582 continue; 583 if (0x0035 != *prop) 584 continue; 585 prop = of_get_property(nec, "reg", NULL); 586 if (prop == NULL) 587 continue; 588 devfn = (prop[0] >> 8) & 0xff; 589 bus = (prop[0] >> 16) & 0xff; 590 if (PCI_FUNC(devfn) != 0) 591 continue; 592 hose = pci_find_hose_for_OF_device(nec); 593 if (!hose) 594 continue; 595 early_read_config_dword(hose, bus, devfn, 0xe4, &data); 596 if (data & 1UL) { 597 printk("Found NEC PD720100A USB2 chip with disabled" 598 " EHCI, fixing up...\n"); 599 data &= ~1UL; 600 early_write_config_dword(hose, bus, devfn, 0xe4, data); 601 } 602 } 603 } 604 605 static void __init setup_bandit(struct pci_controller *hose, 606 struct resource *addr) 607 { 608 hose->ops = ¯isc_pci_ops; 609 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 610 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 611 init_bandit(hose); 612 } 613 614 static int __init setup_uninorth(struct pci_controller *hose, 615 struct resource *addr) 616 { 617 pci_add_flags(PCI_REASSIGN_ALL_BUS); 618 has_uninorth = 1; 619 hose->ops = ¯isc_pci_ops; 620 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 621 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 622 /* We "know" that the bridge at f2000000 has the PCI slots. */ 623 return addr->start == 0xf2000000; 624 } 625 #endif /* CONFIG_PPC32 */ 626 627 #ifdef CONFIG_PPC64 628 static void __init setup_u3_agp(struct pci_controller* hose) 629 { 630 /* On G5, we move AGP up to high bus number so we don't need 631 * to reassign bus numbers for HT. If we ever have P2P bridges 632 * on AGP, we'll have to move pci_assign_all_busses to the 633 * pci_controller structure so we enable it for AGP and not for 634 * HT childs. 635 * We hard code the address because of the different size of 636 * the reg address cell, we shall fix that by killing struct 637 * reg_property and using some accessor functions instead 638 */ 639 hose->first_busno = 0xf0; 640 hose->last_busno = 0xff; 641 has_uninorth = 1; 642 hose->ops = ¯isc_pci_ops; 643 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 644 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 645 u3_agp = hose; 646 } 647 648 static void __init setup_u4_pcie(struct pci_controller* hose) 649 { 650 /* We currently only implement the "non-atomic" config space, to 651 * be optimised later. 652 */ 653 hose->ops = &u4_pcie_pci_ops; 654 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 655 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 656 657 /* The bus contains a bridge from root -> device, we need to 658 * make it visible on bus 0 so that we pick the right type 659 * of config cycles. If we didn't, we would have to force all 660 * config cycles to be type 1. So we override the "bus-range" 661 * property here 662 */ 663 hose->first_busno = 0x00; 664 hose->last_busno = 0xff; 665 } 666 667 static void __init parse_region_decode(struct pci_controller *hose, 668 u32 decode) 669 { 670 unsigned long base, end, next = -1; 671 int i, cur = -1; 672 673 /* Iterate through all bits. We ignore the last bit as this region is 674 * reserved for the ROM among other niceties 675 */ 676 for (i = 0; i < 31; i++) { 677 if ((decode & (0x80000000 >> i)) == 0) 678 continue; 679 if (i < 16) { 680 base = 0xf0000000 | (((u32)i) << 24); 681 end = base + 0x00ffffff; 682 } else { 683 base = ((u32)i-16) << 28; 684 end = base + 0x0fffffff; 685 } 686 if (base != next) { 687 if (++cur >= 3) { 688 printk(KERN_WARNING "PCI: Too many ranges !\n"); 689 break; 690 } 691 hose->mem_resources[cur].flags = IORESOURCE_MEM; 692 hose->mem_resources[cur].name = hose->dn->full_name; 693 hose->mem_resources[cur].start = base; 694 hose->mem_resources[cur].end = end; 695 hose->mem_offset[cur] = 0; 696 DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end); 697 } else { 698 DBG(" : -0x%08lx\n", end); 699 hose->mem_resources[cur].end = end; 700 } 701 next = end + 1; 702 } 703 } 704 705 static void __init setup_u3_ht(struct pci_controller* hose) 706 { 707 struct device_node *np = hose->dn; 708 struct resource cfg_res, self_res; 709 u32 decode; 710 711 hose->ops = &u3_ht_pci_ops; 712 713 /* Get base addresses from OF tree 714 */ 715 if (of_address_to_resource(np, 0, &cfg_res) || 716 of_address_to_resource(np, 1, &self_res)) { 717 printk(KERN_ERR "PCI: Failed to get U3/U4 HT resources !\n"); 718 return; 719 } 720 721 /* Map external cfg space access into cfg_data and self registers 722 * into cfg_addr 723 */ 724 hose->cfg_data = ioremap(cfg_res.start, 0x02000000); 725 hose->cfg_addr = ioremap(self_res.start, resource_size(&self_res)); 726 727 /* 728 * /ht node doesn't expose a "ranges" property, we read the register 729 * that controls the decoding logic and use that for memory regions. 730 * The IO region is hard coded since it is fixed in HW as well. 731 */ 732 hose->io_base_phys = 0xf4000000; 733 hose->pci_io_size = 0x00400000; 734 hose->io_resource.name = np->full_name; 735 hose->io_resource.start = 0; 736 hose->io_resource.end = 0x003fffff; 737 hose->io_resource.flags = IORESOURCE_IO; 738 hose->first_busno = 0; 739 hose->last_busno = 0xef; 740 741 /* Note: fix offset when cfg_addr becomes a void * */ 742 decode = in_be32(hose->cfg_addr + 0x80); 743 744 DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode); 745 746 /* NOTE: The decode register setup is a bit weird... region 747 * 0xf8000000 for example is marked as enabled in there while it's 748 & actually the memory controller registers. 749 * That means that we are incorrectly attributing it to HT. 750 * 751 * In a similar vein, region 0xf4000000 is actually the HT IO space but 752 * also marked as enabled in here and 0xf9000000 is used by some other 753 * internal bits of the northbridge. 754 * 755 * Unfortunately, we can't just mask out those bit as we would end 756 * up with more regions than we can cope (linux can only cope with 757 * 3 memory regions for a PHB at this stage). 758 * 759 * So for now, we just do a little hack. We happen to -know- that 760 * Apple firmware doesn't assign things below 0xfa000000 for that 761 * bridge anyway so we mask out all bits we don't want. 762 */ 763 decode &= 0x003fffff; 764 765 /* Now parse the resulting bits and build resources */ 766 parse_region_decode(hose, decode); 767 } 768 #endif /* CONFIG_PPC64 */ 769 770 /* 771 * We assume that if we have a G3 powermac, we have one bridge called 772 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, 773 * if we have one or more bandit or chaos bridges, we don't have a MPC106. 774 */ 775 static int __init pmac_add_bridge(struct device_node *dev) 776 { 777 int len; 778 struct pci_controller *hose; 779 struct resource rsrc; 780 char *disp_name; 781 const int *bus_range; 782 int primary = 1, has_address = 0; 783 784 DBG("Adding PCI host bridge %s\n", dev->full_name); 785 786 /* Fetch host bridge registers address */ 787 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); 788 789 /* Get bus range if any */ 790 bus_range = of_get_property(dev, "bus-range", &len); 791 if (bus_range == NULL || len < 2 * sizeof(int)) { 792 printk(KERN_WARNING "Can't get bus-range for %s, assume" 793 " bus 0\n", dev->full_name); 794 } 795 796 hose = pcibios_alloc_controller(dev); 797 if (!hose) 798 return -ENOMEM; 799 hose->first_busno = bus_range ? bus_range[0] : 0; 800 hose->last_busno = bus_range ? bus_range[1] : 0xff; 801 802 disp_name = NULL; 803 804 /* 64 bits only bridges */ 805 #ifdef CONFIG_PPC64 806 if (of_device_is_compatible(dev, "u3-agp")) { 807 setup_u3_agp(hose); 808 disp_name = "U3-AGP"; 809 primary = 0; 810 } else if (of_device_is_compatible(dev, "u3-ht")) { 811 setup_u3_ht(hose); 812 disp_name = "U3-HT"; 813 primary = 1; 814 } else if (of_device_is_compatible(dev, "u4-pcie")) { 815 setup_u4_pcie(hose); 816 disp_name = "U4-PCIE"; 817 primary = 0; 818 } 819 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:" 820 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); 821 #endif /* CONFIG_PPC64 */ 822 823 /* 32 bits only bridges */ 824 #ifdef CONFIG_PPC32 825 if (of_device_is_compatible(dev, "uni-north")) { 826 primary = setup_uninorth(hose, &rsrc); 827 disp_name = "UniNorth"; 828 } else if (strcmp(dev->name, "pci") == 0) { 829 /* XXX assume this is a mpc106 (grackle) */ 830 setup_grackle(hose); 831 disp_name = "Grackle (MPC106)"; 832 } else if (strcmp(dev->name, "bandit") == 0) { 833 setup_bandit(hose, &rsrc); 834 disp_name = "Bandit"; 835 } else if (strcmp(dev->name, "chaos") == 0) { 836 setup_chaos(hose, &rsrc); 837 disp_name = "Chaos"; 838 primary = 0; 839 } 840 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. " 841 "Firmware bus number: %d->%d\n", 842 disp_name, (unsigned long long)rsrc.start, hose->first_busno, 843 hose->last_busno); 844 #endif /* CONFIG_PPC32 */ 845 846 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 847 hose, hose->cfg_addr, hose->cfg_data); 848 849 /* Interpret the "ranges" property */ 850 /* This also maps the I/O region and sets isa_io/mem_base */ 851 pci_process_bridge_OF_ranges(hose, dev, primary); 852 853 /* Fixup "bus-range" OF property */ 854 fixup_bus_range(dev); 855 856 return 0; 857 } 858 859 void pmac_pci_irq_fixup(struct pci_dev *dev) 860 { 861 #ifdef CONFIG_PPC32 862 /* Fixup interrupt for the modem/ethernet combo controller. 863 * on machines with a second ohare chip. 864 * The number in the device tree (27) is bogus (correct for 865 * the ethernet-only board but not the combo ethernet/modem 866 * board). The real interrupt is 28 on the second controller 867 * -> 28+32 = 60. 868 */ 869 if (has_second_ohare && 870 dev->vendor == PCI_VENDOR_ID_DEC && 871 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { 872 dev->irq = irq_create_mapping(NULL, 60); 873 irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); 874 } 875 #endif /* CONFIG_PPC32 */ 876 } 877 878 void __init pmac_pci_init(void) 879 { 880 struct device_node *np, *root; 881 struct device_node *ht = NULL; 882 883 pci_set_flags(PCI_CAN_SKIP_ISA_ALIGN); 884 885 root = of_find_node_by_path("/"); 886 if (root == NULL) { 887 printk(KERN_CRIT "pmac_pci_init: can't find root " 888 "of device tree\n"); 889 return; 890 } 891 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { 892 if (np->name == NULL) 893 continue; 894 if (strcmp(np->name, "bandit") == 0 895 || strcmp(np->name, "chaos") == 0 896 || strcmp(np->name, "pci") == 0) { 897 if (pmac_add_bridge(np) == 0) 898 of_node_get(np); 899 } 900 if (strcmp(np->name, "ht") == 0) { 901 of_node_get(np); 902 ht = np; 903 } 904 } 905 of_node_put(root); 906 907 #ifdef CONFIG_PPC64 908 /* Probe HT last as it relies on the agp resources to be already 909 * setup 910 */ 911 if (ht && pmac_add_bridge(ht) != 0) 912 of_node_put(ht); 913 914 /* Setup the linkage between OF nodes and PHBs */ 915 pci_devs_phb_init(); 916 917 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We 918 * assume there is no P2P bridge on the AGP bus, which should be a 919 * safe assumptions for now. We should do something better in the 920 * future though 921 */ 922 if (u3_agp) { 923 struct device_node *np = u3_agp->dn; 924 PCI_DN(np)->busno = 0xf0; 925 for (np = np->child; np; np = np->sibling) 926 PCI_DN(np)->busno = 0xf0; 927 } 928 /* pmac_check_ht_link(); */ 929 930 #else /* CONFIG_PPC64 */ 931 init_p2pbridge(); 932 init_second_ohare(); 933 fixup_nec_usb2(); 934 935 /* We are still having some issues with the Xserve G4, enabling 936 * some offset between bus number and domains for now when we 937 * assign all busses should help for now 938 */ 939 if (pci_has_flag(PCI_REASSIGN_ALL_BUS)) 940 pcibios_assign_bus_offset = 0x10; 941 #endif 942 } 943 944 #ifdef CONFIG_PPC32 945 int pmac_pci_enable_device_hook(struct pci_dev *dev) 946 { 947 struct device_node* node; 948 int updatecfg = 0; 949 int uninorth_child; 950 951 node = pci_device_to_OF_node(dev); 952 953 /* We don't want to enable USB controllers absent from the OF tree 954 * (iBook second controller) 955 */ 956 if (dev->vendor == PCI_VENDOR_ID_APPLE 957 && dev->class == PCI_CLASS_SERIAL_USB_OHCI 958 && !node) { 959 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", 960 pci_name(dev)); 961 return -EINVAL; 962 } 963 964 if (!node) 965 return 0; 966 967 uninorth_child = node->parent && 968 of_device_is_compatible(node->parent, "uni-north"); 969 970 /* Firewire & GMAC were disabled after PCI probe, the driver is 971 * claiming them, we must re-enable them now. 972 */ 973 if (uninorth_child && !strcmp(node->name, "firewire") && 974 (of_device_is_compatible(node, "pci106b,18") || 975 of_device_is_compatible(node, "pci106b,30") || 976 of_device_is_compatible(node, "pci11c1,5811"))) { 977 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); 978 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); 979 updatecfg = 1; 980 } 981 if (uninorth_child && !strcmp(node->name, "ethernet") && 982 of_device_is_compatible(node, "gmac")) { 983 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); 984 updatecfg = 1; 985 } 986 987 /* 988 * Fixup various header fields on 32 bits. We don't do that on 989 * 64 bits as some of these have strange values behind the HT 990 * bridge and we must not, for example, enable MWI or set the 991 * cache line size on them. 992 */ 993 if (updatecfg) { 994 u16 cmd; 995 996 pci_read_config_word(dev, PCI_COMMAND, &cmd); 997 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 998 | PCI_COMMAND_INVALIDATE; 999 pci_write_config_word(dev, PCI_COMMAND, cmd); 1000 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); 1001 1002 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 1003 L1_CACHE_BYTES >> 2); 1004 } 1005 1006 return 0; 1007 } 1008 1009 void pmac_pci_fixup_ohci(struct pci_dev *dev) 1010 { 1011 struct device_node *node = pci_device_to_OF_node(dev); 1012 1013 /* We don't want to assign resources to USB controllers 1014 * absent from the OF tree (iBook second controller) 1015 */ 1016 if (dev->class == PCI_CLASS_SERIAL_USB_OHCI && !node) 1017 dev->resource[0].flags = 0; 1018 } 1019 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_ANY_ID, pmac_pci_fixup_ohci); 1020 1021 /* We power down some devices after they have been probed. They'll 1022 * be powered back on later on 1023 */ 1024 void __init pmac_pcibios_after_init(void) 1025 { 1026 struct device_node* nd; 1027 1028 for_each_node_by_name(nd, "firewire") { 1029 if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") || 1030 of_device_is_compatible(nd, "pci106b,30") || 1031 of_device_is_compatible(nd, "pci11c1,5811")) 1032 && of_device_is_compatible(nd->parent, "uni-north")) { 1033 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); 1034 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); 1035 } 1036 } 1037 for_each_node_by_name(nd, "ethernet") { 1038 if (nd->parent && of_device_is_compatible(nd, "gmac") 1039 && of_device_is_compatible(nd->parent, "uni-north")) 1040 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); 1041 } 1042 } 1043 1044 void pmac_pci_fixup_cardbus(struct pci_dev* dev) 1045 { 1046 if (!machine_is(powermac)) 1047 return; 1048 /* 1049 * Fix the interrupt routing on the various cardbus bridges 1050 * used on powerbooks 1051 */ 1052 if (dev->vendor != PCI_VENDOR_ID_TI) 1053 return; 1054 if (dev->device == PCI_DEVICE_ID_TI_1130 || 1055 dev->device == PCI_DEVICE_ID_TI_1131) { 1056 u8 val; 1057 /* Enable PCI interrupt */ 1058 if (pci_read_config_byte(dev, 0x91, &val) == 0) 1059 pci_write_config_byte(dev, 0x91, val | 0x30); 1060 /* Disable ISA interrupt mode */ 1061 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1062 pci_write_config_byte(dev, 0x92, val & ~0x06); 1063 } 1064 if (dev->device == PCI_DEVICE_ID_TI_1210 || 1065 dev->device == PCI_DEVICE_ID_TI_1211 || 1066 dev->device == PCI_DEVICE_ID_TI_1410 || 1067 dev->device == PCI_DEVICE_ID_TI_1510) { 1068 u8 val; 1069 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA 1070 signal out the MFUNC0 pin */ 1071 if (pci_read_config_byte(dev, 0x8c, &val) == 0) 1072 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); 1073 /* Disable ISA interrupt mode */ 1074 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1075 pci_write_config_byte(dev, 0x92, val & ~0x06); 1076 } 1077 } 1078 1079 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); 1080 1081 void pmac_pci_fixup_pciata(struct pci_dev* dev) 1082 { 1083 u8 progif = 0; 1084 1085 /* 1086 * On PowerMacs, we try to switch any PCI ATA controller to 1087 * fully native mode 1088 */ 1089 if (!machine_is(powermac)) 1090 return; 1091 1092 /* Some controllers don't have the class IDE */ 1093 if (dev->vendor == PCI_VENDOR_ID_PROMISE) 1094 switch(dev->device) { 1095 case PCI_DEVICE_ID_PROMISE_20246: 1096 case PCI_DEVICE_ID_PROMISE_20262: 1097 case PCI_DEVICE_ID_PROMISE_20263: 1098 case PCI_DEVICE_ID_PROMISE_20265: 1099 case PCI_DEVICE_ID_PROMISE_20267: 1100 case PCI_DEVICE_ID_PROMISE_20268: 1101 case PCI_DEVICE_ID_PROMISE_20269: 1102 case PCI_DEVICE_ID_PROMISE_20270: 1103 case PCI_DEVICE_ID_PROMISE_20271: 1104 case PCI_DEVICE_ID_PROMISE_20275: 1105 case PCI_DEVICE_ID_PROMISE_20276: 1106 case PCI_DEVICE_ID_PROMISE_20277: 1107 goto good; 1108 } 1109 /* Others, check PCI class */ 1110 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 1111 return; 1112 good: 1113 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1114 if ((progif & 5) != 5) { 1115 printk(KERN_INFO "PCI: %s Forcing PCI IDE into native mode\n", 1116 pci_name(dev)); 1117 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); 1118 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || 1119 (progif & 5) != 5) 1120 printk(KERN_ERR "Rewrite of PROGIF failed !\n"); 1121 else { 1122 /* Clear IO BARs, they will be reassigned */ 1123 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0); 1124 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); 1125 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0); 1126 pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0); 1127 } 1128 } 1129 } 1130 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); 1131 #endif /* CONFIG_PPC32 */ 1132 1133 /* 1134 * Disable second function on K2-SATA, it's broken 1135 * and disable IO BARs on first one 1136 */ 1137 static void fixup_k2_sata(struct pci_dev* dev) 1138 { 1139 int i; 1140 u16 cmd; 1141 1142 if (PCI_FUNC(dev->devfn) > 0) { 1143 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1144 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1145 pci_write_config_word(dev, PCI_COMMAND, cmd); 1146 for (i = 0; i < 6; i++) { 1147 dev->resource[i].start = dev->resource[i].end = 0; 1148 dev->resource[i].flags = 0; 1149 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1150 0); 1151 } 1152 } else { 1153 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1154 cmd &= ~PCI_COMMAND_IO; 1155 pci_write_config_word(dev, PCI_COMMAND, cmd); 1156 for (i = 0; i < 5; i++) { 1157 dev->resource[i].start = dev->resource[i].end = 0; 1158 dev->resource[i].flags = 0; 1159 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1160 0); 1161 } 1162 } 1163 } 1164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); 1165 1166 /* 1167 * On U4 (aka CPC945) the PCIe root complex "P2P" bridge resource ranges aren't 1168 * configured by the firmware. The bridge itself seems to ignore them but it 1169 * causes problems with Linux which then re-assigns devices below the bridge, 1170 * thus changing addresses of those devices from what was in the device-tree, 1171 * which sucks when those are video cards using offb 1172 * 1173 * We could just mark it transparent but I prefer fixing up the resources to 1174 * properly show what's going on here, as I have some doubts about having them 1175 * badly configured potentially being an issue for DMA. 1176 * 1177 * We leave PIO alone, it seems to be fine 1178 * 1179 * Oh and there's another funny bug. The OF properties advertize the region 1180 * 0xf1000000..0xf1ffffff as being forwarded as memory space. But that's 1181 * actually not true, this region is the memory mapped config space. So we 1182 * also need to filter it out or we'll map things in the wrong place. 1183 */ 1184 static void fixup_u4_pcie(struct pci_dev* dev) 1185 { 1186 struct pci_controller *host = pci_bus_to_host(dev->bus); 1187 struct resource *region = NULL; 1188 u32 reg; 1189 int i; 1190 1191 /* Only do that on PowerMac */ 1192 if (!machine_is(powermac)) 1193 return; 1194 1195 /* Find the largest MMIO region */ 1196 for (i = 0; i < 3; i++) { 1197 struct resource *r = &host->mem_resources[i]; 1198 if (!(r->flags & IORESOURCE_MEM)) 1199 continue; 1200 /* Skip the 0xf0xxxxxx..f2xxxxxx regions, we know they 1201 * are reserved by HW for other things 1202 */ 1203 if (r->start >= 0xf0000000 && r->start < 0xf3000000) 1204 continue; 1205 if (!region || resource_size(r) > resource_size(region)) 1206 region = r; 1207 } 1208 /* Nothing found, bail */ 1209 if (region == 0) 1210 return; 1211 1212 /* Print things out */ 1213 printk(KERN_INFO "PCI: Fixup U4 PCIe bridge range: %pR\n", region); 1214 1215 /* Fixup bridge config space. We know it's a Mac, resource aren't 1216 * offset so let's just blast them as-is. We also know that they 1217 * fit in 32 bits 1218 */ 1219 reg = ((region->start >> 16) & 0xfff0) | (region->end & 0xfff00000); 1220 pci_write_config_dword(dev, PCI_MEMORY_BASE, reg); 1221 pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0); 1222 pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0); 1223 pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0); 1224 } 1225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_U4_PCIE, fixup_u4_pcie); 1226