1 /* 2 * Support for PCI bridges found on Power Macintoshes. 3 * 4 * Copyright (C) 2003-2005 Benjamin Herrenschmuidt (benh@kernel.crashing.org) 5 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org) 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; either version 10 * 2 of the License, or (at your option) any later version. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/delay.h> 16 #include <linux/string.h> 17 #include <linux/init.h> 18 #include <linux/bootmem.h> 19 #include <linux/irq.h> 20 21 #include <asm/sections.h> 22 #include <asm/io.h> 23 #include <asm/prom.h> 24 #include <asm/pci-bridge.h> 25 #include <asm/machdep.h> 26 #include <asm/pmac_feature.h> 27 #include <asm/grackle.h> 28 #include <asm/ppc-pci.h> 29 30 #undef DEBUG 31 32 #ifdef DEBUG 33 #define DBG(x...) printk(x) 34 #else 35 #define DBG(x...) 36 #endif 37 38 /* XXX Could be per-controller, but I don't think we risk anything by 39 * assuming we won't have both UniNorth and Bandit */ 40 static int has_uninorth; 41 #ifdef CONFIG_PPC64 42 static struct pci_controller *u3_agp; 43 #else 44 static int has_second_ohare; 45 #endif /* CONFIG_PPC64 */ 46 47 extern int pcibios_assign_bus_offset; 48 49 struct device_node *k2_skiplist[2]; 50 51 /* 52 * Magic constants for enabling cache coherency in the bandit/PSX bridge. 53 */ 54 #define BANDIT_DEVID_2 8 55 #define BANDIT_REVID 3 56 57 #define BANDIT_DEVNUM 11 58 #define BANDIT_MAGIC 0x50 59 #define BANDIT_COHERENT 0x40 60 61 static int __init fixup_one_level_bus_range(struct device_node *node, int higher) 62 { 63 for (; node != 0;node = node->sibling) { 64 const int * bus_range; 65 const unsigned int *class_code; 66 int len; 67 68 /* For PCI<->PCI bridges or CardBus bridges, we go down */ 69 class_code = of_get_property(node, "class-code", NULL); 70 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 71 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) 72 continue; 73 bus_range = of_get_property(node, "bus-range", &len); 74 if (bus_range != NULL && len > 2 * sizeof(int)) { 75 if (bus_range[1] > higher) 76 higher = bus_range[1]; 77 } 78 higher = fixup_one_level_bus_range(node->child, higher); 79 } 80 return higher; 81 } 82 83 /* This routine fixes the "bus-range" property of all bridges in the 84 * system since they tend to have their "last" member wrong on macs 85 * 86 * Note that the bus numbers manipulated here are OF bus numbers, they 87 * are not Linux bus numbers. 88 */ 89 static void __init fixup_bus_range(struct device_node *bridge) 90 { 91 int *bus_range, len; 92 struct property *prop; 93 94 /* Lookup the "bus-range" property for the hose */ 95 prop = of_find_property(bridge, "bus-range", &len); 96 if (prop == NULL || prop->length < 2 * sizeof(int)) 97 return; 98 99 bus_range = prop->value; 100 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); 101 } 102 103 /* 104 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers. 105 * 106 * The "Bandit" version is present in all early PCI PowerMacs, 107 * and up to the first ones using Grackle. Some machines may 108 * have 2 bandit controllers (2 PCI busses). 109 * 110 * "Chaos" is used in some "Bandit"-type machines as a bridge 111 * for the separate display bus. It is accessed the same 112 * way as bandit, but cannot be probed for devices. It therefore 113 * has its own config access functions. 114 * 115 * The "UniNorth" version is present in all Core99 machines 116 * (iBook, G4, new IMacs, and all the recent Apple machines). 117 * It contains 3 controllers in one ASIC. 118 * 119 * The U3 is the bridge used on G5 machines. It contains an 120 * AGP bus which is dealt with the old UniNorth access routines 121 * and a HyperTransport bus which uses its own set of access 122 * functions. 123 */ 124 125 #define MACRISC_CFA0(devfn, off) \ 126 ((1 << (unsigned int)PCI_SLOT(dev_fn)) \ 127 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 128 | (((unsigned int)(off)) & 0xFCUL)) 129 130 #define MACRISC_CFA1(bus, devfn, off) \ 131 ((((unsigned int)(bus)) << 16) \ 132 |(((unsigned int)(devfn)) << 8) \ 133 |(((unsigned int)(off)) & 0xFCUL) \ 134 |1UL) 135 136 static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose, 137 u8 bus, u8 dev_fn, u8 offset) 138 { 139 unsigned int caddr; 140 141 if (bus == hose->first_busno) { 142 if (dev_fn < (11 << 3)) 143 return NULL; 144 caddr = MACRISC_CFA0(dev_fn, offset); 145 } else 146 caddr = MACRISC_CFA1(bus, dev_fn, offset); 147 148 /* Uninorth will return garbage if we don't read back the value ! */ 149 do { 150 out_le32(hose->cfg_addr, caddr); 151 } while (in_le32(hose->cfg_addr) != caddr); 152 153 offset &= has_uninorth ? 0x07 : 0x03; 154 return hose->cfg_data + offset; 155 } 156 157 static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn, 158 int offset, int len, u32 *val) 159 { 160 struct pci_controller *hose; 161 volatile void __iomem *addr; 162 163 hose = pci_bus_to_host(bus); 164 if (hose == NULL) 165 return PCIBIOS_DEVICE_NOT_FOUND; 166 if (offset >= 0x100) 167 return PCIBIOS_BAD_REGISTER_NUMBER; 168 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 169 if (!addr) 170 return PCIBIOS_DEVICE_NOT_FOUND; 171 /* 172 * Note: the caller has already checked that offset is 173 * suitably aligned and that len is 1, 2 or 4. 174 */ 175 switch (len) { 176 case 1: 177 *val = in_8(addr); 178 break; 179 case 2: 180 *val = in_le16(addr); 181 break; 182 default: 183 *val = in_le32(addr); 184 break; 185 } 186 return PCIBIOS_SUCCESSFUL; 187 } 188 189 static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn, 190 int offset, int len, u32 val) 191 { 192 struct pci_controller *hose; 193 volatile void __iomem *addr; 194 195 hose = pci_bus_to_host(bus); 196 if (hose == NULL) 197 return PCIBIOS_DEVICE_NOT_FOUND; 198 if (offset >= 0x100) 199 return PCIBIOS_BAD_REGISTER_NUMBER; 200 addr = macrisc_cfg_access(hose, bus->number, devfn, offset); 201 if (!addr) 202 return PCIBIOS_DEVICE_NOT_FOUND; 203 /* 204 * Note: the caller has already checked that offset is 205 * suitably aligned and that len is 1, 2 or 4. 206 */ 207 switch (len) { 208 case 1: 209 out_8(addr, val); 210 break; 211 case 2: 212 out_le16(addr, val); 213 break; 214 default: 215 out_le32(addr, val); 216 break; 217 } 218 return PCIBIOS_SUCCESSFUL; 219 } 220 221 static struct pci_ops macrisc_pci_ops = 222 { 223 .read = macrisc_read_config, 224 .write = macrisc_write_config, 225 }; 226 227 #ifdef CONFIG_PPC32 228 /* 229 * Verify that a specific (bus, dev_fn) exists on chaos 230 */ 231 static int chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) 232 { 233 struct device_node *np; 234 const u32 *vendor, *device; 235 236 if (offset >= 0x100) 237 return PCIBIOS_BAD_REGISTER_NUMBER; 238 np = pci_busdev_to_OF_node(bus, devfn); 239 if (np == NULL) 240 return PCIBIOS_DEVICE_NOT_FOUND; 241 242 vendor = of_get_property(np, "vendor-id", NULL); 243 device = of_get_property(np, "device-id", NULL); 244 if (vendor == NULL || device == NULL) 245 return PCIBIOS_DEVICE_NOT_FOUND; 246 247 if ((*vendor == 0x106b) && (*device == 3) && (offset >= 0x10) 248 && (offset != 0x14) && (offset != 0x18) && (offset <= 0x24)) 249 return PCIBIOS_BAD_REGISTER_NUMBER; 250 251 return PCIBIOS_SUCCESSFUL; 252 } 253 254 static int 255 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 256 int len, u32 *val) 257 { 258 int result = chaos_validate_dev(bus, devfn, offset); 259 if (result == PCIBIOS_BAD_REGISTER_NUMBER) 260 *val = ~0U; 261 if (result != PCIBIOS_SUCCESSFUL) 262 return result; 263 return macrisc_read_config(bus, devfn, offset, len, val); 264 } 265 266 static int 267 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 268 int len, u32 val) 269 { 270 int result = chaos_validate_dev(bus, devfn, offset); 271 if (result != PCIBIOS_SUCCESSFUL) 272 return result; 273 return macrisc_write_config(bus, devfn, offset, len, val); 274 } 275 276 static struct pci_ops chaos_pci_ops = 277 { 278 .read = chaos_read_config, 279 .write = chaos_write_config, 280 }; 281 282 static void __init setup_chaos(struct pci_controller *hose, 283 struct resource *addr) 284 { 285 /* assume a `chaos' bridge */ 286 hose->ops = &chaos_pci_ops; 287 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 288 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 289 } 290 #endif /* CONFIG_PPC32 */ 291 292 #ifdef CONFIG_PPC64 293 /* 294 * These versions of U3 HyperTransport config space access ops do not 295 * implement self-view of the HT host yet 296 */ 297 298 /* 299 * This function deals with some "special cases" devices. 300 * 301 * 0 -> No special case 302 * 1 -> Skip the device but act as if the access was successfull 303 * (return 0xff's on reads, eventually, cache config space 304 * accesses in a later version) 305 * -1 -> Hide the device (unsuccessful acess) 306 */ 307 static int u3_ht_skip_device(struct pci_controller *hose, 308 struct pci_bus *bus, unsigned int devfn) 309 { 310 struct device_node *busdn, *dn; 311 int i; 312 313 /* We only allow config cycles to devices that are in OF device-tree 314 * as we are apparently having some weird things going on with some 315 * revs of K2 on recent G5s, except for the host bridge itself, which 316 * is missing from the tree but we know we can probe. 317 */ 318 if (bus->self) 319 busdn = pci_device_to_OF_node(bus->self); 320 else if (devfn == 0) 321 return 0; 322 else 323 busdn = hose->dn; 324 for (dn = busdn->child; dn; dn = dn->sibling) 325 if (PCI_DN(dn) && PCI_DN(dn)->devfn == devfn) 326 break; 327 if (dn == NULL) 328 return -1; 329 330 /* 331 * When a device in K2 is powered down, we die on config 332 * cycle accesses. Fix that here. 333 */ 334 for (i=0; i<2; i++) 335 if (k2_skiplist[i] == dn) 336 return 1; 337 338 return 0; 339 } 340 341 #define U3_HT_CFA0(devfn, off) \ 342 ((((unsigned int)devfn) << 8) | offset) 343 #define U3_HT_CFA1(bus, devfn, off) \ 344 (U3_HT_CFA0(devfn, off) \ 345 + (((unsigned int)bus) << 16) \ 346 + 0x01000000UL) 347 348 static void __iomem *u3_ht_cfg_access(struct pci_controller *hose, u8 bus, 349 u8 devfn, u8 offset, int *swap) 350 { 351 *swap = 1; 352 if (bus == hose->first_busno) { 353 if (devfn != 0) 354 return hose->cfg_data + U3_HT_CFA0(devfn, offset); 355 *swap = 0; 356 return ((void __iomem *)hose->cfg_addr) + (offset << 2); 357 } else 358 return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset); 359 } 360 361 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 362 int offset, int len, u32 *val) 363 { 364 struct pci_controller *hose; 365 void __iomem *addr; 366 int swap; 367 368 hose = pci_bus_to_host(bus); 369 if (hose == NULL) 370 return PCIBIOS_DEVICE_NOT_FOUND; 371 if (offset >= 0x100) 372 return PCIBIOS_BAD_REGISTER_NUMBER; 373 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); 374 if (!addr) 375 return PCIBIOS_DEVICE_NOT_FOUND; 376 377 switch (u3_ht_skip_device(hose, bus, devfn)) { 378 case 0: 379 break; 380 case 1: 381 switch (len) { 382 case 1: 383 *val = 0xff; break; 384 case 2: 385 *val = 0xffff; break; 386 default: 387 *val = 0xfffffffful; break; 388 } 389 return PCIBIOS_SUCCESSFUL; 390 default: 391 return PCIBIOS_DEVICE_NOT_FOUND; 392 } 393 394 /* 395 * Note: the caller has already checked that offset is 396 * suitably aligned and that len is 1, 2 or 4. 397 */ 398 switch (len) { 399 case 1: 400 *val = in_8(addr); 401 break; 402 case 2: 403 *val = swap ? in_le16(addr) : in_be16(addr); 404 break; 405 default: 406 *val = swap ? in_le32(addr) : in_be32(addr); 407 break; 408 } 409 return PCIBIOS_SUCCESSFUL; 410 } 411 412 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, 413 int offset, int len, u32 val) 414 { 415 struct pci_controller *hose; 416 void __iomem *addr; 417 int swap; 418 419 hose = pci_bus_to_host(bus); 420 if (hose == NULL) 421 return PCIBIOS_DEVICE_NOT_FOUND; 422 if (offset >= 0x100) 423 return PCIBIOS_BAD_REGISTER_NUMBER; 424 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset, &swap); 425 if (!addr) 426 return PCIBIOS_DEVICE_NOT_FOUND; 427 428 switch (u3_ht_skip_device(hose, bus, devfn)) { 429 case 0: 430 break; 431 case 1: 432 return PCIBIOS_SUCCESSFUL; 433 default: 434 return PCIBIOS_DEVICE_NOT_FOUND; 435 } 436 437 /* 438 * Note: the caller has already checked that offset is 439 * suitably aligned and that len is 1, 2 or 4. 440 */ 441 switch (len) { 442 case 1: 443 out_8(addr, val); 444 break; 445 case 2: 446 swap ? out_le16(addr, val) : out_be16(addr, val); 447 break; 448 default: 449 swap ? out_le32(addr, val) : out_be32(addr, val); 450 break; 451 } 452 return PCIBIOS_SUCCESSFUL; 453 } 454 455 static struct pci_ops u3_ht_pci_ops = 456 { 457 .read = u3_ht_read_config, 458 .write = u3_ht_write_config, 459 }; 460 461 #define U4_PCIE_CFA0(devfn, off) \ 462 ((1 << ((unsigned int)PCI_SLOT(dev_fn))) \ 463 | (((unsigned int)PCI_FUNC(dev_fn)) << 8) \ 464 | ((((unsigned int)(off)) >> 8) << 28) \ 465 | (((unsigned int)(off)) & 0xfcU)) 466 467 #define U4_PCIE_CFA1(bus, devfn, off) \ 468 ((((unsigned int)(bus)) << 16) \ 469 |(((unsigned int)(devfn)) << 8) \ 470 | ((((unsigned int)(off)) >> 8) << 28) \ 471 |(((unsigned int)(off)) & 0xfcU) \ 472 |1UL) 473 474 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, 475 u8 bus, u8 dev_fn, int offset) 476 { 477 unsigned int caddr; 478 479 if (bus == hose->first_busno) { 480 caddr = U4_PCIE_CFA0(dev_fn, offset); 481 } else 482 caddr = U4_PCIE_CFA1(bus, dev_fn, offset); 483 484 /* Uninorth will return garbage if we don't read back the value ! */ 485 do { 486 out_le32(hose->cfg_addr, caddr); 487 } while (in_le32(hose->cfg_addr) != caddr); 488 489 offset &= 0x03; 490 return hose->cfg_data + offset; 491 } 492 493 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 494 int offset, int len, u32 *val) 495 { 496 struct pci_controller *hose; 497 volatile void __iomem *addr; 498 499 hose = pci_bus_to_host(bus); 500 if (hose == NULL) 501 return PCIBIOS_DEVICE_NOT_FOUND; 502 if (offset >= 0x1000) 503 return PCIBIOS_BAD_REGISTER_NUMBER; 504 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 505 if (!addr) 506 return PCIBIOS_DEVICE_NOT_FOUND; 507 /* 508 * Note: the caller has already checked that offset is 509 * suitably aligned and that len is 1, 2 or 4. 510 */ 511 switch (len) { 512 case 1: 513 *val = in_8(addr); 514 break; 515 case 2: 516 *val = in_le16(addr); 517 break; 518 default: 519 *val = in_le32(addr); 520 break; 521 } 522 return PCIBIOS_SUCCESSFUL; 523 } 524 525 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 526 int offset, int len, u32 val) 527 { 528 struct pci_controller *hose; 529 volatile void __iomem *addr; 530 531 hose = pci_bus_to_host(bus); 532 if (hose == NULL) 533 return PCIBIOS_DEVICE_NOT_FOUND; 534 if (offset >= 0x1000) 535 return PCIBIOS_BAD_REGISTER_NUMBER; 536 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 537 if (!addr) 538 return PCIBIOS_DEVICE_NOT_FOUND; 539 /* 540 * Note: the caller has already checked that offset is 541 * suitably aligned and that len is 1, 2 or 4. 542 */ 543 switch (len) { 544 case 1: 545 out_8(addr, val); 546 break; 547 case 2: 548 out_le16(addr, val); 549 break; 550 default: 551 out_le32(addr, val); 552 break; 553 } 554 return PCIBIOS_SUCCESSFUL; 555 } 556 557 static struct pci_ops u4_pcie_pci_ops = 558 { 559 .read = u4_pcie_read_config, 560 .write = u4_pcie_write_config, 561 }; 562 563 #endif /* CONFIG_PPC64 */ 564 565 #ifdef CONFIG_PPC32 566 /* 567 * For a bandit bridge, turn on cache coherency if necessary. 568 * N.B. we could clean this up using the hose ops directly. 569 */ 570 static void __init init_bandit(struct pci_controller *bp) 571 { 572 unsigned int vendev, magic; 573 int rev; 574 575 /* read the word at offset 0 in config space for device 11 */ 576 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + PCI_VENDOR_ID); 577 udelay(2); 578 vendev = in_le32(bp->cfg_data); 579 if (vendev == (PCI_DEVICE_ID_APPLE_BANDIT << 16) + 580 PCI_VENDOR_ID_APPLE) { 581 /* read the revision id */ 582 out_le32(bp->cfg_addr, 583 (1UL << BANDIT_DEVNUM) + PCI_REVISION_ID); 584 udelay(2); 585 rev = in_8(bp->cfg_data); 586 if (rev != BANDIT_REVID) 587 printk(KERN_WARNING 588 "Unknown revision %d for bandit\n", rev); 589 } else if (vendev != (BANDIT_DEVID_2 << 16) + PCI_VENDOR_ID_APPLE) { 590 printk(KERN_WARNING "bandit isn't? (%x)\n", vendev); 591 return; 592 } 593 594 /* read the word at offset 0x50 */ 595 out_le32(bp->cfg_addr, (1UL << BANDIT_DEVNUM) + BANDIT_MAGIC); 596 udelay(2); 597 magic = in_le32(bp->cfg_data); 598 if ((magic & BANDIT_COHERENT) != 0) 599 return; 600 magic |= BANDIT_COHERENT; 601 udelay(2); 602 out_le32(bp->cfg_data, magic); 603 printk(KERN_INFO "Cache coherency enabled for bandit/PSX\n"); 604 } 605 606 /* 607 * Tweak the PCI-PCI bridge chip on the blue & white G3s. 608 */ 609 static void __init init_p2pbridge(void) 610 { 611 struct device_node *p2pbridge; 612 struct pci_controller* hose; 613 u8 bus, devfn; 614 u16 val; 615 616 /* XXX it would be better here to identify the specific 617 PCI-PCI bridge chip we have. */ 618 p2pbridge = of_find_node_by_name(NULL, "pci-bridge"); 619 if (p2pbridge == NULL 620 || p2pbridge->parent == NULL 621 || strcmp(p2pbridge->parent->name, "pci") != 0) 622 goto done; 623 if (pci_device_from_OF_node(p2pbridge, &bus, &devfn) < 0) { 624 DBG("Can't find PCI infos for PCI<->PCI bridge\n"); 625 goto done; 626 } 627 /* Warning: At this point, we have not yet renumbered all busses. 628 * So we must use OF walking to find out hose 629 */ 630 hose = pci_find_hose_for_OF_device(p2pbridge); 631 if (!hose) { 632 DBG("Can't find hose for PCI<->PCI bridge\n"); 633 goto done; 634 } 635 if (early_read_config_word(hose, bus, devfn, 636 PCI_BRIDGE_CONTROL, &val) < 0) { 637 printk(KERN_ERR "init_p2pbridge: couldn't read bridge" 638 " control\n"); 639 goto done; 640 } 641 val &= ~PCI_BRIDGE_CTL_MASTER_ABORT; 642 early_write_config_word(hose, bus, devfn, PCI_BRIDGE_CONTROL, val); 643 done: 644 of_node_put(p2pbridge); 645 } 646 647 static void __init init_second_ohare(void) 648 { 649 struct device_node *np = of_find_node_by_name(NULL, "pci106b,7"); 650 unsigned char bus, devfn; 651 unsigned short cmd; 652 653 if (np == NULL) 654 return; 655 656 /* This must run before we initialize the PICs since the second 657 * ohare hosts a PIC that will be accessed there. 658 */ 659 if (pci_device_from_OF_node(np, &bus, &devfn) == 0) { 660 struct pci_controller* hose = 661 pci_find_hose_for_OF_device(np); 662 if (!hose) { 663 printk(KERN_ERR "Can't find PCI hose for OHare2 !\n"); 664 return; 665 } 666 early_read_config_word(hose, bus, devfn, PCI_COMMAND, &cmd); 667 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; 668 cmd &= ~PCI_COMMAND_IO; 669 early_write_config_word(hose, bus, devfn, PCI_COMMAND, cmd); 670 } 671 has_second_ohare = 1; 672 } 673 674 /* 675 * Some Apple desktop machines have a NEC PD720100A USB2 controller 676 * on the motherboard. Open Firmware, on these, will disable the 677 * EHCI part of it so it behaves like a pair of OHCI's. This fixup 678 * code re-enables it ;) 679 */ 680 static void __init fixup_nec_usb2(void) 681 { 682 struct device_node *nec; 683 684 for (nec = NULL; (nec = of_find_node_by_name(nec, "usb")) != NULL;) { 685 struct pci_controller *hose; 686 u32 data; 687 const u32 *prop; 688 u8 bus, devfn; 689 690 prop = of_get_property(nec, "vendor-id", NULL); 691 if (prop == NULL) 692 continue; 693 if (0x1033 != *prop) 694 continue; 695 prop = of_get_property(nec, "device-id", NULL); 696 if (prop == NULL) 697 continue; 698 if (0x0035 != *prop) 699 continue; 700 prop = of_get_property(nec, "reg", NULL); 701 if (prop == NULL) 702 continue; 703 devfn = (prop[0] >> 8) & 0xff; 704 bus = (prop[0] >> 16) & 0xff; 705 if (PCI_FUNC(devfn) != 0) 706 continue; 707 hose = pci_find_hose_for_OF_device(nec); 708 if (!hose) 709 continue; 710 early_read_config_dword(hose, bus, devfn, 0xe4, &data); 711 if (data & 1UL) { 712 printk("Found NEC PD720100A USB2 chip with disabled" 713 " EHCI, fixing up...\n"); 714 data &= ~1UL; 715 early_write_config_dword(hose, bus, devfn, 0xe4, data); 716 } 717 } 718 } 719 720 static void __init setup_bandit(struct pci_controller *hose, 721 struct resource *addr) 722 { 723 hose->ops = ¯isc_pci_ops; 724 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 725 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 726 init_bandit(hose); 727 } 728 729 static int __init setup_uninorth(struct pci_controller *hose, 730 struct resource *addr) 731 { 732 ppc_pci_flags |= PPC_PCI_REASSIGN_ALL_BUS; 733 has_uninorth = 1; 734 hose->ops = ¯isc_pci_ops; 735 hose->cfg_addr = ioremap(addr->start + 0x800000, 0x1000); 736 hose->cfg_data = ioremap(addr->start + 0xc00000, 0x1000); 737 /* We "know" that the bridge at f2000000 has the PCI slots. */ 738 return addr->start == 0xf2000000; 739 } 740 #endif /* CONFIG_PPC32 */ 741 742 #ifdef CONFIG_PPC64 743 static void __init setup_u3_agp(struct pci_controller* hose) 744 { 745 /* On G5, we move AGP up to high bus number so we don't need 746 * to reassign bus numbers for HT. If we ever have P2P bridges 747 * on AGP, we'll have to move pci_assign_all_busses to the 748 * pci_controller structure so we enable it for AGP and not for 749 * HT childs. 750 * We hard code the address because of the different size of 751 * the reg address cell, we shall fix that by killing struct 752 * reg_property and using some accessor functions instead 753 */ 754 hose->first_busno = 0xf0; 755 hose->last_busno = 0xff; 756 has_uninorth = 1; 757 hose->ops = ¯isc_pci_ops; 758 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 759 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 760 u3_agp = hose; 761 } 762 763 static void __init setup_u4_pcie(struct pci_controller* hose) 764 { 765 /* We currently only implement the "non-atomic" config space, to 766 * be optimised later. 767 */ 768 hose->ops = &u4_pcie_pci_ops; 769 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 770 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 771 772 /* The bus contains a bridge from root -> device, we need to 773 * make it visible on bus 0 so that we pick the right type 774 * of config cycles. If we didn't, we would have to force all 775 * config cycles to be type 1. So we override the "bus-range" 776 * property here 777 */ 778 hose->first_busno = 0x00; 779 hose->last_busno = 0xff; 780 } 781 782 static void __init parse_region_decode(struct pci_controller *hose, 783 u32 decode) 784 { 785 unsigned long base, end, next = -1; 786 int i, cur = -1; 787 788 /* Iterate through all bits. We ignore the last bit as this region is 789 * reserved for the ROM among other niceties 790 */ 791 for (i = 0; i < 31; i++) { 792 if ((decode & (0x80000000 >> i)) == 0) 793 continue; 794 if (i < 16) { 795 base = 0xf0000000 | (((u32)i) << 24); 796 end = base + 0x00ffffff; 797 } else { 798 base = ((u32)i-16) << 28; 799 end = base + 0x0fffffff; 800 } 801 if (base != next) { 802 if (++cur >= 3) { 803 printk(KERN_WARNING "PCI: Too many ranges !\n"); 804 break; 805 } 806 hose->mem_resources[cur].flags = IORESOURCE_MEM; 807 hose->mem_resources[cur].name = hose->dn->full_name; 808 hose->mem_resources[cur].start = base; 809 hose->mem_resources[cur].end = end; 810 DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end); 811 } else { 812 DBG(" : -0x%08lx\n", end); 813 hose->mem_resources[cur].end = end; 814 } 815 next = end + 1; 816 } 817 } 818 819 static void __init setup_u3_ht(struct pci_controller* hose) 820 { 821 struct device_node *np = hose->dn; 822 struct resource cfg_res, self_res; 823 u32 decode; 824 825 hose->ops = &u3_ht_pci_ops; 826 827 /* Get base addresses from OF tree 828 */ 829 if (of_address_to_resource(np, 0, &cfg_res) || 830 of_address_to_resource(np, 1, &self_res)) { 831 printk(KERN_ERR "PCI: Failed to get U3/U4 HT resources !\n"); 832 return; 833 } 834 835 /* Map external cfg space access into cfg_data and self registers 836 * into cfg_addr 837 */ 838 hose->cfg_data = ioremap(cfg_res.start, 0x02000000); 839 hose->cfg_addr = ioremap(self_res.start, 840 self_res.end - self_res.start + 1); 841 842 /* 843 * /ht node doesn't expose a "ranges" property, we read the register 844 * that controls the decoding logic and use that for memory regions. 845 * The IO region is hard coded since it is fixed in HW as well. 846 */ 847 hose->io_base_phys = 0xf4000000; 848 hose->pci_io_size = 0x00400000; 849 hose->io_resource.name = np->full_name; 850 hose->io_resource.start = 0; 851 hose->io_resource.end = 0x003fffff; 852 hose->io_resource.flags = IORESOURCE_IO; 853 hose->pci_mem_offset = 0; 854 hose->first_busno = 0; 855 hose->last_busno = 0xef; 856 857 /* Note: fix offset when cfg_addr becomes a void * */ 858 decode = in_be32(hose->cfg_addr + 0x80); 859 860 DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode); 861 862 /* NOTE: The decode register setup is a bit weird... region 863 * 0xf8000000 for example is marked as enabled in there while it's 864 & actually the memory controller registers. 865 * That means that we are incorrectly attributing it to HT. 866 * 867 * In a similar vein, region 0xf4000000 is actually the HT IO space but 868 * also marked as enabled in here and 0xf9000000 is used by some other 869 * internal bits of the northbridge. 870 * 871 * Unfortunately, we can't just mask out those bit as we would end 872 * up with more regions than we can cope (linux can only cope with 873 * 3 memory regions for a PHB at this stage). 874 * 875 * So for now, we just do a little hack. We happen to -know- that 876 * Apple firmware doesn't assign things below 0xfa000000 for that 877 * bridge anyway so we mask out all bits we don't want. 878 */ 879 decode &= 0x003fffff; 880 881 /* Now parse the resulting bits and build resources */ 882 parse_region_decode(hose, decode); 883 } 884 #endif /* CONFIG_PPC64 */ 885 886 /* 887 * We assume that if we have a G3 powermac, we have one bridge called 888 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise, 889 * if we have one or more bandit or chaos bridges, we don't have a MPC106. 890 */ 891 static int __init pmac_add_bridge(struct device_node *dev) 892 { 893 int len; 894 struct pci_controller *hose; 895 struct resource rsrc; 896 char *disp_name; 897 const int *bus_range; 898 int primary = 1, has_address = 0; 899 900 DBG("Adding PCI host bridge %s\n", dev->full_name); 901 902 /* Fetch host bridge registers address */ 903 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); 904 905 /* Get bus range if any */ 906 bus_range = of_get_property(dev, "bus-range", &len); 907 if (bus_range == NULL || len < 2 * sizeof(int)) { 908 printk(KERN_WARNING "Can't get bus-range for %s, assume" 909 " bus 0\n", dev->full_name); 910 } 911 912 hose = pcibios_alloc_controller(dev); 913 if (!hose) 914 return -ENOMEM; 915 hose->first_busno = bus_range ? bus_range[0] : 0; 916 hose->last_busno = bus_range ? bus_range[1] : 0xff; 917 918 disp_name = NULL; 919 920 /* 64 bits only bridges */ 921 #ifdef CONFIG_PPC64 922 if (of_device_is_compatible(dev, "u3-agp")) { 923 setup_u3_agp(hose); 924 disp_name = "U3-AGP"; 925 primary = 0; 926 } else if (of_device_is_compatible(dev, "u3-ht")) { 927 setup_u3_ht(hose); 928 disp_name = "U3-HT"; 929 primary = 1; 930 } else if (of_device_is_compatible(dev, "u4-pcie")) { 931 setup_u4_pcie(hose); 932 disp_name = "U4-PCIE"; 933 primary = 0; 934 } 935 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number:" 936 " %d->%d\n", disp_name, hose->first_busno, hose->last_busno); 937 #endif /* CONFIG_PPC64 */ 938 939 /* 32 bits only bridges */ 940 #ifdef CONFIG_PPC32 941 if (of_device_is_compatible(dev, "uni-north")) { 942 primary = setup_uninorth(hose, &rsrc); 943 disp_name = "UniNorth"; 944 } else if (strcmp(dev->name, "pci") == 0) { 945 /* XXX assume this is a mpc106 (grackle) */ 946 setup_grackle(hose); 947 disp_name = "Grackle (MPC106)"; 948 } else if (strcmp(dev->name, "bandit") == 0) { 949 setup_bandit(hose, &rsrc); 950 disp_name = "Bandit"; 951 } else if (strcmp(dev->name, "chaos") == 0) { 952 setup_chaos(hose, &rsrc); 953 disp_name = "Chaos"; 954 primary = 0; 955 } 956 printk(KERN_INFO "Found %s PCI host bridge at 0x%016llx. " 957 "Firmware bus number: %d->%d\n", 958 disp_name, (unsigned long long)rsrc.start, hose->first_busno, 959 hose->last_busno); 960 #endif /* CONFIG_PPC32 */ 961 962 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 963 hose, hose->cfg_addr, hose->cfg_data); 964 965 /* Interpret the "ranges" property */ 966 /* This also maps the I/O region and sets isa_io/mem_base */ 967 pci_process_bridge_OF_ranges(hose, dev, primary); 968 969 /* Fixup "bus-range" OF property */ 970 fixup_bus_range(dev); 971 972 return 0; 973 } 974 975 void __devinit pmac_pci_irq_fixup(struct pci_dev *dev) 976 { 977 #ifdef CONFIG_PPC32 978 /* Fixup interrupt for the modem/ethernet combo controller. 979 * on machines with a second ohare chip. 980 * The number in the device tree (27) is bogus (correct for 981 * the ethernet-only board but not the combo ethernet/modem 982 * board). The real interrupt is 28 on the second controller 983 * -> 28+32 = 60. 984 */ 985 if (has_second_ohare && 986 dev->vendor == PCI_VENDOR_ID_DEC && 987 dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) { 988 dev->irq = irq_create_mapping(NULL, 60); 989 set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); 990 } 991 #endif /* CONFIG_PPC32 */ 992 } 993 994 void __init pmac_pci_init(void) 995 { 996 struct device_node *np, *root; 997 struct device_node *ht = NULL; 998 999 ppc_pci_flags = PPC_PCI_CAN_SKIP_ISA_ALIGN; 1000 1001 root = of_find_node_by_path("/"); 1002 if (root == NULL) { 1003 printk(KERN_CRIT "pmac_pci_init: can't find root " 1004 "of device tree\n"); 1005 return; 1006 } 1007 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { 1008 if (np->name == NULL) 1009 continue; 1010 if (strcmp(np->name, "bandit") == 0 1011 || strcmp(np->name, "chaos") == 0 1012 || strcmp(np->name, "pci") == 0) { 1013 if (pmac_add_bridge(np) == 0) 1014 of_node_get(np); 1015 } 1016 if (strcmp(np->name, "ht") == 0) { 1017 of_node_get(np); 1018 ht = np; 1019 } 1020 } 1021 of_node_put(root); 1022 1023 #ifdef CONFIG_PPC64 1024 /* Probe HT last as it relies on the agp resources to be already 1025 * setup 1026 */ 1027 if (ht && pmac_add_bridge(ht) != 0) 1028 of_node_put(ht); 1029 1030 /* Setup the linkage between OF nodes and PHBs */ 1031 pci_devs_phb_init(); 1032 1033 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We 1034 * assume there is no P2P bridge on the AGP bus, which should be a 1035 * safe assumptions for now. We should do something better in the 1036 * future though 1037 */ 1038 if (u3_agp) { 1039 struct device_node *np = u3_agp->dn; 1040 PCI_DN(np)->busno = 0xf0; 1041 for (np = np->child; np; np = np->sibling) 1042 PCI_DN(np)->busno = 0xf0; 1043 } 1044 /* pmac_check_ht_link(); */ 1045 1046 /* We can allocate missing resources if any */ 1047 pci_probe_only = 0; 1048 1049 #else /* CONFIG_PPC64 */ 1050 init_p2pbridge(); 1051 init_second_ohare(); 1052 fixup_nec_usb2(); 1053 1054 /* We are still having some issues with the Xserve G4, enabling 1055 * some offset between bus number and domains for now when we 1056 * assign all busses should help for now 1057 */ 1058 if (ppc_pci_flags & PPC_PCI_REASSIGN_ALL_BUS) 1059 pcibios_assign_bus_offset = 0x10; 1060 #endif 1061 } 1062 1063 #ifdef CONFIG_PPC32 1064 int pmac_pci_enable_device_hook(struct pci_dev *dev) 1065 { 1066 struct device_node* node; 1067 int updatecfg = 0; 1068 int uninorth_child; 1069 1070 node = pci_device_to_OF_node(dev); 1071 1072 /* We don't want to enable USB controllers absent from the OF tree 1073 * (iBook second controller) 1074 */ 1075 if (dev->vendor == PCI_VENDOR_ID_APPLE 1076 && dev->class == PCI_CLASS_SERIAL_USB_OHCI 1077 && !node) { 1078 printk(KERN_INFO "Apple USB OHCI %s disabled by firmware\n", 1079 pci_name(dev)); 1080 return -EINVAL; 1081 } 1082 1083 if (!node) 1084 return 0; 1085 1086 uninorth_child = node->parent && 1087 of_device_is_compatible(node->parent, "uni-north"); 1088 1089 /* Firewire & GMAC were disabled after PCI probe, the driver is 1090 * claiming them, we must re-enable them now. 1091 */ 1092 if (uninorth_child && !strcmp(node->name, "firewire") && 1093 (of_device_is_compatible(node, "pci106b,18") || 1094 of_device_is_compatible(node, "pci106b,30") || 1095 of_device_is_compatible(node, "pci11c1,5811"))) { 1096 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, node, 0, 1); 1097 pmac_call_feature(PMAC_FTR_1394_ENABLE, node, 0, 1); 1098 updatecfg = 1; 1099 } 1100 if (uninorth_child && !strcmp(node->name, "ethernet") && 1101 of_device_is_compatible(node, "gmac")) { 1102 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, node, 0, 1); 1103 updatecfg = 1; 1104 } 1105 1106 /* 1107 * Fixup various header fields on 32 bits. We don't do that on 1108 * 64 bits as some of these have strange values behind the HT 1109 * bridge and we must not, for example, enable MWI or set the 1110 * cache line size on them. 1111 */ 1112 if (updatecfg) { 1113 u16 cmd; 1114 1115 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1116 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 1117 | PCI_COMMAND_INVALIDATE; 1118 pci_write_config_word(dev, PCI_COMMAND, cmd); 1119 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 16); 1120 1121 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 1122 L1_CACHE_BYTES >> 2); 1123 } 1124 1125 return 0; 1126 } 1127 1128 void __devinit pmac_pci_fixup_ohci(struct pci_dev *dev) 1129 { 1130 struct device_node *node = pci_device_to_OF_node(dev); 1131 1132 /* We don't want to assign resources to USB controllers 1133 * absent from the OF tree (iBook second controller) 1134 */ 1135 if (dev->class == PCI_CLASS_SERIAL_USB_OHCI && !node) 1136 dev->resource[0].flags = 0; 1137 } 1138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_APPLE, PCI_ANY_ID, pmac_pci_fixup_ohci); 1139 1140 /* We power down some devices after they have been probed. They'll 1141 * be powered back on later on 1142 */ 1143 void __init pmac_pcibios_after_init(void) 1144 { 1145 struct device_node* nd; 1146 1147 #ifdef CONFIG_BLK_DEV_IDE 1148 struct pci_dev *dev = NULL; 1149 1150 /* OF fails to initialize IDE controllers on macs 1151 * (and maybe other machines) 1152 * 1153 * Ideally, this should be moved to the IDE layer, but we need 1154 * to check specifically with Andre Hedrick how to do it cleanly 1155 * since the common IDE code seem to care about the fact that the 1156 * BIOS may have disabled a controller. 1157 * 1158 * -- BenH 1159 */ 1160 for_each_pci_dev(dev) { 1161 if ((dev->class >> 16) != PCI_BASE_CLASS_STORAGE) 1162 continue; 1163 if (pci_enable_device(dev)) 1164 printk(KERN_WARNING 1165 "pci: Failed to enable %s\n", pci_name(dev)); 1166 } 1167 #endif /* CONFIG_BLK_DEV_IDE */ 1168 1169 for_each_node_by_name(nd, "firewire") { 1170 if (nd->parent && (of_device_is_compatible(nd, "pci106b,18") || 1171 of_device_is_compatible(nd, "pci106b,30") || 1172 of_device_is_compatible(nd, "pci11c1,5811")) 1173 && of_device_is_compatible(nd->parent, "uni-north")) { 1174 pmac_call_feature(PMAC_FTR_1394_ENABLE, nd, 0, 0); 1175 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, nd, 0, 0); 1176 } 1177 } 1178 of_node_put(nd); 1179 for_each_node_by_name(nd, "ethernet") { 1180 if (nd->parent && of_device_is_compatible(nd, "gmac") 1181 && of_device_is_compatible(nd->parent, "uni-north")) 1182 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, nd, 0, 0); 1183 } 1184 of_node_put(nd); 1185 } 1186 1187 void pmac_pci_fixup_cardbus(struct pci_dev* dev) 1188 { 1189 if (!machine_is(powermac)) 1190 return; 1191 /* 1192 * Fix the interrupt routing on the various cardbus bridges 1193 * used on powerbooks 1194 */ 1195 if (dev->vendor != PCI_VENDOR_ID_TI) 1196 return; 1197 if (dev->device == PCI_DEVICE_ID_TI_1130 || 1198 dev->device == PCI_DEVICE_ID_TI_1131) { 1199 u8 val; 1200 /* Enable PCI interrupt */ 1201 if (pci_read_config_byte(dev, 0x91, &val) == 0) 1202 pci_write_config_byte(dev, 0x91, val | 0x30); 1203 /* Disable ISA interrupt mode */ 1204 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1205 pci_write_config_byte(dev, 0x92, val & ~0x06); 1206 } 1207 if (dev->device == PCI_DEVICE_ID_TI_1210 || 1208 dev->device == PCI_DEVICE_ID_TI_1211 || 1209 dev->device == PCI_DEVICE_ID_TI_1410 || 1210 dev->device == PCI_DEVICE_ID_TI_1510) { 1211 u8 val; 1212 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA 1213 signal out the MFUNC0 pin */ 1214 if (pci_read_config_byte(dev, 0x8c, &val) == 0) 1215 pci_write_config_byte(dev, 0x8c, (val & ~0x0f) | 2); 1216 /* Disable ISA interrupt mode */ 1217 if (pci_read_config_byte(dev, 0x92, &val) == 0) 1218 pci_write_config_byte(dev, 0x92, val & ~0x06); 1219 } 1220 } 1221 1222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_ANY_ID, pmac_pci_fixup_cardbus); 1223 1224 void pmac_pci_fixup_pciata(struct pci_dev* dev) 1225 { 1226 u8 progif = 0; 1227 1228 /* 1229 * On PowerMacs, we try to switch any PCI ATA controller to 1230 * fully native mode 1231 */ 1232 if (!machine_is(powermac)) 1233 return; 1234 1235 /* Some controllers don't have the class IDE */ 1236 if (dev->vendor == PCI_VENDOR_ID_PROMISE) 1237 switch(dev->device) { 1238 case PCI_DEVICE_ID_PROMISE_20246: 1239 case PCI_DEVICE_ID_PROMISE_20262: 1240 case PCI_DEVICE_ID_PROMISE_20263: 1241 case PCI_DEVICE_ID_PROMISE_20265: 1242 case PCI_DEVICE_ID_PROMISE_20267: 1243 case PCI_DEVICE_ID_PROMISE_20268: 1244 case PCI_DEVICE_ID_PROMISE_20269: 1245 case PCI_DEVICE_ID_PROMISE_20270: 1246 case PCI_DEVICE_ID_PROMISE_20271: 1247 case PCI_DEVICE_ID_PROMISE_20275: 1248 case PCI_DEVICE_ID_PROMISE_20276: 1249 case PCI_DEVICE_ID_PROMISE_20277: 1250 goto good; 1251 } 1252 /* Others, check PCI class */ 1253 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) 1254 return; 1255 good: 1256 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 1257 if ((progif & 5) != 5) { 1258 printk(KERN_INFO "PCI: %s Forcing PCI IDE into native mode\n", 1259 pci_name(dev)); 1260 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); 1261 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || 1262 (progif & 5) != 5) 1263 printk(KERN_ERR "Rewrite of PROGIF failed !\n"); 1264 else { 1265 /* Clear IO BARs, they will be reassigned */ 1266 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0); 1267 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0); 1268 pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, 0); 1269 pci_write_config_dword(dev, PCI_BASE_ADDRESS_3, 0); 1270 } 1271 } 1272 } 1273 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, pmac_pci_fixup_pciata); 1274 #endif /* CONFIG_PPC32 */ 1275 1276 /* 1277 * Disable second function on K2-SATA, it's broken 1278 * and disable IO BARs on first one 1279 */ 1280 static void fixup_k2_sata(struct pci_dev* dev) 1281 { 1282 int i; 1283 u16 cmd; 1284 1285 if (PCI_FUNC(dev->devfn) > 0) { 1286 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1287 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1288 pci_write_config_word(dev, PCI_COMMAND, cmd); 1289 for (i = 0; i < 6; i++) { 1290 dev->resource[i].start = dev->resource[i].end = 0; 1291 dev->resource[i].flags = 0; 1292 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1293 0); 1294 } 1295 } else { 1296 pci_read_config_word(dev, PCI_COMMAND, &cmd); 1297 cmd &= ~PCI_COMMAND_IO; 1298 pci_write_config_word(dev, PCI_COMMAND, cmd); 1299 for (i = 0; i < 5; i++) { 1300 dev->resource[i].start = dev->resource[i].end = 0; 1301 dev->resource[i].flags = 0; 1302 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 1303 0); 1304 } 1305 } 1306 } 1307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata); 1308 1309