1 /* 2 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au) 3 * Ben. Herrenschmidt (benh@kernel.crashing.org) 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * TODO: 11 * 12 * - Replace mdelay with some schedule loop if possible 13 * - Shorten some obfuscated delays on some routines (like modem 14 * power) 15 * - Refcount some clocks (see darwin) 16 * - Split split split... 17 * 18 */ 19 #include <linux/types.h> 20 #include <linux/init.h> 21 #include <linux/delay.h> 22 #include <linux/kernel.h> 23 #include <linux/sched.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/spinlock.h> 27 #include <linux/adb.h> 28 #include <linux/pmu.h> 29 #include <linux/ioport.h> 30 #include <linux/export.h> 31 #include <linux/pci.h> 32 #include <asm/sections.h> 33 #include <asm/errno.h> 34 #include <asm/ohare.h> 35 #include <asm/heathrow.h> 36 #include <asm/keylargo.h> 37 #include <asm/uninorth.h> 38 #include <asm/io.h> 39 #include <asm/prom.h> 40 #include <asm/machdep.h> 41 #include <asm/pmac_feature.h> 42 #include <asm/dbdma.h> 43 #include <asm/pci-bridge.h> 44 #include <asm/pmac_low_i2c.h> 45 46 #undef DEBUG_FEATURE 47 48 #ifdef DEBUG_FEATURE 49 #define DBG(fmt...) printk(KERN_DEBUG fmt) 50 #else 51 #define DBG(fmt...) 52 #endif 53 54 #ifdef CONFIG_PPC_BOOK3S_32 55 extern int powersave_lowspeed; 56 #endif 57 58 extern int powersave_nap; 59 extern struct device_node *k2_skiplist[2]; 60 61 /* 62 * We use a single global lock to protect accesses. Each driver has 63 * to take care of its own locking 64 */ 65 DEFINE_RAW_SPINLOCK(feature_lock); 66 67 #define LOCK(flags) raw_spin_lock_irqsave(&feature_lock, flags); 68 #define UNLOCK(flags) raw_spin_unlock_irqrestore(&feature_lock, flags); 69 70 71 /* 72 * Instance of some macio stuffs 73 */ 74 struct macio_chip macio_chips[MAX_MACIO_CHIPS]; 75 76 struct macio_chip *macio_find(struct device_node *child, int type) 77 { 78 while(child) { 79 int i; 80 81 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++) 82 if (child == macio_chips[i].of_node && 83 (!type || macio_chips[i].type == type)) 84 return &macio_chips[i]; 85 child = child->parent; 86 } 87 return NULL; 88 } 89 EXPORT_SYMBOL_GPL(macio_find); 90 91 static const char *macio_names[] = 92 { 93 "Unknown", 94 "Grand Central", 95 "OHare", 96 "OHareII", 97 "Heathrow", 98 "Gatwick", 99 "Paddington", 100 "Keylargo", 101 "Pangea", 102 "Intrepid", 103 "K2", 104 "Shasta", 105 }; 106 107 108 struct device_node *uninorth_node; 109 u32 __iomem *uninorth_base; 110 111 static u32 uninorth_rev; 112 static int uninorth_maj; 113 static void __iomem *u3_ht_base; 114 115 /* 116 * For each motherboard family, we have a table of functions pointers 117 * that handle the various features. 118 */ 119 120 typedef long (*feature_call)(struct device_node *node, long param, long value); 121 122 struct feature_table_entry { 123 unsigned int selector; 124 feature_call function; 125 }; 126 127 struct pmac_mb_def 128 { 129 const char* model_string; 130 const char* model_name; 131 int model_id; 132 struct feature_table_entry* features; 133 unsigned long board_flags; 134 }; 135 static struct pmac_mb_def pmac_mb; 136 137 /* 138 * Here are the chip specific feature functions 139 */ 140 141 static inline int simple_feature_tweak(struct device_node *node, int type, 142 int reg, u32 mask, int value) 143 { 144 struct macio_chip* macio; 145 unsigned long flags; 146 147 macio = macio_find(node, type); 148 if (!macio) 149 return -ENODEV; 150 LOCK(flags); 151 if (value) 152 MACIO_BIS(reg, mask); 153 else 154 MACIO_BIC(reg, mask); 155 (void)MACIO_IN32(reg); 156 UNLOCK(flags); 157 158 return 0; 159 } 160 161 #ifndef CONFIG_PPC64 162 163 static long ohare_htw_scc_enable(struct device_node *node, long param, 164 long value) 165 { 166 struct macio_chip* macio; 167 unsigned long chan_mask; 168 unsigned long fcr; 169 unsigned long flags; 170 int htw, trans; 171 unsigned long rmask; 172 173 macio = macio_find(node, 0); 174 if (!macio) 175 return -ENODEV; 176 if (of_node_name_eq(node, "ch-a")) 177 chan_mask = MACIO_FLAG_SCCA_ON; 178 else if (of_node_name_eq(node, "ch-b")) 179 chan_mask = MACIO_FLAG_SCCB_ON; 180 else 181 return -ENODEV; 182 183 htw = (macio->type == macio_heathrow || macio->type == macio_paddington 184 || macio->type == macio_gatwick); 185 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */ 186 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE && 187 pmac_mb.model_id != PMAC_TYPE_YIKES); 188 if (value) { 189 #ifdef CONFIG_ADB_PMU 190 if ((param & 0xfff) == PMAC_SCC_IRDA) 191 pmu_enable_irled(1); 192 #endif /* CONFIG_ADB_PMU */ 193 LOCK(flags); 194 fcr = MACIO_IN32(OHARE_FCR); 195 /* Check if scc cell need enabling */ 196 if (!(fcr & OH_SCC_ENABLE)) { 197 fcr |= OH_SCC_ENABLE; 198 if (htw) { 199 /* Side effect: this will also power up the 200 * modem, but it's too messy to figure out on which 201 * ports this controls the transceiver and on which 202 * it controls the modem 203 */ 204 if (trans) 205 fcr &= ~HRW_SCC_TRANS_EN_N; 206 MACIO_OUT32(OHARE_FCR, fcr); 207 fcr |= (rmask = HRW_RESET_SCC); 208 MACIO_OUT32(OHARE_FCR, fcr); 209 } else { 210 fcr |= (rmask = OH_SCC_RESET); 211 MACIO_OUT32(OHARE_FCR, fcr); 212 } 213 UNLOCK(flags); 214 (void)MACIO_IN32(OHARE_FCR); 215 mdelay(15); 216 LOCK(flags); 217 fcr &= ~rmask; 218 MACIO_OUT32(OHARE_FCR, fcr); 219 } 220 if (chan_mask & MACIO_FLAG_SCCA_ON) 221 fcr |= OH_SCCA_IO; 222 if (chan_mask & MACIO_FLAG_SCCB_ON) 223 fcr |= OH_SCCB_IO; 224 MACIO_OUT32(OHARE_FCR, fcr); 225 macio->flags |= chan_mask; 226 UNLOCK(flags); 227 if (param & PMAC_SCC_FLAG_XMON) 228 macio->flags |= MACIO_FLAG_SCC_LOCKED; 229 } else { 230 if (macio->flags & MACIO_FLAG_SCC_LOCKED) 231 return -EPERM; 232 LOCK(flags); 233 fcr = MACIO_IN32(OHARE_FCR); 234 if (chan_mask & MACIO_FLAG_SCCA_ON) 235 fcr &= ~OH_SCCA_IO; 236 if (chan_mask & MACIO_FLAG_SCCB_ON) 237 fcr &= ~OH_SCCB_IO; 238 MACIO_OUT32(OHARE_FCR, fcr); 239 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) { 240 fcr &= ~OH_SCC_ENABLE; 241 if (htw && trans) 242 fcr |= HRW_SCC_TRANS_EN_N; 243 MACIO_OUT32(OHARE_FCR, fcr); 244 } 245 macio->flags &= ~(chan_mask); 246 UNLOCK(flags); 247 mdelay(10); 248 #ifdef CONFIG_ADB_PMU 249 if ((param & 0xfff) == PMAC_SCC_IRDA) 250 pmu_enable_irled(0); 251 #endif /* CONFIG_ADB_PMU */ 252 } 253 return 0; 254 } 255 256 static long ohare_floppy_enable(struct device_node *node, long param, 257 long value) 258 { 259 return simple_feature_tweak(node, macio_ohare, 260 OHARE_FCR, OH_FLOPPY_ENABLE, value); 261 } 262 263 static long ohare_mesh_enable(struct device_node *node, long param, long value) 264 { 265 return simple_feature_tweak(node, macio_ohare, 266 OHARE_FCR, OH_MESH_ENABLE, value); 267 } 268 269 static long ohare_ide_enable(struct device_node *node, long param, long value) 270 { 271 switch(param) { 272 case 0: 273 /* For some reason, setting the bit in set_initial_features() 274 * doesn't stick. I'm still investigating... --BenH. 275 */ 276 if (value) 277 simple_feature_tweak(node, macio_ohare, 278 OHARE_FCR, OH_IOBUS_ENABLE, 1); 279 return simple_feature_tweak(node, macio_ohare, 280 OHARE_FCR, OH_IDE0_ENABLE, value); 281 case 1: 282 return simple_feature_tweak(node, macio_ohare, 283 OHARE_FCR, OH_BAY_IDE_ENABLE, value); 284 default: 285 return -ENODEV; 286 } 287 } 288 289 static long ohare_ide_reset(struct device_node *node, long param, long value) 290 { 291 switch(param) { 292 case 0: 293 return simple_feature_tweak(node, macio_ohare, 294 OHARE_FCR, OH_IDE0_RESET_N, !value); 295 case 1: 296 return simple_feature_tweak(node, macio_ohare, 297 OHARE_FCR, OH_IDE1_RESET_N, !value); 298 default: 299 return -ENODEV; 300 } 301 } 302 303 static long ohare_sleep_state(struct device_node *node, long param, long value) 304 { 305 struct macio_chip* macio = &macio_chips[0]; 306 307 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 308 return -EPERM; 309 if (value == 1) { 310 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE); 311 } else if (value == 0) { 312 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 313 } 314 315 return 0; 316 } 317 318 static long heathrow_modem_enable(struct device_node *node, long param, 319 long value) 320 { 321 struct macio_chip* macio; 322 u8 gpio; 323 unsigned long flags; 324 325 macio = macio_find(node, macio_unknown); 326 if (!macio) 327 return -ENODEV; 328 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1; 329 if (!value) { 330 LOCK(flags); 331 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio); 332 UNLOCK(flags); 333 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 334 mdelay(250); 335 } 336 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE && 337 pmac_mb.model_id != PMAC_TYPE_YIKES) { 338 LOCK(flags); 339 if (value) 340 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 341 else 342 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 343 UNLOCK(flags); 344 (void)MACIO_IN32(HEATHROW_FCR); 345 mdelay(250); 346 } 347 if (value) { 348 LOCK(flags); 349 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1); 350 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 351 UNLOCK(flags); mdelay(250); LOCK(flags); 352 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio); 353 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 354 UNLOCK(flags); mdelay(250); LOCK(flags); 355 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1); 356 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 357 UNLOCK(flags); mdelay(250); 358 } 359 return 0; 360 } 361 362 static long heathrow_floppy_enable(struct device_node *node, long param, 363 long value) 364 { 365 return simple_feature_tweak(node, macio_unknown, 366 HEATHROW_FCR, 367 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE, 368 value); 369 } 370 371 static long heathrow_mesh_enable(struct device_node *node, long param, 372 long value) 373 { 374 struct macio_chip* macio; 375 unsigned long flags; 376 377 macio = macio_find(node, macio_unknown); 378 if (!macio) 379 return -ENODEV; 380 LOCK(flags); 381 /* Set clear mesh cell enable */ 382 if (value) 383 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE); 384 else 385 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE); 386 (void)MACIO_IN32(HEATHROW_FCR); 387 udelay(10); 388 /* Set/Clear termination power */ 389 if (value) 390 MACIO_BIC(HEATHROW_MBCR, 0x04000000); 391 else 392 MACIO_BIS(HEATHROW_MBCR, 0x04000000); 393 (void)MACIO_IN32(HEATHROW_MBCR); 394 udelay(10); 395 UNLOCK(flags); 396 397 return 0; 398 } 399 400 static long heathrow_ide_enable(struct device_node *node, long param, 401 long value) 402 { 403 switch(param) { 404 case 0: 405 return simple_feature_tweak(node, macio_unknown, 406 HEATHROW_FCR, HRW_IDE0_ENABLE, value); 407 case 1: 408 return simple_feature_tweak(node, macio_unknown, 409 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value); 410 default: 411 return -ENODEV; 412 } 413 } 414 415 static long heathrow_ide_reset(struct device_node *node, long param, 416 long value) 417 { 418 switch(param) { 419 case 0: 420 return simple_feature_tweak(node, macio_unknown, 421 HEATHROW_FCR, HRW_IDE0_RESET_N, !value); 422 case 1: 423 return simple_feature_tweak(node, macio_unknown, 424 HEATHROW_FCR, HRW_IDE1_RESET_N, !value); 425 default: 426 return -ENODEV; 427 } 428 } 429 430 static long heathrow_bmac_enable(struct device_node *node, long param, 431 long value) 432 { 433 struct macio_chip* macio; 434 unsigned long flags; 435 436 macio = macio_find(node, 0); 437 if (!macio) 438 return -ENODEV; 439 if (value) { 440 LOCK(flags); 441 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE); 442 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET); 443 UNLOCK(flags); 444 (void)MACIO_IN32(HEATHROW_FCR); 445 mdelay(10); 446 LOCK(flags); 447 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET); 448 UNLOCK(flags); 449 (void)MACIO_IN32(HEATHROW_FCR); 450 mdelay(10); 451 } else { 452 LOCK(flags); 453 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE); 454 UNLOCK(flags); 455 } 456 return 0; 457 } 458 459 static long heathrow_sound_enable(struct device_node *node, long param, 460 long value) 461 { 462 struct macio_chip* macio; 463 unsigned long flags; 464 465 /* B&W G3 and Yikes don't support that properly (the 466 * sound appear to never come back after being shut down). 467 */ 468 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE || 469 pmac_mb.model_id == PMAC_TYPE_YIKES) 470 return 0; 471 472 macio = macio_find(node, 0); 473 if (!macio) 474 return -ENODEV; 475 if (value) { 476 LOCK(flags); 477 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 478 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N); 479 UNLOCK(flags); 480 (void)MACIO_IN32(HEATHROW_FCR); 481 } else { 482 LOCK(flags); 483 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N); 484 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 485 UNLOCK(flags); 486 } 487 return 0; 488 } 489 490 static u32 save_fcr[6]; 491 static u32 save_mbcr; 492 static struct dbdma_regs save_dbdma[13]; 493 static struct dbdma_regs save_alt_dbdma[13]; 494 495 static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save) 496 { 497 int i; 498 499 /* Save state & config of DBDMA channels */ 500 for (i = 0; i < 13; i++) { 501 volatile struct dbdma_regs __iomem * chan = (void __iomem *) 502 (macio->base + ((0x8000+i*0x100)>>2)); 503 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi); 504 save[i].cmdptr = in_le32(&chan->cmdptr); 505 save[i].intr_sel = in_le32(&chan->intr_sel); 506 save[i].br_sel = in_le32(&chan->br_sel); 507 save[i].wait_sel = in_le32(&chan->wait_sel); 508 } 509 } 510 511 static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save) 512 { 513 int i; 514 515 /* Save state & config of DBDMA channels */ 516 for (i = 0; i < 13; i++) { 517 volatile struct dbdma_regs __iomem * chan = (void __iomem *) 518 (macio->base + ((0x8000+i*0x100)>>2)); 519 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16); 520 while (in_le32(&chan->status) & ACTIVE) 521 mb(); 522 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi); 523 out_le32(&chan->cmdptr, save[i].cmdptr); 524 out_le32(&chan->intr_sel, save[i].intr_sel); 525 out_le32(&chan->br_sel, save[i].br_sel); 526 out_le32(&chan->wait_sel, save[i].wait_sel); 527 } 528 } 529 530 static void heathrow_sleep(struct macio_chip *macio, int secondary) 531 { 532 if (secondary) { 533 dbdma_save(macio, save_alt_dbdma); 534 save_fcr[2] = MACIO_IN32(0x38); 535 save_fcr[3] = MACIO_IN32(0x3c); 536 } else { 537 dbdma_save(macio, save_dbdma); 538 save_fcr[0] = MACIO_IN32(0x38); 539 save_fcr[1] = MACIO_IN32(0x3c); 540 save_mbcr = MACIO_IN32(0x34); 541 /* Make sure sound is shut down */ 542 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N); 543 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 544 /* This seems to be necessary as well or the fan 545 * keeps coming up and battery drains fast */ 546 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE); 547 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N); 548 /* Make sure eth is down even if module or sleep 549 * won't work properly */ 550 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET); 551 } 552 /* Make sure modem is shut down */ 553 MACIO_OUT8(HRW_GPIO_MODEM_RESET, 554 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1); 555 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 556 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE); 557 558 /* Let things settle */ 559 (void)MACIO_IN32(HEATHROW_FCR); 560 } 561 562 static void heathrow_wakeup(struct macio_chip *macio, int secondary) 563 { 564 if (secondary) { 565 MACIO_OUT32(0x38, save_fcr[2]); 566 (void)MACIO_IN32(0x38); 567 mdelay(1); 568 MACIO_OUT32(0x3c, save_fcr[3]); 569 (void)MACIO_IN32(0x38); 570 mdelay(10); 571 dbdma_restore(macio, save_alt_dbdma); 572 } else { 573 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE); 574 (void)MACIO_IN32(0x38); 575 mdelay(1); 576 MACIO_OUT32(0x3c, save_fcr[1]); 577 (void)MACIO_IN32(0x38); 578 mdelay(1); 579 MACIO_OUT32(0x34, save_mbcr); 580 (void)MACIO_IN32(0x38); 581 mdelay(10); 582 dbdma_restore(macio, save_dbdma); 583 } 584 } 585 586 static long heathrow_sleep_state(struct device_node *node, long param, 587 long value) 588 { 589 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 590 return -EPERM; 591 if (value == 1) { 592 if (macio_chips[1].type == macio_gatwick) 593 heathrow_sleep(&macio_chips[0], 1); 594 heathrow_sleep(&macio_chips[0], 0); 595 } else if (value == 0) { 596 heathrow_wakeup(&macio_chips[0], 0); 597 if (macio_chips[1].type == macio_gatwick) 598 heathrow_wakeup(&macio_chips[0], 1); 599 } 600 return 0; 601 } 602 603 static long core99_scc_enable(struct device_node *node, long param, long value) 604 { 605 struct macio_chip* macio; 606 unsigned long flags; 607 unsigned long chan_mask; 608 u32 fcr; 609 610 macio = macio_find(node, 0); 611 if (!macio) 612 return -ENODEV; 613 if (of_node_name_eq(node, "ch-a")) 614 chan_mask = MACIO_FLAG_SCCA_ON; 615 else if (of_node_name_eq(node, "ch-b")) 616 chan_mask = MACIO_FLAG_SCCB_ON; 617 else 618 return -ENODEV; 619 620 if (value) { 621 int need_reset_scc = 0; 622 int need_reset_irda = 0; 623 624 LOCK(flags); 625 fcr = MACIO_IN32(KEYLARGO_FCR0); 626 /* Check if scc cell need enabling */ 627 if (!(fcr & KL0_SCC_CELL_ENABLE)) { 628 fcr |= KL0_SCC_CELL_ENABLE; 629 need_reset_scc = 1; 630 } 631 if (chan_mask & MACIO_FLAG_SCCA_ON) { 632 fcr |= KL0_SCCA_ENABLE; 633 /* Don't enable line drivers for I2S modem */ 634 if ((param & 0xfff) == PMAC_SCC_I2S1) 635 fcr &= ~KL0_SCC_A_INTF_ENABLE; 636 else 637 fcr |= KL0_SCC_A_INTF_ENABLE; 638 } 639 if (chan_mask & MACIO_FLAG_SCCB_ON) { 640 fcr |= KL0_SCCB_ENABLE; 641 /* Perform irda specific inits */ 642 if ((param & 0xfff) == PMAC_SCC_IRDA) { 643 fcr &= ~KL0_SCC_B_INTF_ENABLE; 644 fcr |= KL0_IRDA_ENABLE; 645 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE; 646 fcr |= KL0_IRDA_SOURCE1_SEL; 647 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); 648 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); 649 need_reset_irda = 1; 650 } else 651 fcr |= KL0_SCC_B_INTF_ENABLE; 652 } 653 MACIO_OUT32(KEYLARGO_FCR0, fcr); 654 macio->flags |= chan_mask; 655 if (need_reset_scc) { 656 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET); 657 (void)MACIO_IN32(KEYLARGO_FCR0); 658 UNLOCK(flags); 659 mdelay(15); 660 LOCK(flags); 661 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET); 662 } 663 if (need_reset_irda) { 664 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET); 665 (void)MACIO_IN32(KEYLARGO_FCR0); 666 UNLOCK(flags); 667 mdelay(15); 668 LOCK(flags); 669 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET); 670 } 671 UNLOCK(flags); 672 if (param & PMAC_SCC_FLAG_XMON) 673 macio->flags |= MACIO_FLAG_SCC_LOCKED; 674 } else { 675 if (macio->flags & MACIO_FLAG_SCC_LOCKED) 676 return -EPERM; 677 LOCK(flags); 678 fcr = MACIO_IN32(KEYLARGO_FCR0); 679 if (chan_mask & MACIO_FLAG_SCCA_ON) 680 fcr &= ~KL0_SCCA_ENABLE; 681 if (chan_mask & MACIO_FLAG_SCCB_ON) { 682 fcr &= ~KL0_SCCB_ENABLE; 683 /* Perform irda specific clears */ 684 if ((param & 0xfff) == PMAC_SCC_IRDA) { 685 fcr &= ~KL0_IRDA_ENABLE; 686 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE); 687 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); 688 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); 689 } 690 } 691 MACIO_OUT32(KEYLARGO_FCR0, fcr); 692 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) { 693 fcr &= ~KL0_SCC_CELL_ENABLE; 694 MACIO_OUT32(KEYLARGO_FCR0, fcr); 695 } 696 macio->flags &= ~(chan_mask); 697 UNLOCK(flags); 698 mdelay(10); 699 } 700 return 0; 701 } 702 703 static long 704 core99_modem_enable(struct device_node *node, long param, long value) 705 { 706 struct macio_chip* macio; 707 u8 gpio; 708 unsigned long flags; 709 710 /* Hack for internal USB modem */ 711 if (node == NULL) { 712 if (macio_chips[0].type != macio_keylargo) 713 return -ENODEV; 714 node = macio_chips[0].of_node; 715 } 716 macio = macio_find(node, 0); 717 if (!macio) 718 return -ENODEV; 719 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET); 720 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE; 721 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA; 722 723 if (!value) { 724 LOCK(flags); 725 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 726 UNLOCK(flags); 727 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 728 mdelay(250); 729 } 730 LOCK(flags); 731 if (value) { 732 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 733 UNLOCK(flags); 734 (void)MACIO_IN32(KEYLARGO_FCR2); 735 mdelay(250); 736 } else { 737 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 738 UNLOCK(flags); 739 } 740 if (value) { 741 LOCK(flags); 742 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 743 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 744 UNLOCK(flags); mdelay(250); LOCK(flags); 745 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 746 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 747 UNLOCK(flags); mdelay(250); LOCK(flags); 748 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 749 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 750 UNLOCK(flags); mdelay(250); 751 } 752 return 0; 753 } 754 755 static long 756 pangea_modem_enable(struct device_node *node, long param, long value) 757 { 758 struct macio_chip* macio; 759 u8 gpio; 760 unsigned long flags; 761 762 /* Hack for internal USB modem */ 763 if (node == NULL) { 764 if (macio_chips[0].type != macio_pangea && 765 macio_chips[0].type != macio_intrepid) 766 return -ENODEV; 767 node = macio_chips[0].of_node; 768 } 769 macio = macio_find(node, 0); 770 if (!macio) 771 return -ENODEV; 772 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET); 773 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE; 774 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA; 775 776 if (!value) { 777 LOCK(flags); 778 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 779 UNLOCK(flags); 780 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 781 mdelay(250); 782 } 783 LOCK(flags); 784 if (value) { 785 MACIO_OUT8(KL_GPIO_MODEM_POWER, 786 KEYLARGO_GPIO_OUTPUT_ENABLE); 787 UNLOCK(flags); 788 (void)MACIO_IN32(KEYLARGO_FCR2); 789 mdelay(250); 790 } else { 791 MACIO_OUT8(KL_GPIO_MODEM_POWER, 792 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA); 793 UNLOCK(flags); 794 } 795 if (value) { 796 LOCK(flags); 797 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 798 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 799 UNLOCK(flags); mdelay(250); LOCK(flags); 800 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 801 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 802 UNLOCK(flags); mdelay(250); LOCK(flags); 803 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 804 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 805 UNLOCK(flags); mdelay(250); 806 } 807 return 0; 808 } 809 810 static long 811 core99_ata100_enable(struct device_node *node, long value) 812 { 813 unsigned long flags; 814 struct pci_dev *pdev = NULL; 815 u8 pbus, pid; 816 int rc; 817 818 if (uninorth_rev < 0x24) 819 return -ENODEV; 820 821 LOCK(flags); 822 if (value) 823 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100); 824 else 825 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100); 826 (void)UN_IN(UNI_N_CLOCK_CNTL); 827 UNLOCK(flags); 828 udelay(20); 829 830 if (value) { 831 if (pci_device_from_OF_node(node, &pbus, &pid) == 0) 832 pdev = pci_get_domain_bus_and_slot(0, pbus, pid); 833 if (pdev == NULL) 834 return 0; 835 rc = pci_enable_device(pdev); 836 if (rc == 0) 837 pci_set_master(pdev); 838 pci_dev_put(pdev); 839 if (rc) 840 return rc; 841 } 842 return 0; 843 } 844 845 static long 846 core99_ide_enable(struct device_node *node, long param, long value) 847 { 848 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2 849 * based ata-100 850 */ 851 switch(param) { 852 case 0: 853 return simple_feature_tweak(node, macio_unknown, 854 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value); 855 case 1: 856 return simple_feature_tweak(node, macio_unknown, 857 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value); 858 case 2: 859 return simple_feature_tweak(node, macio_unknown, 860 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value); 861 case 3: 862 return core99_ata100_enable(node, value); 863 default: 864 return -ENODEV; 865 } 866 } 867 868 static long 869 core99_ide_reset(struct device_node *node, long param, long value) 870 { 871 switch(param) { 872 case 0: 873 return simple_feature_tweak(node, macio_unknown, 874 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value); 875 case 1: 876 return simple_feature_tweak(node, macio_unknown, 877 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value); 878 case 2: 879 return simple_feature_tweak(node, macio_unknown, 880 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value); 881 default: 882 return -ENODEV; 883 } 884 } 885 886 static long 887 core99_gmac_enable(struct device_node *node, long param, long value) 888 { 889 unsigned long flags; 890 891 LOCK(flags); 892 if (value) 893 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC); 894 else 895 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC); 896 (void)UN_IN(UNI_N_CLOCK_CNTL); 897 UNLOCK(flags); 898 udelay(20); 899 900 return 0; 901 } 902 903 static long 904 core99_gmac_phy_reset(struct device_node *node, long param, long value) 905 { 906 unsigned long flags; 907 struct macio_chip *macio; 908 909 macio = &macio_chips[0]; 910 if (macio->type != macio_keylargo && macio->type != macio_pangea && 911 macio->type != macio_intrepid) 912 return -ENODEV; 913 914 LOCK(flags); 915 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE); 916 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET); 917 UNLOCK(flags); 918 mdelay(10); 919 LOCK(flags); 920 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */ 921 KEYLARGO_GPIO_OUTOUT_DATA); 922 UNLOCK(flags); 923 mdelay(10); 924 925 return 0; 926 } 927 928 static long 929 core99_sound_chip_enable(struct device_node *node, long param, long value) 930 { 931 struct macio_chip* macio; 932 unsigned long flags; 933 934 macio = macio_find(node, 0); 935 if (!macio) 936 return -ENODEV; 937 938 /* Do a better probe code, screamer G4 desktops & 939 * iMacs can do that too, add a recalibrate in 940 * the driver as well 941 */ 942 if (pmac_mb.model_id == PMAC_TYPE_PISMO || 943 pmac_mb.model_id == PMAC_TYPE_TITANIUM) { 944 LOCK(flags); 945 if (value) 946 MACIO_OUT8(KL_GPIO_SOUND_POWER, 947 KEYLARGO_GPIO_OUTPUT_ENABLE | 948 KEYLARGO_GPIO_OUTOUT_DATA); 949 else 950 MACIO_OUT8(KL_GPIO_SOUND_POWER, 951 KEYLARGO_GPIO_OUTPUT_ENABLE); 952 (void)MACIO_IN8(KL_GPIO_SOUND_POWER); 953 UNLOCK(flags); 954 } 955 return 0; 956 } 957 958 static long 959 core99_airport_enable(struct device_node *node, long param, long value) 960 { 961 struct macio_chip* macio; 962 unsigned long flags; 963 int state; 964 965 macio = macio_find(node, 0); 966 if (!macio) 967 return -ENODEV; 968 969 /* Hint: we allow passing of macio itself for the sake of the 970 * sleep code 971 */ 972 if (node != macio->of_node && 973 (!node->parent || node->parent != macio->of_node)) 974 return -ENODEV; 975 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0; 976 if (value == state) 977 return 0; 978 if (value) { 979 /* This code is a reproduction of OF enable-cardslot 980 * and init-wireless methods, slightly hacked until 981 * I got it working. 982 */ 983 LOCK(flags); 984 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5); 985 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf); 986 UNLOCK(flags); 987 mdelay(10); 988 LOCK(flags); 989 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4); 990 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf); 991 UNLOCK(flags); 992 993 mdelay(10); 994 995 LOCK(flags); 996 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16); 997 (void)MACIO_IN32(KEYLARGO_FCR2); 998 udelay(10); 999 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0); 1000 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb); 1001 udelay(10); 1002 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28); 1003 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa); 1004 udelay(10); 1005 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28); 1006 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd); 1007 udelay(10); 1008 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28); 1009 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd); 1010 udelay(10); 1011 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28); 1012 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe); 1013 UNLOCK(flags); 1014 udelay(10); 1015 MACIO_OUT32(0x1c000, 0); 1016 mdelay(1); 1017 MACIO_OUT8(0x1a3e0, 0x41); 1018 (void)MACIO_IN8(0x1a3e0); 1019 udelay(10); 1020 LOCK(flags); 1021 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16); 1022 (void)MACIO_IN32(KEYLARGO_FCR2); 1023 UNLOCK(flags); 1024 mdelay(100); 1025 1026 macio->flags |= MACIO_FLAG_AIRPORT_ON; 1027 } else { 1028 LOCK(flags); 1029 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16); 1030 (void)MACIO_IN32(KEYLARGO_FCR2); 1031 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0); 1032 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0); 1033 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0); 1034 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0); 1035 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0); 1036 (void)MACIO_IN8(KL_GPIO_AIRPORT_4); 1037 UNLOCK(flags); 1038 1039 macio->flags &= ~MACIO_FLAG_AIRPORT_ON; 1040 } 1041 return 0; 1042 } 1043 1044 #ifdef CONFIG_SMP 1045 static long 1046 core99_reset_cpu(struct device_node *node, long param, long value) 1047 { 1048 unsigned int reset_io = 0; 1049 unsigned long flags; 1050 struct macio_chip *macio; 1051 struct device_node *np; 1052 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0, 1053 KL_GPIO_RESET_CPU1, 1054 KL_GPIO_RESET_CPU2, 1055 KL_GPIO_RESET_CPU3 }; 1056 1057 macio = &macio_chips[0]; 1058 if (macio->type != macio_keylargo) 1059 return -ENODEV; 1060 1061 for_each_of_cpu_node(np) { 1062 const u32 *num = of_get_property(np, "reg", NULL); 1063 const u32 *rst = of_get_property(np, "soft-reset", NULL); 1064 if (num == NULL || rst == NULL) 1065 continue; 1066 if (param == *num) { 1067 reset_io = *rst; 1068 break; 1069 } 1070 } 1071 if (np == NULL || reset_io == 0) 1072 reset_io = dflt_reset_lines[param]; 1073 1074 LOCK(flags); 1075 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE); 1076 (void)MACIO_IN8(reset_io); 1077 udelay(1); 1078 MACIO_OUT8(reset_io, 0); 1079 (void)MACIO_IN8(reset_io); 1080 UNLOCK(flags); 1081 1082 return 0; 1083 } 1084 #endif /* CONFIG_SMP */ 1085 1086 static long 1087 core99_usb_enable(struct device_node *node, long param, long value) 1088 { 1089 struct macio_chip *macio; 1090 unsigned long flags; 1091 const char *prop; 1092 int number; 1093 u32 reg; 1094 1095 macio = &macio_chips[0]; 1096 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1097 macio->type != macio_intrepid) 1098 return -ENODEV; 1099 1100 prop = of_get_property(node, "AAPL,clock-id", NULL); 1101 if (!prop) 1102 return -ENODEV; 1103 if (strncmp(prop, "usb0u048", 8) == 0) 1104 number = 0; 1105 else if (strncmp(prop, "usb1u148", 8) == 0) 1106 number = 2; 1107 else if (strncmp(prop, "usb2u248", 8) == 0) 1108 number = 4; 1109 else 1110 return -ENODEV; 1111 1112 /* Sorry for the brute-force locking, but this is only used during 1113 * sleep and the timing seem to be critical 1114 */ 1115 LOCK(flags); 1116 if (value) { 1117 /* Turn ON */ 1118 if (number == 0) { 1119 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1)); 1120 (void)MACIO_IN32(KEYLARGO_FCR0); 1121 UNLOCK(flags); 1122 mdelay(1); 1123 LOCK(flags); 1124 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE); 1125 } else if (number == 2) { 1126 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1)); 1127 UNLOCK(flags); 1128 (void)MACIO_IN32(KEYLARGO_FCR0); 1129 mdelay(1); 1130 LOCK(flags); 1131 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE); 1132 } else if (number == 4) { 1133 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1)); 1134 UNLOCK(flags); 1135 (void)MACIO_IN32(KEYLARGO_FCR1); 1136 mdelay(1); 1137 LOCK(flags); 1138 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE); 1139 } 1140 if (number < 4) { 1141 reg = MACIO_IN32(KEYLARGO_FCR4); 1142 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | 1143 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number)); 1144 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | 1145 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1)); 1146 MACIO_OUT32(KEYLARGO_FCR4, reg); 1147 (void)MACIO_IN32(KEYLARGO_FCR4); 1148 udelay(10); 1149 } else { 1150 reg = MACIO_IN32(KEYLARGO_FCR3); 1151 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | 1152 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0)); 1153 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | 1154 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1)); 1155 MACIO_OUT32(KEYLARGO_FCR3, reg); 1156 (void)MACIO_IN32(KEYLARGO_FCR3); 1157 udelay(10); 1158 } 1159 if (macio->type == macio_intrepid) { 1160 /* wait for clock stopped bits to clear */ 1161 u32 test0 = 0, test1 = 0; 1162 u32 status0, status1; 1163 int timeout = 1000; 1164 1165 UNLOCK(flags); 1166 switch (number) { 1167 case 0: 1168 test0 = UNI_N_CLOCK_STOPPED_USB0; 1169 test1 = UNI_N_CLOCK_STOPPED_USB0PCI; 1170 break; 1171 case 2: 1172 test0 = UNI_N_CLOCK_STOPPED_USB1; 1173 test1 = UNI_N_CLOCK_STOPPED_USB1PCI; 1174 break; 1175 case 4: 1176 test0 = UNI_N_CLOCK_STOPPED_USB2; 1177 test1 = UNI_N_CLOCK_STOPPED_USB2PCI; 1178 break; 1179 } 1180 do { 1181 if (--timeout <= 0) { 1182 printk(KERN_ERR "core99_usb_enable: " 1183 "Timeout waiting for clocks\n"); 1184 break; 1185 } 1186 mdelay(1); 1187 status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0); 1188 status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1); 1189 } while ((status0 & test0) | (status1 & test1)); 1190 LOCK(flags); 1191 } 1192 } else { 1193 /* Turn OFF */ 1194 if (number < 4) { 1195 reg = MACIO_IN32(KEYLARGO_FCR4); 1196 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | 1197 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number); 1198 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | 1199 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1); 1200 MACIO_OUT32(KEYLARGO_FCR4, reg); 1201 (void)MACIO_IN32(KEYLARGO_FCR4); 1202 udelay(1); 1203 } else { 1204 reg = MACIO_IN32(KEYLARGO_FCR3); 1205 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | 1206 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0); 1207 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | 1208 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1); 1209 MACIO_OUT32(KEYLARGO_FCR3, reg); 1210 (void)MACIO_IN32(KEYLARGO_FCR3); 1211 udelay(1); 1212 } 1213 if (number == 0) { 1214 if (macio->type != macio_intrepid) 1215 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE); 1216 (void)MACIO_IN32(KEYLARGO_FCR0); 1217 udelay(1); 1218 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1)); 1219 (void)MACIO_IN32(KEYLARGO_FCR0); 1220 } else if (number == 2) { 1221 if (macio->type != macio_intrepid) 1222 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE); 1223 (void)MACIO_IN32(KEYLARGO_FCR0); 1224 udelay(1); 1225 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1)); 1226 (void)MACIO_IN32(KEYLARGO_FCR0); 1227 } else if (number == 4) { 1228 udelay(1); 1229 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1)); 1230 (void)MACIO_IN32(KEYLARGO_FCR1); 1231 } 1232 udelay(1); 1233 } 1234 UNLOCK(flags); 1235 1236 return 0; 1237 } 1238 1239 static long 1240 core99_firewire_enable(struct device_node *node, long param, long value) 1241 { 1242 unsigned long flags; 1243 struct macio_chip *macio; 1244 1245 macio = &macio_chips[0]; 1246 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1247 macio->type != macio_intrepid) 1248 return -ENODEV; 1249 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED)) 1250 return -ENODEV; 1251 1252 LOCK(flags); 1253 if (value) { 1254 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW); 1255 (void)UN_IN(UNI_N_CLOCK_CNTL); 1256 } else { 1257 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW); 1258 (void)UN_IN(UNI_N_CLOCK_CNTL); 1259 } 1260 UNLOCK(flags); 1261 mdelay(1); 1262 1263 return 0; 1264 } 1265 1266 static long 1267 core99_firewire_cable_power(struct device_node *node, long param, long value) 1268 { 1269 unsigned long flags; 1270 struct macio_chip *macio; 1271 1272 /* Trick: we allow NULL node */ 1273 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0) 1274 return -ENODEV; 1275 macio = &macio_chips[0]; 1276 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1277 macio->type != macio_intrepid) 1278 return -ENODEV; 1279 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED)) 1280 return -ENODEV; 1281 1282 LOCK(flags); 1283 if (value) { 1284 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0); 1285 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); 1286 udelay(10); 1287 } else { 1288 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4); 1289 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10); 1290 } 1291 UNLOCK(flags); 1292 mdelay(1); 1293 1294 return 0; 1295 } 1296 1297 static long 1298 intrepid_aack_delay_enable(struct device_node *node, long param, long value) 1299 { 1300 unsigned long flags; 1301 1302 if (uninorth_rev < 0xd2) 1303 return -ENODEV; 1304 1305 LOCK(flags); 1306 if (param) 1307 UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE); 1308 else 1309 UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE); 1310 UNLOCK(flags); 1311 1312 return 0; 1313 } 1314 1315 1316 #endif /* CONFIG_PPC64 */ 1317 1318 static long 1319 core99_read_gpio(struct device_node *node, long param, long value) 1320 { 1321 struct macio_chip *macio = &macio_chips[0]; 1322 1323 return MACIO_IN8(param); 1324 } 1325 1326 1327 static long 1328 core99_write_gpio(struct device_node *node, long param, long value) 1329 { 1330 struct macio_chip *macio = &macio_chips[0]; 1331 1332 MACIO_OUT8(param, (u8)(value & 0xff)); 1333 return 0; 1334 } 1335 1336 #ifdef CONFIG_PPC64 1337 static long g5_gmac_enable(struct device_node *node, long param, long value) 1338 { 1339 struct macio_chip *macio = &macio_chips[0]; 1340 unsigned long flags; 1341 1342 if (node == NULL) 1343 return -ENODEV; 1344 1345 LOCK(flags); 1346 if (value) { 1347 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE); 1348 mb(); 1349 k2_skiplist[0] = NULL; 1350 } else { 1351 k2_skiplist[0] = node; 1352 mb(); 1353 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE); 1354 } 1355 1356 UNLOCK(flags); 1357 mdelay(1); 1358 1359 return 0; 1360 } 1361 1362 static long g5_fw_enable(struct device_node *node, long param, long value) 1363 { 1364 struct macio_chip *macio = &macio_chips[0]; 1365 unsigned long flags; 1366 1367 if (node == NULL) 1368 return -ENODEV; 1369 1370 LOCK(flags); 1371 if (value) { 1372 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE); 1373 mb(); 1374 k2_skiplist[1] = NULL; 1375 } else { 1376 k2_skiplist[1] = node; 1377 mb(); 1378 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE); 1379 } 1380 1381 UNLOCK(flags); 1382 mdelay(1); 1383 1384 return 0; 1385 } 1386 1387 static long g5_mpic_enable(struct device_node *node, long param, long value) 1388 { 1389 unsigned long flags; 1390 struct device_node *parent = of_get_parent(node); 1391 int is_u3; 1392 1393 if (parent == NULL) 1394 return 0; 1395 is_u3 = of_node_name_eq(parent, "u3") || of_node_name_eq(parent, "u4"); 1396 of_node_put(parent); 1397 if (!is_u3) 1398 return 0; 1399 1400 LOCK(flags); 1401 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE); 1402 UNLOCK(flags); 1403 1404 return 0; 1405 } 1406 1407 static long g5_eth_phy_reset(struct device_node *node, long param, long value) 1408 { 1409 struct macio_chip *macio = &macio_chips[0]; 1410 struct device_node *phy; 1411 int need_reset; 1412 1413 /* 1414 * We must not reset the combo PHYs, only the BCM5221 found in 1415 * the iMac G5. 1416 */ 1417 phy = of_get_next_child(node, NULL); 1418 if (!phy) 1419 return -ENODEV; 1420 need_reset = of_device_is_compatible(phy, "B5221"); 1421 of_node_put(phy); 1422 if (!need_reset) 1423 return 0; 1424 1425 /* PHY reset is GPIO 29, not in device-tree unfortunately */ 1426 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 1427 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA); 1428 /* Thankfully, this is now always called at a time when we can 1429 * schedule by sungem. 1430 */ 1431 msleep(10); 1432 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0); 1433 1434 return 0; 1435 } 1436 1437 static long g5_i2s_enable(struct device_node *node, long param, long value) 1438 { 1439 /* Very crude implementation for now */ 1440 struct macio_chip *macio = &macio_chips[0]; 1441 unsigned long flags; 1442 int cell; 1443 u32 fcrs[3][3] = { 1444 { 0, 1445 K2_FCR1_I2S0_CELL_ENABLE | 1446 K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE, 1447 KL3_I2S0_CLK18_ENABLE 1448 }, 1449 { KL0_SCC_A_INTF_ENABLE, 1450 K2_FCR1_I2S1_CELL_ENABLE | 1451 K2_FCR1_I2S1_CLK_ENABLE_BIT | K2_FCR1_I2S1_ENABLE, 1452 KL3_I2S1_CLK18_ENABLE 1453 }, 1454 { KL0_SCC_B_INTF_ENABLE, 1455 SH_FCR1_I2S2_CELL_ENABLE | 1456 SH_FCR1_I2S2_CLK_ENABLE_BIT | SH_FCR1_I2S2_ENABLE, 1457 SH_FCR3_I2S2_CLK18_ENABLE 1458 }, 1459 }; 1460 1461 if (macio->type != macio_keylargo2 && macio->type != macio_shasta) 1462 return -ENODEV; 1463 if (strncmp(node->name, "i2s-", 4)) 1464 return -ENODEV; 1465 cell = node->name[4] - 'a'; 1466 switch(cell) { 1467 case 0: 1468 case 1: 1469 break; 1470 case 2: 1471 if (macio->type == macio_shasta) 1472 break; 1473 /* fall through */ 1474 default: 1475 return -ENODEV; 1476 } 1477 1478 LOCK(flags); 1479 if (value) { 1480 MACIO_BIC(KEYLARGO_FCR0, fcrs[cell][0]); 1481 MACIO_BIS(KEYLARGO_FCR1, fcrs[cell][1]); 1482 MACIO_BIS(KEYLARGO_FCR3, fcrs[cell][2]); 1483 } else { 1484 MACIO_BIC(KEYLARGO_FCR3, fcrs[cell][2]); 1485 MACIO_BIC(KEYLARGO_FCR1, fcrs[cell][1]); 1486 MACIO_BIS(KEYLARGO_FCR0, fcrs[cell][0]); 1487 } 1488 udelay(10); 1489 UNLOCK(flags); 1490 1491 return 0; 1492 } 1493 1494 1495 #ifdef CONFIG_SMP 1496 static long g5_reset_cpu(struct device_node *node, long param, long value) 1497 { 1498 unsigned int reset_io = 0; 1499 unsigned long flags; 1500 struct macio_chip *macio; 1501 struct device_node *np; 1502 1503 macio = &macio_chips[0]; 1504 if (macio->type != macio_keylargo2 && macio->type != macio_shasta) 1505 return -ENODEV; 1506 1507 for_each_of_cpu_node(np) { 1508 const u32 *num = of_get_property(np, "reg", NULL); 1509 const u32 *rst = of_get_property(np, "soft-reset", NULL); 1510 if (num == NULL || rst == NULL) 1511 continue; 1512 if (param == *num) { 1513 reset_io = *rst; 1514 break; 1515 } 1516 } 1517 if (np == NULL || reset_io == 0) 1518 return -ENODEV; 1519 1520 LOCK(flags); 1521 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE); 1522 (void)MACIO_IN8(reset_io); 1523 udelay(1); 1524 MACIO_OUT8(reset_io, 0); 1525 (void)MACIO_IN8(reset_io); 1526 UNLOCK(flags); 1527 1528 return 0; 1529 } 1530 #endif /* CONFIG_SMP */ 1531 1532 /* 1533 * This can be called from pmac_smp so isn't static 1534 * 1535 * This takes the second CPU off the bus on dual CPU machines 1536 * running UP 1537 */ 1538 void g5_phy_disable_cpu1(void) 1539 { 1540 if (uninorth_maj == 3) 1541 UN_OUT(U3_API_PHY_CONFIG_1, 0); 1542 } 1543 #endif /* CONFIG_PPC64 */ 1544 1545 #ifndef CONFIG_PPC64 1546 1547 1548 #ifdef CONFIG_PM 1549 static u32 save_gpio_levels[2]; 1550 static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT]; 1551 static u8 save_gpio_normal[KEYLARGO_GPIO_CNT]; 1552 static u32 save_unin_clock_ctl; 1553 1554 static void keylargo_shutdown(struct macio_chip *macio, int sleep_mode) 1555 { 1556 u32 temp; 1557 1558 if (sleep_mode) { 1559 mdelay(1); 1560 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND); 1561 (void)MACIO_IN32(KEYLARGO_FCR0); 1562 mdelay(1); 1563 } 1564 1565 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1566 KL0_SCC_CELL_ENABLE | 1567 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE | 1568 KL0_IRDA_CLK19_ENABLE); 1569 1570 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK); 1571 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE); 1572 1573 MACIO_BIC(KEYLARGO_FCR1, 1574 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT | 1575 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE | 1576 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1577 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1578 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1579 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N | 1580 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N | 1581 KL1_UIDE_ENABLE); 1582 1583 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 1584 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE); 1585 1586 temp = MACIO_IN32(KEYLARGO_FCR3); 1587 if (macio->rev >= 2) { 1588 temp |= KL3_SHUTDOWN_PLL2X; 1589 if (sleep_mode) 1590 temp |= KL3_SHUTDOWN_PLL_TOTAL; 1591 } 1592 1593 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 | 1594 KL3_SHUTDOWN_PLLKW35; 1595 if (sleep_mode) 1596 temp |= KL3_SHUTDOWN_PLLKW12; 1597 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE 1598 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE); 1599 if (sleep_mode) 1600 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE); 1601 MACIO_OUT32(KEYLARGO_FCR3, temp); 1602 1603 /* Flush posted writes & wait a bit */ 1604 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1); 1605 } 1606 1607 static void pangea_shutdown(struct macio_chip *macio, int sleep_mode) 1608 { 1609 u32 temp; 1610 1611 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1612 KL0_SCC_CELL_ENABLE | 1613 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE); 1614 1615 MACIO_BIC(KEYLARGO_FCR1, 1616 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT | 1617 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE | 1618 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1619 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1620 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1621 KL1_UIDE_ENABLE); 1622 if (pmac_mb.board_flags & PMAC_MB_MOBILE) 1623 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N); 1624 1625 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 1626 1627 temp = MACIO_IN32(KEYLARGO_FCR3); 1628 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 | 1629 KL3_SHUTDOWN_PLLKW35; 1630 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE 1631 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE); 1632 if (sleep_mode) 1633 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE); 1634 MACIO_OUT32(KEYLARGO_FCR3, temp); 1635 1636 /* Flush posted writes & wait a bit */ 1637 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1); 1638 } 1639 1640 static void intrepid_shutdown(struct macio_chip *macio, int sleep_mode) 1641 { 1642 u32 temp; 1643 1644 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1645 KL0_SCC_CELL_ENABLE); 1646 1647 MACIO_BIC(KEYLARGO_FCR1, 1648 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1649 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1650 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1651 KL1_EIDE0_ENABLE); 1652 if (pmac_mb.board_flags & PMAC_MB_MOBILE) 1653 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N); 1654 1655 temp = MACIO_IN32(KEYLARGO_FCR3); 1656 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | 1657 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE); 1658 if (sleep_mode) 1659 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE); 1660 MACIO_OUT32(KEYLARGO_FCR3, temp); 1661 1662 /* Flush posted writes & wait a bit */ 1663 (void)MACIO_IN32(KEYLARGO_FCR0); 1664 mdelay(10); 1665 } 1666 1667 1668 static int 1669 core99_sleep(void) 1670 { 1671 struct macio_chip *macio; 1672 int i; 1673 1674 macio = &macio_chips[0]; 1675 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1676 macio->type != macio_intrepid) 1677 return -ENODEV; 1678 1679 /* We power off the wireless slot in case it was not done 1680 * by the driver. We don't power it on automatically however 1681 */ 1682 if (macio->flags & MACIO_FLAG_AIRPORT_ON) 1683 core99_airport_enable(macio->of_node, 0, 0); 1684 1685 /* We power off the FW cable. Should be done by the driver... */ 1686 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) { 1687 core99_firewire_enable(NULL, 0, 0); 1688 core99_firewire_cable_power(NULL, 0, 0); 1689 } 1690 1691 /* We make sure int. modem is off (in case driver lost it) */ 1692 if (macio->type == macio_keylargo) 1693 core99_modem_enable(macio->of_node, 0, 0); 1694 else 1695 pangea_modem_enable(macio->of_node, 0, 0); 1696 1697 /* We make sure the sound is off as well */ 1698 core99_sound_chip_enable(macio->of_node, 0, 0); 1699 1700 /* 1701 * Save various bits of KeyLargo 1702 */ 1703 1704 /* Save the state of the various GPIOs */ 1705 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0); 1706 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1); 1707 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++) 1708 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i); 1709 for (i=0; i<KEYLARGO_GPIO_CNT; i++) 1710 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i); 1711 1712 /* Save the FCRs */ 1713 if (macio->type == macio_keylargo) 1714 save_mbcr = MACIO_IN32(KEYLARGO_MBCR); 1715 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0); 1716 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1); 1717 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2); 1718 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3); 1719 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4); 1720 if (macio->type == macio_pangea || macio->type == macio_intrepid) 1721 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5); 1722 1723 /* Save state & config of DBDMA channels */ 1724 dbdma_save(macio, save_dbdma); 1725 1726 /* 1727 * Turn off as much as we can 1728 */ 1729 if (macio->type == macio_pangea) 1730 pangea_shutdown(macio, 1); 1731 else if (macio->type == macio_intrepid) 1732 intrepid_shutdown(macio, 1); 1733 else if (macio->type == macio_keylargo) 1734 keylargo_shutdown(macio, 1); 1735 1736 /* 1737 * Put the host bridge to sleep 1738 */ 1739 1740 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL); 1741 /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it 1742 * enabled ! 1743 */ 1744 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl & 1745 ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/)); 1746 udelay(100); 1747 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING); 1748 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP); 1749 mdelay(10); 1750 1751 /* 1752 * FIXME: A bit of black magic with OpenPIC (don't ask me why) 1753 */ 1754 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) { 1755 MACIO_BIS(0x506e0, 0x00400000); 1756 MACIO_BIS(0x506e0, 0x80000000); 1757 } 1758 return 0; 1759 } 1760 1761 static int 1762 core99_wake_up(void) 1763 { 1764 struct macio_chip *macio; 1765 int i; 1766 1767 macio = &macio_chips[0]; 1768 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1769 macio->type != macio_intrepid) 1770 return -ENODEV; 1771 1772 /* 1773 * Wakeup the host bridge 1774 */ 1775 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL); 1776 udelay(10); 1777 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING); 1778 udelay(10); 1779 1780 /* 1781 * Restore KeyLargo 1782 */ 1783 1784 if (macio->type == macio_keylargo) { 1785 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr); 1786 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10); 1787 } 1788 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]); 1789 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10); 1790 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]); 1791 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10); 1792 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]); 1793 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10); 1794 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]); 1795 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10); 1796 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]); 1797 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10); 1798 if (macio->type == macio_pangea || macio->type == macio_intrepid) { 1799 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]); 1800 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10); 1801 } 1802 1803 dbdma_restore(macio, save_dbdma); 1804 1805 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]); 1806 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]); 1807 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++) 1808 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]); 1809 for (i=0; i<KEYLARGO_GPIO_CNT; i++) 1810 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]); 1811 1812 /* FIXME more black magic with OpenPIC ... */ 1813 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) { 1814 MACIO_BIC(0x506e0, 0x00400000); 1815 MACIO_BIC(0x506e0, 0x80000000); 1816 } 1817 1818 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl); 1819 udelay(100); 1820 1821 return 0; 1822 } 1823 1824 #endif /* CONFIG_PM */ 1825 1826 static long 1827 core99_sleep_state(struct device_node *node, long param, long value) 1828 { 1829 /* Param == 1 means to enter the "fake sleep" mode that is 1830 * used for CPU speed switch 1831 */ 1832 if (param == 1) { 1833 if (value == 1) { 1834 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING); 1835 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2); 1836 } else { 1837 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL); 1838 udelay(10); 1839 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING); 1840 udelay(10); 1841 } 1842 return 0; 1843 } 1844 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 1845 return -EPERM; 1846 1847 #ifdef CONFIG_PM 1848 if (value == 1) 1849 return core99_sleep(); 1850 else if (value == 0) 1851 return core99_wake_up(); 1852 1853 #endif /* CONFIG_PM */ 1854 return 0; 1855 } 1856 1857 #endif /* CONFIG_PPC64 */ 1858 1859 static long 1860 generic_dev_can_wake(struct device_node *node, long param, long value) 1861 { 1862 /* Todo: eventually check we are really dealing with on-board 1863 * video device ... 1864 */ 1865 1866 if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP) 1867 pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP; 1868 return 0; 1869 } 1870 1871 static long generic_get_mb_info(struct device_node *node, long param, long value) 1872 { 1873 switch(param) { 1874 case PMAC_MB_INFO_MODEL: 1875 return pmac_mb.model_id; 1876 case PMAC_MB_INFO_FLAGS: 1877 return pmac_mb.board_flags; 1878 case PMAC_MB_INFO_NAME: 1879 /* hack hack hack... but should work */ 1880 *((const char **)value) = pmac_mb.model_name; 1881 return 0; 1882 } 1883 return -EINVAL; 1884 } 1885 1886 1887 /* 1888 * Table definitions 1889 */ 1890 1891 /* Used on any machine 1892 */ 1893 static struct feature_table_entry any_features[] = { 1894 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info }, 1895 { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake }, 1896 { 0, NULL } 1897 }; 1898 1899 #ifndef CONFIG_PPC64 1900 1901 /* OHare based motherboards. Currently, we only use these on the 1902 * 2400,3400 and 3500 series powerbooks. Some older desktops seem 1903 * to have issues with turning on/off those asic cells 1904 */ 1905 static struct feature_table_entry ohare_features[] = { 1906 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1907 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable }, 1908 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable }, 1909 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable}, 1910 { PMAC_FTR_IDE_RESET, ohare_ide_reset}, 1911 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state }, 1912 { 0, NULL } 1913 }; 1914 1915 /* Heathrow desktop machines (Beige G3). 1916 * Separated as some features couldn't be properly tested 1917 * and the serial port control bits appear to confuse it. 1918 */ 1919 static struct feature_table_entry heathrow_desktop_features[] = { 1920 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1921 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1922 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1923 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1924 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1925 { 0, NULL } 1926 }; 1927 1928 /* Heathrow based laptop, that is the Wallstreet and mainstreet 1929 * powerbooks. 1930 */ 1931 static struct feature_table_entry heathrow_laptop_features[] = { 1932 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1933 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable }, 1934 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1935 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1936 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1937 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1938 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1939 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable }, 1940 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state }, 1941 { 0, NULL } 1942 }; 1943 1944 /* Paddington based machines 1945 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4. 1946 */ 1947 static struct feature_table_entry paddington_features[] = { 1948 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1949 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable }, 1950 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1951 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1952 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1953 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1954 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1955 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable }, 1956 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state }, 1957 { 0, NULL } 1958 }; 1959 1960 /* Core99 & MacRISC 2 machines (all machines released since the 1961 * iBook (included), that is all AGP machines, except pangea 1962 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo 1963 * used on iBook2 & iMac "flow power". 1964 */ 1965 static struct feature_table_entry core99_features[] = { 1966 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 1967 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable }, 1968 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 1969 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 1970 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 1971 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 1972 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 1973 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 1974 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 1975 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 1976 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 1977 #ifdef CONFIG_PM 1978 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 1979 #endif 1980 #ifdef CONFIG_SMP 1981 { PMAC_FTR_RESET_CPU, core99_reset_cpu }, 1982 #endif /* CONFIG_SMP */ 1983 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 1984 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 1985 { 0, NULL } 1986 }; 1987 1988 /* RackMac 1989 */ 1990 static struct feature_table_entry rackmac_features[] = { 1991 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 1992 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 1993 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 1994 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 1995 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 1996 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 1997 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 1998 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 1999 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 2000 #ifdef CONFIG_SMP 2001 { PMAC_FTR_RESET_CPU, core99_reset_cpu }, 2002 #endif /* CONFIG_SMP */ 2003 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2004 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2005 { 0, NULL } 2006 }; 2007 2008 /* Pangea features 2009 */ 2010 static struct feature_table_entry pangea_features[] = { 2011 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 2012 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable }, 2013 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 2014 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 2015 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 2016 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 2017 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 2018 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 2019 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 2020 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 2021 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 2022 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 2023 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2024 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2025 { 0, NULL } 2026 }; 2027 2028 /* Intrepid features 2029 */ 2030 static struct feature_table_entry intrepid_features[] = { 2031 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 2032 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable }, 2033 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 2034 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 2035 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 2036 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 2037 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 2038 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 2039 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 2040 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 2041 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 2042 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 2043 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2044 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2045 { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable }, 2046 { 0, NULL } 2047 }; 2048 2049 #else /* CONFIG_PPC64 */ 2050 2051 /* G5 features 2052 */ 2053 static struct feature_table_entry g5_features[] = { 2054 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable }, 2055 { PMAC_FTR_1394_ENABLE, g5_fw_enable }, 2056 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable }, 2057 { PMAC_FTR_GMAC_PHY_RESET, g5_eth_phy_reset }, 2058 { PMAC_FTR_SOUND_CHIP_ENABLE, g5_i2s_enable }, 2059 #ifdef CONFIG_SMP 2060 { PMAC_FTR_RESET_CPU, g5_reset_cpu }, 2061 #endif /* CONFIG_SMP */ 2062 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2063 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2064 { 0, NULL } 2065 }; 2066 2067 #endif /* CONFIG_PPC64 */ 2068 2069 static struct pmac_mb_def pmac_mb_defs[] = { 2070 #ifndef CONFIG_PPC64 2071 /* 2072 * Desktops 2073 */ 2074 2075 { "AAPL,8500", "PowerMac 8500/8600", 2076 PMAC_TYPE_PSURGE, NULL, 2077 0 2078 }, 2079 { "AAPL,9500", "PowerMac 9500/9600", 2080 PMAC_TYPE_PSURGE, NULL, 2081 0 2082 }, 2083 { "AAPL,7200", "PowerMac 7200", 2084 PMAC_TYPE_PSURGE, NULL, 2085 0 2086 }, 2087 { "AAPL,7300", "PowerMac 7200/7300", 2088 PMAC_TYPE_PSURGE, NULL, 2089 0 2090 }, 2091 { "AAPL,7500", "PowerMac 7500", 2092 PMAC_TYPE_PSURGE, NULL, 2093 0 2094 }, 2095 { "AAPL,ShinerESB", "Apple Network Server", 2096 PMAC_TYPE_ANS, NULL, 2097 0 2098 }, 2099 { "AAPL,e407", "Alchemy", 2100 PMAC_TYPE_ALCHEMY, NULL, 2101 0 2102 }, 2103 { "AAPL,e411", "Gazelle", 2104 PMAC_TYPE_GAZELLE, NULL, 2105 0 2106 }, 2107 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)", 2108 PMAC_TYPE_GOSSAMER, heathrow_desktop_features, 2109 0 2110 }, 2111 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)", 2112 PMAC_TYPE_SILK, heathrow_desktop_features, 2113 0 2114 }, 2115 { "PowerMac1,1", "Blue&White G3", 2116 PMAC_TYPE_YOSEMITE, paddington_features, 2117 0 2118 }, 2119 { "PowerMac1,2", "PowerMac G4 PCI Graphics", 2120 PMAC_TYPE_YIKES, paddington_features, 2121 0 2122 }, 2123 { "PowerMac2,1", "iMac FireWire", 2124 PMAC_TYPE_FW_IMAC, core99_features, 2125 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2126 }, 2127 { "PowerMac2,2", "iMac FireWire", 2128 PMAC_TYPE_FW_IMAC, core99_features, 2129 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2130 }, 2131 { "PowerMac3,1", "PowerMac G4 AGP Graphics", 2132 PMAC_TYPE_SAWTOOTH, core99_features, 2133 PMAC_MB_OLD_CORE99 2134 }, 2135 { "PowerMac3,2", "PowerMac G4 AGP Graphics", 2136 PMAC_TYPE_SAWTOOTH, core99_features, 2137 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2138 }, 2139 { "PowerMac3,3", "PowerMac G4 AGP Graphics", 2140 PMAC_TYPE_SAWTOOTH, core99_features, 2141 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2142 }, 2143 { "PowerMac3,4", "PowerMac G4 Silver", 2144 PMAC_TYPE_QUICKSILVER, core99_features, 2145 PMAC_MB_MAY_SLEEP 2146 }, 2147 { "PowerMac3,5", "PowerMac G4 Silver", 2148 PMAC_TYPE_QUICKSILVER, core99_features, 2149 PMAC_MB_MAY_SLEEP 2150 }, 2151 { "PowerMac3,6", "PowerMac G4 Windtunnel", 2152 PMAC_TYPE_WINDTUNNEL, core99_features, 2153 PMAC_MB_MAY_SLEEP, 2154 }, 2155 { "PowerMac4,1", "iMac \"Flower Power\"", 2156 PMAC_TYPE_PANGEA_IMAC, pangea_features, 2157 PMAC_MB_MAY_SLEEP 2158 }, 2159 { "PowerMac4,2", "Flat panel iMac", 2160 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features, 2161 PMAC_MB_CAN_SLEEP 2162 }, 2163 { "PowerMac4,4", "eMac", 2164 PMAC_TYPE_EMAC, core99_features, 2165 PMAC_MB_MAY_SLEEP 2166 }, 2167 { "PowerMac5,1", "PowerMac G4 Cube", 2168 PMAC_TYPE_CUBE, core99_features, 2169 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2170 }, 2171 { "PowerMac6,1", "Flat panel iMac", 2172 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2173 PMAC_MB_MAY_SLEEP, 2174 }, 2175 { "PowerMac6,3", "Flat panel iMac", 2176 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2177 PMAC_MB_MAY_SLEEP, 2178 }, 2179 { "PowerMac6,4", "eMac", 2180 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2181 PMAC_MB_MAY_SLEEP, 2182 }, 2183 { "PowerMac10,1", "Mac mini", 2184 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2185 PMAC_MB_MAY_SLEEP, 2186 }, 2187 { "PowerMac10,2", "Mac mini (Late 2005)", 2188 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2189 PMAC_MB_MAY_SLEEP, 2190 }, 2191 { "iMac,1", "iMac (first generation)", 2192 PMAC_TYPE_ORIG_IMAC, paddington_features, 2193 0 2194 }, 2195 2196 /* 2197 * Xserve's 2198 */ 2199 2200 { "RackMac1,1", "XServe", 2201 PMAC_TYPE_RACKMAC, rackmac_features, 2202 0, 2203 }, 2204 { "RackMac1,2", "XServe rev. 2", 2205 PMAC_TYPE_RACKMAC, rackmac_features, 2206 0, 2207 }, 2208 2209 /* 2210 * Laptops 2211 */ 2212 2213 { "AAPL,3400/2400", "PowerBook 3400", 2214 PMAC_TYPE_HOOPER, ohare_features, 2215 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2216 }, 2217 { "AAPL,3500", "PowerBook 3500", 2218 PMAC_TYPE_KANGA, ohare_features, 2219 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2220 }, 2221 { "AAPL,PowerBook1998", "PowerBook Wallstreet", 2222 PMAC_TYPE_WALLSTREET, heathrow_laptop_features, 2223 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2224 }, 2225 { "PowerBook1,1", "PowerBook 101 (Lombard)", 2226 PMAC_TYPE_101_PBOOK, paddington_features, 2227 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2228 }, 2229 { "PowerBook2,1", "iBook (first generation)", 2230 PMAC_TYPE_ORIG_IBOOK, core99_features, 2231 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2232 }, 2233 { "PowerBook2,2", "iBook FireWire", 2234 PMAC_TYPE_FW_IBOOK, core99_features, 2235 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | 2236 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2237 }, 2238 { "PowerBook3,1", "PowerBook Pismo", 2239 PMAC_TYPE_PISMO, core99_features, 2240 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | 2241 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2242 }, 2243 { "PowerBook3,2", "PowerBook Titanium", 2244 PMAC_TYPE_TITANIUM, core99_features, 2245 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2246 }, 2247 { "PowerBook3,3", "PowerBook Titanium II", 2248 PMAC_TYPE_TITANIUM2, core99_features, 2249 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2250 }, 2251 { "PowerBook3,4", "PowerBook Titanium III", 2252 PMAC_TYPE_TITANIUM3, core99_features, 2253 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2254 }, 2255 { "PowerBook3,5", "PowerBook Titanium IV", 2256 PMAC_TYPE_TITANIUM4, core99_features, 2257 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2258 }, 2259 { "PowerBook4,1", "iBook 2", 2260 PMAC_TYPE_IBOOK2, pangea_features, 2261 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2262 }, 2263 { "PowerBook4,2", "iBook 2", 2264 PMAC_TYPE_IBOOK2, pangea_features, 2265 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2266 }, 2267 { "PowerBook4,3", "iBook 2 rev. 2", 2268 PMAC_TYPE_IBOOK2, pangea_features, 2269 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2270 }, 2271 { "PowerBook5,1", "PowerBook G4 17\"", 2272 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2273 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2274 }, 2275 { "PowerBook5,2", "PowerBook G4 15\"", 2276 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2277 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2278 }, 2279 { "PowerBook5,3", "PowerBook G4 17\"", 2280 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2281 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2282 }, 2283 { "PowerBook5,4", "PowerBook G4 15\"", 2284 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2285 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2286 }, 2287 { "PowerBook5,5", "PowerBook G4 17\"", 2288 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2289 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2290 }, 2291 { "PowerBook5,6", "PowerBook G4 15\"", 2292 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2293 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2294 }, 2295 { "PowerBook5,7", "PowerBook G4 17\"", 2296 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2297 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2298 }, 2299 { "PowerBook5,8", "PowerBook G4 15\"", 2300 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2301 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE, 2302 }, 2303 { "PowerBook5,9", "PowerBook G4 17\"", 2304 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2305 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE, 2306 }, 2307 { "PowerBook6,1", "PowerBook G4 12\"", 2308 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2309 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2310 }, 2311 { "PowerBook6,2", "PowerBook G4", 2312 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2313 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2314 }, 2315 { "PowerBook6,3", "iBook G4", 2316 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2317 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2318 }, 2319 { "PowerBook6,4", "PowerBook G4 12\"", 2320 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2321 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2322 }, 2323 { "PowerBook6,5", "iBook G4", 2324 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2325 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2326 }, 2327 { "PowerBook6,7", "iBook G4", 2328 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2329 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2330 }, 2331 { "PowerBook6,8", "PowerBook G4 12\"", 2332 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2333 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2334 }, 2335 #else /* CONFIG_PPC64 */ 2336 { "PowerMac7,2", "PowerMac G5", 2337 PMAC_TYPE_POWERMAC_G5, g5_features, 2338 0, 2339 }, 2340 #ifdef CONFIG_PPC64 2341 { "PowerMac7,3", "PowerMac G5", 2342 PMAC_TYPE_POWERMAC_G5, g5_features, 2343 0, 2344 }, 2345 { "PowerMac8,1", "iMac G5", 2346 PMAC_TYPE_IMAC_G5, g5_features, 2347 0, 2348 }, 2349 { "PowerMac9,1", "PowerMac G5", 2350 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2351 0, 2352 }, 2353 { "PowerMac11,2", "PowerMac G5 Dual Core", 2354 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2355 0, 2356 }, 2357 { "PowerMac12,1", "iMac G5 (iSight)", 2358 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2359 0, 2360 }, 2361 { "RackMac3,1", "XServe G5", 2362 PMAC_TYPE_XSERVE_G5, g5_features, 2363 0, 2364 }, 2365 #endif /* CONFIG_PPC64 */ 2366 #endif /* CONFIG_PPC64 */ 2367 }; 2368 2369 /* 2370 * The toplevel feature_call callback 2371 */ 2372 long pmac_do_feature_call(unsigned int selector, ...) 2373 { 2374 struct device_node *node; 2375 long param, value; 2376 int i; 2377 feature_call func = NULL; 2378 va_list args; 2379 2380 if (pmac_mb.features) 2381 for (i=0; pmac_mb.features[i].function; i++) 2382 if (pmac_mb.features[i].selector == selector) { 2383 func = pmac_mb.features[i].function; 2384 break; 2385 } 2386 if (!func) 2387 for (i=0; any_features[i].function; i++) 2388 if (any_features[i].selector == selector) { 2389 func = any_features[i].function; 2390 break; 2391 } 2392 if (!func) 2393 return -ENODEV; 2394 2395 va_start(args, selector); 2396 node = (struct device_node*)va_arg(args, void*); 2397 param = va_arg(args, long); 2398 value = va_arg(args, long); 2399 va_end(args); 2400 2401 return func(node, param, value); 2402 } 2403 2404 static int __init probe_motherboard(void) 2405 { 2406 int i; 2407 struct macio_chip *macio = &macio_chips[0]; 2408 const char *model = NULL; 2409 struct device_node *dt; 2410 int ret = 0; 2411 2412 /* Lookup known motherboard type in device-tree. First try an 2413 * exact match on the "model" property, then try a "compatible" 2414 * match is none is found. 2415 */ 2416 dt = of_find_node_by_name(NULL, "device-tree"); 2417 if (dt != NULL) 2418 model = of_get_property(dt, "model", NULL); 2419 for(i=0; model && i<ARRAY_SIZE(pmac_mb_defs); i++) { 2420 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) { 2421 pmac_mb = pmac_mb_defs[i]; 2422 goto found; 2423 } 2424 } 2425 for(i=0; i<ARRAY_SIZE(pmac_mb_defs); i++) { 2426 if (of_machine_is_compatible(pmac_mb_defs[i].model_string)) { 2427 pmac_mb = pmac_mb_defs[i]; 2428 goto found; 2429 } 2430 } 2431 2432 /* Fallback to selection depending on mac-io chip type */ 2433 switch(macio->type) { 2434 #ifndef CONFIG_PPC64 2435 case macio_grand_central: 2436 pmac_mb.model_id = PMAC_TYPE_PSURGE; 2437 pmac_mb.model_name = "Unknown PowerSurge"; 2438 break; 2439 case macio_ohare: 2440 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE; 2441 pmac_mb.model_name = "Unknown OHare-based"; 2442 break; 2443 case macio_heathrow: 2444 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW; 2445 pmac_mb.model_name = "Unknown Heathrow-based"; 2446 pmac_mb.features = heathrow_desktop_features; 2447 break; 2448 case macio_paddington: 2449 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON; 2450 pmac_mb.model_name = "Unknown Paddington-based"; 2451 pmac_mb.features = paddington_features; 2452 break; 2453 case macio_keylargo: 2454 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99; 2455 pmac_mb.model_name = "Unknown Keylargo-based"; 2456 pmac_mb.features = core99_features; 2457 break; 2458 case macio_pangea: 2459 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA; 2460 pmac_mb.model_name = "Unknown Pangea-based"; 2461 pmac_mb.features = pangea_features; 2462 break; 2463 case macio_intrepid: 2464 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID; 2465 pmac_mb.model_name = "Unknown Intrepid-based"; 2466 pmac_mb.features = intrepid_features; 2467 break; 2468 #else /* CONFIG_PPC64 */ 2469 case macio_keylargo2: 2470 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2; 2471 pmac_mb.model_name = "Unknown K2-based"; 2472 pmac_mb.features = g5_features; 2473 break; 2474 case macio_shasta: 2475 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_SHASTA; 2476 pmac_mb.model_name = "Unknown Shasta-based"; 2477 pmac_mb.features = g5_features; 2478 break; 2479 #endif /* CONFIG_PPC64 */ 2480 default: 2481 ret = -ENODEV; 2482 goto done; 2483 } 2484 found: 2485 #ifndef CONFIG_PPC64 2486 /* Fixup Hooper vs. Comet */ 2487 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) { 2488 u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4); 2489 if (!mach_id_ptr) { 2490 ret = -ENODEV; 2491 goto done; 2492 } 2493 /* Here, I used to disable the media-bay on comet. It 2494 * appears this is wrong, the floppy connector is actually 2495 * a kind of media-bay and works with the current driver. 2496 */ 2497 if (__raw_readl(mach_id_ptr) & 0x20000000UL) 2498 pmac_mb.model_id = PMAC_TYPE_COMET; 2499 iounmap(mach_id_ptr); 2500 } 2501 2502 /* Set default value of powersave_nap on machines that support it. 2503 * It appears that uninorth rev 3 has a problem with it, we don't 2504 * enable it on those. In theory, the flush-on-lock property is 2505 * supposed to be set when not supported, but I'm not very confident 2506 * that all Apple OF revs did it properly, I do it the paranoid way. 2507 */ 2508 if (uninorth_base && uninorth_rev > 3) { 2509 struct device_node *np; 2510 2511 for_each_of_cpu_node(np) { 2512 int cpu_count = 1; 2513 2514 /* Nap mode not supported on SMP */ 2515 if (of_get_property(np, "flush-on-lock", NULL) || 2516 (cpu_count > 1)) { 2517 powersave_nap = 0; 2518 of_node_put(np); 2519 break; 2520 } 2521 2522 cpu_count++; 2523 powersave_nap = 1; 2524 } 2525 } 2526 if (powersave_nap) 2527 printk(KERN_DEBUG "Processor NAP mode on idle enabled.\n"); 2528 2529 /* On CPUs that support it (750FX), lowspeed by default during 2530 * NAP mode 2531 */ 2532 powersave_lowspeed = 1; 2533 2534 #else /* CONFIG_PPC64 */ 2535 powersave_nap = 1; 2536 #endif /* CONFIG_PPC64 */ 2537 2538 /* Check for "mobile" machine */ 2539 if (model && (strncmp(model, "PowerBook", 9) == 0 2540 || strncmp(model, "iBook", 5) == 0)) 2541 pmac_mb.board_flags |= PMAC_MB_MOBILE; 2542 2543 2544 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name); 2545 done: 2546 of_node_put(dt); 2547 return ret; 2548 } 2549 2550 /* Initialize the Core99 UniNorth host bridge and memory controller 2551 */ 2552 static void __init probe_uninorth(void) 2553 { 2554 const u32 *addrp; 2555 phys_addr_t address; 2556 unsigned long actrl; 2557 2558 /* Locate core99 Uni-N */ 2559 uninorth_node = of_find_node_by_name(NULL, "uni-n"); 2560 uninorth_maj = 1; 2561 2562 /* Locate G5 u3 */ 2563 if (uninorth_node == NULL) { 2564 uninorth_node = of_find_node_by_name(NULL, "u3"); 2565 uninorth_maj = 3; 2566 } 2567 /* Locate G5 u4 */ 2568 if (uninorth_node == NULL) { 2569 uninorth_node = of_find_node_by_name(NULL, "u4"); 2570 uninorth_maj = 4; 2571 } 2572 if (uninorth_node == NULL) { 2573 uninorth_maj = 0; 2574 return; 2575 } 2576 2577 addrp = of_get_property(uninorth_node, "reg", NULL); 2578 if (addrp == NULL) 2579 return; 2580 address = of_translate_address(uninorth_node, addrp); 2581 if (address == 0) 2582 return; 2583 uninorth_base = ioremap(address, 0x40000); 2584 if (uninorth_base == NULL) 2585 return; 2586 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION)); 2587 if (uninorth_maj == 3 || uninorth_maj == 4) { 2588 u3_ht_base = ioremap(address + U3_HT_CONFIG_BASE, 0x1000); 2589 if (u3_ht_base == NULL) { 2590 iounmap(uninorth_base); 2591 return; 2592 } 2593 } 2594 2595 printk(KERN_INFO "Found %s memory controller & host bridge" 2596 " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" : 2597 uninorth_maj == 4 ? "U4" : "UniNorth", 2598 (unsigned int)address, uninorth_rev); 2599 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base); 2600 2601 /* Set the arbitrer QAck delay according to what Apple does 2602 */ 2603 if (uninorth_rev < 0x11) { 2604 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK; 2605 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 : 2606 UNI_N_ARB_CTRL_QACK_DELAY) << 2607 UNI_N_ARB_CTRL_QACK_DELAY_SHIFT; 2608 UN_OUT(UNI_N_ARB_CTRL, actrl); 2609 } 2610 2611 /* Some more magic as done by them in recent MacOS X on UniNorth 2612 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI 2613 * memory timeout 2614 */ 2615 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) || 2616 uninorth_rev == 0xc0) 2617 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff); 2618 } 2619 2620 static void __init probe_one_macio(const char *name, const char *compat, int type) 2621 { 2622 struct device_node* node; 2623 int i; 2624 volatile u32 __iomem *base; 2625 const u32 *addrp, *revp; 2626 phys_addr_t addr; 2627 u64 size; 2628 2629 for_each_node_by_name(node, name) { 2630 if (!compat) 2631 break; 2632 if (of_device_is_compatible(node, compat)) 2633 break; 2634 } 2635 if (!node) 2636 return; 2637 for(i=0; i<MAX_MACIO_CHIPS; i++) { 2638 if (!macio_chips[i].of_node) 2639 break; 2640 if (macio_chips[i].of_node == node) 2641 return; 2642 } 2643 2644 if (i >= MAX_MACIO_CHIPS) { 2645 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n"); 2646 printk(KERN_ERR "pmac_feature: %pOF skipped\n", node); 2647 return; 2648 } 2649 addrp = of_get_pci_address(node, 0, &size, NULL); 2650 if (addrp == NULL) { 2651 printk(KERN_ERR "pmac_feature: %pOF: can't find base !\n", 2652 node); 2653 return; 2654 } 2655 addr = of_translate_address(node, addrp); 2656 if (addr == 0) { 2657 printk(KERN_ERR "pmac_feature: %pOF, can't translate base !\n", 2658 node); 2659 return; 2660 } 2661 base = ioremap(addr, (unsigned long)size); 2662 if (!base) { 2663 printk(KERN_ERR "pmac_feature: %pOF, can't map mac-io chip !\n", 2664 node); 2665 return; 2666 } 2667 if (type == macio_keylargo || type == macio_keylargo2) { 2668 const u32 *did = of_get_property(node, "device-id", NULL); 2669 if (*did == 0x00000025) 2670 type = macio_pangea; 2671 if (*did == 0x0000003e) 2672 type = macio_intrepid; 2673 if (*did == 0x0000004f) 2674 type = macio_shasta; 2675 } 2676 macio_chips[i].of_node = node; 2677 macio_chips[i].type = type; 2678 macio_chips[i].base = base; 2679 macio_chips[i].flags = MACIO_FLAG_SCCA_ON | MACIO_FLAG_SCCB_ON; 2680 macio_chips[i].name = macio_names[type]; 2681 revp = of_get_property(node, "revision-id", NULL); 2682 if (revp) 2683 macio_chips[i].rev = *revp; 2684 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n", 2685 macio_names[type], macio_chips[i].rev, macio_chips[i].base); 2686 } 2687 2688 static int __init 2689 probe_macios(void) 2690 { 2691 /* Warning, ordering is important */ 2692 probe_one_macio("gc", NULL, macio_grand_central); 2693 probe_one_macio("ohare", NULL, macio_ohare); 2694 probe_one_macio("pci106b,7", NULL, macio_ohareII); 2695 probe_one_macio("mac-io", "keylargo", macio_keylargo); 2696 probe_one_macio("mac-io", "paddington", macio_paddington); 2697 probe_one_macio("mac-io", "gatwick", macio_gatwick); 2698 probe_one_macio("mac-io", "heathrow", macio_heathrow); 2699 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2); 2700 2701 /* Make sure the "main" macio chip appear first */ 2702 if (macio_chips[0].type == macio_gatwick 2703 && macio_chips[1].type == macio_heathrow) { 2704 struct macio_chip temp = macio_chips[0]; 2705 macio_chips[0] = macio_chips[1]; 2706 macio_chips[1] = temp; 2707 } 2708 if (macio_chips[0].type == macio_ohareII 2709 && macio_chips[1].type == macio_ohare) { 2710 struct macio_chip temp = macio_chips[0]; 2711 macio_chips[0] = macio_chips[1]; 2712 macio_chips[1] = temp; 2713 } 2714 macio_chips[0].lbus.index = 0; 2715 macio_chips[1].lbus.index = 1; 2716 2717 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0; 2718 } 2719 2720 static void __init 2721 initial_serial_shutdown(struct device_node *np) 2722 { 2723 int len; 2724 const struct slot_names_prop { 2725 int count; 2726 char name[1]; 2727 } *slots; 2728 const char *conn; 2729 int port_type = PMAC_SCC_ASYNC; 2730 int modem = 0; 2731 2732 slots = of_get_property(np, "slot-names", &len); 2733 conn = of_get_property(np, "AAPL,connector", &len); 2734 if (conn && (strcmp(conn, "infrared") == 0)) 2735 port_type = PMAC_SCC_IRDA; 2736 else if (of_device_is_compatible(np, "cobalt")) 2737 modem = 1; 2738 else if (slots && slots->count > 0) { 2739 if (strcmp(slots->name, "IrDA") == 0) 2740 port_type = PMAC_SCC_IRDA; 2741 else if (strcmp(slots->name, "Modem") == 0) 2742 modem = 1; 2743 } 2744 if (modem) 2745 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0); 2746 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0); 2747 } 2748 2749 static void __init 2750 set_initial_features(void) 2751 { 2752 struct device_node *np; 2753 2754 /* That hack appears to be necessary for some StarMax motherboards 2755 * but I'm not too sure it was audited for side-effects on other 2756 * ohare based machines... 2757 * Since I still have difficulties figuring the right way to 2758 * differentiate them all and since that hack was there for a long 2759 * time, I'll keep it around 2760 */ 2761 if (macio_chips[0].type == macio_ohare) { 2762 struct macio_chip *macio = &macio_chips[0]; 2763 np = of_find_node_by_name(NULL, "via-pmu"); 2764 if (np) 2765 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 2766 else 2767 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES); 2768 of_node_put(np); 2769 } else if (macio_chips[1].type == macio_ohare) { 2770 struct macio_chip *macio = &macio_chips[1]; 2771 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 2772 } 2773 2774 #ifdef CONFIG_PPC64 2775 if (macio_chips[0].type == macio_keylargo2 || 2776 macio_chips[0].type == macio_shasta) { 2777 #ifndef CONFIG_SMP 2778 /* On SMP machines running UP, we have the second CPU eating 2779 * bus cycles. We need to take it off the bus. This is done 2780 * from pmac_smp for SMP kernels running on one CPU 2781 */ 2782 np = of_find_node_by_type(NULL, "cpu"); 2783 if (np != NULL) 2784 np = of_find_node_by_type(np, "cpu"); 2785 if (np != NULL) { 2786 g5_phy_disable_cpu1(); 2787 of_node_put(np); 2788 } 2789 #endif /* CONFIG_SMP */ 2790 /* Enable GMAC for now for PCI probing. It will be disabled 2791 * later on after PCI probe 2792 */ 2793 for_each_node_by_name(np, "ethernet") 2794 if (of_device_is_compatible(np, "K2-GMAC")) 2795 g5_gmac_enable(np, 0, 1); 2796 2797 /* Enable FW before PCI probe. Will be disabled later on 2798 * Note: We should have a batter way to check that we are 2799 * dealing with uninorth internal cell and not a PCI cell 2800 * on the external PCI. The code below works though. 2801 */ 2802 for_each_node_by_name(np, "firewire") { 2803 if (of_device_is_compatible(np, "pci106b,5811")) { 2804 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED; 2805 g5_fw_enable(np, 0, 1); 2806 } 2807 } 2808 } 2809 #else /* CONFIG_PPC64 */ 2810 2811 if (macio_chips[0].type == macio_keylargo || 2812 macio_chips[0].type == macio_pangea || 2813 macio_chips[0].type == macio_intrepid) { 2814 /* Enable GMAC for now for PCI probing. It will be disabled 2815 * later on after PCI probe 2816 */ 2817 for_each_node_by_name(np, "ethernet") { 2818 if (np->parent 2819 && of_device_is_compatible(np->parent, "uni-north") 2820 && of_device_is_compatible(np, "gmac")) 2821 core99_gmac_enable(np, 0, 1); 2822 } 2823 2824 /* Enable FW before PCI probe. Will be disabled later on 2825 * Note: We should have a batter way to check that we are 2826 * dealing with uninorth internal cell and not a PCI cell 2827 * on the external PCI. The code below works though. 2828 */ 2829 for_each_node_by_name(np, "firewire") { 2830 if (np->parent 2831 && of_device_is_compatible(np->parent, "uni-north") 2832 && (of_device_is_compatible(np, "pci106b,18") || 2833 of_device_is_compatible(np, "pci106b,30") || 2834 of_device_is_compatible(np, "pci11c1,5811"))) { 2835 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED; 2836 core99_firewire_enable(np, 0, 1); 2837 } 2838 } 2839 2840 /* Enable ATA-100 before PCI probe. */ 2841 for_each_node_by_name(np, "ata-6") { 2842 if (np->parent 2843 && of_device_is_compatible(np->parent, "uni-north") 2844 && of_device_is_compatible(np, "kauai-ata")) { 2845 core99_ata100_enable(np, 1); 2846 } 2847 } 2848 2849 /* Switch airport off */ 2850 for_each_node_by_name(np, "radio") { 2851 if (np->parent == macio_chips[0].of_node) { 2852 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON; 2853 core99_airport_enable(np, 0, 0); 2854 } 2855 } 2856 } 2857 2858 /* On all machines that support sound PM, switch sound off */ 2859 if (macio_chips[0].of_node) 2860 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE, 2861 macio_chips[0].of_node, 0, 0); 2862 2863 /* While on some desktop G3s, we turn it back on */ 2864 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow 2865 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER || 2866 pmac_mb.model_id == PMAC_TYPE_SILK)) { 2867 struct macio_chip *macio = &macio_chips[0]; 2868 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 2869 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N); 2870 } 2871 2872 #endif /* CONFIG_PPC64 */ 2873 2874 /* On all machines, switch modem & serial ports off */ 2875 for_each_node_by_name(np, "ch-a") 2876 initial_serial_shutdown(np); 2877 for_each_node_by_name(np, "ch-b") 2878 initial_serial_shutdown(np); 2879 } 2880 2881 void __init 2882 pmac_feature_init(void) 2883 { 2884 /* Detect the UniNorth memory controller */ 2885 probe_uninorth(); 2886 2887 /* Probe mac-io controllers */ 2888 if (probe_macios()) { 2889 printk(KERN_WARNING "No mac-io chip found\n"); 2890 return; 2891 } 2892 2893 /* Probe machine type */ 2894 if (probe_motherboard()) 2895 printk(KERN_WARNING "Unknown PowerMac !\n"); 2896 2897 /* Set some initial features (turn off some chips that will 2898 * be later turned on) 2899 */ 2900 set_initial_features(); 2901 } 2902 2903 #if 0 2904 static void dump_HT_speeds(char *name, u32 cfg, u32 frq) 2905 { 2906 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 }; 2907 int bits[8] = { 8,16,0,32,2,4,0,0 }; 2908 int freq = (frq >> 8) & 0xf; 2909 2910 if (freqs[freq] == 0) 2911 printk("%s: Unknown HT link frequency %x\n", name, freq); 2912 else 2913 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n", 2914 name, freqs[freq], 2915 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]); 2916 } 2917 2918 void __init pmac_check_ht_link(void) 2919 { 2920 u32 ufreq, freq, ucfg, cfg; 2921 struct device_node *pcix_node; 2922 u8 px_bus, px_devfn; 2923 struct pci_controller *px_hose; 2924 2925 (void)in_be32(u3_ht_base + U3_HT_LINK_COMMAND); 2926 ucfg = cfg = in_be32(u3_ht_base + U3_HT_LINK_CONFIG); 2927 ufreq = freq = in_be32(u3_ht_base + U3_HT_LINK_FREQ); 2928 dump_HT_speeds("U3 HyperTransport", cfg, freq); 2929 2930 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x"); 2931 if (pcix_node == NULL) { 2932 printk("No PCI-X bridge found\n"); 2933 return; 2934 } 2935 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) { 2936 printk("PCI-X bridge found but not matched to pci\n"); 2937 return; 2938 } 2939 px_hose = pci_find_hose_for_OF_device(pcix_node); 2940 if (px_hose == NULL) { 2941 printk("PCI-X bridge found but not matched to host\n"); 2942 return; 2943 } 2944 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg); 2945 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq); 2946 dump_HT_speeds("PCI-X HT Uplink", cfg, freq); 2947 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg); 2948 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq); 2949 dump_HT_speeds("PCI-X HT Downlink", cfg, freq); 2950 } 2951 #endif /* 0 */ 2952 2953 /* 2954 * Early video resume hook 2955 */ 2956 2957 static void (*pmac_early_vresume_proc)(void *data); 2958 static void *pmac_early_vresume_data; 2959 2960 void pmac_set_early_video_resume(void (*proc)(void *data), void *data) 2961 { 2962 if (!machine_is(powermac)) 2963 return; 2964 preempt_disable(); 2965 pmac_early_vresume_proc = proc; 2966 pmac_early_vresume_data = data; 2967 preempt_enable(); 2968 } 2969 EXPORT_SYMBOL(pmac_set_early_video_resume); 2970 2971 void pmac_call_early_video_resume(void) 2972 { 2973 if (pmac_early_vresume_proc) 2974 pmac_early_vresume_proc(pmac_early_vresume_data); 2975 } 2976 2977 /* 2978 * AGP related suspend/resume code 2979 */ 2980 2981 static struct pci_dev *pmac_agp_bridge; 2982 static int (*pmac_agp_suspend)(struct pci_dev *bridge); 2983 static int (*pmac_agp_resume)(struct pci_dev *bridge); 2984 2985 void pmac_register_agp_pm(struct pci_dev *bridge, 2986 int (*suspend)(struct pci_dev *bridge), 2987 int (*resume)(struct pci_dev *bridge)) 2988 { 2989 if (suspend || resume) { 2990 pmac_agp_bridge = bridge; 2991 pmac_agp_suspend = suspend; 2992 pmac_agp_resume = resume; 2993 return; 2994 } 2995 if (bridge != pmac_agp_bridge) 2996 return; 2997 pmac_agp_suspend = pmac_agp_resume = NULL; 2998 return; 2999 } 3000 EXPORT_SYMBOL(pmac_register_agp_pm); 3001 3002 void pmac_suspend_agp_for_card(struct pci_dev *dev) 3003 { 3004 if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL) 3005 return; 3006 if (pmac_agp_bridge->bus != dev->bus) 3007 return; 3008 pmac_agp_suspend(pmac_agp_bridge); 3009 } 3010 EXPORT_SYMBOL(pmac_suspend_agp_for_card); 3011 3012 void pmac_resume_agp_for_card(struct pci_dev *dev) 3013 { 3014 if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL) 3015 return; 3016 if (pmac_agp_bridge->bus != dev->bus) 3017 return; 3018 pmac_agp_resume(pmac_agp_bridge); 3019 } 3020 EXPORT_SYMBOL(pmac_resume_agp_for_card); 3021 3022 int pmac_get_uninorth_variant(void) 3023 { 3024 return uninorth_maj; 3025 } 3026