1 /* 2 * Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au) 3 * Ben. Herrenschmidt (benh@kernel.crashing.org) 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 * 10 * TODO: 11 * 12 * - Replace mdelay with some schedule loop if possible 13 * - Shorten some obfuscated delays on some routines (like modem 14 * power) 15 * - Refcount some clocks (see darwin) 16 * - Split split split... 17 * 18 */ 19 #include <linux/types.h> 20 #include <linux/init.h> 21 #include <linux/delay.h> 22 #include <linux/kernel.h> 23 #include <linux/sched.h> 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/spinlock.h> 27 #include <linux/adb.h> 28 #include <linux/pmu.h> 29 #include <linux/ioport.h> 30 #include <linux/pci.h> 31 #include <asm/sections.h> 32 #include <asm/errno.h> 33 #include <asm/ohare.h> 34 #include <asm/heathrow.h> 35 #include <asm/keylargo.h> 36 #include <asm/uninorth.h> 37 #include <asm/io.h> 38 #include <asm/prom.h> 39 #include <asm/machdep.h> 40 #include <asm/pmac_feature.h> 41 #include <asm/dbdma.h> 42 #include <asm/pci-bridge.h> 43 #include <asm/pmac_low_i2c.h> 44 45 #undef DEBUG_FEATURE 46 47 #ifdef DEBUG_FEATURE 48 #define DBG(fmt...) printk(KERN_DEBUG fmt) 49 #else 50 #define DBG(fmt...) 51 #endif 52 53 #ifdef CONFIG_6xx 54 extern int powersave_lowspeed; 55 #endif 56 57 extern int powersave_nap; 58 extern struct device_node *k2_skiplist[2]; 59 60 /* 61 * We use a single global lock to protect accesses. Each driver has 62 * to take care of its own locking 63 */ 64 DEFINE_RAW_SPINLOCK(feature_lock); 65 66 #define LOCK(flags) raw_spin_lock_irqsave(&feature_lock, flags); 67 #define UNLOCK(flags) raw_spin_unlock_irqrestore(&feature_lock, flags); 68 69 70 /* 71 * Instance of some macio stuffs 72 */ 73 struct macio_chip macio_chips[MAX_MACIO_CHIPS]; 74 75 struct macio_chip *macio_find(struct device_node *child, int type) 76 { 77 while(child) { 78 int i; 79 80 for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++) 81 if (child == macio_chips[i].of_node && 82 (!type || macio_chips[i].type == type)) 83 return &macio_chips[i]; 84 child = child->parent; 85 } 86 return NULL; 87 } 88 EXPORT_SYMBOL_GPL(macio_find); 89 90 static const char *macio_names[] = 91 { 92 "Unknown", 93 "Grand Central", 94 "OHare", 95 "OHareII", 96 "Heathrow", 97 "Gatwick", 98 "Paddington", 99 "Keylargo", 100 "Pangea", 101 "Intrepid", 102 "K2", 103 "Shasta", 104 }; 105 106 107 struct device_node *uninorth_node; 108 u32 __iomem *uninorth_base; 109 110 static u32 uninorth_rev; 111 static int uninorth_maj; 112 static void __iomem *u3_ht_base; 113 114 /* 115 * For each motherboard family, we have a table of functions pointers 116 * that handle the various features. 117 */ 118 119 typedef long (*feature_call)(struct device_node *node, long param, long value); 120 121 struct feature_table_entry { 122 unsigned int selector; 123 feature_call function; 124 }; 125 126 struct pmac_mb_def 127 { 128 const char* model_string; 129 const char* model_name; 130 int model_id; 131 struct feature_table_entry* features; 132 unsigned long board_flags; 133 }; 134 static struct pmac_mb_def pmac_mb; 135 136 /* 137 * Here are the chip specific feature functions 138 */ 139 140 static inline int simple_feature_tweak(struct device_node *node, int type, 141 int reg, u32 mask, int value) 142 { 143 struct macio_chip* macio; 144 unsigned long flags; 145 146 macio = macio_find(node, type); 147 if (!macio) 148 return -ENODEV; 149 LOCK(flags); 150 if (value) 151 MACIO_BIS(reg, mask); 152 else 153 MACIO_BIC(reg, mask); 154 (void)MACIO_IN32(reg); 155 UNLOCK(flags); 156 157 return 0; 158 } 159 160 #ifndef CONFIG_POWER4 161 162 static long ohare_htw_scc_enable(struct device_node *node, long param, 163 long value) 164 { 165 struct macio_chip* macio; 166 unsigned long chan_mask; 167 unsigned long fcr; 168 unsigned long flags; 169 int htw, trans; 170 unsigned long rmask; 171 172 macio = macio_find(node, 0); 173 if (!macio) 174 return -ENODEV; 175 if (!strcmp(node->name, "ch-a")) 176 chan_mask = MACIO_FLAG_SCCA_ON; 177 else if (!strcmp(node->name, "ch-b")) 178 chan_mask = MACIO_FLAG_SCCB_ON; 179 else 180 return -ENODEV; 181 182 htw = (macio->type == macio_heathrow || macio->type == macio_paddington 183 || macio->type == macio_gatwick); 184 /* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */ 185 trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE && 186 pmac_mb.model_id != PMAC_TYPE_YIKES); 187 if (value) { 188 #ifdef CONFIG_ADB_PMU 189 if ((param & 0xfff) == PMAC_SCC_IRDA) 190 pmu_enable_irled(1); 191 #endif /* CONFIG_ADB_PMU */ 192 LOCK(flags); 193 fcr = MACIO_IN32(OHARE_FCR); 194 /* Check if scc cell need enabling */ 195 if (!(fcr & OH_SCC_ENABLE)) { 196 fcr |= OH_SCC_ENABLE; 197 if (htw) { 198 /* Side effect: this will also power up the 199 * modem, but it's too messy to figure out on which 200 * ports this controls the tranceiver and on which 201 * it controls the modem 202 */ 203 if (trans) 204 fcr &= ~HRW_SCC_TRANS_EN_N; 205 MACIO_OUT32(OHARE_FCR, fcr); 206 fcr |= (rmask = HRW_RESET_SCC); 207 MACIO_OUT32(OHARE_FCR, fcr); 208 } else { 209 fcr |= (rmask = OH_SCC_RESET); 210 MACIO_OUT32(OHARE_FCR, fcr); 211 } 212 UNLOCK(flags); 213 (void)MACIO_IN32(OHARE_FCR); 214 mdelay(15); 215 LOCK(flags); 216 fcr &= ~rmask; 217 MACIO_OUT32(OHARE_FCR, fcr); 218 } 219 if (chan_mask & MACIO_FLAG_SCCA_ON) 220 fcr |= OH_SCCA_IO; 221 if (chan_mask & MACIO_FLAG_SCCB_ON) 222 fcr |= OH_SCCB_IO; 223 MACIO_OUT32(OHARE_FCR, fcr); 224 macio->flags |= chan_mask; 225 UNLOCK(flags); 226 if (param & PMAC_SCC_FLAG_XMON) 227 macio->flags |= MACIO_FLAG_SCC_LOCKED; 228 } else { 229 if (macio->flags & MACIO_FLAG_SCC_LOCKED) 230 return -EPERM; 231 LOCK(flags); 232 fcr = MACIO_IN32(OHARE_FCR); 233 if (chan_mask & MACIO_FLAG_SCCA_ON) 234 fcr &= ~OH_SCCA_IO; 235 if (chan_mask & MACIO_FLAG_SCCB_ON) 236 fcr &= ~OH_SCCB_IO; 237 MACIO_OUT32(OHARE_FCR, fcr); 238 if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) { 239 fcr &= ~OH_SCC_ENABLE; 240 if (htw && trans) 241 fcr |= HRW_SCC_TRANS_EN_N; 242 MACIO_OUT32(OHARE_FCR, fcr); 243 } 244 macio->flags &= ~(chan_mask); 245 UNLOCK(flags); 246 mdelay(10); 247 #ifdef CONFIG_ADB_PMU 248 if ((param & 0xfff) == PMAC_SCC_IRDA) 249 pmu_enable_irled(0); 250 #endif /* CONFIG_ADB_PMU */ 251 } 252 return 0; 253 } 254 255 static long ohare_floppy_enable(struct device_node *node, long param, 256 long value) 257 { 258 return simple_feature_tweak(node, macio_ohare, 259 OHARE_FCR, OH_FLOPPY_ENABLE, value); 260 } 261 262 static long ohare_mesh_enable(struct device_node *node, long param, long value) 263 { 264 return simple_feature_tweak(node, macio_ohare, 265 OHARE_FCR, OH_MESH_ENABLE, value); 266 } 267 268 static long ohare_ide_enable(struct device_node *node, long param, long value) 269 { 270 switch(param) { 271 case 0: 272 /* For some reason, setting the bit in set_initial_features() 273 * doesn't stick. I'm still investigating... --BenH. 274 */ 275 if (value) 276 simple_feature_tweak(node, macio_ohare, 277 OHARE_FCR, OH_IOBUS_ENABLE, 1); 278 return simple_feature_tweak(node, macio_ohare, 279 OHARE_FCR, OH_IDE0_ENABLE, value); 280 case 1: 281 return simple_feature_tweak(node, macio_ohare, 282 OHARE_FCR, OH_BAY_IDE_ENABLE, value); 283 default: 284 return -ENODEV; 285 } 286 } 287 288 static long ohare_ide_reset(struct device_node *node, long param, long value) 289 { 290 switch(param) { 291 case 0: 292 return simple_feature_tweak(node, macio_ohare, 293 OHARE_FCR, OH_IDE0_RESET_N, !value); 294 case 1: 295 return simple_feature_tweak(node, macio_ohare, 296 OHARE_FCR, OH_IDE1_RESET_N, !value); 297 default: 298 return -ENODEV; 299 } 300 } 301 302 static long ohare_sleep_state(struct device_node *node, long param, long value) 303 { 304 struct macio_chip* macio = &macio_chips[0]; 305 306 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 307 return -EPERM; 308 if (value == 1) { 309 MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE); 310 } else if (value == 0) { 311 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 312 } 313 314 return 0; 315 } 316 317 static long heathrow_modem_enable(struct device_node *node, long param, 318 long value) 319 { 320 struct macio_chip* macio; 321 u8 gpio; 322 unsigned long flags; 323 324 macio = macio_find(node, macio_unknown); 325 if (!macio) 326 return -ENODEV; 327 gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1; 328 if (!value) { 329 LOCK(flags); 330 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio); 331 UNLOCK(flags); 332 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 333 mdelay(250); 334 } 335 if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE && 336 pmac_mb.model_id != PMAC_TYPE_YIKES) { 337 LOCK(flags); 338 if (value) 339 MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 340 else 341 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 342 UNLOCK(flags); 343 (void)MACIO_IN32(HEATHROW_FCR); 344 mdelay(250); 345 } 346 if (value) { 347 LOCK(flags); 348 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1); 349 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 350 UNLOCK(flags); mdelay(250); LOCK(flags); 351 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio); 352 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 353 UNLOCK(flags); mdelay(250); LOCK(flags); 354 MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1); 355 (void)MACIO_IN8(HRW_GPIO_MODEM_RESET); 356 UNLOCK(flags); mdelay(250); 357 } 358 return 0; 359 } 360 361 static long heathrow_floppy_enable(struct device_node *node, long param, 362 long value) 363 { 364 return simple_feature_tweak(node, macio_unknown, 365 HEATHROW_FCR, 366 HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE, 367 value); 368 } 369 370 static long heathrow_mesh_enable(struct device_node *node, long param, 371 long value) 372 { 373 struct macio_chip* macio; 374 unsigned long flags; 375 376 macio = macio_find(node, macio_unknown); 377 if (!macio) 378 return -ENODEV; 379 LOCK(flags); 380 /* Set clear mesh cell enable */ 381 if (value) 382 MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE); 383 else 384 MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE); 385 (void)MACIO_IN32(HEATHROW_FCR); 386 udelay(10); 387 /* Set/Clear termination power */ 388 if (value) 389 MACIO_BIC(HEATHROW_MBCR, 0x04000000); 390 else 391 MACIO_BIS(HEATHROW_MBCR, 0x04000000); 392 (void)MACIO_IN32(HEATHROW_MBCR); 393 udelay(10); 394 UNLOCK(flags); 395 396 return 0; 397 } 398 399 static long heathrow_ide_enable(struct device_node *node, long param, 400 long value) 401 { 402 switch(param) { 403 case 0: 404 return simple_feature_tweak(node, macio_unknown, 405 HEATHROW_FCR, HRW_IDE0_ENABLE, value); 406 case 1: 407 return simple_feature_tweak(node, macio_unknown, 408 HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value); 409 default: 410 return -ENODEV; 411 } 412 } 413 414 static long heathrow_ide_reset(struct device_node *node, long param, 415 long value) 416 { 417 switch(param) { 418 case 0: 419 return simple_feature_tweak(node, macio_unknown, 420 HEATHROW_FCR, HRW_IDE0_RESET_N, !value); 421 case 1: 422 return simple_feature_tweak(node, macio_unknown, 423 HEATHROW_FCR, HRW_IDE1_RESET_N, !value); 424 default: 425 return -ENODEV; 426 } 427 } 428 429 static long heathrow_bmac_enable(struct device_node *node, long param, 430 long value) 431 { 432 struct macio_chip* macio; 433 unsigned long flags; 434 435 macio = macio_find(node, 0); 436 if (!macio) 437 return -ENODEV; 438 if (value) { 439 LOCK(flags); 440 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE); 441 MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET); 442 UNLOCK(flags); 443 (void)MACIO_IN32(HEATHROW_FCR); 444 mdelay(10); 445 LOCK(flags); 446 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET); 447 UNLOCK(flags); 448 (void)MACIO_IN32(HEATHROW_FCR); 449 mdelay(10); 450 } else { 451 LOCK(flags); 452 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE); 453 UNLOCK(flags); 454 } 455 return 0; 456 } 457 458 static long heathrow_sound_enable(struct device_node *node, long param, 459 long value) 460 { 461 struct macio_chip* macio; 462 unsigned long flags; 463 464 /* B&W G3 and Yikes don't support that properly (the 465 * sound appear to never come back after beeing shut down). 466 */ 467 if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE || 468 pmac_mb.model_id == PMAC_TYPE_YIKES) 469 return 0; 470 471 macio = macio_find(node, 0); 472 if (!macio) 473 return -ENODEV; 474 if (value) { 475 LOCK(flags); 476 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 477 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N); 478 UNLOCK(flags); 479 (void)MACIO_IN32(HEATHROW_FCR); 480 } else { 481 LOCK(flags); 482 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N); 483 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 484 UNLOCK(flags); 485 } 486 return 0; 487 } 488 489 static u32 save_fcr[6]; 490 static u32 save_mbcr; 491 static struct dbdma_regs save_dbdma[13]; 492 static struct dbdma_regs save_alt_dbdma[13]; 493 494 static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save) 495 { 496 int i; 497 498 /* Save state & config of DBDMA channels */ 499 for (i = 0; i < 13; i++) { 500 volatile struct dbdma_regs __iomem * chan = (void __iomem *) 501 (macio->base + ((0x8000+i*0x100)>>2)); 502 save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi); 503 save[i].cmdptr = in_le32(&chan->cmdptr); 504 save[i].intr_sel = in_le32(&chan->intr_sel); 505 save[i].br_sel = in_le32(&chan->br_sel); 506 save[i].wait_sel = in_le32(&chan->wait_sel); 507 } 508 } 509 510 static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save) 511 { 512 int i; 513 514 /* Save state & config of DBDMA channels */ 515 for (i = 0; i < 13; i++) { 516 volatile struct dbdma_regs __iomem * chan = (void __iomem *) 517 (macio->base + ((0x8000+i*0x100)>>2)); 518 out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16); 519 while (in_le32(&chan->status) & ACTIVE) 520 mb(); 521 out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi); 522 out_le32(&chan->cmdptr, save[i].cmdptr); 523 out_le32(&chan->intr_sel, save[i].intr_sel); 524 out_le32(&chan->br_sel, save[i].br_sel); 525 out_le32(&chan->wait_sel, save[i].wait_sel); 526 } 527 } 528 529 static void heathrow_sleep(struct macio_chip *macio, int secondary) 530 { 531 if (secondary) { 532 dbdma_save(macio, save_alt_dbdma); 533 save_fcr[2] = MACIO_IN32(0x38); 534 save_fcr[3] = MACIO_IN32(0x3c); 535 } else { 536 dbdma_save(macio, save_dbdma); 537 save_fcr[0] = MACIO_IN32(0x38); 538 save_fcr[1] = MACIO_IN32(0x3c); 539 save_mbcr = MACIO_IN32(0x34); 540 /* Make sure sound is shut down */ 541 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N); 542 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 543 /* This seems to be necessary as well or the fan 544 * keeps coming up and battery drains fast */ 545 MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE); 546 MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N); 547 /* Make sure eth is down even if module or sleep 548 * won't work properly */ 549 MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET); 550 } 551 /* Make sure modem is shut down */ 552 MACIO_OUT8(HRW_GPIO_MODEM_RESET, 553 MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1); 554 MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N); 555 MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE); 556 557 /* Let things settle */ 558 (void)MACIO_IN32(HEATHROW_FCR); 559 } 560 561 static void heathrow_wakeup(struct macio_chip *macio, int secondary) 562 { 563 if (secondary) { 564 MACIO_OUT32(0x38, save_fcr[2]); 565 (void)MACIO_IN32(0x38); 566 mdelay(1); 567 MACIO_OUT32(0x3c, save_fcr[3]); 568 (void)MACIO_IN32(0x38); 569 mdelay(10); 570 dbdma_restore(macio, save_alt_dbdma); 571 } else { 572 MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE); 573 (void)MACIO_IN32(0x38); 574 mdelay(1); 575 MACIO_OUT32(0x3c, save_fcr[1]); 576 (void)MACIO_IN32(0x38); 577 mdelay(1); 578 MACIO_OUT32(0x34, save_mbcr); 579 (void)MACIO_IN32(0x38); 580 mdelay(10); 581 dbdma_restore(macio, save_dbdma); 582 } 583 } 584 585 static long heathrow_sleep_state(struct device_node *node, long param, 586 long value) 587 { 588 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 589 return -EPERM; 590 if (value == 1) { 591 if (macio_chips[1].type == macio_gatwick) 592 heathrow_sleep(&macio_chips[0], 1); 593 heathrow_sleep(&macio_chips[0], 0); 594 } else if (value == 0) { 595 heathrow_wakeup(&macio_chips[0], 0); 596 if (macio_chips[1].type == macio_gatwick) 597 heathrow_wakeup(&macio_chips[0], 1); 598 } 599 return 0; 600 } 601 602 static long core99_scc_enable(struct device_node *node, long param, long value) 603 { 604 struct macio_chip* macio; 605 unsigned long flags; 606 unsigned long chan_mask; 607 u32 fcr; 608 609 macio = macio_find(node, 0); 610 if (!macio) 611 return -ENODEV; 612 if (!strcmp(node->name, "ch-a")) 613 chan_mask = MACIO_FLAG_SCCA_ON; 614 else if (!strcmp(node->name, "ch-b")) 615 chan_mask = MACIO_FLAG_SCCB_ON; 616 else 617 return -ENODEV; 618 619 if (value) { 620 int need_reset_scc = 0; 621 int need_reset_irda = 0; 622 623 LOCK(flags); 624 fcr = MACIO_IN32(KEYLARGO_FCR0); 625 /* Check if scc cell need enabling */ 626 if (!(fcr & KL0_SCC_CELL_ENABLE)) { 627 fcr |= KL0_SCC_CELL_ENABLE; 628 need_reset_scc = 1; 629 } 630 if (chan_mask & MACIO_FLAG_SCCA_ON) { 631 fcr |= KL0_SCCA_ENABLE; 632 /* Don't enable line drivers for I2S modem */ 633 if ((param & 0xfff) == PMAC_SCC_I2S1) 634 fcr &= ~KL0_SCC_A_INTF_ENABLE; 635 else 636 fcr |= KL0_SCC_A_INTF_ENABLE; 637 } 638 if (chan_mask & MACIO_FLAG_SCCB_ON) { 639 fcr |= KL0_SCCB_ENABLE; 640 /* Perform irda specific inits */ 641 if ((param & 0xfff) == PMAC_SCC_IRDA) { 642 fcr &= ~KL0_SCC_B_INTF_ENABLE; 643 fcr |= KL0_IRDA_ENABLE; 644 fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE; 645 fcr |= KL0_IRDA_SOURCE1_SEL; 646 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); 647 fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); 648 need_reset_irda = 1; 649 } else 650 fcr |= KL0_SCC_B_INTF_ENABLE; 651 } 652 MACIO_OUT32(KEYLARGO_FCR0, fcr); 653 macio->flags |= chan_mask; 654 if (need_reset_scc) { 655 MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET); 656 (void)MACIO_IN32(KEYLARGO_FCR0); 657 UNLOCK(flags); 658 mdelay(15); 659 LOCK(flags); 660 MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET); 661 } 662 if (need_reset_irda) { 663 MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET); 664 (void)MACIO_IN32(KEYLARGO_FCR0); 665 UNLOCK(flags); 666 mdelay(15); 667 LOCK(flags); 668 MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET); 669 } 670 UNLOCK(flags); 671 if (param & PMAC_SCC_FLAG_XMON) 672 macio->flags |= MACIO_FLAG_SCC_LOCKED; 673 } else { 674 if (macio->flags & MACIO_FLAG_SCC_LOCKED) 675 return -EPERM; 676 LOCK(flags); 677 fcr = MACIO_IN32(KEYLARGO_FCR0); 678 if (chan_mask & MACIO_FLAG_SCCA_ON) 679 fcr &= ~KL0_SCCA_ENABLE; 680 if (chan_mask & MACIO_FLAG_SCCB_ON) { 681 fcr &= ~KL0_SCCB_ENABLE; 682 /* Perform irda specific clears */ 683 if ((param & 0xfff) == PMAC_SCC_IRDA) { 684 fcr &= ~KL0_IRDA_ENABLE; 685 fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE); 686 fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0); 687 fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND); 688 } 689 } 690 MACIO_OUT32(KEYLARGO_FCR0, fcr); 691 if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) { 692 fcr &= ~KL0_SCC_CELL_ENABLE; 693 MACIO_OUT32(KEYLARGO_FCR0, fcr); 694 } 695 macio->flags &= ~(chan_mask); 696 UNLOCK(flags); 697 mdelay(10); 698 } 699 return 0; 700 } 701 702 static long 703 core99_modem_enable(struct device_node *node, long param, long value) 704 { 705 struct macio_chip* macio; 706 u8 gpio; 707 unsigned long flags; 708 709 /* Hack for internal USB modem */ 710 if (node == NULL) { 711 if (macio_chips[0].type != macio_keylargo) 712 return -ENODEV; 713 node = macio_chips[0].of_node; 714 } 715 macio = macio_find(node, 0); 716 if (!macio) 717 return -ENODEV; 718 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET); 719 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE; 720 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA; 721 722 if (!value) { 723 LOCK(flags); 724 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 725 UNLOCK(flags); 726 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 727 mdelay(250); 728 } 729 LOCK(flags); 730 if (value) { 731 MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 732 UNLOCK(flags); 733 (void)MACIO_IN32(KEYLARGO_FCR2); 734 mdelay(250); 735 } else { 736 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 737 UNLOCK(flags); 738 } 739 if (value) { 740 LOCK(flags); 741 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 742 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 743 UNLOCK(flags); mdelay(250); LOCK(flags); 744 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 745 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 746 UNLOCK(flags); mdelay(250); LOCK(flags); 747 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 748 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 749 UNLOCK(flags); mdelay(250); 750 } 751 return 0; 752 } 753 754 static long 755 pangea_modem_enable(struct device_node *node, long param, long value) 756 { 757 struct macio_chip* macio; 758 u8 gpio; 759 unsigned long flags; 760 761 /* Hack for internal USB modem */ 762 if (node == NULL) { 763 if (macio_chips[0].type != macio_pangea && 764 macio_chips[0].type != macio_intrepid) 765 return -ENODEV; 766 node = macio_chips[0].of_node; 767 } 768 macio = macio_find(node, 0); 769 if (!macio) 770 return -ENODEV; 771 gpio = MACIO_IN8(KL_GPIO_MODEM_RESET); 772 gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE; 773 gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA; 774 775 if (!value) { 776 LOCK(flags); 777 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 778 UNLOCK(flags); 779 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 780 mdelay(250); 781 } 782 LOCK(flags); 783 if (value) { 784 MACIO_OUT8(KL_GPIO_MODEM_POWER, 785 KEYLARGO_GPIO_OUTPUT_ENABLE); 786 UNLOCK(flags); 787 (void)MACIO_IN32(KEYLARGO_FCR2); 788 mdelay(250); 789 } else { 790 MACIO_OUT8(KL_GPIO_MODEM_POWER, 791 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA); 792 UNLOCK(flags); 793 } 794 if (value) { 795 LOCK(flags); 796 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 797 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 798 UNLOCK(flags); mdelay(250); LOCK(flags); 799 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio); 800 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 801 UNLOCK(flags); mdelay(250); LOCK(flags); 802 MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA); 803 (void)MACIO_IN8(KL_GPIO_MODEM_RESET); 804 UNLOCK(flags); mdelay(250); 805 } 806 return 0; 807 } 808 809 static long 810 core99_ata100_enable(struct device_node *node, long value) 811 { 812 unsigned long flags; 813 struct pci_dev *pdev = NULL; 814 u8 pbus, pid; 815 int rc; 816 817 if (uninorth_rev < 0x24) 818 return -ENODEV; 819 820 LOCK(flags); 821 if (value) 822 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100); 823 else 824 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100); 825 (void)UN_IN(UNI_N_CLOCK_CNTL); 826 UNLOCK(flags); 827 udelay(20); 828 829 if (value) { 830 if (pci_device_from_OF_node(node, &pbus, &pid) == 0) 831 pdev = pci_get_bus_and_slot(pbus, pid); 832 if (pdev == NULL) 833 return 0; 834 rc = pci_enable_device(pdev); 835 if (rc == 0) 836 pci_set_master(pdev); 837 pci_dev_put(pdev); 838 if (rc) 839 return rc; 840 } 841 return 0; 842 } 843 844 static long 845 core99_ide_enable(struct device_node *node, long param, long value) 846 { 847 /* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2 848 * based ata-100 849 */ 850 switch(param) { 851 case 0: 852 return simple_feature_tweak(node, macio_unknown, 853 KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value); 854 case 1: 855 return simple_feature_tweak(node, macio_unknown, 856 KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value); 857 case 2: 858 return simple_feature_tweak(node, macio_unknown, 859 KEYLARGO_FCR1, KL1_UIDE_ENABLE, value); 860 case 3: 861 return core99_ata100_enable(node, value); 862 default: 863 return -ENODEV; 864 } 865 } 866 867 static long 868 core99_ide_reset(struct device_node *node, long param, long value) 869 { 870 switch(param) { 871 case 0: 872 return simple_feature_tweak(node, macio_unknown, 873 KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value); 874 case 1: 875 return simple_feature_tweak(node, macio_unknown, 876 KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value); 877 case 2: 878 return simple_feature_tweak(node, macio_unknown, 879 KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value); 880 default: 881 return -ENODEV; 882 } 883 } 884 885 static long 886 core99_gmac_enable(struct device_node *node, long param, long value) 887 { 888 unsigned long flags; 889 890 LOCK(flags); 891 if (value) 892 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC); 893 else 894 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC); 895 (void)UN_IN(UNI_N_CLOCK_CNTL); 896 UNLOCK(flags); 897 udelay(20); 898 899 return 0; 900 } 901 902 static long 903 core99_gmac_phy_reset(struct device_node *node, long param, long value) 904 { 905 unsigned long flags; 906 struct macio_chip *macio; 907 908 macio = &macio_chips[0]; 909 if (macio->type != macio_keylargo && macio->type != macio_pangea && 910 macio->type != macio_intrepid) 911 return -ENODEV; 912 913 LOCK(flags); 914 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE); 915 (void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET); 916 UNLOCK(flags); 917 mdelay(10); 918 LOCK(flags); 919 MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */ 920 KEYLARGO_GPIO_OUTOUT_DATA); 921 UNLOCK(flags); 922 mdelay(10); 923 924 return 0; 925 } 926 927 static long 928 core99_sound_chip_enable(struct device_node *node, long param, long value) 929 { 930 struct macio_chip* macio; 931 unsigned long flags; 932 933 macio = macio_find(node, 0); 934 if (!macio) 935 return -ENODEV; 936 937 /* Do a better probe code, screamer G4 desktops & 938 * iMacs can do that too, add a recalibrate in 939 * the driver as well 940 */ 941 if (pmac_mb.model_id == PMAC_TYPE_PISMO || 942 pmac_mb.model_id == PMAC_TYPE_TITANIUM) { 943 LOCK(flags); 944 if (value) 945 MACIO_OUT8(KL_GPIO_SOUND_POWER, 946 KEYLARGO_GPIO_OUTPUT_ENABLE | 947 KEYLARGO_GPIO_OUTOUT_DATA); 948 else 949 MACIO_OUT8(KL_GPIO_SOUND_POWER, 950 KEYLARGO_GPIO_OUTPUT_ENABLE); 951 (void)MACIO_IN8(KL_GPIO_SOUND_POWER); 952 UNLOCK(flags); 953 } 954 return 0; 955 } 956 957 static long 958 core99_airport_enable(struct device_node *node, long param, long value) 959 { 960 struct macio_chip* macio; 961 unsigned long flags; 962 int state; 963 964 macio = macio_find(node, 0); 965 if (!macio) 966 return -ENODEV; 967 968 /* Hint: we allow passing of macio itself for the sake of the 969 * sleep code 970 */ 971 if (node != macio->of_node && 972 (!node->parent || node->parent != macio->of_node)) 973 return -ENODEV; 974 state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0; 975 if (value == state) 976 return 0; 977 if (value) { 978 /* This code is a reproduction of OF enable-cardslot 979 * and init-wireless methods, slightly hacked until 980 * I got it working. 981 */ 982 LOCK(flags); 983 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5); 984 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf); 985 UNLOCK(flags); 986 mdelay(10); 987 LOCK(flags); 988 MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4); 989 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xf); 990 UNLOCK(flags); 991 992 mdelay(10); 993 994 LOCK(flags); 995 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16); 996 (void)MACIO_IN32(KEYLARGO_FCR2); 997 udelay(10); 998 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0); 999 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb); 1000 udelay(10); 1001 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28); 1002 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa); 1003 udelay(10); 1004 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28); 1005 (void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd); 1006 udelay(10); 1007 MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28); 1008 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xd); 1009 udelay(10); 1010 MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28); 1011 (void)MACIO_IN8(KEYLARGO_GPIO_0+0xe); 1012 UNLOCK(flags); 1013 udelay(10); 1014 MACIO_OUT32(0x1c000, 0); 1015 mdelay(1); 1016 MACIO_OUT8(0x1a3e0, 0x41); 1017 (void)MACIO_IN8(0x1a3e0); 1018 udelay(10); 1019 LOCK(flags); 1020 MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16); 1021 (void)MACIO_IN32(KEYLARGO_FCR2); 1022 UNLOCK(flags); 1023 mdelay(100); 1024 1025 macio->flags |= MACIO_FLAG_AIRPORT_ON; 1026 } else { 1027 LOCK(flags); 1028 MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16); 1029 (void)MACIO_IN32(KEYLARGO_FCR2); 1030 MACIO_OUT8(KL_GPIO_AIRPORT_0, 0); 1031 MACIO_OUT8(KL_GPIO_AIRPORT_1, 0); 1032 MACIO_OUT8(KL_GPIO_AIRPORT_2, 0); 1033 MACIO_OUT8(KL_GPIO_AIRPORT_3, 0); 1034 MACIO_OUT8(KL_GPIO_AIRPORT_4, 0); 1035 (void)MACIO_IN8(KL_GPIO_AIRPORT_4); 1036 UNLOCK(flags); 1037 1038 macio->flags &= ~MACIO_FLAG_AIRPORT_ON; 1039 } 1040 return 0; 1041 } 1042 1043 #ifdef CONFIG_SMP 1044 static long 1045 core99_reset_cpu(struct device_node *node, long param, long value) 1046 { 1047 unsigned int reset_io = 0; 1048 unsigned long flags; 1049 struct macio_chip *macio; 1050 struct device_node *np; 1051 struct device_node *cpus; 1052 const int dflt_reset_lines[] = { KL_GPIO_RESET_CPU0, 1053 KL_GPIO_RESET_CPU1, 1054 KL_GPIO_RESET_CPU2, 1055 KL_GPIO_RESET_CPU3 }; 1056 1057 macio = &macio_chips[0]; 1058 if (macio->type != macio_keylargo) 1059 return -ENODEV; 1060 1061 cpus = of_find_node_by_path("/cpus"); 1062 if (cpus == NULL) 1063 return -ENODEV; 1064 for (np = cpus->child; np != NULL; np = np->sibling) { 1065 const u32 *num = of_get_property(np, "reg", NULL); 1066 const u32 *rst = of_get_property(np, "soft-reset", NULL); 1067 if (num == NULL || rst == NULL) 1068 continue; 1069 if (param == *num) { 1070 reset_io = *rst; 1071 break; 1072 } 1073 } 1074 of_node_put(cpus); 1075 if (np == NULL || reset_io == 0) 1076 reset_io = dflt_reset_lines[param]; 1077 1078 LOCK(flags); 1079 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE); 1080 (void)MACIO_IN8(reset_io); 1081 udelay(1); 1082 MACIO_OUT8(reset_io, 0); 1083 (void)MACIO_IN8(reset_io); 1084 UNLOCK(flags); 1085 1086 return 0; 1087 } 1088 #endif /* CONFIG_SMP */ 1089 1090 static long 1091 core99_usb_enable(struct device_node *node, long param, long value) 1092 { 1093 struct macio_chip *macio; 1094 unsigned long flags; 1095 const char *prop; 1096 int number; 1097 u32 reg; 1098 1099 macio = &macio_chips[0]; 1100 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1101 macio->type != macio_intrepid) 1102 return -ENODEV; 1103 1104 prop = of_get_property(node, "AAPL,clock-id", NULL); 1105 if (!prop) 1106 return -ENODEV; 1107 if (strncmp(prop, "usb0u048", 8) == 0) 1108 number = 0; 1109 else if (strncmp(prop, "usb1u148", 8) == 0) 1110 number = 2; 1111 else if (strncmp(prop, "usb2u248", 8) == 0) 1112 number = 4; 1113 else 1114 return -ENODEV; 1115 1116 /* Sorry for the brute-force locking, but this is only used during 1117 * sleep and the timing seem to be critical 1118 */ 1119 LOCK(flags); 1120 if (value) { 1121 /* Turn ON */ 1122 if (number == 0) { 1123 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1)); 1124 (void)MACIO_IN32(KEYLARGO_FCR0); 1125 UNLOCK(flags); 1126 mdelay(1); 1127 LOCK(flags); 1128 MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE); 1129 } else if (number == 2) { 1130 MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1)); 1131 UNLOCK(flags); 1132 (void)MACIO_IN32(KEYLARGO_FCR0); 1133 mdelay(1); 1134 LOCK(flags); 1135 MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE); 1136 } else if (number == 4) { 1137 MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1)); 1138 UNLOCK(flags); 1139 (void)MACIO_IN32(KEYLARGO_FCR1); 1140 mdelay(1); 1141 LOCK(flags); 1142 MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE); 1143 } 1144 if (number < 4) { 1145 reg = MACIO_IN32(KEYLARGO_FCR4); 1146 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | 1147 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number)); 1148 reg &= ~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | 1149 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1)); 1150 MACIO_OUT32(KEYLARGO_FCR4, reg); 1151 (void)MACIO_IN32(KEYLARGO_FCR4); 1152 udelay(10); 1153 } else { 1154 reg = MACIO_IN32(KEYLARGO_FCR3); 1155 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | 1156 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0)); 1157 reg &= ~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | 1158 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1)); 1159 MACIO_OUT32(KEYLARGO_FCR3, reg); 1160 (void)MACIO_IN32(KEYLARGO_FCR3); 1161 udelay(10); 1162 } 1163 if (macio->type == macio_intrepid) { 1164 /* wait for clock stopped bits to clear */ 1165 u32 test0 = 0, test1 = 0; 1166 u32 status0, status1; 1167 int timeout = 1000; 1168 1169 UNLOCK(flags); 1170 switch (number) { 1171 case 0: 1172 test0 = UNI_N_CLOCK_STOPPED_USB0; 1173 test1 = UNI_N_CLOCK_STOPPED_USB0PCI; 1174 break; 1175 case 2: 1176 test0 = UNI_N_CLOCK_STOPPED_USB1; 1177 test1 = UNI_N_CLOCK_STOPPED_USB1PCI; 1178 break; 1179 case 4: 1180 test0 = UNI_N_CLOCK_STOPPED_USB2; 1181 test1 = UNI_N_CLOCK_STOPPED_USB2PCI; 1182 break; 1183 } 1184 do { 1185 if (--timeout <= 0) { 1186 printk(KERN_ERR "core99_usb_enable: " 1187 "Timeout waiting for clocks\n"); 1188 break; 1189 } 1190 mdelay(1); 1191 status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0); 1192 status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1); 1193 } while ((status0 & test0) | (status1 & test1)); 1194 LOCK(flags); 1195 } 1196 } else { 1197 /* Turn OFF */ 1198 if (number < 4) { 1199 reg = MACIO_IN32(KEYLARGO_FCR4); 1200 reg |= KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) | 1201 KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number); 1202 reg |= KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) | 1203 KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1); 1204 MACIO_OUT32(KEYLARGO_FCR4, reg); 1205 (void)MACIO_IN32(KEYLARGO_FCR4); 1206 udelay(1); 1207 } else { 1208 reg = MACIO_IN32(KEYLARGO_FCR3); 1209 reg |= KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) | 1210 KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0); 1211 reg |= KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) | 1212 KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1); 1213 MACIO_OUT32(KEYLARGO_FCR3, reg); 1214 (void)MACIO_IN32(KEYLARGO_FCR3); 1215 udelay(1); 1216 } 1217 if (number == 0) { 1218 if (macio->type != macio_intrepid) 1219 MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE); 1220 (void)MACIO_IN32(KEYLARGO_FCR0); 1221 udelay(1); 1222 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1)); 1223 (void)MACIO_IN32(KEYLARGO_FCR0); 1224 } else if (number == 2) { 1225 if (macio->type != macio_intrepid) 1226 MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE); 1227 (void)MACIO_IN32(KEYLARGO_FCR0); 1228 udelay(1); 1229 MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1)); 1230 (void)MACIO_IN32(KEYLARGO_FCR0); 1231 } else if (number == 4) { 1232 udelay(1); 1233 MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1)); 1234 (void)MACIO_IN32(KEYLARGO_FCR1); 1235 } 1236 udelay(1); 1237 } 1238 UNLOCK(flags); 1239 1240 return 0; 1241 } 1242 1243 static long 1244 core99_firewire_enable(struct device_node *node, long param, long value) 1245 { 1246 unsigned long flags; 1247 struct macio_chip *macio; 1248 1249 macio = &macio_chips[0]; 1250 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1251 macio->type != macio_intrepid) 1252 return -ENODEV; 1253 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED)) 1254 return -ENODEV; 1255 1256 LOCK(flags); 1257 if (value) { 1258 UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW); 1259 (void)UN_IN(UNI_N_CLOCK_CNTL); 1260 } else { 1261 UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW); 1262 (void)UN_IN(UNI_N_CLOCK_CNTL); 1263 } 1264 UNLOCK(flags); 1265 mdelay(1); 1266 1267 return 0; 1268 } 1269 1270 static long 1271 core99_firewire_cable_power(struct device_node *node, long param, long value) 1272 { 1273 unsigned long flags; 1274 struct macio_chip *macio; 1275 1276 /* Trick: we allow NULL node */ 1277 if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0) 1278 return -ENODEV; 1279 macio = &macio_chips[0]; 1280 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1281 macio->type != macio_intrepid) 1282 return -ENODEV; 1283 if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED)) 1284 return -ENODEV; 1285 1286 LOCK(flags); 1287 if (value) { 1288 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0); 1289 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); 1290 udelay(10); 1291 } else { 1292 MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4); 1293 MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10); 1294 } 1295 UNLOCK(flags); 1296 mdelay(1); 1297 1298 return 0; 1299 } 1300 1301 static long 1302 intrepid_aack_delay_enable(struct device_node *node, long param, long value) 1303 { 1304 unsigned long flags; 1305 1306 if (uninorth_rev < 0xd2) 1307 return -ENODEV; 1308 1309 LOCK(flags); 1310 if (param) 1311 UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE); 1312 else 1313 UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE); 1314 UNLOCK(flags); 1315 1316 return 0; 1317 } 1318 1319 1320 #endif /* CONFIG_POWER4 */ 1321 1322 static long 1323 core99_read_gpio(struct device_node *node, long param, long value) 1324 { 1325 struct macio_chip *macio = &macio_chips[0]; 1326 1327 return MACIO_IN8(param); 1328 } 1329 1330 1331 static long 1332 core99_write_gpio(struct device_node *node, long param, long value) 1333 { 1334 struct macio_chip *macio = &macio_chips[0]; 1335 1336 MACIO_OUT8(param, (u8)(value & 0xff)); 1337 return 0; 1338 } 1339 1340 #ifdef CONFIG_POWER4 1341 static long g5_gmac_enable(struct device_node *node, long param, long value) 1342 { 1343 struct macio_chip *macio = &macio_chips[0]; 1344 unsigned long flags; 1345 1346 if (node == NULL) 1347 return -ENODEV; 1348 1349 LOCK(flags); 1350 if (value) { 1351 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE); 1352 mb(); 1353 k2_skiplist[0] = NULL; 1354 } else { 1355 k2_skiplist[0] = node; 1356 mb(); 1357 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE); 1358 } 1359 1360 UNLOCK(flags); 1361 mdelay(1); 1362 1363 return 0; 1364 } 1365 1366 static long g5_fw_enable(struct device_node *node, long param, long value) 1367 { 1368 struct macio_chip *macio = &macio_chips[0]; 1369 unsigned long flags; 1370 1371 if (node == NULL) 1372 return -ENODEV; 1373 1374 LOCK(flags); 1375 if (value) { 1376 MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE); 1377 mb(); 1378 k2_skiplist[1] = NULL; 1379 } else { 1380 k2_skiplist[1] = node; 1381 mb(); 1382 MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE); 1383 } 1384 1385 UNLOCK(flags); 1386 mdelay(1); 1387 1388 return 0; 1389 } 1390 1391 static long g5_mpic_enable(struct device_node *node, long param, long value) 1392 { 1393 unsigned long flags; 1394 struct device_node *parent = of_get_parent(node); 1395 int is_u3; 1396 1397 if (parent == NULL) 1398 return 0; 1399 is_u3 = strcmp(parent->name, "u3") == 0 || 1400 strcmp(parent->name, "u4") == 0; 1401 of_node_put(parent); 1402 if (!is_u3) 1403 return 0; 1404 1405 LOCK(flags); 1406 UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE); 1407 UNLOCK(flags); 1408 1409 return 0; 1410 } 1411 1412 static long g5_eth_phy_reset(struct device_node *node, long param, long value) 1413 { 1414 struct macio_chip *macio = &macio_chips[0]; 1415 struct device_node *phy; 1416 int need_reset; 1417 1418 /* 1419 * We must not reset the combo PHYs, only the BCM5221 found in 1420 * the iMac G5. 1421 */ 1422 phy = of_get_next_child(node, NULL); 1423 if (!phy) 1424 return -ENODEV; 1425 need_reset = of_device_is_compatible(phy, "B5221"); 1426 of_node_put(phy); 1427 if (!need_reset) 1428 return 0; 1429 1430 /* PHY reset is GPIO 29, not in device-tree unfortunately */ 1431 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 1432 KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA); 1433 /* Thankfully, this is now always called at a time when we can 1434 * schedule by sungem. 1435 */ 1436 msleep(10); 1437 MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0); 1438 1439 return 0; 1440 } 1441 1442 static long g5_i2s_enable(struct device_node *node, long param, long value) 1443 { 1444 /* Very crude implementation for now */ 1445 struct macio_chip *macio = &macio_chips[0]; 1446 unsigned long flags; 1447 int cell; 1448 u32 fcrs[3][3] = { 1449 { 0, 1450 K2_FCR1_I2S0_CELL_ENABLE | 1451 K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE, 1452 KL3_I2S0_CLK18_ENABLE 1453 }, 1454 { KL0_SCC_A_INTF_ENABLE, 1455 K2_FCR1_I2S1_CELL_ENABLE | 1456 K2_FCR1_I2S1_CLK_ENABLE_BIT | K2_FCR1_I2S1_ENABLE, 1457 KL3_I2S1_CLK18_ENABLE 1458 }, 1459 { KL0_SCC_B_INTF_ENABLE, 1460 SH_FCR1_I2S2_CELL_ENABLE | 1461 SH_FCR1_I2S2_CLK_ENABLE_BIT | SH_FCR1_I2S2_ENABLE, 1462 SH_FCR3_I2S2_CLK18_ENABLE 1463 }, 1464 }; 1465 1466 if (macio->type != macio_keylargo2 && macio->type != macio_shasta) 1467 return -ENODEV; 1468 if (strncmp(node->name, "i2s-", 4)) 1469 return -ENODEV; 1470 cell = node->name[4] - 'a'; 1471 switch(cell) { 1472 case 0: 1473 case 1: 1474 break; 1475 case 2: 1476 if (macio->type == macio_shasta) 1477 break; 1478 default: 1479 return -ENODEV; 1480 } 1481 1482 LOCK(flags); 1483 if (value) { 1484 MACIO_BIC(KEYLARGO_FCR0, fcrs[cell][0]); 1485 MACIO_BIS(KEYLARGO_FCR1, fcrs[cell][1]); 1486 MACIO_BIS(KEYLARGO_FCR3, fcrs[cell][2]); 1487 } else { 1488 MACIO_BIC(KEYLARGO_FCR3, fcrs[cell][2]); 1489 MACIO_BIC(KEYLARGO_FCR1, fcrs[cell][1]); 1490 MACIO_BIS(KEYLARGO_FCR0, fcrs[cell][0]); 1491 } 1492 udelay(10); 1493 UNLOCK(flags); 1494 1495 return 0; 1496 } 1497 1498 1499 #ifdef CONFIG_SMP 1500 static long g5_reset_cpu(struct device_node *node, long param, long value) 1501 { 1502 unsigned int reset_io = 0; 1503 unsigned long flags; 1504 struct macio_chip *macio; 1505 struct device_node *np; 1506 struct device_node *cpus; 1507 1508 macio = &macio_chips[0]; 1509 if (macio->type != macio_keylargo2 && macio->type != macio_shasta) 1510 return -ENODEV; 1511 1512 cpus = of_find_node_by_path("/cpus"); 1513 if (cpus == NULL) 1514 return -ENODEV; 1515 for (np = cpus->child; np != NULL; np = np->sibling) { 1516 const u32 *num = of_get_property(np, "reg", NULL); 1517 const u32 *rst = of_get_property(np, "soft-reset", NULL); 1518 if (num == NULL || rst == NULL) 1519 continue; 1520 if (param == *num) { 1521 reset_io = *rst; 1522 break; 1523 } 1524 } 1525 of_node_put(cpus); 1526 if (np == NULL || reset_io == 0) 1527 return -ENODEV; 1528 1529 LOCK(flags); 1530 MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE); 1531 (void)MACIO_IN8(reset_io); 1532 udelay(1); 1533 MACIO_OUT8(reset_io, 0); 1534 (void)MACIO_IN8(reset_io); 1535 UNLOCK(flags); 1536 1537 return 0; 1538 } 1539 #endif /* CONFIG_SMP */ 1540 1541 /* 1542 * This can be called from pmac_smp so isn't static 1543 * 1544 * This takes the second CPU off the bus on dual CPU machines 1545 * running UP 1546 */ 1547 void g5_phy_disable_cpu1(void) 1548 { 1549 if (uninorth_maj == 3) 1550 UN_OUT(U3_API_PHY_CONFIG_1, 0); 1551 } 1552 #endif /* CONFIG_POWER4 */ 1553 1554 #ifndef CONFIG_POWER4 1555 1556 1557 #ifdef CONFIG_PM 1558 static u32 save_gpio_levels[2]; 1559 static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT]; 1560 static u8 save_gpio_normal[KEYLARGO_GPIO_CNT]; 1561 static u32 save_unin_clock_ctl; 1562 1563 static void keylargo_shutdown(struct macio_chip *macio, int sleep_mode) 1564 { 1565 u32 temp; 1566 1567 if (sleep_mode) { 1568 mdelay(1); 1569 MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND); 1570 (void)MACIO_IN32(KEYLARGO_FCR0); 1571 mdelay(1); 1572 } 1573 1574 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1575 KL0_SCC_CELL_ENABLE | 1576 KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE | 1577 KL0_IRDA_CLK19_ENABLE); 1578 1579 MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK); 1580 MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE); 1581 1582 MACIO_BIC(KEYLARGO_FCR1, 1583 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT | 1584 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE | 1585 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1586 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1587 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1588 KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N | 1589 KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N | 1590 KL1_UIDE_ENABLE); 1591 1592 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 1593 MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE); 1594 1595 temp = MACIO_IN32(KEYLARGO_FCR3); 1596 if (macio->rev >= 2) { 1597 temp |= KL3_SHUTDOWN_PLL2X; 1598 if (sleep_mode) 1599 temp |= KL3_SHUTDOWN_PLL_TOTAL; 1600 } 1601 1602 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 | 1603 KL3_SHUTDOWN_PLLKW35; 1604 if (sleep_mode) 1605 temp |= KL3_SHUTDOWN_PLLKW12; 1606 temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE 1607 | KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE); 1608 if (sleep_mode) 1609 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE); 1610 MACIO_OUT32(KEYLARGO_FCR3, temp); 1611 1612 /* Flush posted writes & wait a bit */ 1613 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1); 1614 } 1615 1616 static void pangea_shutdown(struct macio_chip *macio, int sleep_mode) 1617 { 1618 u32 temp; 1619 1620 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1621 KL0_SCC_CELL_ENABLE | 1622 KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE); 1623 1624 MACIO_BIC(KEYLARGO_FCR1, 1625 KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT | 1626 KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE | 1627 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1628 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1629 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1630 KL1_UIDE_ENABLE); 1631 if (pmac_mb.board_flags & PMAC_MB_MOBILE) 1632 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N); 1633 1634 MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT); 1635 1636 temp = MACIO_IN32(KEYLARGO_FCR3); 1637 temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 | 1638 KL3_SHUTDOWN_PLLKW35; 1639 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE 1640 | KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE); 1641 if (sleep_mode) 1642 temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE); 1643 MACIO_OUT32(KEYLARGO_FCR3, temp); 1644 1645 /* Flush posted writes & wait a bit */ 1646 (void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1); 1647 } 1648 1649 static void intrepid_shutdown(struct macio_chip *macio, int sleep_mode) 1650 { 1651 u32 temp; 1652 1653 MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE | 1654 KL0_SCC_CELL_ENABLE); 1655 1656 MACIO_BIC(KEYLARGO_FCR1, 1657 KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT | 1658 KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE | 1659 KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE | 1660 KL1_EIDE0_ENABLE); 1661 if (pmac_mb.board_flags & PMAC_MB_MOBILE) 1662 MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N); 1663 1664 temp = MACIO_IN32(KEYLARGO_FCR3); 1665 temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | 1666 KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE); 1667 if (sleep_mode) 1668 temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE); 1669 MACIO_OUT32(KEYLARGO_FCR3, temp); 1670 1671 /* Flush posted writes & wait a bit */ 1672 (void)MACIO_IN32(KEYLARGO_FCR0); 1673 mdelay(10); 1674 } 1675 1676 1677 static int 1678 core99_sleep(void) 1679 { 1680 struct macio_chip *macio; 1681 int i; 1682 1683 macio = &macio_chips[0]; 1684 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1685 macio->type != macio_intrepid) 1686 return -ENODEV; 1687 1688 /* We power off the wireless slot in case it was not done 1689 * by the driver. We don't power it on automatically however 1690 */ 1691 if (macio->flags & MACIO_FLAG_AIRPORT_ON) 1692 core99_airport_enable(macio->of_node, 0, 0); 1693 1694 /* We power off the FW cable. Should be done by the driver... */ 1695 if (macio->flags & MACIO_FLAG_FW_SUPPORTED) { 1696 core99_firewire_enable(NULL, 0, 0); 1697 core99_firewire_cable_power(NULL, 0, 0); 1698 } 1699 1700 /* We make sure int. modem is off (in case driver lost it) */ 1701 if (macio->type == macio_keylargo) 1702 core99_modem_enable(macio->of_node, 0, 0); 1703 else 1704 pangea_modem_enable(macio->of_node, 0, 0); 1705 1706 /* We make sure the sound is off as well */ 1707 core99_sound_chip_enable(macio->of_node, 0, 0); 1708 1709 /* 1710 * Save various bits of KeyLargo 1711 */ 1712 1713 /* Save the state of the various GPIOs */ 1714 save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0); 1715 save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1); 1716 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++) 1717 save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i); 1718 for (i=0; i<KEYLARGO_GPIO_CNT; i++) 1719 save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i); 1720 1721 /* Save the FCRs */ 1722 if (macio->type == macio_keylargo) 1723 save_mbcr = MACIO_IN32(KEYLARGO_MBCR); 1724 save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0); 1725 save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1); 1726 save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2); 1727 save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3); 1728 save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4); 1729 if (macio->type == macio_pangea || macio->type == macio_intrepid) 1730 save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5); 1731 1732 /* Save state & config of DBDMA channels */ 1733 dbdma_save(macio, save_dbdma); 1734 1735 /* 1736 * Turn off as much as we can 1737 */ 1738 if (macio->type == macio_pangea) 1739 pangea_shutdown(macio, 1); 1740 else if (macio->type == macio_intrepid) 1741 intrepid_shutdown(macio, 1); 1742 else if (macio->type == macio_keylargo) 1743 keylargo_shutdown(macio, 1); 1744 1745 /* 1746 * Put the host bridge to sleep 1747 */ 1748 1749 save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL); 1750 /* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it 1751 * enabled ! 1752 */ 1753 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl & 1754 ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/)); 1755 udelay(100); 1756 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING); 1757 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP); 1758 mdelay(10); 1759 1760 /* 1761 * FIXME: A bit of black magic with OpenPIC (don't ask me why) 1762 */ 1763 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) { 1764 MACIO_BIS(0x506e0, 0x00400000); 1765 MACIO_BIS(0x506e0, 0x80000000); 1766 } 1767 return 0; 1768 } 1769 1770 static int 1771 core99_wake_up(void) 1772 { 1773 struct macio_chip *macio; 1774 int i; 1775 1776 macio = &macio_chips[0]; 1777 if (macio->type != macio_keylargo && macio->type != macio_pangea && 1778 macio->type != macio_intrepid) 1779 return -ENODEV; 1780 1781 /* 1782 * Wakeup the host bridge 1783 */ 1784 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL); 1785 udelay(10); 1786 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING); 1787 udelay(10); 1788 1789 /* 1790 * Restore KeyLargo 1791 */ 1792 1793 if (macio->type == macio_keylargo) { 1794 MACIO_OUT32(KEYLARGO_MBCR, save_mbcr); 1795 (void)MACIO_IN32(KEYLARGO_MBCR); udelay(10); 1796 } 1797 MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]); 1798 (void)MACIO_IN32(KEYLARGO_FCR0); udelay(10); 1799 MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]); 1800 (void)MACIO_IN32(KEYLARGO_FCR1); udelay(10); 1801 MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]); 1802 (void)MACIO_IN32(KEYLARGO_FCR2); udelay(10); 1803 MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]); 1804 (void)MACIO_IN32(KEYLARGO_FCR3); udelay(10); 1805 MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]); 1806 (void)MACIO_IN32(KEYLARGO_FCR4); udelay(10); 1807 if (macio->type == macio_pangea || macio->type == macio_intrepid) { 1808 MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]); 1809 (void)MACIO_IN32(KEYLARGO_FCR5); udelay(10); 1810 } 1811 1812 dbdma_restore(macio, save_dbdma); 1813 1814 MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]); 1815 MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]); 1816 for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++) 1817 MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]); 1818 for (i=0; i<KEYLARGO_GPIO_CNT; i++) 1819 MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]); 1820 1821 /* FIXME more black magic with OpenPIC ... */ 1822 if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) { 1823 MACIO_BIC(0x506e0, 0x00400000); 1824 MACIO_BIC(0x506e0, 0x80000000); 1825 } 1826 1827 UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl); 1828 udelay(100); 1829 1830 return 0; 1831 } 1832 1833 #endif /* CONFIG_PM */ 1834 1835 static long 1836 core99_sleep_state(struct device_node *node, long param, long value) 1837 { 1838 /* Param == 1 means to enter the "fake sleep" mode that is 1839 * used for CPU speed switch 1840 */ 1841 if (param == 1) { 1842 if (value == 1) { 1843 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING); 1844 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2); 1845 } else { 1846 UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL); 1847 udelay(10); 1848 UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING); 1849 udelay(10); 1850 } 1851 return 0; 1852 } 1853 if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0) 1854 return -EPERM; 1855 1856 #ifdef CONFIG_PM 1857 if (value == 1) 1858 return core99_sleep(); 1859 else if (value == 0) 1860 return core99_wake_up(); 1861 1862 #endif /* CONFIG_PM */ 1863 return 0; 1864 } 1865 1866 #endif /* CONFIG_POWER4 */ 1867 1868 static long 1869 generic_dev_can_wake(struct device_node *node, long param, long value) 1870 { 1871 /* Todo: eventually check we are really dealing with on-board 1872 * video device ... 1873 */ 1874 1875 if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP) 1876 pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP; 1877 return 0; 1878 } 1879 1880 static long generic_get_mb_info(struct device_node *node, long param, long value) 1881 { 1882 switch(param) { 1883 case PMAC_MB_INFO_MODEL: 1884 return pmac_mb.model_id; 1885 case PMAC_MB_INFO_FLAGS: 1886 return pmac_mb.board_flags; 1887 case PMAC_MB_INFO_NAME: 1888 /* hack hack hack... but should work */ 1889 *((const char **)value) = pmac_mb.model_name; 1890 return 0; 1891 } 1892 return -EINVAL; 1893 } 1894 1895 1896 /* 1897 * Table definitions 1898 */ 1899 1900 /* Used on any machine 1901 */ 1902 static struct feature_table_entry any_features[] = { 1903 { PMAC_FTR_GET_MB_INFO, generic_get_mb_info }, 1904 { PMAC_FTR_DEVICE_CAN_WAKE, generic_dev_can_wake }, 1905 { 0, NULL } 1906 }; 1907 1908 #ifndef CONFIG_POWER4 1909 1910 /* OHare based motherboards. Currently, we only use these on the 1911 * 2400,3400 and 3500 series powerbooks. Some older desktops seem 1912 * to have issues with turning on/off those asic cells 1913 */ 1914 static struct feature_table_entry ohare_features[] = { 1915 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1916 { PMAC_FTR_SWIM3_ENABLE, ohare_floppy_enable }, 1917 { PMAC_FTR_MESH_ENABLE, ohare_mesh_enable }, 1918 { PMAC_FTR_IDE_ENABLE, ohare_ide_enable}, 1919 { PMAC_FTR_IDE_RESET, ohare_ide_reset}, 1920 { PMAC_FTR_SLEEP_STATE, ohare_sleep_state }, 1921 { 0, NULL } 1922 }; 1923 1924 /* Heathrow desktop machines (Beige G3). 1925 * Separated as some features couldn't be properly tested 1926 * and the serial port control bits appear to confuse it. 1927 */ 1928 static struct feature_table_entry heathrow_desktop_features[] = { 1929 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1930 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1931 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1932 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1933 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1934 { 0, NULL } 1935 }; 1936 1937 /* Heathrow based laptop, that is the Wallstreet and mainstreet 1938 * powerbooks. 1939 */ 1940 static struct feature_table_entry heathrow_laptop_features[] = { 1941 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1942 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable }, 1943 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1944 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1945 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1946 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1947 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1948 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable }, 1949 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state }, 1950 { 0, NULL } 1951 }; 1952 1953 /* Paddington based machines 1954 * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4. 1955 */ 1956 static struct feature_table_entry paddington_features[] = { 1957 { PMAC_FTR_SCC_ENABLE, ohare_htw_scc_enable }, 1958 { PMAC_FTR_MODEM_ENABLE, heathrow_modem_enable }, 1959 { PMAC_FTR_SWIM3_ENABLE, heathrow_floppy_enable }, 1960 { PMAC_FTR_MESH_ENABLE, heathrow_mesh_enable }, 1961 { PMAC_FTR_IDE_ENABLE, heathrow_ide_enable }, 1962 { PMAC_FTR_IDE_RESET, heathrow_ide_reset }, 1963 { PMAC_FTR_BMAC_ENABLE, heathrow_bmac_enable }, 1964 { PMAC_FTR_SOUND_CHIP_ENABLE, heathrow_sound_enable }, 1965 { PMAC_FTR_SLEEP_STATE, heathrow_sleep_state }, 1966 { 0, NULL } 1967 }; 1968 1969 /* Core99 & MacRISC 2 machines (all machines released since the 1970 * iBook (included), that is all AGP machines, except pangea 1971 * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo 1972 * used on iBook2 & iMac "flow power". 1973 */ 1974 static struct feature_table_entry core99_features[] = { 1975 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 1976 { PMAC_FTR_MODEM_ENABLE, core99_modem_enable }, 1977 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 1978 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 1979 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 1980 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 1981 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 1982 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 1983 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 1984 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 1985 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 1986 #ifdef CONFIG_PM 1987 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 1988 #endif 1989 #ifdef CONFIG_SMP 1990 { PMAC_FTR_RESET_CPU, core99_reset_cpu }, 1991 #endif /* CONFIG_SMP */ 1992 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 1993 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 1994 { 0, NULL } 1995 }; 1996 1997 /* RackMac 1998 */ 1999 static struct feature_table_entry rackmac_features[] = { 2000 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 2001 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 2002 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 2003 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 2004 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 2005 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 2006 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 2007 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 2008 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 2009 #ifdef CONFIG_SMP 2010 { PMAC_FTR_RESET_CPU, core99_reset_cpu }, 2011 #endif /* CONFIG_SMP */ 2012 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2013 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2014 { 0, NULL } 2015 }; 2016 2017 /* Pangea features 2018 */ 2019 static struct feature_table_entry pangea_features[] = { 2020 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 2021 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable }, 2022 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 2023 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 2024 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 2025 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 2026 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 2027 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 2028 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 2029 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 2030 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 2031 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 2032 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2033 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2034 { 0, NULL } 2035 }; 2036 2037 /* Intrepid features 2038 */ 2039 static struct feature_table_entry intrepid_features[] = { 2040 { PMAC_FTR_SCC_ENABLE, core99_scc_enable }, 2041 { PMAC_FTR_MODEM_ENABLE, pangea_modem_enable }, 2042 { PMAC_FTR_IDE_ENABLE, core99_ide_enable }, 2043 { PMAC_FTR_IDE_RESET, core99_ide_reset }, 2044 { PMAC_FTR_GMAC_ENABLE, core99_gmac_enable }, 2045 { PMAC_FTR_GMAC_PHY_RESET, core99_gmac_phy_reset }, 2046 { PMAC_FTR_SOUND_CHIP_ENABLE, core99_sound_chip_enable }, 2047 { PMAC_FTR_AIRPORT_ENABLE, core99_airport_enable }, 2048 { PMAC_FTR_USB_ENABLE, core99_usb_enable }, 2049 { PMAC_FTR_1394_ENABLE, core99_firewire_enable }, 2050 { PMAC_FTR_1394_CABLE_POWER, core99_firewire_cable_power }, 2051 { PMAC_FTR_SLEEP_STATE, core99_sleep_state }, 2052 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2053 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2054 { PMAC_FTR_AACK_DELAY_ENABLE, intrepid_aack_delay_enable }, 2055 { 0, NULL } 2056 }; 2057 2058 #else /* CONFIG_POWER4 */ 2059 2060 /* G5 features 2061 */ 2062 static struct feature_table_entry g5_features[] = { 2063 { PMAC_FTR_GMAC_ENABLE, g5_gmac_enable }, 2064 { PMAC_FTR_1394_ENABLE, g5_fw_enable }, 2065 { PMAC_FTR_ENABLE_MPIC, g5_mpic_enable }, 2066 { PMAC_FTR_GMAC_PHY_RESET, g5_eth_phy_reset }, 2067 { PMAC_FTR_SOUND_CHIP_ENABLE, g5_i2s_enable }, 2068 #ifdef CONFIG_SMP 2069 { PMAC_FTR_RESET_CPU, g5_reset_cpu }, 2070 #endif /* CONFIG_SMP */ 2071 { PMAC_FTR_READ_GPIO, core99_read_gpio }, 2072 { PMAC_FTR_WRITE_GPIO, core99_write_gpio }, 2073 { 0, NULL } 2074 }; 2075 2076 #endif /* CONFIG_POWER4 */ 2077 2078 static struct pmac_mb_def pmac_mb_defs[] = { 2079 #ifndef CONFIG_POWER4 2080 /* 2081 * Desktops 2082 */ 2083 2084 { "AAPL,8500", "PowerMac 8500/8600", 2085 PMAC_TYPE_PSURGE, NULL, 2086 0 2087 }, 2088 { "AAPL,9500", "PowerMac 9500/9600", 2089 PMAC_TYPE_PSURGE, NULL, 2090 0 2091 }, 2092 { "AAPL,7200", "PowerMac 7200", 2093 PMAC_TYPE_PSURGE, NULL, 2094 0 2095 }, 2096 { "AAPL,7300", "PowerMac 7200/7300", 2097 PMAC_TYPE_PSURGE, NULL, 2098 0 2099 }, 2100 { "AAPL,7500", "PowerMac 7500", 2101 PMAC_TYPE_PSURGE, NULL, 2102 0 2103 }, 2104 { "AAPL,ShinerESB", "Apple Network Server", 2105 PMAC_TYPE_ANS, NULL, 2106 0 2107 }, 2108 { "AAPL,e407", "Alchemy", 2109 PMAC_TYPE_ALCHEMY, NULL, 2110 0 2111 }, 2112 { "AAPL,e411", "Gazelle", 2113 PMAC_TYPE_GAZELLE, NULL, 2114 0 2115 }, 2116 { "AAPL,Gossamer", "PowerMac G3 (Gossamer)", 2117 PMAC_TYPE_GOSSAMER, heathrow_desktop_features, 2118 0 2119 }, 2120 { "AAPL,PowerMac G3", "PowerMac G3 (Silk)", 2121 PMAC_TYPE_SILK, heathrow_desktop_features, 2122 0 2123 }, 2124 { "PowerMac1,1", "Blue&White G3", 2125 PMAC_TYPE_YOSEMITE, paddington_features, 2126 0 2127 }, 2128 { "PowerMac1,2", "PowerMac G4 PCI Graphics", 2129 PMAC_TYPE_YIKES, paddington_features, 2130 0 2131 }, 2132 { "PowerMac2,1", "iMac FireWire", 2133 PMAC_TYPE_FW_IMAC, core99_features, 2134 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2135 }, 2136 { "PowerMac2,2", "iMac FireWire", 2137 PMAC_TYPE_FW_IMAC, core99_features, 2138 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2139 }, 2140 { "PowerMac3,1", "PowerMac G4 AGP Graphics", 2141 PMAC_TYPE_SAWTOOTH, core99_features, 2142 PMAC_MB_OLD_CORE99 2143 }, 2144 { "PowerMac3,2", "PowerMac G4 AGP Graphics", 2145 PMAC_TYPE_SAWTOOTH, core99_features, 2146 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2147 }, 2148 { "PowerMac3,3", "PowerMac G4 AGP Graphics", 2149 PMAC_TYPE_SAWTOOTH, core99_features, 2150 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2151 }, 2152 { "PowerMac3,4", "PowerMac G4 Silver", 2153 PMAC_TYPE_QUICKSILVER, core99_features, 2154 PMAC_MB_MAY_SLEEP 2155 }, 2156 { "PowerMac3,5", "PowerMac G4 Silver", 2157 PMAC_TYPE_QUICKSILVER, core99_features, 2158 PMAC_MB_MAY_SLEEP 2159 }, 2160 { "PowerMac3,6", "PowerMac G4 Windtunnel", 2161 PMAC_TYPE_WINDTUNNEL, core99_features, 2162 PMAC_MB_MAY_SLEEP, 2163 }, 2164 { "PowerMac4,1", "iMac \"Flower Power\"", 2165 PMAC_TYPE_PANGEA_IMAC, pangea_features, 2166 PMAC_MB_MAY_SLEEP 2167 }, 2168 { "PowerMac4,2", "Flat panel iMac", 2169 PMAC_TYPE_FLAT_PANEL_IMAC, pangea_features, 2170 PMAC_MB_CAN_SLEEP 2171 }, 2172 { "PowerMac4,4", "eMac", 2173 PMAC_TYPE_EMAC, core99_features, 2174 PMAC_MB_MAY_SLEEP 2175 }, 2176 { "PowerMac5,1", "PowerMac G4 Cube", 2177 PMAC_TYPE_CUBE, core99_features, 2178 PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99 2179 }, 2180 { "PowerMac6,1", "Flat panel iMac", 2181 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2182 PMAC_MB_MAY_SLEEP, 2183 }, 2184 { "PowerMac6,3", "Flat panel iMac", 2185 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2186 PMAC_MB_MAY_SLEEP, 2187 }, 2188 { "PowerMac6,4", "eMac", 2189 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2190 PMAC_MB_MAY_SLEEP, 2191 }, 2192 { "PowerMac10,1", "Mac mini", 2193 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2194 PMAC_MB_MAY_SLEEP, 2195 }, 2196 { "PowerMac10,2", "Mac mini (Late 2005)", 2197 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2198 PMAC_MB_MAY_SLEEP, 2199 }, 2200 { "iMac,1", "iMac (first generation)", 2201 PMAC_TYPE_ORIG_IMAC, paddington_features, 2202 0 2203 }, 2204 2205 /* 2206 * Xserve's 2207 */ 2208 2209 { "RackMac1,1", "XServe", 2210 PMAC_TYPE_RACKMAC, rackmac_features, 2211 0, 2212 }, 2213 { "RackMac1,2", "XServe rev. 2", 2214 PMAC_TYPE_RACKMAC, rackmac_features, 2215 0, 2216 }, 2217 2218 /* 2219 * Laptops 2220 */ 2221 2222 { "AAPL,3400/2400", "PowerBook 3400", 2223 PMAC_TYPE_HOOPER, ohare_features, 2224 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2225 }, 2226 { "AAPL,3500", "PowerBook 3500", 2227 PMAC_TYPE_KANGA, ohare_features, 2228 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2229 }, 2230 { "AAPL,PowerBook1998", "PowerBook Wallstreet", 2231 PMAC_TYPE_WALLSTREET, heathrow_laptop_features, 2232 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2233 }, 2234 { "PowerBook1,1", "PowerBook 101 (Lombard)", 2235 PMAC_TYPE_101_PBOOK, paddington_features, 2236 PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE 2237 }, 2238 { "PowerBook2,1", "iBook (first generation)", 2239 PMAC_TYPE_ORIG_IBOOK, core99_features, 2240 PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2241 }, 2242 { "PowerBook2,2", "iBook FireWire", 2243 PMAC_TYPE_FW_IBOOK, core99_features, 2244 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | 2245 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2246 }, 2247 { "PowerBook3,1", "PowerBook Pismo", 2248 PMAC_TYPE_PISMO, core99_features, 2249 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | 2250 PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE 2251 }, 2252 { "PowerBook3,2", "PowerBook Titanium", 2253 PMAC_TYPE_TITANIUM, core99_features, 2254 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2255 }, 2256 { "PowerBook3,3", "PowerBook Titanium II", 2257 PMAC_TYPE_TITANIUM2, core99_features, 2258 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2259 }, 2260 { "PowerBook3,4", "PowerBook Titanium III", 2261 PMAC_TYPE_TITANIUM3, core99_features, 2262 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2263 }, 2264 { "PowerBook3,5", "PowerBook Titanium IV", 2265 PMAC_TYPE_TITANIUM4, core99_features, 2266 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2267 }, 2268 { "PowerBook4,1", "iBook 2", 2269 PMAC_TYPE_IBOOK2, pangea_features, 2270 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2271 }, 2272 { "PowerBook4,2", "iBook 2", 2273 PMAC_TYPE_IBOOK2, pangea_features, 2274 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2275 }, 2276 { "PowerBook4,3", "iBook 2 rev. 2", 2277 PMAC_TYPE_IBOOK2, pangea_features, 2278 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE 2279 }, 2280 { "PowerBook5,1", "PowerBook G4 17\"", 2281 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2282 PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2283 }, 2284 { "PowerBook5,2", "PowerBook G4 15\"", 2285 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2286 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2287 }, 2288 { "PowerBook5,3", "PowerBook G4 17\"", 2289 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2290 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2291 }, 2292 { "PowerBook5,4", "PowerBook G4 15\"", 2293 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2294 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2295 }, 2296 { "PowerBook5,5", "PowerBook G4 17\"", 2297 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2298 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2299 }, 2300 { "PowerBook5,6", "PowerBook G4 15\"", 2301 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2302 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2303 }, 2304 { "PowerBook5,7", "PowerBook G4 17\"", 2305 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2306 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2307 }, 2308 { "PowerBook5,8", "PowerBook G4 15\"", 2309 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2310 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE, 2311 }, 2312 { "PowerBook5,9", "PowerBook G4 17\"", 2313 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2314 PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE, 2315 }, 2316 { "PowerBook6,1", "PowerBook G4 12\"", 2317 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2318 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2319 }, 2320 { "PowerBook6,2", "PowerBook G4", 2321 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2322 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2323 }, 2324 { "PowerBook6,3", "iBook G4", 2325 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2326 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2327 }, 2328 { "PowerBook6,4", "PowerBook G4 12\"", 2329 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2330 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2331 }, 2332 { "PowerBook6,5", "iBook G4", 2333 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2334 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2335 }, 2336 { "PowerBook6,7", "iBook G4", 2337 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2338 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2339 }, 2340 { "PowerBook6,8", "PowerBook G4 12\"", 2341 PMAC_TYPE_UNKNOWN_INTREPID, intrepid_features, 2342 PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE, 2343 }, 2344 #else /* CONFIG_POWER4 */ 2345 { "PowerMac7,2", "PowerMac G5", 2346 PMAC_TYPE_POWERMAC_G5, g5_features, 2347 0, 2348 }, 2349 #ifdef CONFIG_PPC64 2350 { "PowerMac7,3", "PowerMac G5", 2351 PMAC_TYPE_POWERMAC_G5, g5_features, 2352 0, 2353 }, 2354 { "PowerMac8,1", "iMac G5", 2355 PMAC_TYPE_IMAC_G5, g5_features, 2356 0, 2357 }, 2358 { "PowerMac9,1", "PowerMac G5", 2359 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2360 0, 2361 }, 2362 { "PowerMac11,2", "PowerMac G5 Dual Core", 2363 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2364 0, 2365 }, 2366 { "PowerMac12,1", "iMac G5 (iSight)", 2367 PMAC_TYPE_POWERMAC_G5_U3L, g5_features, 2368 0, 2369 }, 2370 { "RackMac3,1", "XServe G5", 2371 PMAC_TYPE_XSERVE_G5, g5_features, 2372 0, 2373 }, 2374 #endif /* CONFIG_PPC64 */ 2375 #endif /* CONFIG_POWER4 */ 2376 }; 2377 2378 /* 2379 * The toplevel feature_call callback 2380 */ 2381 long pmac_do_feature_call(unsigned int selector, ...) 2382 { 2383 struct device_node *node; 2384 long param, value; 2385 int i; 2386 feature_call func = NULL; 2387 va_list args; 2388 2389 if (pmac_mb.features) 2390 for (i=0; pmac_mb.features[i].function; i++) 2391 if (pmac_mb.features[i].selector == selector) { 2392 func = pmac_mb.features[i].function; 2393 break; 2394 } 2395 if (!func) 2396 for (i=0; any_features[i].function; i++) 2397 if (any_features[i].selector == selector) { 2398 func = any_features[i].function; 2399 break; 2400 } 2401 if (!func) 2402 return -ENODEV; 2403 2404 va_start(args, selector); 2405 node = (struct device_node*)va_arg(args, void*); 2406 param = va_arg(args, long); 2407 value = va_arg(args, long); 2408 va_end(args); 2409 2410 return func(node, param, value); 2411 } 2412 2413 static int __init probe_motherboard(void) 2414 { 2415 int i; 2416 struct macio_chip *macio = &macio_chips[0]; 2417 const char *model = NULL; 2418 struct device_node *dt; 2419 int ret = 0; 2420 2421 /* Lookup known motherboard type in device-tree. First try an 2422 * exact match on the "model" property, then try a "compatible" 2423 * match is none is found. 2424 */ 2425 dt = of_find_node_by_name(NULL, "device-tree"); 2426 if (dt != NULL) 2427 model = of_get_property(dt, "model", NULL); 2428 for(i=0; model && i<ARRAY_SIZE(pmac_mb_defs); i++) { 2429 if (strcmp(model, pmac_mb_defs[i].model_string) == 0) { 2430 pmac_mb = pmac_mb_defs[i]; 2431 goto found; 2432 } 2433 } 2434 for(i=0; i<ARRAY_SIZE(pmac_mb_defs); i++) { 2435 if (of_machine_is_compatible(pmac_mb_defs[i].model_string)) { 2436 pmac_mb = pmac_mb_defs[i]; 2437 goto found; 2438 } 2439 } 2440 2441 /* Fallback to selection depending on mac-io chip type */ 2442 switch(macio->type) { 2443 #ifndef CONFIG_POWER4 2444 case macio_grand_central: 2445 pmac_mb.model_id = PMAC_TYPE_PSURGE; 2446 pmac_mb.model_name = "Unknown PowerSurge"; 2447 break; 2448 case macio_ohare: 2449 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE; 2450 pmac_mb.model_name = "Unknown OHare-based"; 2451 break; 2452 case macio_heathrow: 2453 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW; 2454 pmac_mb.model_name = "Unknown Heathrow-based"; 2455 pmac_mb.features = heathrow_desktop_features; 2456 break; 2457 case macio_paddington: 2458 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON; 2459 pmac_mb.model_name = "Unknown Paddington-based"; 2460 pmac_mb.features = paddington_features; 2461 break; 2462 case macio_keylargo: 2463 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99; 2464 pmac_mb.model_name = "Unknown Keylargo-based"; 2465 pmac_mb.features = core99_features; 2466 break; 2467 case macio_pangea: 2468 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA; 2469 pmac_mb.model_name = "Unknown Pangea-based"; 2470 pmac_mb.features = pangea_features; 2471 break; 2472 case macio_intrepid: 2473 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID; 2474 pmac_mb.model_name = "Unknown Intrepid-based"; 2475 pmac_mb.features = intrepid_features; 2476 break; 2477 #else /* CONFIG_POWER4 */ 2478 case macio_keylargo2: 2479 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2; 2480 pmac_mb.model_name = "Unknown K2-based"; 2481 pmac_mb.features = g5_features; 2482 break; 2483 case macio_shasta: 2484 pmac_mb.model_id = PMAC_TYPE_UNKNOWN_SHASTA; 2485 pmac_mb.model_name = "Unknown Shasta-based"; 2486 pmac_mb.features = g5_features; 2487 break; 2488 #endif /* CONFIG_POWER4 */ 2489 default: 2490 ret = -ENODEV; 2491 goto done; 2492 } 2493 found: 2494 #ifndef CONFIG_POWER4 2495 /* Fixup Hooper vs. Comet */ 2496 if (pmac_mb.model_id == PMAC_TYPE_HOOPER) { 2497 u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4); 2498 if (!mach_id_ptr) { 2499 ret = -ENODEV; 2500 goto done; 2501 } 2502 /* Here, I used to disable the media-bay on comet. It 2503 * appears this is wrong, the floppy connector is actually 2504 * a kind of media-bay and works with the current driver. 2505 */ 2506 if (__raw_readl(mach_id_ptr) & 0x20000000UL) 2507 pmac_mb.model_id = PMAC_TYPE_COMET; 2508 iounmap(mach_id_ptr); 2509 } 2510 2511 /* Set default value of powersave_nap on machines that support it. 2512 * It appears that uninorth rev 3 has a problem with it, we don't 2513 * enable it on those. In theory, the flush-on-lock property is 2514 * supposed to be set when not supported, but I'm not very confident 2515 * that all Apple OF revs did it properly, I do it the paranoid way. 2516 */ 2517 while (uninorth_base && uninorth_rev > 3) { 2518 struct device_node *cpus = of_find_node_by_path("/cpus"); 2519 struct device_node *np; 2520 2521 if (!cpus || !cpus->child) { 2522 printk(KERN_WARNING "Can't find CPU(s) in device tree !\n"); 2523 of_node_put(cpus); 2524 break; 2525 } 2526 np = cpus->child; 2527 /* Nap mode not supported on SMP */ 2528 if (np->sibling) { 2529 of_node_put(cpus); 2530 break; 2531 } 2532 /* Nap mode not supported if flush-on-lock property is present */ 2533 if (of_get_property(np, "flush-on-lock", NULL)) { 2534 of_node_put(cpus); 2535 break; 2536 } 2537 of_node_put(cpus); 2538 powersave_nap = 1; 2539 printk(KERN_DEBUG "Processor NAP mode on idle enabled.\n"); 2540 break; 2541 } 2542 2543 /* On CPUs that support it (750FX), lowspeed by default during 2544 * NAP mode 2545 */ 2546 powersave_lowspeed = 1; 2547 2548 #else /* CONFIG_POWER4 */ 2549 powersave_nap = 1; 2550 #endif /* CONFIG_POWER4 */ 2551 2552 /* Check for "mobile" machine */ 2553 if (model && (strncmp(model, "PowerBook", 9) == 0 2554 || strncmp(model, "iBook", 5) == 0)) 2555 pmac_mb.board_flags |= PMAC_MB_MOBILE; 2556 2557 2558 printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name); 2559 done: 2560 of_node_put(dt); 2561 return ret; 2562 } 2563 2564 /* Initialize the Core99 UniNorth host bridge and memory controller 2565 */ 2566 static void __init probe_uninorth(void) 2567 { 2568 const u32 *addrp; 2569 phys_addr_t address; 2570 unsigned long actrl; 2571 2572 /* Locate core99 Uni-N */ 2573 uninorth_node = of_find_node_by_name(NULL, "uni-n"); 2574 uninorth_maj = 1; 2575 2576 /* Locate G5 u3 */ 2577 if (uninorth_node == NULL) { 2578 uninorth_node = of_find_node_by_name(NULL, "u3"); 2579 uninorth_maj = 3; 2580 } 2581 /* Locate G5 u4 */ 2582 if (uninorth_node == NULL) { 2583 uninorth_node = of_find_node_by_name(NULL, "u4"); 2584 uninorth_maj = 4; 2585 } 2586 if (uninorth_node == NULL) { 2587 uninorth_maj = 0; 2588 return; 2589 } 2590 2591 addrp = of_get_property(uninorth_node, "reg", NULL); 2592 if (addrp == NULL) 2593 return; 2594 address = of_translate_address(uninorth_node, addrp); 2595 if (address == 0) 2596 return; 2597 uninorth_base = ioremap(address, 0x40000); 2598 if (uninorth_base == NULL) 2599 return; 2600 uninorth_rev = in_be32(UN_REG(UNI_N_VERSION)); 2601 if (uninorth_maj == 3 || uninorth_maj == 4) { 2602 u3_ht_base = ioremap(address + U3_HT_CONFIG_BASE, 0x1000); 2603 if (u3_ht_base == NULL) { 2604 iounmap(uninorth_base); 2605 return; 2606 } 2607 } 2608 2609 printk(KERN_INFO "Found %s memory controller & host bridge" 2610 " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" : 2611 uninorth_maj == 4 ? "U4" : "UniNorth", 2612 (unsigned int)address, uninorth_rev); 2613 printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base); 2614 2615 /* Set the arbitrer QAck delay according to what Apple does 2616 */ 2617 if (uninorth_rev < 0x11) { 2618 actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK; 2619 actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 : 2620 UNI_N_ARB_CTRL_QACK_DELAY) << 2621 UNI_N_ARB_CTRL_QACK_DELAY_SHIFT; 2622 UN_OUT(UNI_N_ARB_CTRL, actrl); 2623 } 2624 2625 /* Some more magic as done by them in recent MacOS X on UniNorth 2626 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI 2627 * memory timeout 2628 */ 2629 if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) || 2630 uninorth_rev == 0xc0) 2631 UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff); 2632 } 2633 2634 static void __init probe_one_macio(const char *name, const char *compat, int type) 2635 { 2636 struct device_node* node; 2637 int i; 2638 volatile u32 __iomem *base; 2639 const u32 *addrp, *revp; 2640 phys_addr_t addr; 2641 u64 size; 2642 2643 for (node = NULL; (node = of_find_node_by_name(node, name)) != NULL;) { 2644 if (!compat) 2645 break; 2646 if (of_device_is_compatible(node, compat)) 2647 break; 2648 } 2649 if (!node) 2650 return; 2651 for(i=0; i<MAX_MACIO_CHIPS; i++) { 2652 if (!macio_chips[i].of_node) 2653 break; 2654 if (macio_chips[i].of_node == node) 2655 return; 2656 } 2657 2658 if (i >= MAX_MACIO_CHIPS) { 2659 printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n"); 2660 printk(KERN_ERR "pmac_feature: %s skipped\n", node->full_name); 2661 return; 2662 } 2663 addrp = of_get_pci_address(node, 0, &size, NULL); 2664 if (addrp == NULL) { 2665 printk(KERN_ERR "pmac_feature: %s: can't find base !\n", 2666 node->full_name); 2667 return; 2668 } 2669 addr = of_translate_address(node, addrp); 2670 if (addr == 0) { 2671 printk(KERN_ERR "pmac_feature: %s, can't translate base !\n", 2672 node->full_name); 2673 return; 2674 } 2675 base = ioremap(addr, (unsigned long)size); 2676 if (!base) { 2677 printk(KERN_ERR "pmac_feature: %s, can't map mac-io chip !\n", 2678 node->full_name); 2679 return; 2680 } 2681 if (type == macio_keylargo || type == macio_keylargo2) { 2682 const u32 *did = of_get_property(node, "device-id", NULL); 2683 if (*did == 0x00000025) 2684 type = macio_pangea; 2685 if (*did == 0x0000003e) 2686 type = macio_intrepid; 2687 if (*did == 0x0000004f) 2688 type = macio_shasta; 2689 } 2690 macio_chips[i].of_node = node; 2691 macio_chips[i].type = type; 2692 macio_chips[i].base = base; 2693 macio_chips[i].flags = MACIO_FLAG_SCCA_ON | MACIO_FLAG_SCCB_ON; 2694 macio_chips[i].name = macio_names[type]; 2695 revp = of_get_property(node, "revision-id", NULL); 2696 if (revp) 2697 macio_chips[i].rev = *revp; 2698 printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n", 2699 macio_names[type], macio_chips[i].rev, macio_chips[i].base); 2700 } 2701 2702 static int __init 2703 probe_macios(void) 2704 { 2705 /* Warning, ordering is important */ 2706 probe_one_macio("gc", NULL, macio_grand_central); 2707 probe_one_macio("ohare", NULL, macio_ohare); 2708 probe_one_macio("pci106b,7", NULL, macio_ohareII); 2709 probe_one_macio("mac-io", "keylargo", macio_keylargo); 2710 probe_one_macio("mac-io", "paddington", macio_paddington); 2711 probe_one_macio("mac-io", "gatwick", macio_gatwick); 2712 probe_one_macio("mac-io", "heathrow", macio_heathrow); 2713 probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2); 2714 2715 /* Make sure the "main" macio chip appear first */ 2716 if (macio_chips[0].type == macio_gatwick 2717 && macio_chips[1].type == macio_heathrow) { 2718 struct macio_chip temp = macio_chips[0]; 2719 macio_chips[0] = macio_chips[1]; 2720 macio_chips[1] = temp; 2721 } 2722 if (macio_chips[0].type == macio_ohareII 2723 && macio_chips[1].type == macio_ohare) { 2724 struct macio_chip temp = macio_chips[0]; 2725 macio_chips[0] = macio_chips[1]; 2726 macio_chips[1] = temp; 2727 } 2728 macio_chips[0].lbus.index = 0; 2729 macio_chips[1].lbus.index = 1; 2730 2731 return (macio_chips[0].of_node == NULL) ? -ENODEV : 0; 2732 } 2733 2734 static void __init 2735 initial_serial_shutdown(struct device_node *np) 2736 { 2737 int len; 2738 const struct slot_names_prop { 2739 int count; 2740 char name[1]; 2741 } *slots; 2742 const char *conn; 2743 int port_type = PMAC_SCC_ASYNC; 2744 int modem = 0; 2745 2746 slots = of_get_property(np, "slot-names", &len); 2747 conn = of_get_property(np, "AAPL,connector", &len); 2748 if (conn && (strcmp(conn, "infrared") == 0)) 2749 port_type = PMAC_SCC_IRDA; 2750 else if (of_device_is_compatible(np, "cobalt")) 2751 modem = 1; 2752 else if (slots && slots->count > 0) { 2753 if (strcmp(slots->name, "IrDA") == 0) 2754 port_type = PMAC_SCC_IRDA; 2755 else if (strcmp(slots->name, "Modem") == 0) 2756 modem = 1; 2757 } 2758 if (modem) 2759 pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0); 2760 pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0); 2761 } 2762 2763 static void __init 2764 set_initial_features(void) 2765 { 2766 struct device_node *np; 2767 2768 /* That hack appears to be necessary for some StarMax motherboards 2769 * but I'm not too sure it was audited for side-effects on other 2770 * ohare based machines... 2771 * Since I still have difficulties figuring the right way to 2772 * differenciate them all and since that hack was there for a long 2773 * time, I'll keep it around 2774 */ 2775 if (macio_chips[0].type == macio_ohare) { 2776 struct macio_chip *macio = &macio_chips[0]; 2777 np = of_find_node_by_name(NULL, "via-pmu"); 2778 if (np) 2779 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 2780 else 2781 MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES); 2782 of_node_put(np); 2783 } else if (macio_chips[1].type == macio_ohare) { 2784 struct macio_chip *macio = &macio_chips[1]; 2785 MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE); 2786 } 2787 2788 #ifdef CONFIG_POWER4 2789 if (macio_chips[0].type == macio_keylargo2 || 2790 macio_chips[0].type == macio_shasta) { 2791 #ifndef CONFIG_SMP 2792 /* On SMP machines running UP, we have the second CPU eating 2793 * bus cycles. We need to take it off the bus. This is done 2794 * from pmac_smp for SMP kernels running on one CPU 2795 */ 2796 np = of_find_node_by_type(NULL, "cpu"); 2797 if (np != NULL) 2798 np = of_find_node_by_type(np, "cpu"); 2799 if (np != NULL) { 2800 g5_phy_disable_cpu1(); 2801 of_node_put(np); 2802 } 2803 #endif /* CONFIG_SMP */ 2804 /* Enable GMAC for now for PCI probing. It will be disabled 2805 * later on after PCI probe 2806 */ 2807 np = of_find_node_by_name(NULL, "ethernet"); 2808 while(np) { 2809 if (of_device_is_compatible(np, "K2-GMAC")) 2810 g5_gmac_enable(np, 0, 1); 2811 np = of_find_node_by_name(np, "ethernet"); 2812 } 2813 2814 /* Enable FW before PCI probe. Will be disabled later on 2815 * Note: We should have a batter way to check that we are 2816 * dealing with uninorth internal cell and not a PCI cell 2817 * on the external PCI. The code below works though. 2818 */ 2819 np = of_find_node_by_name(NULL, "firewire"); 2820 while(np) { 2821 if (of_device_is_compatible(np, "pci106b,5811")) { 2822 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED; 2823 g5_fw_enable(np, 0, 1); 2824 } 2825 np = of_find_node_by_name(np, "firewire"); 2826 } 2827 } 2828 #else /* CONFIG_POWER4 */ 2829 2830 if (macio_chips[0].type == macio_keylargo || 2831 macio_chips[0].type == macio_pangea || 2832 macio_chips[0].type == macio_intrepid) { 2833 /* Enable GMAC for now for PCI probing. It will be disabled 2834 * later on after PCI probe 2835 */ 2836 np = of_find_node_by_name(NULL, "ethernet"); 2837 while(np) { 2838 if (np->parent 2839 && of_device_is_compatible(np->parent, "uni-north") 2840 && of_device_is_compatible(np, "gmac")) 2841 core99_gmac_enable(np, 0, 1); 2842 np = of_find_node_by_name(np, "ethernet"); 2843 } 2844 2845 /* Enable FW before PCI probe. Will be disabled later on 2846 * Note: We should have a batter way to check that we are 2847 * dealing with uninorth internal cell and not a PCI cell 2848 * on the external PCI. The code below works though. 2849 */ 2850 np = of_find_node_by_name(NULL, "firewire"); 2851 while(np) { 2852 if (np->parent 2853 && of_device_is_compatible(np->parent, "uni-north") 2854 && (of_device_is_compatible(np, "pci106b,18") || 2855 of_device_is_compatible(np, "pci106b,30") || 2856 of_device_is_compatible(np, "pci11c1,5811"))) { 2857 macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED; 2858 core99_firewire_enable(np, 0, 1); 2859 } 2860 np = of_find_node_by_name(np, "firewire"); 2861 } 2862 2863 /* Enable ATA-100 before PCI probe. */ 2864 np = of_find_node_by_name(NULL, "ata-6"); 2865 while(np) { 2866 if (np->parent 2867 && of_device_is_compatible(np->parent, "uni-north") 2868 && of_device_is_compatible(np, "kauai-ata")) { 2869 core99_ata100_enable(np, 1); 2870 } 2871 np = of_find_node_by_name(np, "ata-6"); 2872 } 2873 2874 /* Switch airport off */ 2875 for_each_node_by_name(np, "radio") { 2876 if (np->parent == macio_chips[0].of_node) { 2877 macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON; 2878 core99_airport_enable(np, 0, 0); 2879 } 2880 } 2881 } 2882 2883 /* On all machines that support sound PM, switch sound off */ 2884 if (macio_chips[0].of_node) 2885 pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE, 2886 macio_chips[0].of_node, 0, 0); 2887 2888 /* While on some desktop G3s, we turn it back on */ 2889 if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow 2890 && (pmac_mb.model_id == PMAC_TYPE_GOSSAMER || 2891 pmac_mb.model_id == PMAC_TYPE_SILK)) { 2892 struct macio_chip *macio = &macio_chips[0]; 2893 MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE); 2894 MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N); 2895 } 2896 2897 #endif /* CONFIG_POWER4 */ 2898 2899 /* On all machines, switch modem & serial ports off */ 2900 for_each_node_by_name(np, "ch-a") 2901 initial_serial_shutdown(np); 2902 of_node_put(np); 2903 for_each_node_by_name(np, "ch-b") 2904 initial_serial_shutdown(np); 2905 of_node_put(np); 2906 } 2907 2908 void __init 2909 pmac_feature_init(void) 2910 { 2911 /* Detect the UniNorth memory controller */ 2912 probe_uninorth(); 2913 2914 /* Probe mac-io controllers */ 2915 if (probe_macios()) { 2916 printk(KERN_WARNING "No mac-io chip found\n"); 2917 return; 2918 } 2919 2920 /* Probe machine type */ 2921 if (probe_motherboard()) 2922 printk(KERN_WARNING "Unknown PowerMac !\n"); 2923 2924 /* Set some initial features (turn off some chips that will 2925 * be later turned on) 2926 */ 2927 set_initial_features(); 2928 } 2929 2930 #if 0 2931 static void dump_HT_speeds(char *name, u32 cfg, u32 frq) 2932 { 2933 int freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 }; 2934 int bits[8] = { 8,16,0,32,2,4,0,0 }; 2935 int freq = (frq >> 8) & 0xf; 2936 2937 if (freqs[freq] == 0) 2938 printk("%s: Unknown HT link frequency %x\n", name, freq); 2939 else 2940 printk("%s: %d MHz on main link, (%d in / %d out) bits width\n", 2941 name, freqs[freq], 2942 bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]); 2943 } 2944 2945 void __init pmac_check_ht_link(void) 2946 { 2947 u32 ufreq, freq, ucfg, cfg; 2948 struct device_node *pcix_node; 2949 u8 px_bus, px_devfn; 2950 struct pci_controller *px_hose; 2951 2952 (void)in_be32(u3_ht_base + U3_HT_LINK_COMMAND); 2953 ucfg = cfg = in_be32(u3_ht_base + U3_HT_LINK_CONFIG); 2954 ufreq = freq = in_be32(u3_ht_base + U3_HT_LINK_FREQ); 2955 dump_HT_speeds("U3 HyperTransport", cfg, freq); 2956 2957 pcix_node = of_find_compatible_node(NULL, "pci", "pci-x"); 2958 if (pcix_node == NULL) { 2959 printk("No PCI-X bridge found\n"); 2960 return; 2961 } 2962 if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) { 2963 printk("PCI-X bridge found but not matched to pci\n"); 2964 return; 2965 } 2966 px_hose = pci_find_hose_for_OF_device(pcix_node); 2967 if (px_hose == NULL) { 2968 printk("PCI-X bridge found but not matched to host\n"); 2969 return; 2970 } 2971 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg); 2972 early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq); 2973 dump_HT_speeds("PCI-X HT Uplink", cfg, freq); 2974 early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg); 2975 early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq); 2976 dump_HT_speeds("PCI-X HT Downlink", cfg, freq); 2977 } 2978 #endif /* 0 */ 2979 2980 /* 2981 * Early video resume hook 2982 */ 2983 2984 static void (*pmac_early_vresume_proc)(void *data); 2985 static void *pmac_early_vresume_data; 2986 2987 void pmac_set_early_video_resume(void (*proc)(void *data), void *data) 2988 { 2989 if (!machine_is(powermac)) 2990 return; 2991 preempt_disable(); 2992 pmac_early_vresume_proc = proc; 2993 pmac_early_vresume_data = data; 2994 preempt_enable(); 2995 } 2996 EXPORT_SYMBOL(pmac_set_early_video_resume); 2997 2998 void pmac_call_early_video_resume(void) 2999 { 3000 if (pmac_early_vresume_proc) 3001 pmac_early_vresume_proc(pmac_early_vresume_data); 3002 } 3003 3004 /* 3005 * AGP related suspend/resume code 3006 */ 3007 3008 static struct pci_dev *pmac_agp_bridge; 3009 static int (*pmac_agp_suspend)(struct pci_dev *bridge); 3010 static int (*pmac_agp_resume)(struct pci_dev *bridge); 3011 3012 void pmac_register_agp_pm(struct pci_dev *bridge, 3013 int (*suspend)(struct pci_dev *bridge), 3014 int (*resume)(struct pci_dev *bridge)) 3015 { 3016 if (suspend || resume) { 3017 pmac_agp_bridge = bridge; 3018 pmac_agp_suspend = suspend; 3019 pmac_agp_resume = resume; 3020 return; 3021 } 3022 if (bridge != pmac_agp_bridge) 3023 return; 3024 pmac_agp_suspend = pmac_agp_resume = NULL; 3025 return; 3026 } 3027 EXPORT_SYMBOL(pmac_register_agp_pm); 3028 3029 void pmac_suspend_agp_for_card(struct pci_dev *dev) 3030 { 3031 if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL) 3032 return; 3033 if (pmac_agp_bridge->bus != dev->bus) 3034 return; 3035 pmac_agp_suspend(pmac_agp_bridge); 3036 } 3037 EXPORT_SYMBOL(pmac_suspend_agp_for_card); 3038 3039 void pmac_resume_agp_for_card(struct pci_dev *dev) 3040 { 3041 if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL) 3042 return; 3043 if (pmac_agp_bridge->bus != dev->bus) 3044 return; 3045 pmac_agp_resume(pmac_agp_bridge); 3046 } 3047 EXPORT_SYMBOL(pmac_resume_agp_for_card); 3048 3049 int pmac_get_uninorth_variant(void) 3050 { 3051 return uninorth_maj; 3052 } 3053