1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *  Copyright (C) 1996-2001 Paul Mackerras (paulus@cs.anu.edu.au)
4  *                          Ben. Herrenschmidt (benh@kernel.crashing.org)
5  *
6  *  TODO:
7  *
8  *   - Replace mdelay with some schedule loop if possible
9  *   - Shorten some obfuscated delays on some routines (like modem
10  *     power)
11  *   - Refcount some clocks (see darwin)
12  *   - Split split split...
13  */
14 #include <linux/types.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/spinlock.h>
22 #include <linux/adb.h>
23 #include <linux/pmu.h>
24 #include <linux/ioport.h>
25 #include <linux/export.h>
26 #include <linux/pci.h>
27 #include <asm/sections.h>
28 #include <asm/errno.h>
29 #include <asm/ohare.h>
30 #include <asm/heathrow.h>
31 #include <asm/keylargo.h>
32 #include <asm/uninorth.h>
33 #include <asm/io.h>
34 #include <asm/prom.h>
35 #include <asm/machdep.h>
36 #include <asm/pmac_feature.h>
37 #include <asm/dbdma.h>
38 #include <asm/pci-bridge.h>
39 #include <asm/pmac_low_i2c.h>
40 
41 #undef DEBUG_FEATURE
42 
43 #ifdef DEBUG_FEATURE
44 #define DBG(fmt...) printk(KERN_DEBUG fmt)
45 #else
46 #define DBG(fmt...)
47 #endif
48 
49 #ifdef CONFIG_PPC_BOOK3S_32
50 extern int powersave_lowspeed;
51 #endif
52 
53 extern int powersave_nap;
54 extern struct device_node *k2_skiplist[2];
55 
56 /*
57  * We use a single global lock to protect accesses. Each driver has
58  * to take care of its own locking
59  */
60 DEFINE_RAW_SPINLOCK(feature_lock);
61 
62 #define LOCK(flags)	raw_spin_lock_irqsave(&feature_lock, flags);
63 #define UNLOCK(flags)	raw_spin_unlock_irqrestore(&feature_lock, flags);
64 
65 
66 /*
67  * Instance of some macio stuffs
68  */
69 struct macio_chip macio_chips[MAX_MACIO_CHIPS];
70 
71 struct macio_chip *macio_find(struct device_node *child, int type)
72 {
73 	while(child) {
74 		int	i;
75 
76 		for (i=0; i < MAX_MACIO_CHIPS && macio_chips[i].of_node; i++)
77 			if (child == macio_chips[i].of_node &&
78 			    (!type || macio_chips[i].type == type))
79 				return &macio_chips[i];
80 		child = child->parent;
81 	}
82 	return NULL;
83 }
84 EXPORT_SYMBOL_GPL(macio_find);
85 
86 static const char *macio_names[] =
87 {
88 	"Unknown",
89 	"Grand Central",
90 	"OHare",
91 	"OHareII",
92 	"Heathrow",
93 	"Gatwick",
94 	"Paddington",
95 	"Keylargo",
96 	"Pangea",
97 	"Intrepid",
98 	"K2",
99 	"Shasta",
100 };
101 
102 
103 struct device_node *uninorth_node;
104 u32 __iomem *uninorth_base;
105 
106 static u32 uninorth_rev;
107 static int uninorth_maj;
108 static void __iomem *u3_ht_base;
109 
110 /*
111  * For each motherboard family, we have a table of functions pointers
112  * that handle the various features.
113  */
114 
115 typedef long (*feature_call)(struct device_node *node, long param, long value);
116 
117 struct feature_table_entry {
118 	unsigned int	selector;
119 	feature_call	function;
120 };
121 
122 struct pmac_mb_def
123 {
124 	const char*			model_string;
125 	const char*			model_name;
126 	int				model_id;
127 	struct feature_table_entry*	features;
128 	unsigned long			board_flags;
129 };
130 static struct pmac_mb_def pmac_mb;
131 
132 /*
133  * Here are the chip specific feature functions
134  */
135 
136 static inline int simple_feature_tweak(struct device_node *node, int type,
137 				       int reg, u32 mask, int value)
138 {
139 	struct macio_chip*	macio;
140 	unsigned long		flags;
141 
142 	macio = macio_find(node, type);
143 	if (!macio)
144 		return -ENODEV;
145 	LOCK(flags);
146 	if (value)
147 		MACIO_BIS(reg, mask);
148 	else
149 		MACIO_BIC(reg, mask);
150 	(void)MACIO_IN32(reg);
151 	UNLOCK(flags);
152 
153 	return 0;
154 }
155 
156 #ifndef CONFIG_PPC64
157 
158 static long ohare_htw_scc_enable(struct device_node *node, long param,
159 				 long value)
160 {
161 	struct macio_chip*	macio;
162 	unsigned long		chan_mask;
163 	unsigned long		fcr;
164 	unsigned long		flags;
165 	int			htw, trans;
166 	unsigned long		rmask;
167 
168 	macio = macio_find(node, 0);
169 	if (!macio)
170 		return -ENODEV;
171 	if (of_node_name_eq(node, "ch-a"))
172 		chan_mask = MACIO_FLAG_SCCA_ON;
173 	else if (of_node_name_eq(node, "ch-b"))
174 		chan_mask = MACIO_FLAG_SCCB_ON;
175 	else
176 		return -ENODEV;
177 
178 	htw = (macio->type == macio_heathrow || macio->type == macio_paddington
179 		|| macio->type == macio_gatwick);
180 	/* On these machines, the HRW_SCC_TRANS_EN_N bit mustn't be touched */
181 	trans = (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
182 		 pmac_mb.model_id != PMAC_TYPE_YIKES);
183 	if (value) {
184 #ifdef CONFIG_ADB_PMU
185 		if ((param & 0xfff) == PMAC_SCC_IRDA)
186 			pmu_enable_irled(1);
187 #endif /* CONFIG_ADB_PMU */
188 		LOCK(flags);
189 		fcr = MACIO_IN32(OHARE_FCR);
190 		/* Check if scc cell need enabling */
191 		if (!(fcr & OH_SCC_ENABLE)) {
192 			fcr |= OH_SCC_ENABLE;
193 			if (htw) {
194 				/* Side effect: this will also power up the
195 				 * modem, but it's too messy to figure out on which
196 				 * ports this controls the transceiver and on which
197 				 * it controls the modem
198 				 */
199 				if (trans)
200 					fcr &= ~HRW_SCC_TRANS_EN_N;
201 				MACIO_OUT32(OHARE_FCR, fcr);
202 				fcr |= (rmask = HRW_RESET_SCC);
203 				MACIO_OUT32(OHARE_FCR, fcr);
204 			} else {
205 				fcr |= (rmask = OH_SCC_RESET);
206 				MACIO_OUT32(OHARE_FCR, fcr);
207 			}
208 			UNLOCK(flags);
209 			(void)MACIO_IN32(OHARE_FCR);
210 			mdelay(15);
211 			LOCK(flags);
212 			fcr &= ~rmask;
213 			MACIO_OUT32(OHARE_FCR, fcr);
214 		}
215 		if (chan_mask & MACIO_FLAG_SCCA_ON)
216 			fcr |= OH_SCCA_IO;
217 		if (chan_mask & MACIO_FLAG_SCCB_ON)
218 			fcr |= OH_SCCB_IO;
219 		MACIO_OUT32(OHARE_FCR, fcr);
220 		macio->flags |= chan_mask;
221 		UNLOCK(flags);
222 		if (param & PMAC_SCC_FLAG_XMON)
223 			macio->flags |= MACIO_FLAG_SCC_LOCKED;
224 	} else {
225 		if (macio->flags & MACIO_FLAG_SCC_LOCKED)
226 			return -EPERM;
227 		LOCK(flags);
228 		fcr = MACIO_IN32(OHARE_FCR);
229 		if (chan_mask & MACIO_FLAG_SCCA_ON)
230 			fcr &= ~OH_SCCA_IO;
231 		if (chan_mask & MACIO_FLAG_SCCB_ON)
232 			fcr &= ~OH_SCCB_IO;
233 		MACIO_OUT32(OHARE_FCR, fcr);
234 		if ((fcr & (OH_SCCA_IO | OH_SCCB_IO)) == 0) {
235 			fcr &= ~OH_SCC_ENABLE;
236 			if (htw && trans)
237 				fcr |= HRW_SCC_TRANS_EN_N;
238 			MACIO_OUT32(OHARE_FCR, fcr);
239 		}
240 		macio->flags &= ~(chan_mask);
241 		UNLOCK(flags);
242 		mdelay(10);
243 #ifdef CONFIG_ADB_PMU
244 		if ((param & 0xfff) == PMAC_SCC_IRDA)
245 			pmu_enable_irled(0);
246 #endif /* CONFIG_ADB_PMU */
247 	}
248 	return 0;
249 }
250 
251 static long ohare_floppy_enable(struct device_node *node, long param,
252 				long value)
253 {
254 	return simple_feature_tweak(node, macio_ohare,
255 		OHARE_FCR, OH_FLOPPY_ENABLE, value);
256 }
257 
258 static long ohare_mesh_enable(struct device_node *node, long param, long value)
259 {
260 	return simple_feature_tweak(node, macio_ohare,
261 		OHARE_FCR, OH_MESH_ENABLE, value);
262 }
263 
264 static long ohare_ide_enable(struct device_node *node, long param, long value)
265 {
266 	switch(param) {
267 	case 0:
268 		/* For some reason, setting the bit in set_initial_features()
269 		 * doesn't stick. I'm still investigating... --BenH.
270 		 */
271 		if (value)
272 			simple_feature_tweak(node, macio_ohare,
273 				OHARE_FCR, OH_IOBUS_ENABLE, 1);
274 		return simple_feature_tweak(node, macio_ohare,
275 			OHARE_FCR, OH_IDE0_ENABLE, value);
276 	case 1:
277 		return simple_feature_tweak(node, macio_ohare,
278 			OHARE_FCR, OH_BAY_IDE_ENABLE, value);
279 	default:
280 		return -ENODEV;
281 	}
282 }
283 
284 static long ohare_ide_reset(struct device_node *node, long param, long value)
285 {
286 	switch(param) {
287 	case 0:
288 		return simple_feature_tweak(node, macio_ohare,
289 			OHARE_FCR, OH_IDE0_RESET_N, !value);
290 	case 1:
291 		return simple_feature_tweak(node, macio_ohare,
292 			OHARE_FCR, OH_IDE1_RESET_N, !value);
293 	default:
294 		return -ENODEV;
295 	}
296 }
297 
298 static long ohare_sleep_state(struct device_node *node, long param, long value)
299 {
300 	struct macio_chip*	macio = &macio_chips[0];
301 
302 	if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
303 		return -EPERM;
304 	if (value == 1) {
305 		MACIO_BIC(OHARE_FCR, OH_IOBUS_ENABLE);
306 	} else if (value == 0) {
307 		MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
308 	}
309 
310 	return 0;
311 }
312 
313 static long heathrow_modem_enable(struct device_node *node, long param,
314 				  long value)
315 {
316 	struct macio_chip*	macio;
317 	u8			gpio;
318 	unsigned long		flags;
319 
320 	macio = macio_find(node, macio_unknown);
321 	if (!macio)
322 		return -ENODEV;
323 	gpio = MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1;
324 	if (!value) {
325 		LOCK(flags);
326 		MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
327 		UNLOCK(flags);
328 		(void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
329 		mdelay(250);
330 	}
331 	if (pmac_mb.model_id != PMAC_TYPE_YOSEMITE &&
332 	    pmac_mb.model_id != PMAC_TYPE_YIKES) {
333 		LOCK(flags);
334 		if (value)
335 			MACIO_BIC(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
336 		else
337 			MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
338 		UNLOCK(flags);
339 		(void)MACIO_IN32(HEATHROW_FCR);
340 		mdelay(250);
341 	}
342 	if (value) {
343 		LOCK(flags);
344 		MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
345 		(void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
346 		UNLOCK(flags); mdelay(250); LOCK(flags);
347 		MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio);
348 		(void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
349 		UNLOCK(flags); mdelay(250); LOCK(flags);
350 		MACIO_OUT8(HRW_GPIO_MODEM_RESET, gpio | 1);
351 		(void)MACIO_IN8(HRW_GPIO_MODEM_RESET);
352 		UNLOCK(flags); mdelay(250);
353 	}
354 	return 0;
355 }
356 
357 static long heathrow_floppy_enable(struct device_node *node, long param,
358 				   long value)
359 {
360 	return simple_feature_tweak(node, macio_unknown,
361 		HEATHROW_FCR,
362 		HRW_SWIM_ENABLE|HRW_BAY_FLOPPY_ENABLE,
363 		value);
364 }
365 
366 static long heathrow_mesh_enable(struct device_node *node, long param,
367 				 long value)
368 {
369 	struct macio_chip*	macio;
370 	unsigned long		flags;
371 
372 	macio = macio_find(node, macio_unknown);
373 	if (!macio)
374 		return -ENODEV;
375 	LOCK(flags);
376 	/* Set clear mesh cell enable */
377 	if (value)
378 		MACIO_BIS(HEATHROW_FCR, HRW_MESH_ENABLE);
379 	else
380 		MACIO_BIC(HEATHROW_FCR, HRW_MESH_ENABLE);
381 	(void)MACIO_IN32(HEATHROW_FCR);
382 	udelay(10);
383 	/* Set/Clear termination power */
384 	if (value)
385 		MACIO_BIC(HEATHROW_MBCR, 0x04000000);
386 	else
387 		MACIO_BIS(HEATHROW_MBCR, 0x04000000);
388 	(void)MACIO_IN32(HEATHROW_MBCR);
389 	udelay(10);
390 	UNLOCK(flags);
391 
392 	return 0;
393 }
394 
395 static long heathrow_ide_enable(struct device_node *node, long param,
396 				long value)
397 {
398 	switch(param) {
399 	case 0:
400 		return simple_feature_tweak(node, macio_unknown,
401 			HEATHROW_FCR, HRW_IDE0_ENABLE, value);
402 	case 1:
403 		return simple_feature_tweak(node, macio_unknown,
404 			HEATHROW_FCR, HRW_BAY_IDE_ENABLE, value);
405 	default:
406 		return -ENODEV;
407 	}
408 }
409 
410 static long heathrow_ide_reset(struct device_node *node, long param,
411 			       long value)
412 {
413 	switch(param) {
414 	case 0:
415 		return simple_feature_tweak(node, macio_unknown,
416 			HEATHROW_FCR, HRW_IDE0_RESET_N, !value);
417 	case 1:
418 		return simple_feature_tweak(node, macio_unknown,
419 			HEATHROW_FCR, HRW_IDE1_RESET_N, !value);
420 	default:
421 		return -ENODEV;
422 	}
423 }
424 
425 static long heathrow_bmac_enable(struct device_node *node, long param,
426 				 long value)
427 {
428 	struct macio_chip*	macio;
429 	unsigned long		flags;
430 
431 	macio = macio_find(node, 0);
432 	if (!macio)
433 		return -ENODEV;
434 	if (value) {
435 		LOCK(flags);
436 		MACIO_BIS(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
437 		MACIO_BIS(HEATHROW_FCR, HRW_BMAC_RESET);
438 		UNLOCK(flags);
439 		(void)MACIO_IN32(HEATHROW_FCR);
440 		mdelay(10);
441 		LOCK(flags);
442 		MACIO_BIC(HEATHROW_FCR, HRW_BMAC_RESET);
443 		UNLOCK(flags);
444 		(void)MACIO_IN32(HEATHROW_FCR);
445 		mdelay(10);
446 	} else {
447 		LOCK(flags);
448 		MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE);
449 		UNLOCK(flags);
450 	}
451 	return 0;
452 }
453 
454 static long heathrow_sound_enable(struct device_node *node, long param,
455 				  long value)
456 {
457 	struct macio_chip*	macio;
458 	unsigned long		flags;
459 
460 	/* B&W G3 and Yikes don't support that properly (the
461 	 * sound appear to never come back after being shut down).
462 	 */
463 	if (pmac_mb.model_id == PMAC_TYPE_YOSEMITE ||
464 	    pmac_mb.model_id == PMAC_TYPE_YIKES)
465 		return 0;
466 
467 	macio = macio_find(node, 0);
468 	if (!macio)
469 		return -ENODEV;
470 	if (value) {
471 		LOCK(flags);
472 		MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
473 		MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
474 		UNLOCK(flags);
475 		(void)MACIO_IN32(HEATHROW_FCR);
476 	} else {
477 		LOCK(flags);
478 		MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
479 		MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
480 		UNLOCK(flags);
481 	}
482 	return 0;
483 }
484 
485 static u32 save_fcr[6];
486 static u32 save_mbcr;
487 static struct dbdma_regs save_dbdma[13];
488 static struct dbdma_regs save_alt_dbdma[13];
489 
490 static void dbdma_save(struct macio_chip *macio, struct dbdma_regs *save)
491 {
492 	int i;
493 
494 	/* Save state & config of DBDMA channels */
495 	for (i = 0; i < 13; i++) {
496 		volatile struct dbdma_regs __iomem * chan = (void __iomem *)
497 			(macio->base + ((0x8000+i*0x100)>>2));
498 		save[i].cmdptr_hi = in_le32(&chan->cmdptr_hi);
499 		save[i].cmdptr = in_le32(&chan->cmdptr);
500 		save[i].intr_sel = in_le32(&chan->intr_sel);
501 		save[i].br_sel = in_le32(&chan->br_sel);
502 		save[i].wait_sel = in_le32(&chan->wait_sel);
503 	}
504 }
505 
506 static void dbdma_restore(struct macio_chip *macio, struct dbdma_regs *save)
507 {
508 	int i;
509 
510 	/* Save state & config of DBDMA channels */
511 	for (i = 0; i < 13; i++) {
512 		volatile struct dbdma_regs __iomem * chan = (void __iomem *)
513 			(macio->base + ((0x8000+i*0x100)>>2));
514 		out_le32(&chan->control, (ACTIVE|DEAD|WAKE|FLUSH|PAUSE|RUN)<<16);
515 		while (in_le32(&chan->status) & ACTIVE)
516 			mb();
517 		out_le32(&chan->cmdptr_hi, save[i].cmdptr_hi);
518 		out_le32(&chan->cmdptr, save[i].cmdptr);
519 		out_le32(&chan->intr_sel, save[i].intr_sel);
520 		out_le32(&chan->br_sel, save[i].br_sel);
521 		out_le32(&chan->wait_sel, save[i].wait_sel);
522 	}
523 }
524 
525 static void heathrow_sleep(struct macio_chip *macio, int secondary)
526 {
527 	if (secondary) {
528 		dbdma_save(macio, save_alt_dbdma);
529 		save_fcr[2] = MACIO_IN32(0x38);
530 		save_fcr[3] = MACIO_IN32(0x3c);
531 	} else {
532 		dbdma_save(macio, save_dbdma);
533 		save_fcr[0] = MACIO_IN32(0x38);
534 		save_fcr[1] = MACIO_IN32(0x3c);
535 		save_mbcr = MACIO_IN32(0x34);
536 		/* Make sure sound is shut down */
537 		MACIO_BIS(HEATHROW_FCR, HRW_SOUND_POWER_N);
538 		MACIO_BIC(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
539 		/* This seems to be necessary as well or the fan
540 		 * keeps coming up and battery drains fast */
541 		MACIO_BIC(HEATHROW_FCR, HRW_IOBUS_ENABLE);
542 		MACIO_BIC(HEATHROW_FCR, HRW_IDE0_RESET_N);
543 		/* Make sure eth is down even if module or sleep
544 		 * won't work properly */
545 		MACIO_BIC(HEATHROW_FCR, HRW_BMAC_IO_ENABLE | HRW_BMAC_RESET);
546 	}
547 	/* Make sure modem is shut down */
548 	MACIO_OUT8(HRW_GPIO_MODEM_RESET,
549 		MACIO_IN8(HRW_GPIO_MODEM_RESET) & ~1);
550 	MACIO_BIS(HEATHROW_FCR, HRW_SCC_TRANS_EN_N);
551 	MACIO_BIC(HEATHROW_FCR, OH_SCCA_IO|OH_SCCB_IO|HRW_SCC_ENABLE);
552 
553 	/* Let things settle */
554 	(void)MACIO_IN32(HEATHROW_FCR);
555 }
556 
557 static void heathrow_wakeup(struct macio_chip *macio, int secondary)
558 {
559 	if (secondary) {
560 		MACIO_OUT32(0x38, save_fcr[2]);
561 		(void)MACIO_IN32(0x38);
562 		mdelay(1);
563 		MACIO_OUT32(0x3c, save_fcr[3]);
564 		(void)MACIO_IN32(0x38);
565 		mdelay(10);
566 		dbdma_restore(macio, save_alt_dbdma);
567 	} else {
568 		MACIO_OUT32(0x38, save_fcr[0] | HRW_IOBUS_ENABLE);
569 		(void)MACIO_IN32(0x38);
570 		mdelay(1);
571 		MACIO_OUT32(0x3c, save_fcr[1]);
572 		(void)MACIO_IN32(0x38);
573 		mdelay(1);
574 		MACIO_OUT32(0x34, save_mbcr);
575 		(void)MACIO_IN32(0x38);
576 		mdelay(10);
577 		dbdma_restore(macio, save_dbdma);
578 	}
579 }
580 
581 static long heathrow_sleep_state(struct device_node *node, long param,
582 				 long value)
583 {
584 	if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
585 		return -EPERM;
586 	if (value == 1) {
587 		if (macio_chips[1].type == macio_gatwick)
588 			heathrow_sleep(&macio_chips[0], 1);
589 		heathrow_sleep(&macio_chips[0], 0);
590 	} else if (value == 0) {
591 		heathrow_wakeup(&macio_chips[0], 0);
592 		if (macio_chips[1].type == macio_gatwick)
593 			heathrow_wakeup(&macio_chips[0], 1);
594 	}
595 	return 0;
596 }
597 
598 static long core99_scc_enable(struct device_node *node, long param, long value)
599 {
600 	struct macio_chip*	macio;
601 	unsigned long		flags;
602 	unsigned long		chan_mask;
603 	u32			fcr;
604 
605 	macio = macio_find(node, 0);
606 	if (!macio)
607 		return -ENODEV;
608 	if (of_node_name_eq(node, "ch-a"))
609 		chan_mask = MACIO_FLAG_SCCA_ON;
610 	else if (of_node_name_eq(node, "ch-b"))
611 		chan_mask = MACIO_FLAG_SCCB_ON;
612 	else
613 		return -ENODEV;
614 
615 	if (value) {
616 		int need_reset_scc = 0;
617 		int need_reset_irda = 0;
618 
619 		LOCK(flags);
620 		fcr = MACIO_IN32(KEYLARGO_FCR0);
621 		/* Check if scc cell need enabling */
622 		if (!(fcr & KL0_SCC_CELL_ENABLE)) {
623 			fcr |= KL0_SCC_CELL_ENABLE;
624 			need_reset_scc = 1;
625 		}
626 		if (chan_mask & MACIO_FLAG_SCCA_ON) {
627 			fcr |= KL0_SCCA_ENABLE;
628 			/* Don't enable line drivers for I2S modem */
629 			if ((param & 0xfff) == PMAC_SCC_I2S1)
630 				fcr &= ~KL0_SCC_A_INTF_ENABLE;
631 			else
632 				fcr |= KL0_SCC_A_INTF_ENABLE;
633 		}
634 		if (chan_mask & MACIO_FLAG_SCCB_ON) {
635 			fcr |= KL0_SCCB_ENABLE;
636 			/* Perform irda specific inits */
637 			if ((param & 0xfff) == PMAC_SCC_IRDA) {
638 				fcr &= ~KL0_SCC_B_INTF_ENABLE;
639 				fcr |= KL0_IRDA_ENABLE;
640 				fcr |= KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE;
641 				fcr |= KL0_IRDA_SOURCE1_SEL;
642 				fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
643 				fcr &= ~(KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
644 				need_reset_irda = 1;
645 			} else
646 				fcr |= KL0_SCC_B_INTF_ENABLE;
647 		}
648 		MACIO_OUT32(KEYLARGO_FCR0, fcr);
649 		macio->flags |= chan_mask;
650 		if (need_reset_scc)  {
651 			MACIO_BIS(KEYLARGO_FCR0, KL0_SCC_RESET);
652 			(void)MACIO_IN32(KEYLARGO_FCR0);
653 			UNLOCK(flags);
654 			mdelay(15);
655 			LOCK(flags);
656 			MACIO_BIC(KEYLARGO_FCR0, KL0_SCC_RESET);
657 		}
658 		if (need_reset_irda)  {
659 			MACIO_BIS(KEYLARGO_FCR0, KL0_IRDA_RESET);
660 			(void)MACIO_IN32(KEYLARGO_FCR0);
661 			UNLOCK(flags);
662 			mdelay(15);
663 			LOCK(flags);
664 			MACIO_BIC(KEYLARGO_FCR0, KL0_IRDA_RESET);
665 		}
666 		UNLOCK(flags);
667 		if (param & PMAC_SCC_FLAG_XMON)
668 			macio->flags |= MACIO_FLAG_SCC_LOCKED;
669 	} else {
670 		if (macio->flags & MACIO_FLAG_SCC_LOCKED)
671 			return -EPERM;
672 		LOCK(flags);
673 		fcr = MACIO_IN32(KEYLARGO_FCR0);
674 		if (chan_mask & MACIO_FLAG_SCCA_ON)
675 			fcr &= ~KL0_SCCA_ENABLE;
676 		if (chan_mask & MACIO_FLAG_SCCB_ON) {
677 			fcr &= ~KL0_SCCB_ENABLE;
678 			/* Perform irda specific clears */
679 			if ((param & 0xfff) == PMAC_SCC_IRDA) {
680 				fcr &= ~KL0_IRDA_ENABLE;
681 				fcr &= ~(KL0_IRDA_CLK32_ENABLE | KL0_IRDA_CLK19_ENABLE);
682 				fcr &= ~(KL0_IRDA_FAST_CONNECT|KL0_IRDA_DEFAULT1|KL0_IRDA_DEFAULT0);
683 				fcr &= ~(KL0_IRDA_SOURCE1_SEL|KL0_IRDA_SOURCE2_SEL|KL0_IRDA_HIGH_BAND);
684 			}
685 		}
686 		MACIO_OUT32(KEYLARGO_FCR0, fcr);
687 		if ((fcr & (KL0_SCCA_ENABLE | KL0_SCCB_ENABLE)) == 0) {
688 			fcr &= ~KL0_SCC_CELL_ENABLE;
689 			MACIO_OUT32(KEYLARGO_FCR0, fcr);
690 		}
691 		macio->flags &= ~(chan_mask);
692 		UNLOCK(flags);
693 		mdelay(10);
694 	}
695 	return 0;
696 }
697 
698 static long
699 core99_modem_enable(struct device_node *node, long param, long value)
700 {
701 	struct macio_chip*	macio;
702 	u8			gpio;
703 	unsigned long		flags;
704 
705 	/* Hack for internal USB modem */
706 	if (node == NULL) {
707 		if (macio_chips[0].type != macio_keylargo)
708 			return -ENODEV;
709 		node = macio_chips[0].of_node;
710 	}
711 	macio = macio_find(node, 0);
712 	if (!macio)
713 		return -ENODEV;
714 	gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
715 	gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
716 	gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
717 
718 	if (!value) {
719 		LOCK(flags);
720 		MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
721 		UNLOCK(flags);
722 		(void)MACIO_IN8(KL_GPIO_MODEM_RESET);
723 		mdelay(250);
724 	}
725 	LOCK(flags);
726 	if (value) {
727 		MACIO_BIC(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
728 		UNLOCK(flags);
729 		(void)MACIO_IN32(KEYLARGO_FCR2);
730 		mdelay(250);
731 	} else {
732 		MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
733 		UNLOCK(flags);
734 	}
735 	if (value) {
736 		LOCK(flags);
737 		MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
738 		(void)MACIO_IN8(KL_GPIO_MODEM_RESET);
739 		UNLOCK(flags); mdelay(250); LOCK(flags);
740 		MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
741 		(void)MACIO_IN8(KL_GPIO_MODEM_RESET);
742 		UNLOCK(flags); mdelay(250); LOCK(flags);
743 		MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
744 		(void)MACIO_IN8(KL_GPIO_MODEM_RESET);
745 		UNLOCK(flags); mdelay(250);
746 	}
747 	return 0;
748 }
749 
750 static long
751 pangea_modem_enable(struct device_node *node, long param, long value)
752 {
753 	struct macio_chip*	macio;
754 	u8			gpio;
755 	unsigned long		flags;
756 
757 	/* Hack for internal USB modem */
758 	if (node == NULL) {
759 		if (macio_chips[0].type != macio_pangea &&
760 		    macio_chips[0].type != macio_intrepid)
761 			return -ENODEV;
762 		node = macio_chips[0].of_node;
763 	}
764 	macio = macio_find(node, 0);
765 	if (!macio)
766 		return -ENODEV;
767 	gpio = MACIO_IN8(KL_GPIO_MODEM_RESET);
768 	gpio |= KEYLARGO_GPIO_OUTPUT_ENABLE;
769 	gpio &= ~KEYLARGO_GPIO_OUTOUT_DATA;
770 
771 	if (!value) {
772 		LOCK(flags);
773 		MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
774 		UNLOCK(flags);
775 		(void)MACIO_IN8(KL_GPIO_MODEM_RESET);
776 		mdelay(250);
777 	}
778 	LOCK(flags);
779 	if (value) {
780 		MACIO_OUT8(KL_GPIO_MODEM_POWER,
781 			KEYLARGO_GPIO_OUTPUT_ENABLE);
782 		UNLOCK(flags);
783 		(void)MACIO_IN32(KEYLARGO_FCR2);
784 		mdelay(250);
785 	} else {
786 		MACIO_OUT8(KL_GPIO_MODEM_POWER,
787 			KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
788 		UNLOCK(flags);
789 	}
790 	if (value) {
791 		LOCK(flags);
792 		MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
793 		(void)MACIO_IN8(KL_GPIO_MODEM_RESET);
794 		UNLOCK(flags); mdelay(250); LOCK(flags);
795 		MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio);
796 		(void)MACIO_IN8(KL_GPIO_MODEM_RESET);
797 		UNLOCK(flags); mdelay(250); LOCK(flags);
798 		MACIO_OUT8(KL_GPIO_MODEM_RESET, gpio | KEYLARGO_GPIO_OUTOUT_DATA);
799 		(void)MACIO_IN8(KL_GPIO_MODEM_RESET);
800 		UNLOCK(flags); mdelay(250);
801 	}
802 	return 0;
803 }
804 
805 static long
806 core99_ata100_enable(struct device_node *node, long value)
807 {
808 	unsigned long flags;
809 	struct pci_dev *pdev = NULL;
810 	u8 pbus, pid;
811 	int rc;
812 
813 	if (uninorth_rev < 0x24)
814 		return -ENODEV;
815 
816 	LOCK(flags);
817 	if (value)
818 		UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
819 	else
820 		UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_ATA100);
821 	(void)UN_IN(UNI_N_CLOCK_CNTL);
822 	UNLOCK(flags);
823 	udelay(20);
824 
825 	if (value) {
826 		if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
827 			pdev = pci_get_domain_bus_and_slot(0, pbus, pid);
828 		if (pdev == NULL)
829 			return 0;
830 		rc = pci_enable_device(pdev);
831 		if (rc == 0)
832 			pci_set_master(pdev);
833 		pci_dev_put(pdev);
834 		if (rc)
835 			return rc;
836 	}
837 	return 0;
838 }
839 
840 static long
841 core99_ide_enable(struct device_node *node, long param, long value)
842 {
843 	/* Bus ID 0 to 2 are KeyLargo based IDE, busID 3 is U2
844 	 * based ata-100
845 	 */
846 	switch(param) {
847 	    case 0:
848 		return simple_feature_tweak(node, macio_unknown,
849 			KEYLARGO_FCR1, KL1_EIDE0_ENABLE, value);
850 	    case 1:
851 		return simple_feature_tweak(node, macio_unknown,
852 			KEYLARGO_FCR1, KL1_EIDE1_ENABLE, value);
853 	    case 2:
854 		return simple_feature_tweak(node, macio_unknown,
855 			KEYLARGO_FCR1, KL1_UIDE_ENABLE, value);
856 	    case 3:
857 		return core99_ata100_enable(node, value);
858 	    default:
859 		return -ENODEV;
860 	}
861 }
862 
863 static long
864 core99_ide_reset(struct device_node *node, long param, long value)
865 {
866 	switch(param) {
867 	    case 0:
868 		return simple_feature_tweak(node, macio_unknown,
869 			KEYLARGO_FCR1, KL1_EIDE0_RESET_N, !value);
870 	    case 1:
871 		return simple_feature_tweak(node, macio_unknown,
872 			KEYLARGO_FCR1, KL1_EIDE1_RESET_N, !value);
873 	    case 2:
874 		return simple_feature_tweak(node, macio_unknown,
875 			KEYLARGO_FCR1, KL1_UIDE_RESET_N, !value);
876 	    default:
877 		return -ENODEV;
878 	}
879 }
880 
881 static long
882 core99_gmac_enable(struct device_node *node, long param, long value)
883 {
884 	unsigned long flags;
885 
886 	LOCK(flags);
887 	if (value)
888 		UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
889 	else
890 		UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_GMAC);
891 	(void)UN_IN(UNI_N_CLOCK_CNTL);
892 	UNLOCK(flags);
893 	udelay(20);
894 
895 	return 0;
896 }
897 
898 static long
899 core99_gmac_phy_reset(struct device_node *node, long param, long value)
900 {
901 	unsigned long flags;
902 	struct macio_chip *macio;
903 
904 	macio = &macio_chips[0];
905 	if (macio->type != macio_keylargo && macio->type != macio_pangea &&
906 	    macio->type != macio_intrepid)
907 		return -ENODEV;
908 
909 	LOCK(flags);
910 	MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, KEYLARGO_GPIO_OUTPUT_ENABLE);
911 	(void)MACIO_IN8(KL_GPIO_ETH_PHY_RESET);
912 	UNLOCK(flags);
913 	mdelay(10);
914 	LOCK(flags);
915 	MACIO_OUT8(KL_GPIO_ETH_PHY_RESET, /*KEYLARGO_GPIO_OUTPUT_ENABLE | */
916 		KEYLARGO_GPIO_OUTOUT_DATA);
917 	UNLOCK(flags);
918 	mdelay(10);
919 
920 	return 0;
921 }
922 
923 static long
924 core99_sound_chip_enable(struct device_node *node, long param, long value)
925 {
926 	struct macio_chip*	macio;
927 	unsigned long		flags;
928 
929 	macio = macio_find(node, 0);
930 	if (!macio)
931 		return -ENODEV;
932 
933 	/* Do a better probe code, screamer G4 desktops &
934 	 * iMacs can do that too, add a recalibrate  in
935 	 * the driver as well
936 	 */
937 	if (pmac_mb.model_id == PMAC_TYPE_PISMO ||
938 	    pmac_mb.model_id == PMAC_TYPE_TITANIUM) {
939 		LOCK(flags);
940 		if (value)
941 			MACIO_OUT8(KL_GPIO_SOUND_POWER,
942 				KEYLARGO_GPIO_OUTPUT_ENABLE |
943 				KEYLARGO_GPIO_OUTOUT_DATA);
944 		else
945 			MACIO_OUT8(KL_GPIO_SOUND_POWER,
946 				KEYLARGO_GPIO_OUTPUT_ENABLE);
947 		(void)MACIO_IN8(KL_GPIO_SOUND_POWER);
948 		UNLOCK(flags);
949 	}
950 	return 0;
951 }
952 
953 static long
954 core99_airport_enable(struct device_node *node, long param, long value)
955 {
956 	struct macio_chip*	macio;
957 	unsigned long		flags;
958 	int			state;
959 
960 	macio = macio_find(node, 0);
961 	if (!macio)
962 		return -ENODEV;
963 
964 	/* Hint: we allow passing of macio itself for the sake of the
965 	 * sleep code
966 	 */
967 	if (node != macio->of_node &&
968 	    (!node->parent || node->parent != macio->of_node))
969 		return -ENODEV;
970 	state = (macio->flags & MACIO_FLAG_AIRPORT_ON) != 0;
971 	if (value == state)
972 		return 0;
973 	if (value) {
974 		/* This code is a reproduction of OF enable-cardslot
975 		 * and init-wireless methods, slightly hacked until
976 		 * I got it working.
977 		 */
978 		LOCK(flags);
979 		MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 5);
980 		(void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
981 		UNLOCK(flags);
982 		mdelay(10);
983 		LOCK(flags);
984 		MACIO_OUT8(KEYLARGO_GPIO_0+0xf, 4);
985 		(void)MACIO_IN8(KEYLARGO_GPIO_0+0xf);
986 		UNLOCK(flags);
987 
988 		mdelay(10);
989 
990 		LOCK(flags);
991 		MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
992 		(void)MACIO_IN32(KEYLARGO_FCR2);
993 		udelay(10);
994 		MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xb, 0);
995 		(void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xb);
996 		udelay(10);
997 		MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xa, 0x28);
998 		(void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xa);
999 		udelay(10);
1000 		MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+0xd, 0x28);
1001 		(void)MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+0xd);
1002 		udelay(10);
1003 		MACIO_OUT8(KEYLARGO_GPIO_0+0xd, 0x28);
1004 		(void)MACIO_IN8(KEYLARGO_GPIO_0+0xd);
1005 		udelay(10);
1006 		MACIO_OUT8(KEYLARGO_GPIO_0+0xe, 0x28);
1007 		(void)MACIO_IN8(KEYLARGO_GPIO_0+0xe);
1008 		UNLOCK(flags);
1009 		udelay(10);
1010 		MACIO_OUT32(0x1c000, 0);
1011 		mdelay(1);
1012 		MACIO_OUT8(0x1a3e0, 0x41);
1013 		(void)MACIO_IN8(0x1a3e0);
1014 		udelay(10);
1015 		LOCK(flags);
1016 		MACIO_BIS(KEYLARGO_FCR2, KL2_CARDSEL_16);
1017 		(void)MACIO_IN32(KEYLARGO_FCR2);
1018 		UNLOCK(flags);
1019 		mdelay(100);
1020 
1021 		macio->flags |= MACIO_FLAG_AIRPORT_ON;
1022 	} else {
1023 		LOCK(flags);
1024 		MACIO_BIC(KEYLARGO_FCR2, KL2_CARDSEL_16);
1025 		(void)MACIO_IN32(KEYLARGO_FCR2);
1026 		MACIO_OUT8(KL_GPIO_AIRPORT_0, 0);
1027 		MACIO_OUT8(KL_GPIO_AIRPORT_1, 0);
1028 		MACIO_OUT8(KL_GPIO_AIRPORT_2, 0);
1029 		MACIO_OUT8(KL_GPIO_AIRPORT_3, 0);
1030 		MACIO_OUT8(KL_GPIO_AIRPORT_4, 0);
1031 		(void)MACIO_IN8(KL_GPIO_AIRPORT_4);
1032 		UNLOCK(flags);
1033 
1034 		macio->flags &= ~MACIO_FLAG_AIRPORT_ON;
1035 	}
1036 	return 0;
1037 }
1038 
1039 #ifdef CONFIG_SMP
1040 static long
1041 core99_reset_cpu(struct device_node *node, long param, long value)
1042 {
1043 	unsigned int reset_io = 0;
1044 	unsigned long flags;
1045 	struct macio_chip *macio;
1046 	struct device_node *np;
1047 	const int dflt_reset_lines[] = {	KL_GPIO_RESET_CPU0,
1048 						KL_GPIO_RESET_CPU1,
1049 						KL_GPIO_RESET_CPU2,
1050 						KL_GPIO_RESET_CPU3 };
1051 
1052 	macio = &macio_chips[0];
1053 	if (macio->type != macio_keylargo)
1054 		return -ENODEV;
1055 
1056 	for_each_of_cpu_node(np) {
1057 		const u32 *num = of_get_property(np, "reg", NULL);
1058 		const u32 *rst = of_get_property(np, "soft-reset", NULL);
1059 		if (num == NULL || rst == NULL)
1060 			continue;
1061 		if (param == *num) {
1062 			reset_io = *rst;
1063 			break;
1064 		}
1065 	}
1066 	if (np == NULL || reset_io == 0)
1067 		reset_io = dflt_reset_lines[param];
1068 
1069 	LOCK(flags);
1070 	MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1071 	(void)MACIO_IN8(reset_io);
1072 	udelay(1);
1073 	MACIO_OUT8(reset_io, 0);
1074 	(void)MACIO_IN8(reset_io);
1075 	UNLOCK(flags);
1076 
1077 	return 0;
1078 }
1079 #endif /* CONFIG_SMP */
1080 
1081 static long
1082 core99_usb_enable(struct device_node *node, long param, long value)
1083 {
1084 	struct macio_chip *macio;
1085 	unsigned long flags;
1086 	const char *prop;
1087 	int number;
1088 	u32 reg;
1089 
1090 	macio = &macio_chips[0];
1091 	if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1092 	    macio->type != macio_intrepid)
1093 		return -ENODEV;
1094 
1095 	prop = of_get_property(node, "AAPL,clock-id", NULL);
1096 	if (!prop)
1097 		return -ENODEV;
1098 	if (strncmp(prop, "usb0u048", 8) == 0)
1099 		number = 0;
1100 	else if (strncmp(prop, "usb1u148", 8) == 0)
1101 		number = 2;
1102 	else if (strncmp(prop, "usb2u248", 8) == 0)
1103 		number = 4;
1104 	else
1105 		return -ENODEV;
1106 
1107 	/* Sorry for the brute-force locking, but this is only used during
1108 	 * sleep and the timing seem to be critical
1109 	 */
1110 	LOCK(flags);
1111 	if (value) {
1112 		/* Turn ON */
1113 		if (number == 0) {
1114 			MACIO_BIC(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1115 			(void)MACIO_IN32(KEYLARGO_FCR0);
1116 			UNLOCK(flags);
1117 			mdelay(1);
1118 			LOCK(flags);
1119 			MACIO_BIS(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1120 		} else if (number == 2) {
1121 			MACIO_BIC(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1122 			UNLOCK(flags);
1123 			(void)MACIO_IN32(KEYLARGO_FCR0);
1124 			mdelay(1);
1125 			LOCK(flags);
1126 			MACIO_BIS(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1127 		} else if (number == 4) {
1128 			MACIO_BIC(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1129 			UNLOCK(flags);
1130 			(void)MACIO_IN32(KEYLARGO_FCR1);
1131 			mdelay(1);
1132 			LOCK(flags);
1133 			MACIO_BIS(KEYLARGO_FCR1, KL1_USB2_CELL_ENABLE);
1134 		}
1135 		if (number < 4) {
1136 			reg = MACIO_IN32(KEYLARGO_FCR4);
1137 			reg &=	~(KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1138 				KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number));
1139 			reg &=	~(KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1140 				KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1));
1141 			MACIO_OUT32(KEYLARGO_FCR4, reg);
1142 			(void)MACIO_IN32(KEYLARGO_FCR4);
1143 			udelay(10);
1144 		} else {
1145 			reg = MACIO_IN32(KEYLARGO_FCR3);
1146 			reg &=	~(KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1147 				KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0));
1148 			reg &=	~(KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1149 				KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1));
1150 			MACIO_OUT32(KEYLARGO_FCR3, reg);
1151 			(void)MACIO_IN32(KEYLARGO_FCR3);
1152 			udelay(10);
1153 		}
1154 		if (macio->type == macio_intrepid) {
1155 			/* wait for clock stopped bits to clear */
1156 			u32 test0 = 0, test1 = 0;
1157 			u32 status0, status1;
1158 			int timeout = 1000;
1159 
1160 			UNLOCK(flags);
1161 			switch (number) {
1162 			case 0:
1163 				test0 = UNI_N_CLOCK_STOPPED_USB0;
1164 				test1 = UNI_N_CLOCK_STOPPED_USB0PCI;
1165 				break;
1166 			case 2:
1167 				test0 = UNI_N_CLOCK_STOPPED_USB1;
1168 				test1 = UNI_N_CLOCK_STOPPED_USB1PCI;
1169 				break;
1170 			case 4:
1171 				test0 = UNI_N_CLOCK_STOPPED_USB2;
1172 				test1 = UNI_N_CLOCK_STOPPED_USB2PCI;
1173 				break;
1174 			}
1175 			do {
1176 				if (--timeout <= 0) {
1177 					printk(KERN_ERR "core99_usb_enable: "
1178 					       "Timeout waiting for clocks\n");
1179 					break;
1180 				}
1181 				mdelay(1);
1182 				status0 = UN_IN(UNI_N_CLOCK_STOP_STATUS0);
1183 				status1 = UN_IN(UNI_N_CLOCK_STOP_STATUS1);
1184 			} while ((status0 & test0) | (status1 & test1));
1185 			LOCK(flags);
1186 		}
1187 	} else {
1188 		/* Turn OFF */
1189 		if (number < 4) {
1190 			reg = MACIO_IN32(KEYLARGO_FCR4);
1191 			reg |=	KL4_PORT_WAKEUP_ENABLE(number) | KL4_PORT_RESUME_WAKE_EN(number) |
1192 				KL4_PORT_CONNECT_WAKE_EN(number) | KL4_PORT_DISCONNECT_WAKE_EN(number);
1193 			reg |=	KL4_PORT_WAKEUP_ENABLE(number+1) | KL4_PORT_RESUME_WAKE_EN(number+1) |
1194 				KL4_PORT_CONNECT_WAKE_EN(number+1) | KL4_PORT_DISCONNECT_WAKE_EN(number+1);
1195 			MACIO_OUT32(KEYLARGO_FCR4, reg);
1196 			(void)MACIO_IN32(KEYLARGO_FCR4);
1197 			udelay(1);
1198 		} else {
1199 			reg = MACIO_IN32(KEYLARGO_FCR3);
1200 			reg |=	KL3_IT_PORT_WAKEUP_ENABLE(0) | KL3_IT_PORT_RESUME_WAKE_EN(0) |
1201 				KL3_IT_PORT_CONNECT_WAKE_EN(0) | KL3_IT_PORT_DISCONNECT_WAKE_EN(0);
1202 			reg |=	KL3_IT_PORT_WAKEUP_ENABLE(1) | KL3_IT_PORT_RESUME_WAKE_EN(1) |
1203 				KL3_IT_PORT_CONNECT_WAKE_EN(1) | KL3_IT_PORT_DISCONNECT_WAKE_EN(1);
1204 			MACIO_OUT32(KEYLARGO_FCR3, reg);
1205 			(void)MACIO_IN32(KEYLARGO_FCR3);
1206 			udelay(1);
1207 		}
1208 		if (number == 0) {
1209 			if (macio->type != macio_intrepid)
1210 				MACIO_BIC(KEYLARGO_FCR0, KL0_USB0_CELL_ENABLE);
1211 			(void)MACIO_IN32(KEYLARGO_FCR0);
1212 			udelay(1);
1213 			MACIO_BIS(KEYLARGO_FCR0, (KL0_USB0_PAD_SUSPEND0 | KL0_USB0_PAD_SUSPEND1));
1214 			(void)MACIO_IN32(KEYLARGO_FCR0);
1215 		} else if (number == 2) {
1216 			if (macio->type != macio_intrepid)
1217 				MACIO_BIC(KEYLARGO_FCR0, KL0_USB1_CELL_ENABLE);
1218 			(void)MACIO_IN32(KEYLARGO_FCR0);
1219 			udelay(1);
1220 			MACIO_BIS(KEYLARGO_FCR0, (KL0_USB1_PAD_SUSPEND0 | KL0_USB1_PAD_SUSPEND1));
1221 			(void)MACIO_IN32(KEYLARGO_FCR0);
1222 		} else if (number == 4) {
1223 			udelay(1);
1224 			MACIO_BIS(KEYLARGO_FCR1, (KL1_USB2_PAD_SUSPEND0 | KL1_USB2_PAD_SUSPEND1));
1225 			(void)MACIO_IN32(KEYLARGO_FCR1);
1226 		}
1227 		udelay(1);
1228 	}
1229 	UNLOCK(flags);
1230 
1231 	return 0;
1232 }
1233 
1234 static long
1235 core99_firewire_enable(struct device_node *node, long param, long value)
1236 {
1237 	unsigned long flags;
1238 	struct macio_chip *macio;
1239 
1240 	macio = &macio_chips[0];
1241 	if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1242 	    macio->type != macio_intrepid)
1243 		return -ENODEV;
1244 	if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1245 		return -ENODEV;
1246 
1247 	LOCK(flags);
1248 	if (value) {
1249 		UN_BIS(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1250 		(void)UN_IN(UNI_N_CLOCK_CNTL);
1251 	} else {
1252 		UN_BIC(UNI_N_CLOCK_CNTL, UNI_N_CLOCK_CNTL_FW);
1253 		(void)UN_IN(UNI_N_CLOCK_CNTL);
1254 	}
1255 	UNLOCK(flags);
1256 	mdelay(1);
1257 
1258 	return 0;
1259 }
1260 
1261 static long
1262 core99_firewire_cable_power(struct device_node *node, long param, long value)
1263 {
1264 	unsigned long flags;
1265 	struct macio_chip *macio;
1266 
1267 	/* Trick: we allow NULL node */
1268 	if ((pmac_mb.board_flags & PMAC_MB_HAS_FW_POWER) == 0)
1269 		return -ENODEV;
1270 	macio = &macio_chips[0];
1271 	if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1272 	    macio->type != macio_intrepid)
1273 		return -ENODEV;
1274 	if (!(macio->flags & MACIO_FLAG_FW_SUPPORTED))
1275 		return -ENODEV;
1276 
1277 	LOCK(flags);
1278 	if (value) {
1279 		MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 0);
1280 		MACIO_IN8(KL_GPIO_FW_CABLE_POWER);
1281 		udelay(10);
1282 	} else {
1283 		MACIO_OUT8(KL_GPIO_FW_CABLE_POWER , 4);
1284 		MACIO_IN8(KL_GPIO_FW_CABLE_POWER); udelay(10);
1285 	}
1286 	UNLOCK(flags);
1287 	mdelay(1);
1288 
1289 	return 0;
1290 }
1291 
1292 static long
1293 intrepid_aack_delay_enable(struct device_node *node, long param, long value)
1294 {
1295 	unsigned long flags;
1296 
1297 	if (uninorth_rev < 0xd2)
1298 		return -ENODEV;
1299 
1300 	LOCK(flags);
1301 	if (param)
1302 		UN_BIS(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1303 	else
1304 		UN_BIC(UNI_N_AACK_DELAY, UNI_N_AACK_DELAY_ENABLE);
1305 	UNLOCK(flags);
1306 
1307 	return 0;
1308 }
1309 
1310 
1311 #endif /* CONFIG_PPC64 */
1312 
1313 static long
1314 core99_read_gpio(struct device_node *node, long param, long value)
1315 {
1316 	struct macio_chip *macio = &macio_chips[0];
1317 
1318 	return MACIO_IN8(param);
1319 }
1320 
1321 
1322 static long
1323 core99_write_gpio(struct device_node *node, long param, long value)
1324 {
1325 	struct macio_chip *macio = &macio_chips[0];
1326 
1327 	MACIO_OUT8(param, (u8)(value & 0xff));
1328 	return 0;
1329 }
1330 
1331 #ifdef CONFIG_PPC64
1332 static long g5_gmac_enable(struct device_node *node, long param, long value)
1333 {
1334 	struct macio_chip *macio = &macio_chips[0];
1335 	unsigned long flags;
1336 
1337 	if (node == NULL)
1338 		return -ENODEV;
1339 
1340 	LOCK(flags);
1341 	if (value) {
1342 		MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1343 		mb();
1344 		k2_skiplist[0] = NULL;
1345 	} else {
1346 		k2_skiplist[0] = node;
1347 		mb();
1348 		MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_GMAC_CLK_ENABLE);
1349 	}
1350 
1351 	UNLOCK(flags);
1352 	mdelay(1);
1353 
1354 	return 0;
1355 }
1356 
1357 static long g5_fw_enable(struct device_node *node, long param, long value)
1358 {
1359 	struct macio_chip *macio = &macio_chips[0];
1360 	unsigned long flags;
1361 
1362 	if (node == NULL)
1363 		return -ENODEV;
1364 
1365 	LOCK(flags);
1366 	if (value) {
1367 		MACIO_BIS(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1368 		mb();
1369 		k2_skiplist[1] = NULL;
1370 	} else {
1371 		k2_skiplist[1] = node;
1372 		mb();
1373 		MACIO_BIC(KEYLARGO_FCR1, K2_FCR1_FW_CLK_ENABLE);
1374 	}
1375 
1376 	UNLOCK(flags);
1377 	mdelay(1);
1378 
1379 	return 0;
1380 }
1381 
1382 static long g5_mpic_enable(struct device_node *node, long param, long value)
1383 {
1384 	unsigned long flags;
1385 	struct device_node *parent = of_get_parent(node);
1386 	int is_u3;
1387 
1388 	if (parent == NULL)
1389 		return 0;
1390 	is_u3 = of_node_name_eq(parent, "u3") || of_node_name_eq(parent, "u4");
1391 	of_node_put(parent);
1392 	if (!is_u3)
1393 		return 0;
1394 
1395 	LOCK(flags);
1396 	UN_BIS(U3_TOGGLE_REG, U3_MPIC_RESET | U3_MPIC_OUTPUT_ENABLE);
1397 	UNLOCK(flags);
1398 
1399 	return 0;
1400 }
1401 
1402 static long g5_eth_phy_reset(struct device_node *node, long param, long value)
1403 {
1404 	struct macio_chip *macio = &macio_chips[0];
1405 	struct device_node *phy;
1406 	int need_reset;
1407 
1408 	/*
1409 	 * We must not reset the combo PHYs, only the BCM5221 found in
1410 	 * the iMac G5.
1411 	 */
1412 	phy = of_get_next_child(node, NULL);
1413 	if (!phy)
1414 		return -ENODEV;
1415 	need_reset = of_device_is_compatible(phy, "B5221");
1416 	of_node_put(phy);
1417 	if (!need_reset)
1418 		return 0;
1419 
1420 	/* PHY reset is GPIO 29, not in device-tree unfortunately */
1421 	MACIO_OUT8(K2_GPIO_EXTINT_0 + 29,
1422 		   KEYLARGO_GPIO_OUTPUT_ENABLE | KEYLARGO_GPIO_OUTOUT_DATA);
1423 	/* Thankfully, this is now always called at a time when we can
1424 	 * schedule by sungem.
1425 	 */
1426 	msleep(10);
1427 	MACIO_OUT8(K2_GPIO_EXTINT_0 + 29, 0);
1428 
1429 	return 0;
1430 }
1431 
1432 static long g5_i2s_enable(struct device_node *node, long param, long value)
1433 {
1434 	/* Very crude implementation for now */
1435 	struct macio_chip *macio = &macio_chips[0];
1436 	unsigned long flags;
1437 	int cell;
1438 	u32 fcrs[3][3] = {
1439 		{ 0,
1440 		  K2_FCR1_I2S0_CELL_ENABLE |
1441 		  K2_FCR1_I2S0_CLK_ENABLE_BIT | K2_FCR1_I2S0_ENABLE,
1442 		  KL3_I2S0_CLK18_ENABLE
1443 		},
1444 		{ KL0_SCC_A_INTF_ENABLE,
1445 		  K2_FCR1_I2S1_CELL_ENABLE |
1446 		  K2_FCR1_I2S1_CLK_ENABLE_BIT | K2_FCR1_I2S1_ENABLE,
1447 		  KL3_I2S1_CLK18_ENABLE
1448 		},
1449 		{ KL0_SCC_B_INTF_ENABLE,
1450 		  SH_FCR1_I2S2_CELL_ENABLE |
1451 		  SH_FCR1_I2S2_CLK_ENABLE_BIT | SH_FCR1_I2S2_ENABLE,
1452 		  SH_FCR3_I2S2_CLK18_ENABLE
1453 		},
1454 	};
1455 
1456 	if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
1457 		return -ENODEV;
1458 	if (strncmp(node->name, "i2s-", 4))
1459 		return -ENODEV;
1460 	cell = node->name[4] - 'a';
1461 	switch(cell) {
1462 	case 0:
1463 	case 1:
1464 		break;
1465 	case 2:
1466 		if (macio->type == macio_shasta)
1467 			break;
1468 		/* fall through */
1469 	default:
1470 		return -ENODEV;
1471 	}
1472 
1473 	LOCK(flags);
1474 	if (value) {
1475 		MACIO_BIC(KEYLARGO_FCR0, fcrs[cell][0]);
1476 		MACIO_BIS(KEYLARGO_FCR1, fcrs[cell][1]);
1477 		MACIO_BIS(KEYLARGO_FCR3, fcrs[cell][2]);
1478 	} else {
1479 		MACIO_BIC(KEYLARGO_FCR3, fcrs[cell][2]);
1480 		MACIO_BIC(KEYLARGO_FCR1, fcrs[cell][1]);
1481 		MACIO_BIS(KEYLARGO_FCR0, fcrs[cell][0]);
1482 	}
1483 	udelay(10);
1484 	UNLOCK(flags);
1485 
1486 	return 0;
1487 }
1488 
1489 
1490 #ifdef CONFIG_SMP
1491 static long g5_reset_cpu(struct device_node *node, long param, long value)
1492 {
1493 	unsigned int reset_io = 0;
1494 	unsigned long flags;
1495 	struct macio_chip *macio;
1496 	struct device_node *np;
1497 
1498 	macio = &macio_chips[0];
1499 	if (macio->type != macio_keylargo2 && macio->type != macio_shasta)
1500 		return -ENODEV;
1501 
1502 	for_each_of_cpu_node(np) {
1503 		const u32 *num = of_get_property(np, "reg", NULL);
1504 		const u32 *rst = of_get_property(np, "soft-reset", NULL);
1505 		if (num == NULL || rst == NULL)
1506 			continue;
1507 		if (param == *num) {
1508 			reset_io = *rst;
1509 			break;
1510 		}
1511 	}
1512 	if (np == NULL || reset_io == 0)
1513 		return -ENODEV;
1514 
1515 	LOCK(flags);
1516 	MACIO_OUT8(reset_io, KEYLARGO_GPIO_OUTPUT_ENABLE);
1517 	(void)MACIO_IN8(reset_io);
1518 	udelay(1);
1519 	MACIO_OUT8(reset_io, 0);
1520 	(void)MACIO_IN8(reset_io);
1521 	UNLOCK(flags);
1522 
1523 	return 0;
1524 }
1525 #endif /* CONFIG_SMP */
1526 
1527 /*
1528  * This can be called from pmac_smp so isn't static
1529  *
1530  * This takes the second CPU off the bus on dual CPU machines
1531  * running UP
1532  */
1533 void g5_phy_disable_cpu1(void)
1534 {
1535 	if (uninorth_maj == 3)
1536 		UN_OUT(U3_API_PHY_CONFIG_1, 0);
1537 }
1538 #endif /* CONFIG_PPC64 */
1539 
1540 #ifndef CONFIG_PPC64
1541 
1542 
1543 #ifdef CONFIG_PM
1544 static u32 save_gpio_levels[2];
1545 static u8 save_gpio_extint[KEYLARGO_GPIO_EXTINT_CNT];
1546 static u8 save_gpio_normal[KEYLARGO_GPIO_CNT];
1547 static u32 save_unin_clock_ctl;
1548 
1549 static void keylargo_shutdown(struct macio_chip *macio, int sleep_mode)
1550 {
1551 	u32 temp;
1552 
1553 	if (sleep_mode) {
1554 		mdelay(1);
1555 		MACIO_BIS(KEYLARGO_FCR0, KL0_USB_REF_SUSPEND);
1556 		(void)MACIO_IN32(KEYLARGO_FCR0);
1557 		mdelay(1);
1558 	}
1559 
1560 	MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1561 				KL0_SCC_CELL_ENABLE |
1562 				KL0_IRDA_ENABLE | KL0_IRDA_CLK32_ENABLE |
1563 				KL0_IRDA_CLK19_ENABLE);
1564 
1565 	MACIO_BIC(KEYLARGO_MBCR, KL_MBCR_MB0_DEV_MASK);
1566 	MACIO_BIS(KEYLARGO_MBCR, KL_MBCR_MB0_IDE_ENABLE);
1567 
1568 	MACIO_BIC(KEYLARGO_FCR1,
1569 		KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1570 		KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1571 		KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1572 		KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1573 		KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1574 		KL1_EIDE0_ENABLE | KL1_EIDE0_RESET_N |
1575 		KL1_EIDE1_ENABLE | KL1_EIDE1_RESET_N |
1576 		KL1_UIDE_ENABLE);
1577 
1578 	MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1579 	MACIO_BIC(KEYLARGO_FCR2, KL2_IOBUS_ENABLE);
1580 
1581 	temp = MACIO_IN32(KEYLARGO_FCR3);
1582 	if (macio->rev >= 2) {
1583 		temp |= KL3_SHUTDOWN_PLL2X;
1584 		if (sleep_mode)
1585 			temp |= KL3_SHUTDOWN_PLL_TOTAL;
1586 	}
1587 
1588 	temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1589 		KL3_SHUTDOWN_PLLKW35;
1590 	if (sleep_mode)
1591 		temp |= KL3_SHUTDOWN_PLLKW12;
1592 	temp &= ~(KL3_CLK66_ENABLE | KL3_CLK49_ENABLE | KL3_CLK45_ENABLE
1593 		| KL3_CLK31_ENABLE | KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1594 	if (sleep_mode)
1595 		temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_VIA_CLK16_ENABLE);
1596 	MACIO_OUT32(KEYLARGO_FCR3, temp);
1597 
1598 	/* Flush posted writes & wait a bit */
1599 	(void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1600 }
1601 
1602 static void pangea_shutdown(struct macio_chip *macio, int sleep_mode)
1603 {
1604 	u32 temp;
1605 
1606 	MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1607 				KL0_SCC_CELL_ENABLE |
1608 				KL0_USB0_CELL_ENABLE | KL0_USB1_CELL_ENABLE);
1609 
1610 	MACIO_BIC(KEYLARGO_FCR1,
1611 		KL1_AUDIO_SEL_22MCLK | KL1_AUDIO_CLK_ENABLE_BIT |
1612 		KL1_AUDIO_CLK_OUT_ENABLE | KL1_AUDIO_CELL_ENABLE |
1613 		KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1614 		KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1615 		KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1616 		KL1_UIDE_ENABLE);
1617 	if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1618 		MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1619 
1620 	MACIO_BIS(KEYLARGO_FCR2, KL2_ALT_DATA_OUT);
1621 
1622 	temp = MACIO_IN32(KEYLARGO_FCR3);
1623 	temp |= KL3_SHUTDOWN_PLLKW6 | KL3_SHUTDOWN_PLLKW4 |
1624 		KL3_SHUTDOWN_PLLKW35;
1625 	temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE | KL3_CLK31_ENABLE
1626 		| KL3_I2S0_CLK18_ENABLE | KL3_I2S1_CLK18_ENABLE);
1627 	if (sleep_mode)
1628 		temp &= ~(KL3_VIA_CLK16_ENABLE | KL3_TIMER_CLK18_ENABLE);
1629 	MACIO_OUT32(KEYLARGO_FCR3, temp);
1630 
1631 	/* Flush posted writes & wait a bit */
1632 	(void)MACIO_IN32(KEYLARGO_FCR0); mdelay(1);
1633 }
1634 
1635 static void intrepid_shutdown(struct macio_chip *macio, int sleep_mode)
1636 {
1637 	u32 temp;
1638 
1639 	MACIO_BIC(KEYLARGO_FCR0,KL0_SCCA_ENABLE | KL0_SCCB_ENABLE |
1640 		  KL0_SCC_CELL_ENABLE);
1641 
1642 	MACIO_BIC(KEYLARGO_FCR1,
1643 		KL1_I2S0_CELL_ENABLE | KL1_I2S0_CLK_ENABLE_BIT |
1644 		KL1_I2S0_ENABLE | KL1_I2S1_CELL_ENABLE |
1645 		KL1_I2S1_CLK_ENABLE_BIT | KL1_I2S1_ENABLE |
1646 		KL1_EIDE0_ENABLE);
1647 	if (pmac_mb.board_flags & PMAC_MB_MOBILE)
1648 		MACIO_BIC(KEYLARGO_FCR1, KL1_UIDE_RESET_N);
1649 
1650 	temp = MACIO_IN32(KEYLARGO_FCR3);
1651 	temp &= ~(KL3_CLK49_ENABLE | KL3_CLK45_ENABLE |
1652 		  KL3_I2S1_CLK18_ENABLE | KL3_I2S0_CLK18_ENABLE);
1653 	if (sleep_mode)
1654 		temp &= ~(KL3_TIMER_CLK18_ENABLE | KL3_IT_VIA_CLK32_ENABLE);
1655 	MACIO_OUT32(KEYLARGO_FCR3, temp);
1656 
1657 	/* Flush posted writes & wait a bit */
1658 	(void)MACIO_IN32(KEYLARGO_FCR0);
1659 	mdelay(10);
1660 }
1661 
1662 
1663 static int
1664 core99_sleep(void)
1665 {
1666 	struct macio_chip *macio;
1667 	int i;
1668 
1669 	macio = &macio_chips[0];
1670 	if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1671 	    macio->type != macio_intrepid)
1672 		return -ENODEV;
1673 
1674 	/* We power off the wireless slot in case it was not done
1675 	 * by the driver. We don't power it on automatically however
1676 	 */
1677 	if (macio->flags & MACIO_FLAG_AIRPORT_ON)
1678 		core99_airport_enable(macio->of_node, 0, 0);
1679 
1680 	/* We power off the FW cable. Should be done by the driver... */
1681 	if (macio->flags & MACIO_FLAG_FW_SUPPORTED) {
1682 		core99_firewire_enable(NULL, 0, 0);
1683 		core99_firewire_cable_power(NULL, 0, 0);
1684 	}
1685 
1686 	/* We make sure int. modem is off (in case driver lost it) */
1687 	if (macio->type == macio_keylargo)
1688 		core99_modem_enable(macio->of_node, 0, 0);
1689 	else
1690 		pangea_modem_enable(macio->of_node, 0, 0);
1691 
1692 	/* We make sure the sound is off as well */
1693 	core99_sound_chip_enable(macio->of_node, 0, 0);
1694 
1695 	/*
1696 	 * Save various bits of KeyLargo
1697 	 */
1698 
1699 	/* Save the state of the various GPIOs */
1700 	save_gpio_levels[0] = MACIO_IN32(KEYLARGO_GPIO_LEVELS0);
1701 	save_gpio_levels[1] = MACIO_IN32(KEYLARGO_GPIO_LEVELS1);
1702 	for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1703 		save_gpio_extint[i] = MACIO_IN8(KEYLARGO_GPIO_EXTINT_0+i);
1704 	for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1705 		save_gpio_normal[i] = MACIO_IN8(KEYLARGO_GPIO_0+i);
1706 
1707 	/* Save the FCRs */
1708 	if (macio->type == macio_keylargo)
1709 		save_mbcr = MACIO_IN32(KEYLARGO_MBCR);
1710 	save_fcr[0] = MACIO_IN32(KEYLARGO_FCR0);
1711 	save_fcr[1] = MACIO_IN32(KEYLARGO_FCR1);
1712 	save_fcr[2] = MACIO_IN32(KEYLARGO_FCR2);
1713 	save_fcr[3] = MACIO_IN32(KEYLARGO_FCR3);
1714 	save_fcr[4] = MACIO_IN32(KEYLARGO_FCR4);
1715 	if (macio->type == macio_pangea || macio->type == macio_intrepid)
1716 		save_fcr[5] = MACIO_IN32(KEYLARGO_FCR5);
1717 
1718 	/* Save state & config of DBDMA channels */
1719 	dbdma_save(macio, save_dbdma);
1720 
1721 	/*
1722 	 * Turn off as much as we can
1723 	 */
1724 	if (macio->type == macio_pangea)
1725 		pangea_shutdown(macio, 1);
1726 	else if (macio->type == macio_intrepid)
1727 		intrepid_shutdown(macio, 1);
1728 	else if (macio->type == macio_keylargo)
1729 		keylargo_shutdown(macio, 1);
1730 
1731 	/*
1732 	 * Put the host bridge to sleep
1733 	 */
1734 
1735 	save_unin_clock_ctl = UN_IN(UNI_N_CLOCK_CNTL);
1736 	/* Note: do not switch GMAC off, driver does it when necessary, WOL must keep it
1737 	 * enabled !
1738 	 */
1739 	UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl &
1740 	       ~(/*UNI_N_CLOCK_CNTL_GMAC|*/UNI_N_CLOCK_CNTL_FW/*|UNI_N_CLOCK_CNTL_PCI*/));
1741 	udelay(100);
1742 	UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1743 	UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_SLEEP);
1744 	mdelay(10);
1745 
1746 	/*
1747 	 * FIXME: A bit of black magic with OpenPIC (don't ask me why)
1748 	 */
1749 	if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1750 		MACIO_BIS(0x506e0, 0x00400000);
1751 		MACIO_BIS(0x506e0, 0x80000000);
1752 	}
1753 	return 0;
1754 }
1755 
1756 static int
1757 core99_wake_up(void)
1758 {
1759 	struct macio_chip *macio;
1760 	int i;
1761 
1762 	macio = &macio_chips[0];
1763 	if (macio->type != macio_keylargo && macio->type != macio_pangea &&
1764 	    macio->type != macio_intrepid)
1765 		return -ENODEV;
1766 
1767 	/*
1768 	 * Wakeup the host bridge
1769 	 */
1770 	UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1771 	udelay(10);
1772 	UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1773 	udelay(10);
1774 
1775 	/*
1776 	 * Restore KeyLargo
1777 	 */
1778 
1779 	if (macio->type == macio_keylargo) {
1780 		MACIO_OUT32(KEYLARGO_MBCR, save_mbcr);
1781 		(void)MACIO_IN32(KEYLARGO_MBCR); udelay(10);
1782 	}
1783 	MACIO_OUT32(KEYLARGO_FCR0, save_fcr[0]);
1784 	(void)MACIO_IN32(KEYLARGO_FCR0); udelay(10);
1785 	MACIO_OUT32(KEYLARGO_FCR1, save_fcr[1]);
1786 	(void)MACIO_IN32(KEYLARGO_FCR1); udelay(10);
1787 	MACIO_OUT32(KEYLARGO_FCR2, save_fcr[2]);
1788 	(void)MACIO_IN32(KEYLARGO_FCR2); udelay(10);
1789 	MACIO_OUT32(KEYLARGO_FCR3, save_fcr[3]);
1790 	(void)MACIO_IN32(KEYLARGO_FCR3); udelay(10);
1791 	MACIO_OUT32(KEYLARGO_FCR4, save_fcr[4]);
1792 	(void)MACIO_IN32(KEYLARGO_FCR4); udelay(10);
1793 	if (macio->type == macio_pangea || macio->type == macio_intrepid) {
1794 		MACIO_OUT32(KEYLARGO_FCR5, save_fcr[5]);
1795 		(void)MACIO_IN32(KEYLARGO_FCR5); udelay(10);
1796 	}
1797 
1798 	dbdma_restore(macio, save_dbdma);
1799 
1800 	MACIO_OUT32(KEYLARGO_GPIO_LEVELS0, save_gpio_levels[0]);
1801 	MACIO_OUT32(KEYLARGO_GPIO_LEVELS1, save_gpio_levels[1]);
1802 	for (i=0; i<KEYLARGO_GPIO_EXTINT_CNT; i++)
1803 		MACIO_OUT8(KEYLARGO_GPIO_EXTINT_0+i, save_gpio_extint[i]);
1804 	for (i=0; i<KEYLARGO_GPIO_CNT; i++)
1805 		MACIO_OUT8(KEYLARGO_GPIO_0+i, save_gpio_normal[i]);
1806 
1807 	/* FIXME more black magic with OpenPIC ... */
1808 	if (pmac_mb.model_id == PMAC_TYPE_SAWTOOTH) {
1809 		MACIO_BIC(0x506e0, 0x00400000);
1810 		MACIO_BIC(0x506e0, 0x80000000);
1811 	}
1812 
1813 	UN_OUT(UNI_N_CLOCK_CNTL, save_unin_clock_ctl);
1814 	udelay(100);
1815 
1816 	return 0;
1817 }
1818 
1819 #endif /* CONFIG_PM */
1820 
1821 static long
1822 core99_sleep_state(struct device_node *node, long param, long value)
1823 {
1824 	/* Param == 1 means to enter the "fake sleep" mode that is
1825 	 * used for CPU speed switch
1826 	 */
1827 	if (param == 1) {
1828 		if (value == 1) {
1829 			UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_SLEEPING);
1830 			UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_IDLE2);
1831 		} else {
1832 			UN_OUT(UNI_N_POWER_MGT, UNI_N_POWER_MGT_NORMAL);
1833 			udelay(10);
1834 			UN_OUT(UNI_N_HWINIT_STATE, UNI_N_HWINIT_STATE_RUNNING);
1835 			udelay(10);
1836 		}
1837 		return 0;
1838 	}
1839 	if ((pmac_mb.board_flags & PMAC_MB_CAN_SLEEP) == 0)
1840 		return -EPERM;
1841 
1842 #ifdef CONFIG_PM
1843 	if (value == 1)
1844 		return core99_sleep();
1845 	else if (value == 0)
1846 		return core99_wake_up();
1847 
1848 #endif /* CONFIG_PM */
1849 	return 0;
1850 }
1851 
1852 #endif /* CONFIG_PPC64 */
1853 
1854 static long
1855 generic_dev_can_wake(struct device_node *node, long param, long value)
1856 {
1857 	/* Todo: eventually check we are really dealing with on-board
1858 	 * video device ...
1859 	 */
1860 
1861 	if (pmac_mb.board_flags & PMAC_MB_MAY_SLEEP)
1862 		pmac_mb.board_flags |= PMAC_MB_CAN_SLEEP;
1863 	return 0;
1864 }
1865 
1866 static long generic_get_mb_info(struct device_node *node, long param, long value)
1867 {
1868 	switch(param) {
1869 		case PMAC_MB_INFO_MODEL:
1870 			return pmac_mb.model_id;
1871 		case PMAC_MB_INFO_FLAGS:
1872 			return pmac_mb.board_flags;
1873 		case PMAC_MB_INFO_NAME:
1874 			/* hack hack hack... but should work */
1875 			*((const char **)value) = pmac_mb.model_name;
1876 			return 0;
1877 	}
1878 	return -EINVAL;
1879 }
1880 
1881 
1882 /*
1883  * Table definitions
1884  */
1885 
1886 /* Used on any machine
1887  */
1888 static struct feature_table_entry any_features[] = {
1889 	{ PMAC_FTR_GET_MB_INFO,		generic_get_mb_info },
1890 	{ PMAC_FTR_DEVICE_CAN_WAKE,	generic_dev_can_wake },
1891 	{ 0, NULL }
1892 };
1893 
1894 #ifndef CONFIG_PPC64
1895 
1896 /* OHare based motherboards. Currently, we only use these on the
1897  * 2400,3400 and 3500 series powerbooks. Some older desktops seem
1898  * to have issues with turning on/off those asic cells
1899  */
1900 static struct feature_table_entry ohare_features[] = {
1901 	{ PMAC_FTR_SCC_ENABLE,		ohare_htw_scc_enable },
1902 	{ PMAC_FTR_SWIM3_ENABLE,	ohare_floppy_enable },
1903 	{ PMAC_FTR_MESH_ENABLE,		ohare_mesh_enable },
1904 	{ PMAC_FTR_IDE_ENABLE,		ohare_ide_enable},
1905 	{ PMAC_FTR_IDE_RESET,		ohare_ide_reset},
1906 	{ PMAC_FTR_SLEEP_STATE,		ohare_sleep_state },
1907 	{ 0, NULL }
1908 };
1909 
1910 /* Heathrow desktop machines (Beige G3).
1911  * Separated as some features couldn't be properly tested
1912  * and the serial port control bits appear to confuse it.
1913  */
1914 static struct feature_table_entry heathrow_desktop_features[] = {
1915 	{ PMAC_FTR_SWIM3_ENABLE,	heathrow_floppy_enable },
1916 	{ PMAC_FTR_MESH_ENABLE,		heathrow_mesh_enable },
1917 	{ PMAC_FTR_IDE_ENABLE,		heathrow_ide_enable },
1918 	{ PMAC_FTR_IDE_RESET,		heathrow_ide_reset },
1919 	{ PMAC_FTR_BMAC_ENABLE,		heathrow_bmac_enable },
1920 	{ 0, NULL }
1921 };
1922 
1923 /* Heathrow based laptop, that is the Wallstreet and mainstreet
1924  * powerbooks.
1925  */
1926 static struct feature_table_entry heathrow_laptop_features[] = {
1927 	{ PMAC_FTR_SCC_ENABLE,		ohare_htw_scc_enable },
1928 	{ PMAC_FTR_MODEM_ENABLE,	heathrow_modem_enable },
1929 	{ PMAC_FTR_SWIM3_ENABLE,	heathrow_floppy_enable },
1930 	{ PMAC_FTR_MESH_ENABLE,		heathrow_mesh_enable },
1931 	{ PMAC_FTR_IDE_ENABLE,		heathrow_ide_enable },
1932 	{ PMAC_FTR_IDE_RESET,		heathrow_ide_reset },
1933 	{ PMAC_FTR_BMAC_ENABLE,		heathrow_bmac_enable },
1934 	{ PMAC_FTR_SOUND_CHIP_ENABLE,	heathrow_sound_enable },
1935 	{ PMAC_FTR_SLEEP_STATE,		heathrow_sleep_state },
1936 	{ 0, NULL }
1937 };
1938 
1939 /* Paddington based machines
1940  * The lombard (101) powerbook, first iMac models, B&W G3 and Yikes G4.
1941  */
1942 static struct feature_table_entry paddington_features[] = {
1943 	{ PMAC_FTR_SCC_ENABLE,		ohare_htw_scc_enable },
1944 	{ PMAC_FTR_MODEM_ENABLE,	heathrow_modem_enable },
1945 	{ PMAC_FTR_SWIM3_ENABLE,	heathrow_floppy_enable },
1946 	{ PMAC_FTR_MESH_ENABLE,		heathrow_mesh_enable },
1947 	{ PMAC_FTR_IDE_ENABLE,		heathrow_ide_enable },
1948 	{ PMAC_FTR_IDE_RESET,		heathrow_ide_reset },
1949 	{ PMAC_FTR_BMAC_ENABLE,		heathrow_bmac_enable },
1950 	{ PMAC_FTR_SOUND_CHIP_ENABLE,	heathrow_sound_enable },
1951 	{ PMAC_FTR_SLEEP_STATE,		heathrow_sleep_state },
1952 	{ 0, NULL }
1953 };
1954 
1955 /* Core99 & MacRISC 2 machines (all machines released since the
1956  * iBook (included), that is all AGP machines, except pangea
1957  * chipset. The pangea chipset is the "combo" UniNorth/KeyLargo
1958  * used on iBook2 & iMac "flow power".
1959  */
1960 static struct feature_table_entry core99_features[] = {
1961 	{ PMAC_FTR_SCC_ENABLE,		core99_scc_enable },
1962 	{ PMAC_FTR_MODEM_ENABLE,	core99_modem_enable },
1963 	{ PMAC_FTR_IDE_ENABLE,		core99_ide_enable },
1964 	{ PMAC_FTR_IDE_RESET,		core99_ide_reset },
1965 	{ PMAC_FTR_GMAC_ENABLE,		core99_gmac_enable },
1966 	{ PMAC_FTR_GMAC_PHY_RESET,	core99_gmac_phy_reset },
1967 	{ PMAC_FTR_SOUND_CHIP_ENABLE,	core99_sound_chip_enable },
1968 	{ PMAC_FTR_AIRPORT_ENABLE,	core99_airport_enable },
1969 	{ PMAC_FTR_USB_ENABLE,		core99_usb_enable },
1970 	{ PMAC_FTR_1394_ENABLE,		core99_firewire_enable },
1971 	{ PMAC_FTR_1394_CABLE_POWER,	core99_firewire_cable_power },
1972 #ifdef CONFIG_PM
1973 	{ PMAC_FTR_SLEEP_STATE,		core99_sleep_state },
1974 #endif
1975 #ifdef CONFIG_SMP
1976 	{ PMAC_FTR_RESET_CPU,		core99_reset_cpu },
1977 #endif /* CONFIG_SMP */
1978 	{ PMAC_FTR_READ_GPIO,		core99_read_gpio },
1979 	{ PMAC_FTR_WRITE_GPIO,		core99_write_gpio },
1980 	{ 0, NULL }
1981 };
1982 
1983 /* RackMac
1984  */
1985 static struct feature_table_entry rackmac_features[] = {
1986 	{ PMAC_FTR_SCC_ENABLE,		core99_scc_enable },
1987 	{ PMAC_FTR_IDE_ENABLE,		core99_ide_enable },
1988 	{ PMAC_FTR_IDE_RESET,		core99_ide_reset },
1989 	{ PMAC_FTR_GMAC_ENABLE,		core99_gmac_enable },
1990 	{ PMAC_FTR_GMAC_PHY_RESET,	core99_gmac_phy_reset },
1991 	{ PMAC_FTR_USB_ENABLE,		core99_usb_enable },
1992 	{ PMAC_FTR_1394_ENABLE,		core99_firewire_enable },
1993 	{ PMAC_FTR_1394_CABLE_POWER,	core99_firewire_cable_power },
1994 	{ PMAC_FTR_SLEEP_STATE,		core99_sleep_state },
1995 #ifdef CONFIG_SMP
1996 	{ PMAC_FTR_RESET_CPU,		core99_reset_cpu },
1997 #endif /* CONFIG_SMP */
1998 	{ PMAC_FTR_READ_GPIO,		core99_read_gpio },
1999 	{ PMAC_FTR_WRITE_GPIO,		core99_write_gpio },
2000 	{ 0, NULL }
2001 };
2002 
2003 /* Pangea features
2004  */
2005 static struct feature_table_entry pangea_features[] = {
2006 	{ PMAC_FTR_SCC_ENABLE,		core99_scc_enable },
2007 	{ PMAC_FTR_MODEM_ENABLE,	pangea_modem_enable },
2008 	{ PMAC_FTR_IDE_ENABLE,		core99_ide_enable },
2009 	{ PMAC_FTR_IDE_RESET,		core99_ide_reset },
2010 	{ PMAC_FTR_GMAC_ENABLE,		core99_gmac_enable },
2011 	{ PMAC_FTR_GMAC_PHY_RESET,	core99_gmac_phy_reset },
2012 	{ PMAC_FTR_SOUND_CHIP_ENABLE,	core99_sound_chip_enable },
2013 	{ PMAC_FTR_AIRPORT_ENABLE,	core99_airport_enable },
2014 	{ PMAC_FTR_USB_ENABLE,		core99_usb_enable },
2015 	{ PMAC_FTR_1394_ENABLE,		core99_firewire_enable },
2016 	{ PMAC_FTR_1394_CABLE_POWER,	core99_firewire_cable_power },
2017 	{ PMAC_FTR_SLEEP_STATE,		core99_sleep_state },
2018 	{ PMAC_FTR_READ_GPIO,		core99_read_gpio },
2019 	{ PMAC_FTR_WRITE_GPIO,		core99_write_gpio },
2020 	{ 0, NULL }
2021 };
2022 
2023 /* Intrepid features
2024  */
2025 static struct feature_table_entry intrepid_features[] = {
2026 	{ PMAC_FTR_SCC_ENABLE,		core99_scc_enable },
2027 	{ PMAC_FTR_MODEM_ENABLE,	pangea_modem_enable },
2028 	{ PMAC_FTR_IDE_ENABLE,		core99_ide_enable },
2029 	{ PMAC_FTR_IDE_RESET,		core99_ide_reset },
2030 	{ PMAC_FTR_GMAC_ENABLE,		core99_gmac_enable },
2031 	{ PMAC_FTR_GMAC_PHY_RESET,	core99_gmac_phy_reset },
2032 	{ PMAC_FTR_SOUND_CHIP_ENABLE,	core99_sound_chip_enable },
2033 	{ PMAC_FTR_AIRPORT_ENABLE,	core99_airport_enable },
2034 	{ PMAC_FTR_USB_ENABLE,		core99_usb_enable },
2035 	{ PMAC_FTR_1394_ENABLE,		core99_firewire_enable },
2036 	{ PMAC_FTR_1394_CABLE_POWER,	core99_firewire_cable_power },
2037 	{ PMAC_FTR_SLEEP_STATE,		core99_sleep_state },
2038 	{ PMAC_FTR_READ_GPIO,		core99_read_gpio },
2039 	{ PMAC_FTR_WRITE_GPIO,		core99_write_gpio },
2040 	{ PMAC_FTR_AACK_DELAY_ENABLE,	intrepid_aack_delay_enable },
2041 	{ 0, NULL }
2042 };
2043 
2044 #else /* CONFIG_PPC64 */
2045 
2046 /* G5 features
2047  */
2048 static struct feature_table_entry g5_features[] = {
2049 	{ PMAC_FTR_GMAC_ENABLE,		g5_gmac_enable },
2050 	{ PMAC_FTR_1394_ENABLE,		g5_fw_enable },
2051 	{ PMAC_FTR_ENABLE_MPIC,		g5_mpic_enable },
2052 	{ PMAC_FTR_GMAC_PHY_RESET,	g5_eth_phy_reset },
2053 	{ PMAC_FTR_SOUND_CHIP_ENABLE,	g5_i2s_enable },
2054 #ifdef CONFIG_SMP
2055 	{ PMAC_FTR_RESET_CPU,		g5_reset_cpu },
2056 #endif /* CONFIG_SMP */
2057 	{ PMAC_FTR_READ_GPIO,		core99_read_gpio },
2058 	{ PMAC_FTR_WRITE_GPIO,		core99_write_gpio },
2059 	{ 0, NULL }
2060 };
2061 
2062 #endif /* CONFIG_PPC64 */
2063 
2064 static struct pmac_mb_def pmac_mb_defs[] = {
2065 #ifndef CONFIG_PPC64
2066 	/*
2067 	 * Desktops
2068 	 */
2069 
2070 	{	"AAPL,8500",			"PowerMac 8500/8600",
2071 		PMAC_TYPE_PSURGE,		NULL,
2072 		0
2073 	},
2074 	{	"AAPL,9500",			"PowerMac 9500/9600",
2075 		PMAC_TYPE_PSURGE,		NULL,
2076 		0
2077 	},
2078 	{	"AAPL,7200",			"PowerMac 7200",
2079 		PMAC_TYPE_PSURGE,		NULL,
2080 		0
2081 	},
2082 	{	"AAPL,7300",			"PowerMac 7200/7300",
2083 		PMAC_TYPE_PSURGE,		NULL,
2084 		0
2085 	},
2086 	{	"AAPL,7500",			"PowerMac 7500",
2087 		PMAC_TYPE_PSURGE,		NULL,
2088 		0
2089 	},
2090 	{	"AAPL,ShinerESB",		"Apple Network Server",
2091 		PMAC_TYPE_ANS,			NULL,
2092 		0
2093 	},
2094 	{	"AAPL,e407",			"Alchemy",
2095 		PMAC_TYPE_ALCHEMY,		NULL,
2096 		0
2097 	},
2098 	{	"AAPL,e411",			"Gazelle",
2099 		PMAC_TYPE_GAZELLE,		NULL,
2100 		0
2101 	},
2102 	{	"AAPL,Gossamer",		"PowerMac G3 (Gossamer)",
2103 		PMAC_TYPE_GOSSAMER,		heathrow_desktop_features,
2104 		0
2105 	},
2106 	{	"AAPL,PowerMac G3",		"PowerMac G3 (Silk)",
2107 		PMAC_TYPE_SILK,			heathrow_desktop_features,
2108 		0
2109 	},
2110 	{	"PowerMac1,1",			"Blue&White G3",
2111 		PMAC_TYPE_YOSEMITE,		paddington_features,
2112 		0
2113 	},
2114 	{	"PowerMac1,2",			"PowerMac G4 PCI Graphics",
2115 		PMAC_TYPE_YIKES,		paddington_features,
2116 		0
2117 	},
2118 	{	"PowerMac2,1",			"iMac FireWire",
2119 		PMAC_TYPE_FW_IMAC,		core99_features,
2120 		PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2121 	},
2122 	{	"PowerMac2,2",			"iMac FireWire",
2123 		PMAC_TYPE_FW_IMAC,		core99_features,
2124 		PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2125 	},
2126 	{	"PowerMac3,1",			"PowerMac G4 AGP Graphics",
2127 		PMAC_TYPE_SAWTOOTH,		core99_features,
2128 		PMAC_MB_OLD_CORE99
2129 	},
2130 	{	"PowerMac3,2",			"PowerMac G4 AGP Graphics",
2131 		PMAC_TYPE_SAWTOOTH,		core99_features,
2132 		PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2133 	},
2134 	{	"PowerMac3,3",			"PowerMac G4 AGP Graphics",
2135 		PMAC_TYPE_SAWTOOTH,		core99_features,
2136 		PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2137 	},
2138 	{	"PowerMac3,4",			"PowerMac G4 Silver",
2139 		PMAC_TYPE_QUICKSILVER,		core99_features,
2140 		PMAC_MB_MAY_SLEEP
2141 	},
2142 	{	"PowerMac3,5",			"PowerMac G4 Silver",
2143 		PMAC_TYPE_QUICKSILVER,		core99_features,
2144 		PMAC_MB_MAY_SLEEP
2145 	},
2146 	{	"PowerMac3,6",			"PowerMac G4 Windtunnel",
2147 		PMAC_TYPE_WINDTUNNEL,		core99_features,
2148 		PMAC_MB_MAY_SLEEP,
2149 	},
2150 	{	"PowerMac4,1",			"iMac \"Flower Power\"",
2151 		PMAC_TYPE_PANGEA_IMAC,		pangea_features,
2152 		PMAC_MB_MAY_SLEEP
2153 	},
2154 	{	"PowerMac4,2",			"Flat panel iMac",
2155 		PMAC_TYPE_FLAT_PANEL_IMAC,	pangea_features,
2156 		PMAC_MB_CAN_SLEEP
2157 	},
2158 	{	"PowerMac4,4",			"eMac",
2159 		PMAC_TYPE_EMAC,			core99_features,
2160 		PMAC_MB_MAY_SLEEP
2161 	},
2162 	{	"PowerMac5,1",			"PowerMac G4 Cube",
2163 		PMAC_TYPE_CUBE,			core99_features,
2164 		PMAC_MB_MAY_SLEEP | PMAC_MB_OLD_CORE99
2165 	},
2166 	{	"PowerMac6,1",			"Flat panel iMac",
2167 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2168 		PMAC_MB_MAY_SLEEP,
2169 	},
2170 	{	"PowerMac6,3",			"Flat panel iMac",
2171 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2172 		PMAC_MB_MAY_SLEEP,
2173 	},
2174 	{	"PowerMac6,4",			"eMac",
2175 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2176 		PMAC_MB_MAY_SLEEP,
2177 	},
2178 	{	"PowerMac10,1",			"Mac mini",
2179 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2180 		PMAC_MB_MAY_SLEEP,
2181 	},
2182 	{       "PowerMac10,2",                 "Mac mini (Late 2005)",
2183 		PMAC_TYPE_UNKNOWN_INTREPID,     intrepid_features,
2184 		PMAC_MB_MAY_SLEEP,
2185 	},
2186  	{	"iMac,1",			"iMac (first generation)",
2187 		PMAC_TYPE_ORIG_IMAC,		paddington_features,
2188 		0
2189 	},
2190 
2191 	/*
2192 	 * Xserve's
2193 	 */
2194 
2195 	{	"RackMac1,1",			"XServe",
2196 		PMAC_TYPE_RACKMAC,		rackmac_features,
2197 		0,
2198 	},
2199 	{	"RackMac1,2",			"XServe rev. 2",
2200 		PMAC_TYPE_RACKMAC,		rackmac_features,
2201 		0,
2202 	},
2203 
2204 	/*
2205 	 * Laptops
2206 	 */
2207 
2208 	{	"AAPL,3400/2400",		"PowerBook 3400",
2209 		PMAC_TYPE_HOOPER,		ohare_features,
2210 		PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2211 	},
2212 	{	"AAPL,3500",			"PowerBook 3500",
2213 		PMAC_TYPE_KANGA,		ohare_features,
2214 		PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2215 	},
2216 	{	"AAPL,PowerBook1998",		"PowerBook Wallstreet",
2217 		PMAC_TYPE_WALLSTREET,		heathrow_laptop_features,
2218 		PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2219 	},
2220 	{	"PowerBook1,1",			"PowerBook 101 (Lombard)",
2221 		PMAC_TYPE_101_PBOOK,		paddington_features,
2222 		PMAC_MB_CAN_SLEEP | PMAC_MB_MOBILE
2223 	},
2224 	{	"PowerBook2,1",			"iBook (first generation)",
2225 		PMAC_TYPE_ORIG_IBOOK,		core99_features,
2226 		PMAC_MB_CAN_SLEEP | PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2227 	},
2228 	{	"PowerBook2,2",			"iBook FireWire",
2229 		PMAC_TYPE_FW_IBOOK,		core99_features,
2230 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2231 		PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2232 	},
2233 	{	"PowerBook3,1",			"PowerBook Pismo",
2234 		PMAC_TYPE_PISMO,		core99_features,
2235 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER |
2236 		PMAC_MB_OLD_CORE99 | PMAC_MB_MOBILE
2237 	},
2238 	{	"PowerBook3,2",			"PowerBook Titanium",
2239 		PMAC_TYPE_TITANIUM,		core99_features,
2240 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2241 	},
2242 	{	"PowerBook3,3",			"PowerBook Titanium II",
2243 		PMAC_TYPE_TITANIUM2,		core99_features,
2244 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2245 	},
2246 	{	"PowerBook3,4",			"PowerBook Titanium III",
2247 		PMAC_TYPE_TITANIUM3,		core99_features,
2248 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2249 	},
2250 	{	"PowerBook3,5",			"PowerBook Titanium IV",
2251 		PMAC_TYPE_TITANIUM4,		core99_features,
2252 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2253 	},
2254 	{	"PowerBook4,1",			"iBook 2",
2255 		PMAC_TYPE_IBOOK2,		pangea_features,
2256 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2257 	},
2258 	{	"PowerBook4,2",			"iBook 2",
2259 		PMAC_TYPE_IBOOK2,		pangea_features,
2260 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2261 	},
2262 	{	"PowerBook4,3",			"iBook 2 rev. 2",
2263 		PMAC_TYPE_IBOOK2,		pangea_features,
2264 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE
2265 	},
2266 	{	"PowerBook5,1",			"PowerBook G4 17\"",
2267 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2268 		PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2269 	},
2270 	{	"PowerBook5,2",			"PowerBook G4 15\"",
2271 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2272 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2273 	},
2274 	{	"PowerBook5,3",			"PowerBook G4 17\"",
2275 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2276 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2277 	},
2278 	{	"PowerBook5,4",			"PowerBook G4 15\"",
2279 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2280 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2281 	},
2282 	{	"PowerBook5,5",			"PowerBook G4 17\"",
2283 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2284 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2285 	},
2286 	{	"PowerBook5,6",			"PowerBook G4 15\"",
2287 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2288 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2289 	},
2290 	{	"PowerBook5,7",			"PowerBook G4 17\"",
2291 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2292 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2293 	},
2294 	{	"PowerBook5,8",			"PowerBook G4 15\"",
2295 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2296 		PMAC_MB_MAY_SLEEP  | PMAC_MB_MOBILE,
2297 	},
2298 	{	"PowerBook5,9",			"PowerBook G4 17\"",
2299 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2300 		PMAC_MB_MAY_SLEEP | PMAC_MB_MOBILE,
2301 	},
2302 	{	"PowerBook6,1",			"PowerBook G4 12\"",
2303 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2304 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2305 	},
2306 	{	"PowerBook6,2",			"PowerBook G4",
2307 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2308 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2309 	},
2310 	{	"PowerBook6,3",			"iBook G4",
2311 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2312 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2313 	},
2314 	{	"PowerBook6,4",			"PowerBook G4 12\"",
2315 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2316 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2317 	},
2318 	{	"PowerBook6,5",			"iBook G4",
2319 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2320 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2321 	},
2322 	{	"PowerBook6,7",			"iBook G4",
2323 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2324 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2325 	},
2326 	{	"PowerBook6,8",			"PowerBook G4 12\"",
2327 		PMAC_TYPE_UNKNOWN_INTREPID,	intrepid_features,
2328 		PMAC_MB_MAY_SLEEP | PMAC_MB_HAS_FW_POWER | PMAC_MB_MOBILE,
2329 	},
2330 #else /* CONFIG_PPC64 */
2331 	{	"PowerMac7,2",			"PowerMac G5",
2332 		PMAC_TYPE_POWERMAC_G5,		g5_features,
2333 		0,
2334 	},
2335 #ifdef CONFIG_PPC64
2336 	{	"PowerMac7,3",			"PowerMac G5",
2337 		PMAC_TYPE_POWERMAC_G5,		g5_features,
2338 		0,
2339 	},
2340 	{	"PowerMac8,1",			"iMac G5",
2341 		PMAC_TYPE_IMAC_G5,		g5_features,
2342 		0,
2343 	},
2344 	{	"PowerMac9,1",			"PowerMac G5",
2345 		PMAC_TYPE_POWERMAC_G5_U3L,	g5_features,
2346 		0,
2347 	},
2348 	{	"PowerMac11,2",			"PowerMac G5 Dual Core",
2349 		PMAC_TYPE_POWERMAC_G5_U3L,	g5_features,
2350 		0,
2351 	},
2352 	{	"PowerMac12,1",			"iMac G5 (iSight)",
2353 		PMAC_TYPE_POWERMAC_G5_U3L,	g5_features,
2354 		0,
2355 	},
2356 	{       "RackMac3,1",                   "XServe G5",
2357 		PMAC_TYPE_XSERVE_G5,		g5_features,
2358 		0,
2359 	},
2360 #endif /* CONFIG_PPC64 */
2361 #endif /* CONFIG_PPC64 */
2362 };
2363 
2364 /*
2365  * The toplevel feature_call callback
2366  */
2367 long pmac_do_feature_call(unsigned int selector, ...)
2368 {
2369 	struct device_node *node;
2370 	long param, value;
2371 	int i;
2372 	feature_call func = NULL;
2373 	va_list args;
2374 
2375 	if (pmac_mb.features)
2376 		for (i=0; pmac_mb.features[i].function; i++)
2377 			if (pmac_mb.features[i].selector == selector) {
2378 				func = pmac_mb.features[i].function;
2379 				break;
2380 			}
2381 	if (!func)
2382 		for (i=0; any_features[i].function; i++)
2383 			if (any_features[i].selector == selector) {
2384 				func = any_features[i].function;
2385 				break;
2386 			}
2387 	if (!func)
2388 		return -ENODEV;
2389 
2390 	va_start(args, selector);
2391 	node = (struct device_node*)va_arg(args, void*);
2392 	param = va_arg(args, long);
2393 	value = va_arg(args, long);
2394 	va_end(args);
2395 
2396 	return func(node, param, value);
2397 }
2398 
2399 static int __init probe_motherboard(void)
2400 {
2401 	int i;
2402 	struct macio_chip *macio = &macio_chips[0];
2403 	const char *model = NULL;
2404 	struct device_node *dt;
2405 	int ret = 0;
2406 
2407 	/* Lookup known motherboard type in device-tree. First try an
2408 	 * exact match on the "model" property, then try a "compatible"
2409 	 * match is none is found.
2410 	 */
2411 	dt = of_find_node_by_name(NULL, "device-tree");
2412 	if (dt != NULL)
2413 		model = of_get_property(dt, "model", NULL);
2414 	for(i=0; model && i<ARRAY_SIZE(pmac_mb_defs); i++) {
2415 	    if (strcmp(model, pmac_mb_defs[i].model_string) == 0) {
2416 		pmac_mb = pmac_mb_defs[i];
2417 		goto found;
2418 	    }
2419 	}
2420 	for(i=0; i<ARRAY_SIZE(pmac_mb_defs); i++) {
2421 	    if (of_machine_is_compatible(pmac_mb_defs[i].model_string)) {
2422 		pmac_mb = pmac_mb_defs[i];
2423 		goto found;
2424 	    }
2425 	}
2426 
2427 	/* Fallback to selection depending on mac-io chip type */
2428 	switch(macio->type) {
2429 #ifndef CONFIG_PPC64
2430 	    case macio_grand_central:
2431 		pmac_mb.model_id = PMAC_TYPE_PSURGE;
2432 		pmac_mb.model_name = "Unknown PowerSurge";
2433 		break;
2434 	    case macio_ohare:
2435 		pmac_mb.model_id = PMAC_TYPE_UNKNOWN_OHARE;
2436 		pmac_mb.model_name = "Unknown OHare-based";
2437 		break;
2438 	    case macio_heathrow:
2439 		pmac_mb.model_id = PMAC_TYPE_UNKNOWN_HEATHROW;
2440 		pmac_mb.model_name = "Unknown Heathrow-based";
2441 		pmac_mb.features = heathrow_desktop_features;
2442 		break;
2443 	    case macio_paddington:
2444 		pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PADDINGTON;
2445 		pmac_mb.model_name = "Unknown Paddington-based";
2446 		pmac_mb.features = paddington_features;
2447 		break;
2448 	    case macio_keylargo:
2449 		pmac_mb.model_id = PMAC_TYPE_UNKNOWN_CORE99;
2450 		pmac_mb.model_name = "Unknown Keylargo-based";
2451 		pmac_mb.features = core99_features;
2452 		break;
2453 	    case macio_pangea:
2454 		pmac_mb.model_id = PMAC_TYPE_UNKNOWN_PANGEA;
2455 		pmac_mb.model_name = "Unknown Pangea-based";
2456 		pmac_mb.features = pangea_features;
2457 		break;
2458 	    case macio_intrepid:
2459 		pmac_mb.model_id = PMAC_TYPE_UNKNOWN_INTREPID;
2460 		pmac_mb.model_name = "Unknown Intrepid-based";
2461 		pmac_mb.features = intrepid_features;
2462 		break;
2463 #else /* CONFIG_PPC64 */
2464 	case macio_keylargo2:
2465 		pmac_mb.model_id = PMAC_TYPE_UNKNOWN_K2;
2466 		pmac_mb.model_name = "Unknown K2-based";
2467 		pmac_mb.features = g5_features;
2468 		break;
2469 	case macio_shasta:
2470 		pmac_mb.model_id = PMAC_TYPE_UNKNOWN_SHASTA;
2471 		pmac_mb.model_name = "Unknown Shasta-based";
2472 		pmac_mb.features = g5_features;
2473 		break;
2474 #endif /* CONFIG_PPC64 */
2475 	default:
2476 		ret = -ENODEV;
2477 		goto done;
2478 	}
2479 found:
2480 #ifndef CONFIG_PPC64
2481 	/* Fixup Hooper vs. Comet */
2482 	if (pmac_mb.model_id == PMAC_TYPE_HOOPER) {
2483 		u32 __iomem * mach_id_ptr = ioremap(0xf3000034, 4);
2484 		if (!mach_id_ptr) {
2485 			ret = -ENODEV;
2486 			goto done;
2487 		}
2488 		/* Here, I used to disable the media-bay on comet. It
2489 		 * appears this is wrong, the floppy connector is actually
2490 		 * a kind of media-bay and works with the current driver.
2491 		 */
2492 		if (__raw_readl(mach_id_ptr) & 0x20000000UL)
2493 			pmac_mb.model_id = PMAC_TYPE_COMET;
2494 		iounmap(mach_id_ptr);
2495 	}
2496 
2497 	/* Set default value of powersave_nap on machines that support it.
2498 	 * It appears that uninorth rev 3 has a problem with it, we don't
2499 	 * enable it on those. In theory, the flush-on-lock property is
2500 	 * supposed to be set when not supported, but I'm not very confident
2501 	 * that all Apple OF revs did it properly, I do it the paranoid way.
2502 	 */
2503 	if (uninorth_base && uninorth_rev > 3) {
2504 		struct device_node *np;
2505 
2506 		for_each_of_cpu_node(np) {
2507 			int cpu_count = 1;
2508 
2509 			/* Nap mode not supported on SMP */
2510 			if (of_get_property(np, "flush-on-lock", NULL) ||
2511 			    (cpu_count > 1)) {
2512 				powersave_nap = 0;
2513 				of_node_put(np);
2514 				break;
2515 			}
2516 
2517 			cpu_count++;
2518 			powersave_nap = 1;
2519 		}
2520 	}
2521 	if (powersave_nap)
2522 		printk(KERN_DEBUG "Processor NAP mode on idle enabled.\n");
2523 
2524 	/* On CPUs that support it (750FX), lowspeed by default during
2525 	 * NAP mode
2526 	 */
2527 	powersave_lowspeed = 1;
2528 
2529 #else /* CONFIG_PPC64 */
2530 	powersave_nap = 1;
2531 #endif  /* CONFIG_PPC64 */
2532 
2533 	/* Check for "mobile" machine */
2534 	if (model && (strncmp(model, "PowerBook", 9) == 0
2535 		   || strncmp(model, "iBook", 5) == 0))
2536 		pmac_mb.board_flags |= PMAC_MB_MOBILE;
2537 
2538 
2539 	printk(KERN_INFO "PowerMac motherboard: %s\n", pmac_mb.model_name);
2540 done:
2541 	of_node_put(dt);
2542 	return ret;
2543 }
2544 
2545 /* Initialize the Core99 UniNorth host bridge and memory controller
2546  */
2547 static void __init probe_uninorth(void)
2548 {
2549 	const u32 *addrp;
2550 	phys_addr_t address;
2551 	unsigned long actrl;
2552 
2553 	/* Locate core99 Uni-N */
2554 	uninorth_node = of_find_node_by_name(NULL, "uni-n");
2555 	uninorth_maj = 1;
2556 
2557 	/* Locate G5 u3 */
2558 	if (uninorth_node == NULL) {
2559 		uninorth_node = of_find_node_by_name(NULL, "u3");
2560 		uninorth_maj = 3;
2561 	}
2562 	/* Locate G5 u4 */
2563 	if (uninorth_node == NULL) {
2564 		uninorth_node = of_find_node_by_name(NULL, "u4");
2565 		uninorth_maj = 4;
2566 	}
2567 	if (uninorth_node == NULL) {
2568 		uninorth_maj = 0;
2569 		return;
2570 	}
2571 
2572 	addrp = of_get_property(uninorth_node, "reg", NULL);
2573 	if (addrp == NULL)
2574 		return;
2575 	address = of_translate_address(uninorth_node, addrp);
2576 	if (address == 0)
2577 		return;
2578 	uninorth_base = ioremap(address, 0x40000);
2579 	if (uninorth_base == NULL)
2580 		return;
2581 	uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
2582 	if (uninorth_maj == 3 || uninorth_maj == 4) {
2583 		u3_ht_base = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
2584 		if (u3_ht_base == NULL) {
2585 			iounmap(uninorth_base);
2586 			return;
2587 		}
2588 	}
2589 
2590 	printk(KERN_INFO "Found %s memory controller & host bridge"
2591 	       " @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" :
2592 	       uninorth_maj == 4 ? "U4" : "UniNorth",
2593 	       (unsigned int)address, uninorth_rev);
2594 	printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
2595 
2596 	/* Set the arbitrer QAck delay according to what Apple does
2597 	 */
2598 	if (uninorth_rev < 0x11) {
2599 		actrl = UN_IN(UNI_N_ARB_CTRL) & ~UNI_N_ARB_CTRL_QACK_DELAY_MASK;
2600 		actrl |= ((uninorth_rev < 3) ? UNI_N_ARB_CTRL_QACK_DELAY105 :
2601 			UNI_N_ARB_CTRL_QACK_DELAY) <<
2602 			UNI_N_ARB_CTRL_QACK_DELAY_SHIFT;
2603 		UN_OUT(UNI_N_ARB_CTRL, actrl);
2604 	}
2605 
2606 	/* Some more magic as done by them in recent MacOS X on UniNorth
2607 	 * revs 1.5 to 2.O and Pangea. Seem to toggle the UniN Maxbus/PCI
2608 	 * memory timeout
2609 	 */
2610 	if ((uninorth_rev >= 0x11 && uninorth_rev <= 0x24) ||
2611 	    uninorth_rev == 0xc0)
2612 		UN_OUT(0x2160, UN_IN(0x2160) & 0x00ffffff);
2613 }
2614 
2615 static void __init probe_one_macio(const char *name, const char *compat, int type)
2616 {
2617 	struct device_node*	node;
2618 	int			i;
2619 	volatile u32 __iomem	*base;
2620 	const u32		*addrp, *revp;
2621 	phys_addr_t		addr;
2622 	u64			size;
2623 
2624 	for_each_node_by_name(node, name) {
2625 		if (!compat)
2626 			break;
2627 		if (of_device_is_compatible(node, compat))
2628 			break;
2629 	}
2630 	if (!node)
2631 		return;
2632 	for(i=0; i<MAX_MACIO_CHIPS; i++) {
2633 		if (!macio_chips[i].of_node)
2634 			break;
2635 		if (macio_chips[i].of_node == node)
2636 			return;
2637 	}
2638 
2639 	if (i >= MAX_MACIO_CHIPS) {
2640 		printk(KERN_ERR "pmac_feature: Please increase MAX_MACIO_CHIPS !\n");
2641 		printk(KERN_ERR "pmac_feature: %pOF skipped\n", node);
2642 		return;
2643 	}
2644 	addrp = of_get_pci_address(node, 0, &size, NULL);
2645 	if (addrp == NULL) {
2646 		printk(KERN_ERR "pmac_feature: %pOF: can't find base !\n",
2647 		       node);
2648 		return;
2649 	}
2650 	addr = of_translate_address(node, addrp);
2651 	if (addr == 0) {
2652 		printk(KERN_ERR "pmac_feature: %pOF, can't translate base !\n",
2653 		       node);
2654 		return;
2655 	}
2656 	base = ioremap(addr, (unsigned long)size);
2657 	if (!base) {
2658 		printk(KERN_ERR "pmac_feature: %pOF, can't map mac-io chip !\n",
2659 		       node);
2660 		return;
2661 	}
2662 	if (type == macio_keylargo || type == macio_keylargo2) {
2663 		const u32 *did = of_get_property(node, "device-id", NULL);
2664 		if (*did == 0x00000025)
2665 			type = macio_pangea;
2666 		if (*did == 0x0000003e)
2667 			type = macio_intrepid;
2668 		if (*did == 0x0000004f)
2669 			type = macio_shasta;
2670 	}
2671 	macio_chips[i].of_node	= node;
2672 	macio_chips[i].type	= type;
2673 	macio_chips[i].base	= base;
2674 	macio_chips[i].flags	= MACIO_FLAG_SCCA_ON | MACIO_FLAG_SCCB_ON;
2675 	macio_chips[i].name	= macio_names[type];
2676 	revp = of_get_property(node, "revision-id", NULL);
2677 	if (revp)
2678 		macio_chips[i].rev = *revp;
2679 	printk(KERN_INFO "Found a %s mac-io controller, rev: %d, mapped at 0x%p\n",
2680 		macio_names[type], macio_chips[i].rev, macio_chips[i].base);
2681 }
2682 
2683 static int __init
2684 probe_macios(void)
2685 {
2686 	/* Warning, ordering is important */
2687 	probe_one_macio("gc", NULL, macio_grand_central);
2688 	probe_one_macio("ohare", NULL, macio_ohare);
2689 	probe_one_macio("pci106b,7", NULL, macio_ohareII);
2690 	probe_one_macio("mac-io", "keylargo", macio_keylargo);
2691 	probe_one_macio("mac-io", "paddington", macio_paddington);
2692 	probe_one_macio("mac-io", "gatwick", macio_gatwick);
2693 	probe_one_macio("mac-io", "heathrow", macio_heathrow);
2694 	probe_one_macio("mac-io", "K2-Keylargo", macio_keylargo2);
2695 
2696 	/* Make sure the "main" macio chip appear first */
2697 	if (macio_chips[0].type == macio_gatwick
2698 	    && macio_chips[1].type == macio_heathrow) {
2699 		struct macio_chip temp = macio_chips[0];
2700 		macio_chips[0] = macio_chips[1];
2701 		macio_chips[1] = temp;
2702 	}
2703 	if (macio_chips[0].type == macio_ohareII
2704 	    && macio_chips[1].type == macio_ohare) {
2705 		struct macio_chip temp = macio_chips[0];
2706 		macio_chips[0] = macio_chips[1];
2707 		macio_chips[1] = temp;
2708 	}
2709 	macio_chips[0].lbus.index = 0;
2710 	macio_chips[1].lbus.index = 1;
2711 
2712 	return (macio_chips[0].of_node == NULL) ? -ENODEV : 0;
2713 }
2714 
2715 static void __init
2716 initial_serial_shutdown(struct device_node *np)
2717 {
2718 	int len;
2719 	const struct slot_names_prop {
2720 		int	count;
2721 		char	name[1];
2722 	} *slots;
2723 	const char *conn;
2724 	int port_type = PMAC_SCC_ASYNC;
2725 	int modem = 0;
2726 
2727 	slots = of_get_property(np, "slot-names", &len);
2728 	conn = of_get_property(np, "AAPL,connector", &len);
2729 	if (conn && (strcmp(conn, "infrared") == 0))
2730 		port_type = PMAC_SCC_IRDA;
2731 	else if (of_device_is_compatible(np, "cobalt"))
2732 		modem = 1;
2733 	else if (slots && slots->count > 0) {
2734 		if (strcmp(slots->name, "IrDA") == 0)
2735 			port_type = PMAC_SCC_IRDA;
2736 		else if (strcmp(slots->name, "Modem") == 0)
2737 			modem = 1;
2738 	}
2739 	if (modem)
2740 		pmac_call_feature(PMAC_FTR_MODEM_ENABLE, np, 0, 0);
2741 	pmac_call_feature(PMAC_FTR_SCC_ENABLE, np, port_type, 0);
2742 }
2743 
2744 static void __init
2745 set_initial_features(void)
2746 {
2747 	struct device_node *np;
2748 
2749 	/* That hack appears to be necessary for some StarMax motherboards
2750 	 * but I'm not too sure it was audited for side-effects on other
2751 	 * ohare based machines...
2752 	 * Since I still have difficulties figuring the right way to
2753 	 * differentiate them all and since that hack was there for a long
2754 	 * time, I'll keep it around
2755 	 */
2756 	if (macio_chips[0].type == macio_ohare) {
2757 		struct macio_chip *macio = &macio_chips[0];
2758 		np = of_find_node_by_name(NULL, "via-pmu");
2759 		if (np)
2760 			MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2761 		else
2762 			MACIO_OUT32(OHARE_FCR, STARMAX_FEATURES);
2763 		of_node_put(np);
2764 	} else if (macio_chips[1].type == macio_ohare) {
2765 		struct macio_chip *macio = &macio_chips[1];
2766 		MACIO_BIS(OHARE_FCR, OH_IOBUS_ENABLE);
2767 	}
2768 
2769 #ifdef CONFIG_PPC64
2770 	if (macio_chips[0].type == macio_keylargo2 ||
2771 	    macio_chips[0].type == macio_shasta) {
2772 #ifndef CONFIG_SMP
2773 		/* On SMP machines running UP, we have the second CPU eating
2774 		 * bus cycles. We need to take it off the bus. This is done
2775 		 * from pmac_smp for SMP kernels running on one CPU
2776 		 */
2777 		np = of_find_node_by_type(NULL, "cpu");
2778 		if (np != NULL)
2779 			np = of_find_node_by_type(np, "cpu");
2780 		if (np != NULL) {
2781 			g5_phy_disable_cpu1();
2782 			of_node_put(np);
2783 		}
2784 #endif /* CONFIG_SMP */
2785 		/* Enable GMAC for now for PCI probing. It will be disabled
2786 		 * later on after PCI probe
2787 		 */
2788 		for_each_node_by_name(np, "ethernet")
2789 			if (of_device_is_compatible(np, "K2-GMAC"))
2790 				g5_gmac_enable(np, 0, 1);
2791 
2792 		/* Enable FW before PCI probe. Will be disabled later on
2793 		 * Note: We should have a batter way to check that we are
2794 		 * dealing with uninorth internal cell and not a PCI cell
2795 		 * on the external PCI. The code below works though.
2796 		 */
2797 		for_each_node_by_name(np, "firewire") {
2798 			if (of_device_is_compatible(np, "pci106b,5811")) {
2799 				macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2800 				g5_fw_enable(np, 0, 1);
2801 			}
2802 		}
2803 	}
2804 #else /* CONFIG_PPC64 */
2805 
2806 	if (macio_chips[0].type == macio_keylargo ||
2807 	    macio_chips[0].type == macio_pangea ||
2808 	    macio_chips[0].type == macio_intrepid) {
2809 		/* Enable GMAC for now for PCI probing. It will be disabled
2810 		 * later on after PCI probe
2811 		 */
2812 		for_each_node_by_name(np, "ethernet") {
2813 			if (np->parent
2814 			    && of_device_is_compatible(np->parent, "uni-north")
2815 			    && of_device_is_compatible(np, "gmac"))
2816 				core99_gmac_enable(np, 0, 1);
2817 		}
2818 
2819 		/* Enable FW before PCI probe. Will be disabled later on
2820 		 * Note: We should have a batter way to check that we are
2821 		 * dealing with uninorth internal cell and not a PCI cell
2822 		 * on the external PCI. The code below works though.
2823 		 */
2824 		for_each_node_by_name(np, "firewire") {
2825 			if (np->parent
2826 			    && of_device_is_compatible(np->parent, "uni-north")
2827 			    && (of_device_is_compatible(np, "pci106b,18") ||
2828 			        of_device_is_compatible(np, "pci106b,30") ||
2829 			        of_device_is_compatible(np, "pci11c1,5811"))) {
2830 				macio_chips[0].flags |= MACIO_FLAG_FW_SUPPORTED;
2831 				core99_firewire_enable(np, 0, 1);
2832 			}
2833 		}
2834 
2835 		/* Enable ATA-100 before PCI probe. */
2836 		for_each_node_by_name(np, "ata-6") {
2837 			if (np->parent
2838 			    && of_device_is_compatible(np->parent, "uni-north")
2839 			    && of_device_is_compatible(np, "kauai-ata")) {
2840 				core99_ata100_enable(np, 1);
2841 			}
2842 		}
2843 
2844 		/* Switch airport off */
2845 		for_each_node_by_name(np, "radio") {
2846 			if (np->parent == macio_chips[0].of_node) {
2847 				macio_chips[0].flags |= MACIO_FLAG_AIRPORT_ON;
2848 				core99_airport_enable(np, 0, 0);
2849 			}
2850 		}
2851 	}
2852 
2853 	/* On all machines that support sound PM, switch sound off */
2854 	if (macio_chips[0].of_node)
2855 		pmac_do_feature_call(PMAC_FTR_SOUND_CHIP_ENABLE,
2856 			macio_chips[0].of_node, 0, 0);
2857 
2858 	/* While on some desktop G3s, we turn it back on */
2859 	if (macio_chips[0].of_node && macio_chips[0].type == macio_heathrow
2860 		&& (pmac_mb.model_id == PMAC_TYPE_GOSSAMER ||
2861 		    pmac_mb.model_id == PMAC_TYPE_SILK)) {
2862 		struct macio_chip *macio = &macio_chips[0];
2863 		MACIO_BIS(HEATHROW_FCR, HRW_SOUND_CLK_ENABLE);
2864 		MACIO_BIC(HEATHROW_FCR, HRW_SOUND_POWER_N);
2865 	}
2866 
2867 #endif /* CONFIG_PPC64 */
2868 
2869 	/* On all machines, switch modem & serial ports off */
2870 	for_each_node_by_name(np, "ch-a")
2871 		initial_serial_shutdown(np);
2872 	for_each_node_by_name(np, "ch-b")
2873 		initial_serial_shutdown(np);
2874 }
2875 
2876 void __init
2877 pmac_feature_init(void)
2878 {
2879 	/* Detect the UniNorth memory controller */
2880 	probe_uninorth();
2881 
2882 	/* Probe mac-io controllers */
2883 	if (probe_macios()) {
2884 		printk(KERN_WARNING "No mac-io chip found\n");
2885 		return;
2886 	}
2887 
2888 	/* Probe machine type */
2889 	if (probe_motherboard())
2890 		printk(KERN_WARNING "Unknown PowerMac !\n");
2891 
2892 	/* Set some initial features (turn off some chips that will
2893 	 * be later turned on)
2894 	 */
2895 	set_initial_features();
2896 }
2897 
2898 #if 0
2899 static void dump_HT_speeds(char *name, u32 cfg, u32 frq)
2900 {
2901 	int	freqs[16] = { 200,300,400,500,600,800,1000,0,0,0,0,0,0,0,0,0 };
2902 	int	bits[8] = { 8,16,0,32,2,4,0,0 };
2903 	int	freq = (frq >> 8) & 0xf;
2904 
2905 	if (freqs[freq] == 0)
2906 		printk("%s: Unknown HT link frequency %x\n", name, freq);
2907 	else
2908 		printk("%s: %d MHz on main link, (%d in / %d out) bits width\n",
2909 		       name, freqs[freq],
2910 		       bits[(cfg >> 28) & 0x7], bits[(cfg >> 24) & 0x7]);
2911 }
2912 
2913 void __init pmac_check_ht_link(void)
2914 {
2915 	u32	ufreq, freq, ucfg, cfg;
2916 	struct device_node *pcix_node;
2917 	u8	px_bus, px_devfn;
2918 	struct pci_controller *px_hose;
2919 
2920 	(void)in_be32(u3_ht_base + U3_HT_LINK_COMMAND);
2921 	ucfg = cfg = in_be32(u3_ht_base + U3_HT_LINK_CONFIG);
2922 	ufreq = freq = in_be32(u3_ht_base + U3_HT_LINK_FREQ);
2923 	dump_HT_speeds("U3 HyperTransport", cfg, freq);
2924 
2925 	pcix_node = of_find_compatible_node(NULL, "pci", "pci-x");
2926 	if (pcix_node == NULL) {
2927 		printk("No PCI-X bridge found\n");
2928 		return;
2929 	}
2930 	if (pci_device_from_OF_node(pcix_node, &px_bus, &px_devfn) != 0) {
2931 		printk("PCI-X bridge found but not matched to pci\n");
2932 		return;
2933 	}
2934 	px_hose = pci_find_hose_for_OF_device(pcix_node);
2935 	if (px_hose == NULL) {
2936 		printk("PCI-X bridge found but not matched to host\n");
2937 		return;
2938 	}
2939 	early_read_config_dword(px_hose, px_bus, px_devfn, 0xc4, &cfg);
2940 	early_read_config_dword(px_hose, px_bus, px_devfn, 0xcc, &freq);
2941 	dump_HT_speeds("PCI-X HT Uplink", cfg, freq);
2942 	early_read_config_dword(px_hose, px_bus, px_devfn, 0xc8, &cfg);
2943 	early_read_config_dword(px_hose, px_bus, px_devfn, 0xd0, &freq);
2944 	dump_HT_speeds("PCI-X HT Downlink", cfg, freq);
2945 }
2946 #endif /* 0 */
2947 
2948 /*
2949  * Early video resume hook
2950  */
2951 
2952 static void (*pmac_early_vresume_proc)(void *data);
2953 static void *pmac_early_vresume_data;
2954 
2955 void pmac_set_early_video_resume(void (*proc)(void *data), void *data)
2956 {
2957 	if (!machine_is(powermac))
2958 		return;
2959 	preempt_disable();
2960 	pmac_early_vresume_proc = proc;
2961 	pmac_early_vresume_data = data;
2962 	preempt_enable();
2963 }
2964 EXPORT_SYMBOL(pmac_set_early_video_resume);
2965 
2966 void pmac_call_early_video_resume(void)
2967 {
2968 	if (pmac_early_vresume_proc)
2969 		pmac_early_vresume_proc(pmac_early_vresume_data);
2970 }
2971 
2972 /*
2973  * AGP related suspend/resume code
2974  */
2975 
2976 static struct pci_dev *pmac_agp_bridge;
2977 static int (*pmac_agp_suspend)(struct pci_dev *bridge);
2978 static int (*pmac_agp_resume)(struct pci_dev *bridge);
2979 
2980 void pmac_register_agp_pm(struct pci_dev *bridge,
2981 				 int (*suspend)(struct pci_dev *bridge),
2982 				 int (*resume)(struct pci_dev *bridge))
2983 {
2984 	if (suspend || resume) {
2985 		pmac_agp_bridge = bridge;
2986 		pmac_agp_suspend = suspend;
2987 		pmac_agp_resume = resume;
2988 		return;
2989 	}
2990 	if (bridge != pmac_agp_bridge)
2991 		return;
2992 	pmac_agp_suspend = pmac_agp_resume = NULL;
2993 	return;
2994 }
2995 EXPORT_SYMBOL(pmac_register_agp_pm);
2996 
2997 void pmac_suspend_agp_for_card(struct pci_dev *dev)
2998 {
2999 	if (pmac_agp_bridge == NULL || pmac_agp_suspend == NULL)
3000 		return;
3001 	if (pmac_agp_bridge->bus != dev->bus)
3002 		return;
3003 	pmac_agp_suspend(pmac_agp_bridge);
3004 }
3005 EXPORT_SYMBOL(pmac_suspend_agp_for_card);
3006 
3007 void pmac_resume_agp_for_card(struct pci_dev *dev)
3008 {
3009 	if (pmac_agp_bridge == NULL || pmac_agp_resume == NULL)
3010 		return;
3011 	if (pmac_agp_bridge->bus != dev->bus)
3012 		return;
3013 	pmac_agp_resume(pmac_agp_bridge);
3014 }
3015 EXPORT_SYMBOL(pmac_resume_agp_for_card);
3016 
3017 int pmac_get_uninorth_variant(void)
3018 {
3019 	return uninorth_maj;
3020 }
3021