1 /* 2 * Copyright (C) 2006-2007 PA Semi, Inc 3 * 4 * Authors: Kip Walker, PA Semi 5 * Olof Johansson, PA Semi 6 * 7 * Maintained by: Olof Johansson <olof@lixom.net> 8 * 9 * Based on arch/powerpc/platforms/maple/setup.c 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 */ 24 25 #include <linux/errno.h> 26 #include <linux/kernel.h> 27 #include <linux/delay.h> 28 #include <linux/console.h> 29 #include <linux/export.h> 30 #include <linux/pci.h> 31 #include <linux/of_platform.h> 32 #include <linux/gfp.h> 33 34 #include <asm/prom.h> 35 #include <asm/iommu.h> 36 #include <asm/machdep.h> 37 #include <asm/mpic.h> 38 #include <asm/smp.h> 39 #include <asm/time.h> 40 #include <asm/mmu.h> 41 #include <asm/debug.h> 42 43 #include <pcmcia/ss.h> 44 #include <pcmcia/cistpl.h> 45 #include <pcmcia/ds.h> 46 47 #include "pasemi.h" 48 49 /* SDC reset register, must be pre-mapped at reset time */ 50 static void __iomem *reset_reg; 51 52 /* Various error status registers, must be pre-mapped at MCE time */ 53 54 #define MAX_MCE_REGS 32 55 struct mce_regs { 56 char *name; 57 void __iomem *addr; 58 }; 59 60 static struct mce_regs mce_regs[MAX_MCE_REGS]; 61 static int num_mce_regs; 62 static int nmi_virq = 0; 63 64 65 static void __noreturn pas_restart(char *cmd) 66 { 67 /* Need to put others cpu in hold loop so they're not sleeping */ 68 smp_send_stop(); 69 udelay(10000); 70 printk("Restarting...\n"); 71 while (1) 72 out_le32(reset_reg, 0x6000000); 73 } 74 75 #ifdef CONFIG_SMP 76 static arch_spinlock_t timebase_lock; 77 static unsigned long timebase; 78 79 static void pas_give_timebase(void) 80 { 81 unsigned long flags; 82 83 local_irq_save(flags); 84 hard_irq_disable(); 85 arch_spin_lock(&timebase_lock); 86 mtspr(SPRN_TBCTL, TBCTL_FREEZE); 87 isync(); 88 timebase = get_tb(); 89 arch_spin_unlock(&timebase_lock); 90 91 while (timebase) 92 barrier(); 93 mtspr(SPRN_TBCTL, TBCTL_RESTART); 94 local_irq_restore(flags); 95 } 96 97 static void pas_take_timebase(void) 98 { 99 while (!timebase) 100 smp_rmb(); 101 102 arch_spin_lock(&timebase_lock); 103 set_tb(timebase >> 32, timebase & 0xffffffff); 104 timebase = 0; 105 arch_spin_unlock(&timebase_lock); 106 } 107 108 static struct smp_ops_t pas_smp_ops = { 109 .probe = smp_mpic_probe, 110 .message_pass = smp_mpic_message_pass, 111 .kick_cpu = smp_generic_kick_cpu, 112 .setup_cpu = smp_mpic_setup_cpu, 113 .give_timebase = pas_give_timebase, 114 .take_timebase = pas_take_timebase, 115 }; 116 #endif /* CONFIG_SMP */ 117 118 static void __init pas_setup_arch(void) 119 { 120 #ifdef CONFIG_SMP 121 /* Setup SMP callback */ 122 smp_ops = &pas_smp_ops; 123 #endif 124 /* Lookup PCI hosts */ 125 pas_pci_init(); 126 127 #ifdef CONFIG_DUMMY_CONSOLE 128 conswitchp = &dummy_con; 129 #endif 130 131 /* Remap SDC register for doing reset */ 132 /* XXXOJN This should maybe come out of the device tree */ 133 reset_reg = ioremap(0xfc101100, 4); 134 } 135 136 static int __init pas_setup_mce_regs(void) 137 { 138 struct pci_dev *dev; 139 int reg; 140 141 /* Remap various SoC status registers for use by the MCE handler */ 142 143 reg = 0; 144 145 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL); 146 while (dev && reg < MAX_MCE_REGS) { 147 mce_regs[reg].name = kasprintf(GFP_KERNEL, 148 "mc%d_mcdebug_errsta", reg); 149 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730); 150 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev); 151 reg++; 152 } 153 154 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); 155 if (dev && reg+4 < MAX_MCE_REGS) { 156 mce_regs[reg].name = "iobdbg_IntStatus1"; 157 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438); 158 reg++; 159 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg"; 160 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454); 161 reg++; 162 mce_regs[reg].name = "iobiom_IntStatus"; 163 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10); 164 reg++; 165 mce_regs[reg].name = "iobiom_IntDbgReg"; 166 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c); 167 reg++; 168 } 169 170 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL); 171 if (dev && reg+2 < MAX_MCE_REGS) { 172 mce_regs[reg].name = "l2csts_IntStatus"; 173 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200); 174 reg++; 175 mce_regs[reg].name = "l2csts_Cnt"; 176 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214); 177 reg++; 178 } 179 180 num_mce_regs = reg; 181 182 return 0; 183 } 184 machine_device_initcall(pasemi, pas_setup_mce_regs); 185 186 static __init void pas_init_IRQ(void) 187 { 188 struct device_node *np; 189 struct device_node *root, *mpic_node; 190 unsigned long openpic_addr; 191 const unsigned int *opprop; 192 int naddr, opplen; 193 int mpic_flags; 194 const unsigned int *nmiprop; 195 struct mpic *mpic; 196 197 mpic_node = NULL; 198 199 for_each_node_by_type(np, "interrupt-controller") 200 if (of_device_is_compatible(np, "open-pic")) { 201 mpic_node = np; 202 break; 203 } 204 if (!mpic_node) 205 for_each_node_by_type(np, "open-pic") { 206 mpic_node = np; 207 break; 208 } 209 if (!mpic_node) { 210 pr_err("Failed to locate the MPIC interrupt controller\n"); 211 return; 212 } 213 214 /* Find address list in /platform-open-pic */ 215 root = of_find_node_by_path("/"); 216 naddr = of_n_addr_cells(root); 217 opprop = of_get_property(root, "platform-open-pic", &opplen); 218 if (!opprop) { 219 pr_err("No platform-open-pic property.\n"); 220 of_node_put(root); 221 return; 222 } 223 openpic_addr = of_read_number(opprop, naddr); 224 pr_debug("OpenPIC addr: %lx\n", openpic_addr); 225 226 mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS | MPIC_NO_RESET; 227 228 nmiprop = of_get_property(mpic_node, "nmi-source", NULL); 229 if (nmiprop) 230 mpic_flags |= MPIC_ENABLE_MCK; 231 232 mpic = mpic_alloc(mpic_node, openpic_addr, 233 mpic_flags, 0, 0, "PASEMI-OPIC"); 234 BUG_ON(!mpic); 235 236 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000); 237 mpic_init(mpic); 238 /* The NMI/MCK source needs to be prio 15 */ 239 if (nmiprop) { 240 nmi_virq = irq_create_mapping(NULL, *nmiprop); 241 mpic_irq_set_priority(nmi_virq, 15); 242 irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); 243 mpic_unmask_irq(irq_get_irq_data(nmi_virq)); 244 } 245 246 of_node_put(mpic_node); 247 of_node_put(root); 248 } 249 250 static void __init pas_progress(char *s, unsigned short hex) 251 { 252 printk("[%04x] : %s\n", hex, s ? s : ""); 253 } 254 255 256 static int pas_machine_check_handler(struct pt_regs *regs) 257 { 258 int cpu = smp_processor_id(); 259 unsigned long srr0, srr1, dsisr; 260 int dump_slb = 0; 261 int i; 262 263 srr0 = regs->nip; 264 srr1 = regs->msr; 265 266 if (nmi_virq && mpic_get_mcirq() == nmi_virq) { 267 pr_err("NMI delivered\n"); 268 debugger(regs); 269 mpic_end_irq(irq_get_irq_data(nmi_virq)); 270 goto out; 271 } 272 273 dsisr = mfspr(SPRN_DSISR); 274 pr_err("Machine Check on CPU %d\n", cpu); 275 pr_err("SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1); 276 pr_err("DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar); 277 pr_err("BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER), 278 mfspr(SPRN_PA6T_MER)); 279 pr_err("IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER), 280 mfspr(SPRN_PA6T_DER)); 281 pr_err("Cause:\n"); 282 283 if (srr1 & 0x200000) 284 pr_err("Signalled by SDC\n"); 285 286 if (srr1 & 0x100000) { 287 pr_err("Load/Store detected error:\n"); 288 if (dsisr & 0x8000) 289 pr_err("D-cache ECC double-bit error or bus error\n"); 290 if (dsisr & 0x4000) 291 pr_err("LSU snoop response error\n"); 292 if (dsisr & 0x2000) { 293 pr_err("MMU SLB multi-hit or invalid B field\n"); 294 dump_slb = 1; 295 } 296 if (dsisr & 0x1000) 297 pr_err("Recoverable Duptags\n"); 298 if (dsisr & 0x800) 299 pr_err("Recoverable D-cache parity error count overflow\n"); 300 if (dsisr & 0x400) 301 pr_err("TLB parity error count overflow\n"); 302 } 303 304 if (srr1 & 0x80000) 305 pr_err("Bus Error\n"); 306 307 if (srr1 & 0x40000) { 308 pr_err("I-side SLB multiple hit\n"); 309 dump_slb = 1; 310 } 311 312 if (srr1 & 0x20000) 313 pr_err("I-cache parity error hit\n"); 314 315 if (num_mce_regs == 0) 316 pr_err("No MCE registers mapped yet, can't dump\n"); 317 else 318 pr_err("SoC debug registers:\n"); 319 320 for (i = 0; i < num_mce_regs; i++) 321 pr_err("%s: 0x%08x\n", mce_regs[i].name, 322 in_le32(mce_regs[i].addr)); 323 324 if (dump_slb) { 325 unsigned long e, v; 326 int i; 327 328 pr_err("slb contents:\n"); 329 for (i = 0; i < mmu_slb_size; i++) { 330 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i)); 331 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i)); 332 pr_err("%02d %016lx %016lx\n", i, e, v); 333 } 334 } 335 336 out: 337 /* SRR1[62] is from MSR[62] if recoverable, so pass that back */ 338 return !!(srr1 & 0x2); 339 } 340 341 #ifdef CONFIG_PCMCIA 342 static int pcmcia_notify(struct notifier_block *nb, unsigned long action, 343 void *data) 344 { 345 struct device *dev = data; 346 struct device *parent; 347 struct pcmcia_device *pdev = to_pcmcia_dev(dev); 348 349 /* We are only intereted in device addition */ 350 if (action != BUS_NOTIFY_ADD_DEVICE) 351 return 0; 352 353 parent = pdev->socket->dev.parent; 354 355 /* We know electra_cf devices will always have of_node set, since 356 * electra_cf is an of_platform driver. 357 */ 358 if (!parent->of_node) 359 return 0; 360 361 if (!of_device_is_compatible(parent->of_node, "electra-cf")) 362 return 0; 363 364 /* We use the direct ops for localbus */ 365 dev->dma_ops = &dma_nommu_ops; 366 367 return 0; 368 } 369 370 static struct notifier_block pcmcia_notifier = { 371 .notifier_call = pcmcia_notify, 372 }; 373 374 static inline void pasemi_pcmcia_init(void) 375 { 376 extern struct bus_type pcmcia_bus_type; 377 378 bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier); 379 } 380 381 #else 382 383 static inline void pasemi_pcmcia_init(void) 384 { 385 } 386 387 #endif 388 389 390 static const struct of_device_id pasemi_bus_ids[] = { 391 /* Unfortunately needed for legacy firmwares */ 392 { .type = "localbus", }, 393 { .type = "sdc", }, 394 /* These are the proper entries, which newer firmware uses */ 395 { .compatible = "pasemi,localbus", }, 396 { .compatible = "pasemi,sdc", }, 397 {}, 398 }; 399 400 static int __init pasemi_publish_devices(void) 401 { 402 pasemi_pcmcia_init(); 403 404 /* Publish OF platform devices for SDC and other non-PCI devices */ 405 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL); 406 407 return 0; 408 } 409 machine_device_initcall(pasemi, pasemi_publish_devices); 410 411 412 /* 413 * Called very early, MMU is off, device-tree isn't unflattened 414 */ 415 static int __init pas_probe(void) 416 { 417 if (!of_machine_is_compatible("PA6T-1682M") && 418 !of_machine_is_compatible("pasemi,pwrficient")) 419 return 0; 420 421 iommu_init_early_pasemi(); 422 423 return 1; 424 } 425 426 define_machine(pasemi) { 427 .name = "PA Semi PWRficient", 428 .probe = pas_probe, 429 .setup_arch = pas_setup_arch, 430 .init_IRQ = pas_init_IRQ, 431 .get_irq = mpic_get_irq, 432 .restart = pas_restart, 433 .get_boot_time = pas_get_boot_time, 434 .calibrate_decr = generic_calibrate_decr, 435 .progress = pas_progress, 436 .machine_check_exception = pas_machine_check_handler, 437 }; 438