1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2006-2007 PA Semi, Inc 4 * 5 * Authors: Kip Walker, PA Semi 6 * Olof Johansson, PA Semi 7 * 8 * Maintained by: Olof Johansson <olof@lixom.net> 9 * 10 * Based on arch/powerpc/platforms/maple/setup.c 11 */ 12 13 #include <linux/errno.h> 14 #include <linux/kernel.h> 15 #include <linux/delay.h> 16 #include <linux/console.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/of_platform.h> 20 #include <linux/gfp.h> 21 22 #include <asm/prom.h> 23 #include <asm/iommu.h> 24 #include <asm/machdep.h> 25 #include <asm/i8259.h> 26 #include <asm/mpic.h> 27 #include <asm/smp.h> 28 #include <asm/time.h> 29 #include <asm/mmu.h> 30 #include <asm/debug.h> 31 32 #include <pcmcia/ss.h> 33 #include <pcmcia/cistpl.h> 34 #include <pcmcia/ds.h> 35 36 #include "pasemi.h" 37 38 /* SDC reset register, must be pre-mapped at reset time */ 39 static void __iomem *reset_reg; 40 41 /* Various error status registers, must be pre-mapped at MCE time */ 42 43 #define MAX_MCE_REGS 32 44 struct mce_regs { 45 char *name; 46 void __iomem *addr; 47 }; 48 49 static struct mce_regs mce_regs[MAX_MCE_REGS]; 50 static int num_mce_regs; 51 static int nmi_virq = 0; 52 53 54 static void __noreturn pas_restart(char *cmd) 55 { 56 /* Need to put others cpu in hold loop so they're not sleeping */ 57 smp_send_stop(); 58 udelay(10000); 59 printk("Restarting...\n"); 60 while (1) 61 out_le32(reset_reg, 0x6000000); 62 } 63 64 #ifdef CONFIG_PPC_PASEMI_NEMO 65 void pas_shutdown(void) 66 { 67 /* Set the PLD bit that makes the SB600 think the power button is being pressed */ 68 void __iomem *pld_map = ioremap(0xf5000000,4096); 69 while (1) 70 out_8(pld_map+7,0x01); 71 } 72 73 /* RTC platform device structure as is not in device tree */ 74 static struct resource rtc_resource[] = {{ 75 .name = "rtc", 76 .start = 0x70, 77 .end = 0x71, 78 .flags = IORESOURCE_IO, 79 }, { 80 .name = "rtc", 81 .start = 8, 82 .end = 8, 83 .flags = IORESOURCE_IRQ, 84 }}; 85 86 static inline void nemo_init_rtc(void) 87 { 88 platform_device_register_simple("rtc_cmos", -1, rtc_resource, 2); 89 } 90 91 #else 92 93 static inline void nemo_init_rtc(void) 94 { 95 } 96 #endif 97 98 #ifdef CONFIG_SMP 99 static arch_spinlock_t timebase_lock; 100 static unsigned long timebase; 101 102 static void pas_give_timebase(void) 103 { 104 unsigned long flags; 105 106 local_irq_save(flags); 107 hard_irq_disable(); 108 arch_spin_lock(&timebase_lock); 109 mtspr(SPRN_TBCTL, TBCTL_FREEZE); 110 isync(); 111 timebase = get_tb(); 112 arch_spin_unlock(&timebase_lock); 113 114 while (timebase) 115 barrier(); 116 mtspr(SPRN_TBCTL, TBCTL_RESTART); 117 local_irq_restore(flags); 118 } 119 120 static void pas_take_timebase(void) 121 { 122 while (!timebase) 123 smp_rmb(); 124 125 arch_spin_lock(&timebase_lock); 126 set_tb(timebase >> 32, timebase & 0xffffffff); 127 timebase = 0; 128 arch_spin_unlock(&timebase_lock); 129 } 130 131 static struct smp_ops_t pas_smp_ops = { 132 .probe = smp_mpic_probe, 133 .message_pass = smp_mpic_message_pass, 134 .kick_cpu = smp_generic_kick_cpu, 135 .setup_cpu = smp_mpic_setup_cpu, 136 .give_timebase = pas_give_timebase, 137 .take_timebase = pas_take_timebase, 138 }; 139 #endif /* CONFIG_SMP */ 140 141 static void __init pas_setup_arch(void) 142 { 143 #ifdef CONFIG_SMP 144 /* Setup SMP callback */ 145 smp_ops = &pas_smp_ops; 146 #endif 147 /* Lookup PCI hosts */ 148 pas_pci_init(); 149 150 #ifdef CONFIG_DUMMY_CONSOLE 151 conswitchp = &dummy_con; 152 #endif 153 154 /* Remap SDC register for doing reset */ 155 /* XXXOJN This should maybe come out of the device tree */ 156 reset_reg = ioremap(0xfc101100, 4); 157 } 158 159 static int __init pas_setup_mce_regs(void) 160 { 161 struct pci_dev *dev; 162 int reg; 163 164 /* Remap various SoC status registers for use by the MCE handler */ 165 166 reg = 0; 167 168 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL); 169 while (dev && reg < MAX_MCE_REGS) { 170 mce_regs[reg].name = kasprintf(GFP_KERNEL, 171 "mc%d_mcdebug_errsta", reg); 172 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730); 173 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev); 174 reg++; 175 } 176 177 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); 178 if (dev && reg+4 < MAX_MCE_REGS) { 179 mce_regs[reg].name = "iobdbg_IntStatus1"; 180 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438); 181 reg++; 182 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg"; 183 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454); 184 reg++; 185 mce_regs[reg].name = "iobiom_IntStatus"; 186 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10); 187 reg++; 188 mce_regs[reg].name = "iobiom_IntDbgReg"; 189 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c); 190 reg++; 191 } 192 193 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL); 194 if (dev && reg+2 < MAX_MCE_REGS) { 195 mce_regs[reg].name = "l2csts_IntStatus"; 196 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200); 197 reg++; 198 mce_regs[reg].name = "l2csts_Cnt"; 199 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214); 200 reg++; 201 } 202 203 num_mce_regs = reg; 204 205 return 0; 206 } 207 machine_device_initcall(pasemi, pas_setup_mce_regs); 208 209 #ifdef CONFIG_PPC_PASEMI_NEMO 210 static void sb600_8259_cascade(struct irq_desc *desc) 211 { 212 struct irq_chip *chip = irq_desc_get_chip(desc); 213 unsigned int cascade_irq = i8259_irq(); 214 215 if (cascade_irq) 216 generic_handle_irq(cascade_irq); 217 218 chip->irq_eoi(&desc->irq_data); 219 } 220 221 static void nemo_init_IRQ(struct mpic *mpic) 222 { 223 struct device_node *np; 224 int gpio_virq; 225 /* Connect the SB600's legacy i8259 controller */ 226 np = of_find_node_by_path("/pxp@0,e0000000"); 227 i8259_init(np, 0); 228 of_node_put(np); 229 230 gpio_virq = irq_create_mapping(NULL, 3); 231 irq_set_irq_type(gpio_virq, IRQ_TYPE_LEVEL_HIGH); 232 irq_set_chained_handler(gpio_virq, sb600_8259_cascade); 233 mpic_unmask_irq(irq_get_irq_data(gpio_virq)); 234 235 irq_set_default_host(mpic->irqhost); 236 } 237 238 #else 239 240 static inline void nemo_init_IRQ(struct mpic *mpic) 241 { 242 } 243 #endif 244 245 static __init void pas_init_IRQ(void) 246 { 247 struct device_node *np; 248 struct device_node *root, *mpic_node; 249 unsigned long openpic_addr; 250 const unsigned int *opprop; 251 int naddr, opplen; 252 int mpic_flags; 253 const unsigned int *nmiprop; 254 struct mpic *mpic; 255 256 mpic_node = NULL; 257 258 for_each_node_by_type(np, "interrupt-controller") 259 if (of_device_is_compatible(np, "open-pic")) { 260 mpic_node = np; 261 break; 262 } 263 if (!mpic_node) 264 for_each_node_by_type(np, "open-pic") { 265 mpic_node = np; 266 break; 267 } 268 if (!mpic_node) { 269 pr_err("Failed to locate the MPIC interrupt controller\n"); 270 return; 271 } 272 273 /* Find address list in /platform-open-pic */ 274 root = of_find_node_by_path("/"); 275 naddr = of_n_addr_cells(root); 276 opprop = of_get_property(root, "platform-open-pic", &opplen); 277 if (!opprop) { 278 pr_err("No platform-open-pic property.\n"); 279 of_node_put(root); 280 return; 281 } 282 openpic_addr = of_read_number(opprop, naddr); 283 pr_debug("OpenPIC addr: %lx\n", openpic_addr); 284 285 mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS | MPIC_NO_RESET; 286 287 nmiprop = of_get_property(mpic_node, "nmi-source", NULL); 288 if (nmiprop) 289 mpic_flags |= MPIC_ENABLE_MCK; 290 291 mpic = mpic_alloc(mpic_node, openpic_addr, 292 mpic_flags, 0, 0, "PASEMI-OPIC"); 293 BUG_ON(!mpic); 294 295 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000); 296 mpic_init(mpic); 297 /* The NMI/MCK source needs to be prio 15 */ 298 if (nmiprop) { 299 nmi_virq = irq_create_mapping(NULL, *nmiprop); 300 mpic_irq_set_priority(nmi_virq, 15); 301 irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); 302 mpic_unmask_irq(irq_get_irq_data(nmi_virq)); 303 } 304 305 nemo_init_IRQ(mpic); 306 307 of_node_put(mpic_node); 308 of_node_put(root); 309 } 310 311 static void __init pas_progress(char *s, unsigned short hex) 312 { 313 printk("[%04x] : %s\n", hex, s ? s : ""); 314 } 315 316 317 static int pas_machine_check_handler(struct pt_regs *regs) 318 { 319 int cpu = smp_processor_id(); 320 unsigned long srr0, srr1, dsisr; 321 int dump_slb = 0; 322 int i; 323 324 srr0 = regs->nip; 325 srr1 = regs->msr; 326 327 if (nmi_virq && mpic_get_mcirq() == nmi_virq) { 328 pr_err("NMI delivered\n"); 329 debugger(regs); 330 mpic_end_irq(irq_get_irq_data(nmi_virq)); 331 goto out; 332 } 333 334 dsisr = mfspr(SPRN_DSISR); 335 pr_err("Machine Check on CPU %d\n", cpu); 336 pr_err("SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1); 337 pr_err("DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar); 338 pr_err("BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER), 339 mfspr(SPRN_PA6T_MER)); 340 pr_err("IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER), 341 mfspr(SPRN_PA6T_DER)); 342 pr_err("Cause:\n"); 343 344 if (srr1 & 0x200000) 345 pr_err("Signalled by SDC\n"); 346 347 if (srr1 & 0x100000) { 348 pr_err("Load/Store detected error:\n"); 349 if (dsisr & 0x8000) 350 pr_err("D-cache ECC double-bit error or bus error\n"); 351 if (dsisr & 0x4000) 352 pr_err("LSU snoop response error\n"); 353 if (dsisr & 0x2000) { 354 pr_err("MMU SLB multi-hit or invalid B field\n"); 355 dump_slb = 1; 356 } 357 if (dsisr & 0x1000) 358 pr_err("Recoverable Duptags\n"); 359 if (dsisr & 0x800) 360 pr_err("Recoverable D-cache parity error count overflow\n"); 361 if (dsisr & 0x400) 362 pr_err("TLB parity error count overflow\n"); 363 } 364 365 if (srr1 & 0x80000) 366 pr_err("Bus Error\n"); 367 368 if (srr1 & 0x40000) { 369 pr_err("I-side SLB multiple hit\n"); 370 dump_slb = 1; 371 } 372 373 if (srr1 & 0x20000) 374 pr_err("I-cache parity error hit\n"); 375 376 if (num_mce_regs == 0) 377 pr_err("No MCE registers mapped yet, can't dump\n"); 378 else 379 pr_err("SoC debug registers:\n"); 380 381 for (i = 0; i < num_mce_regs; i++) 382 pr_err("%s: 0x%08x\n", mce_regs[i].name, 383 in_le32(mce_regs[i].addr)); 384 385 if (dump_slb) { 386 unsigned long e, v; 387 int i; 388 389 pr_err("slb contents:\n"); 390 for (i = 0; i < mmu_slb_size; i++) { 391 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i)); 392 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i)); 393 pr_err("%02d %016lx %016lx\n", i, e, v); 394 } 395 } 396 397 out: 398 /* SRR1[62] is from MSR[62] if recoverable, so pass that back */ 399 return !!(srr1 & 0x2); 400 } 401 402 static const struct of_device_id pasemi_bus_ids[] = { 403 /* Unfortunately needed for legacy firmwares */ 404 { .type = "localbus", }, 405 { .type = "sdc", }, 406 /* These are the proper entries, which newer firmware uses */ 407 { .compatible = "pasemi,localbus", }, 408 { .compatible = "pasemi,sdc", }, 409 {}, 410 }; 411 412 static int __init pasemi_publish_devices(void) 413 { 414 /* Publish OF platform devices for SDC and other non-PCI devices */ 415 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL); 416 417 nemo_init_rtc(); 418 419 return 0; 420 } 421 machine_device_initcall(pasemi, pasemi_publish_devices); 422 423 424 /* 425 * Called very early, MMU is off, device-tree isn't unflattened 426 */ 427 static int __init pas_probe(void) 428 { 429 if (!of_machine_is_compatible("PA6T-1682M") && 430 !of_machine_is_compatible("pasemi,pwrficient")) 431 return 0; 432 433 #ifdef CONFIG_PPC_PASEMI_NEMO 434 /* 435 * Check for the Nemo motherboard here, if we are running on one 436 * change the machine definition to fit 437 */ 438 if (of_machine_is_compatible("pasemi,nemo")) { 439 pm_power_off = pas_shutdown; 440 ppc_md.name = "A-EON Amigaone X1000"; 441 } 442 #endif 443 444 iommu_init_early_pasemi(); 445 446 return 1; 447 } 448 449 define_machine(pasemi) { 450 .name = "PA Semi PWRficient", 451 .probe = pas_probe, 452 .setup_arch = pas_setup_arch, 453 .init_IRQ = pas_init_IRQ, 454 .get_irq = mpic_get_irq, 455 .restart = pas_restart, 456 .get_boot_time = pas_get_boot_time, 457 .calibrate_decr = generic_calibrate_decr, 458 .progress = pas_progress, 459 .machine_check_exception = pas_machine_check_handler, 460 }; 461