1 /* 2 * Copyright (C) 2006-2007 PA Semi, Inc 3 * 4 * Authors: Kip Walker, PA Semi 5 * Olof Johansson, PA Semi 6 * 7 * Maintained by: Olof Johansson <olof@lixom.net> 8 * 9 * Based on arch/powerpc/platforms/maple/setup.c 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 */ 24 25 #include <linux/errno.h> 26 #include <linux/kernel.h> 27 #include <linux/delay.h> 28 #include <linux/console.h> 29 #include <linux/export.h> 30 #include <linux/pci.h> 31 #include <linux/of_platform.h> 32 #include <linux/gfp.h> 33 34 #include <asm/prom.h> 35 #include <asm/iommu.h> 36 #include <asm/machdep.h> 37 #include <asm/mpic.h> 38 #include <asm/smp.h> 39 #include <asm/time.h> 40 #include <asm/mmu.h> 41 #include <asm/debug.h> 42 43 #include <pcmcia/ss.h> 44 #include <pcmcia/cistpl.h> 45 #include <pcmcia/ds.h> 46 47 #include "pasemi.h" 48 49 /* SDC reset register, must be pre-mapped at reset time */ 50 static void __iomem *reset_reg; 51 52 /* Various error status registers, must be pre-mapped at MCE time */ 53 54 #define MAX_MCE_REGS 32 55 struct mce_regs { 56 char *name; 57 void __iomem *addr; 58 }; 59 60 static struct mce_regs mce_regs[MAX_MCE_REGS]; 61 static int num_mce_regs; 62 static int nmi_virq = 0; 63 64 65 static void __noreturn pas_restart(char *cmd) 66 { 67 /* Need to put others cpu in hold loop so they're not sleeping */ 68 smp_send_stop(); 69 udelay(10000); 70 printk("Restarting...\n"); 71 while (1) 72 out_le32(reset_reg, 0x6000000); 73 } 74 75 #ifdef CONFIG_SMP 76 static arch_spinlock_t timebase_lock; 77 static unsigned long timebase; 78 79 static void pas_give_timebase(void) 80 { 81 unsigned long flags; 82 83 local_irq_save(flags); 84 hard_irq_disable(); 85 arch_spin_lock(&timebase_lock); 86 mtspr(SPRN_TBCTL, TBCTL_FREEZE); 87 isync(); 88 timebase = get_tb(); 89 arch_spin_unlock(&timebase_lock); 90 91 while (timebase) 92 barrier(); 93 mtspr(SPRN_TBCTL, TBCTL_RESTART); 94 local_irq_restore(flags); 95 } 96 97 static void pas_take_timebase(void) 98 { 99 while (!timebase) 100 smp_rmb(); 101 102 arch_spin_lock(&timebase_lock); 103 set_tb(timebase >> 32, timebase & 0xffffffff); 104 timebase = 0; 105 arch_spin_unlock(&timebase_lock); 106 } 107 108 static struct smp_ops_t pas_smp_ops = { 109 .probe = smp_mpic_probe, 110 .message_pass = smp_mpic_message_pass, 111 .kick_cpu = smp_generic_kick_cpu, 112 .setup_cpu = smp_mpic_setup_cpu, 113 .give_timebase = pas_give_timebase, 114 .take_timebase = pas_take_timebase, 115 }; 116 #endif /* CONFIG_SMP */ 117 118 static void __init pas_setup_arch(void) 119 { 120 #ifdef CONFIG_SMP 121 /* Setup SMP callback */ 122 smp_ops = &pas_smp_ops; 123 #endif 124 /* Lookup PCI hosts */ 125 pas_pci_init(); 126 127 #ifdef CONFIG_DUMMY_CONSOLE 128 conswitchp = &dummy_con; 129 #endif 130 131 /* Remap SDC register for doing reset */ 132 /* XXXOJN This should maybe come out of the device tree */ 133 reset_reg = ioremap(0xfc101100, 4); 134 } 135 136 static int __init pas_setup_mce_regs(void) 137 { 138 struct pci_dev *dev; 139 int reg; 140 141 /* Remap various SoC status registers for use by the MCE handler */ 142 143 reg = 0; 144 145 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL); 146 while (dev && reg < MAX_MCE_REGS) { 147 mce_regs[reg].name = kasprintf(GFP_KERNEL, 148 "mc%d_mcdebug_errsta", reg); 149 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730); 150 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev); 151 reg++; 152 } 153 154 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); 155 if (dev && reg+4 < MAX_MCE_REGS) { 156 mce_regs[reg].name = "iobdbg_IntStatus1"; 157 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438); 158 reg++; 159 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg"; 160 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454); 161 reg++; 162 mce_regs[reg].name = "iobiom_IntStatus"; 163 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10); 164 reg++; 165 mce_regs[reg].name = "iobiom_IntDbgReg"; 166 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c); 167 reg++; 168 } 169 170 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL); 171 if (dev && reg+2 < MAX_MCE_REGS) { 172 mce_regs[reg].name = "l2csts_IntStatus"; 173 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200); 174 reg++; 175 mce_regs[reg].name = "l2csts_Cnt"; 176 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214); 177 reg++; 178 } 179 180 num_mce_regs = reg; 181 182 return 0; 183 } 184 machine_device_initcall(pasemi, pas_setup_mce_regs); 185 186 static __init void pas_init_IRQ(void) 187 { 188 struct device_node *np; 189 struct device_node *root, *mpic_node; 190 unsigned long openpic_addr; 191 const unsigned int *opprop; 192 int naddr, opplen; 193 int mpic_flags; 194 const unsigned int *nmiprop; 195 struct mpic *mpic; 196 197 mpic_node = NULL; 198 199 for_each_node_by_type(np, "interrupt-controller") 200 if (of_device_is_compatible(np, "open-pic")) { 201 mpic_node = np; 202 break; 203 } 204 if (!mpic_node) 205 for_each_node_by_type(np, "open-pic") { 206 mpic_node = np; 207 break; 208 } 209 if (!mpic_node) { 210 printk(KERN_ERR 211 "Failed to locate the MPIC interrupt controller\n"); 212 return; 213 } 214 215 /* Find address list in /platform-open-pic */ 216 root = of_find_node_by_path("/"); 217 naddr = of_n_addr_cells(root); 218 opprop = of_get_property(root, "platform-open-pic", &opplen); 219 if (!opprop) { 220 printk(KERN_ERR "No platform-open-pic property.\n"); 221 of_node_put(root); 222 return; 223 } 224 openpic_addr = of_read_number(opprop, naddr); 225 printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr); 226 227 mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS | MPIC_NO_RESET; 228 229 nmiprop = of_get_property(mpic_node, "nmi-source", NULL); 230 if (nmiprop) 231 mpic_flags |= MPIC_ENABLE_MCK; 232 233 mpic = mpic_alloc(mpic_node, openpic_addr, 234 mpic_flags, 0, 0, "PASEMI-OPIC"); 235 BUG_ON(!mpic); 236 237 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000); 238 mpic_init(mpic); 239 /* The NMI/MCK source needs to be prio 15 */ 240 if (nmiprop) { 241 nmi_virq = irq_create_mapping(NULL, *nmiprop); 242 mpic_irq_set_priority(nmi_virq, 15); 243 irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); 244 mpic_unmask_irq(irq_get_irq_data(nmi_virq)); 245 } 246 247 of_node_put(mpic_node); 248 of_node_put(root); 249 } 250 251 static void __init pas_progress(char *s, unsigned short hex) 252 { 253 printk("[%04x] : %s\n", hex, s ? s : ""); 254 } 255 256 257 static int pas_machine_check_handler(struct pt_regs *regs) 258 { 259 int cpu = smp_processor_id(); 260 unsigned long srr0, srr1, dsisr; 261 int dump_slb = 0; 262 int i; 263 264 srr0 = regs->nip; 265 srr1 = regs->msr; 266 267 if (nmi_virq && mpic_get_mcirq() == nmi_virq) { 268 printk(KERN_ERR "NMI delivered\n"); 269 debugger(regs); 270 mpic_end_irq(irq_get_irq_data(nmi_virq)); 271 goto out; 272 } 273 274 dsisr = mfspr(SPRN_DSISR); 275 printk(KERN_ERR "Machine Check on CPU %d\n", cpu); 276 printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1); 277 printk(KERN_ERR "DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar); 278 printk(KERN_ERR "BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER), 279 mfspr(SPRN_PA6T_MER)); 280 printk(KERN_ERR "IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER), 281 mfspr(SPRN_PA6T_DER)); 282 printk(KERN_ERR "Cause:\n"); 283 284 if (srr1 & 0x200000) 285 printk(KERN_ERR "Signalled by SDC\n"); 286 287 if (srr1 & 0x100000) { 288 printk(KERN_ERR "Load/Store detected error:\n"); 289 if (dsisr & 0x8000) 290 printk(KERN_ERR "D-cache ECC double-bit error or bus error\n"); 291 if (dsisr & 0x4000) 292 printk(KERN_ERR "LSU snoop response error\n"); 293 if (dsisr & 0x2000) { 294 printk(KERN_ERR "MMU SLB multi-hit or invalid B field\n"); 295 dump_slb = 1; 296 } 297 if (dsisr & 0x1000) 298 printk(KERN_ERR "Recoverable Duptags\n"); 299 if (dsisr & 0x800) 300 printk(KERN_ERR "Recoverable D-cache parity error count overflow\n"); 301 if (dsisr & 0x400) 302 printk(KERN_ERR "TLB parity error count overflow\n"); 303 } 304 305 if (srr1 & 0x80000) 306 printk(KERN_ERR "Bus Error\n"); 307 308 if (srr1 & 0x40000) { 309 printk(KERN_ERR "I-side SLB multiple hit\n"); 310 dump_slb = 1; 311 } 312 313 if (srr1 & 0x20000) 314 printk(KERN_ERR "I-cache parity error hit\n"); 315 316 if (num_mce_regs == 0) 317 printk(KERN_ERR "No MCE registers mapped yet, can't dump\n"); 318 else 319 printk(KERN_ERR "SoC debug registers:\n"); 320 321 for (i = 0; i < num_mce_regs; i++) 322 printk(KERN_ERR "%s: 0x%08x\n", mce_regs[i].name, 323 in_le32(mce_regs[i].addr)); 324 325 if (dump_slb) { 326 unsigned long e, v; 327 int i; 328 329 printk(KERN_ERR "slb contents:\n"); 330 for (i = 0; i < mmu_slb_size; i++) { 331 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i)); 332 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i)); 333 printk(KERN_ERR "%02d %016lx %016lx\n", i, e, v); 334 } 335 } 336 337 out: 338 /* SRR1[62] is from MSR[62] if recoverable, so pass that back */ 339 return !!(srr1 & 0x2); 340 } 341 342 #ifdef CONFIG_PCMCIA 343 static int pcmcia_notify(struct notifier_block *nb, unsigned long action, 344 void *data) 345 { 346 struct device *dev = data; 347 struct device *parent; 348 struct pcmcia_device *pdev = to_pcmcia_dev(dev); 349 350 /* We are only intereted in device addition */ 351 if (action != BUS_NOTIFY_ADD_DEVICE) 352 return 0; 353 354 parent = pdev->socket->dev.parent; 355 356 /* We know electra_cf devices will always have of_node set, since 357 * electra_cf is an of_platform driver. 358 */ 359 if (!parent->of_node) 360 return 0; 361 362 if (!of_device_is_compatible(parent->of_node, "electra-cf")) 363 return 0; 364 365 /* We use the direct ops for localbus */ 366 dev->dma_ops = &dma_nommu_ops; 367 368 return 0; 369 } 370 371 static struct notifier_block pcmcia_notifier = { 372 .notifier_call = pcmcia_notify, 373 }; 374 375 static inline void pasemi_pcmcia_init(void) 376 { 377 extern struct bus_type pcmcia_bus_type; 378 379 bus_register_notifier(&pcmcia_bus_type, &pcmcia_notifier); 380 } 381 382 #else 383 384 static inline void pasemi_pcmcia_init(void) 385 { 386 } 387 388 #endif 389 390 391 static const struct of_device_id pasemi_bus_ids[] = { 392 /* Unfortunately needed for legacy firmwares */ 393 { .type = "localbus", }, 394 { .type = "sdc", }, 395 /* These are the proper entries, which newer firmware uses */ 396 { .compatible = "pasemi,localbus", }, 397 { .compatible = "pasemi,sdc", }, 398 {}, 399 }; 400 401 static int __init pasemi_publish_devices(void) 402 { 403 pasemi_pcmcia_init(); 404 405 /* Publish OF platform devices for SDC and other non-PCI devices */ 406 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL); 407 408 return 0; 409 } 410 machine_device_initcall(pasemi, pasemi_publish_devices); 411 412 413 /* 414 * Called very early, MMU is off, device-tree isn't unflattened 415 */ 416 static int __init pas_probe(void) 417 { 418 if (!of_machine_is_compatible("PA6T-1682M") && 419 !of_machine_is_compatible("pasemi,pwrficient")) 420 return 0; 421 422 iommu_init_early_pasemi(); 423 424 return 1; 425 } 426 427 define_machine(pasemi) { 428 .name = "PA Semi PWRficient", 429 .probe = pas_probe, 430 .setup_arch = pas_setup_arch, 431 .init_IRQ = pas_init_IRQ, 432 .get_irq = mpic_get_irq, 433 .restart = pas_restart, 434 .get_boot_time = pas_get_boot_time, 435 .calibrate_decr = generic_calibrate_decr, 436 .progress = pas_progress, 437 .machine_check_exception = pas_machine_check_handler, 438 }; 439