1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2006-2007 PA Semi, Inc 4 * 5 * Authors: Kip Walker, PA Semi 6 * Olof Johansson, PA Semi 7 * 8 * Maintained by: Olof Johansson <olof@lixom.net> 9 * 10 * Based on arch/powerpc/platforms/maple/setup.c 11 */ 12 13 #include <linux/errno.h> 14 #include <linux/kernel.h> 15 #include <linux/delay.h> 16 #include <linux/console.h> 17 #include <linux/export.h> 18 #include <linux/pci.h> 19 #include <linux/of.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/gfp.h> 23 #include <linux/irqdomain.h> 24 25 #include <asm/iommu.h> 26 #include <asm/machdep.h> 27 #include <asm/i8259.h> 28 #include <asm/mpic.h> 29 #include <asm/smp.h> 30 #include <asm/time.h> 31 #include <asm/mmu.h> 32 #include <asm/debug.h> 33 34 #include <pcmcia/ss.h> 35 #include <pcmcia/cistpl.h> 36 #include <pcmcia/ds.h> 37 38 #include "pasemi.h" 39 40 /* SDC reset register, must be pre-mapped at reset time */ 41 static void __iomem *reset_reg; 42 43 /* Various error status registers, must be pre-mapped at MCE time */ 44 45 #define MAX_MCE_REGS 32 46 struct mce_regs { 47 char *name; 48 void __iomem *addr; 49 }; 50 51 static struct mce_regs mce_regs[MAX_MCE_REGS]; 52 static int num_mce_regs; 53 static int nmi_virq = 0; 54 55 56 static void __noreturn pas_restart(char *cmd) 57 { 58 /* Need to put others cpu in hold loop so they're not sleeping */ 59 smp_send_stop(); 60 udelay(10000); 61 printk("Restarting...\n"); 62 while (1) 63 out_le32(reset_reg, 0x6000000); 64 } 65 66 #ifdef CONFIG_PPC_PASEMI_NEMO 67 void pas_shutdown(void) 68 { 69 /* Set the PLD bit that makes the SB600 think the power button is being pressed */ 70 void __iomem *pld_map = ioremap(0xf5000000,4096); 71 while (1) 72 out_8(pld_map+7,0x01); 73 } 74 75 /* RTC platform device structure as is not in device tree */ 76 static struct resource rtc_resource[] = {{ 77 .name = "rtc", 78 .start = 0x70, 79 .end = 0x71, 80 .flags = IORESOURCE_IO, 81 }, { 82 .name = "rtc", 83 .start = 8, 84 .end = 8, 85 .flags = IORESOURCE_IRQ, 86 }}; 87 88 static inline void nemo_init_rtc(void) 89 { 90 platform_device_register_simple("rtc_cmos", -1, rtc_resource, 2); 91 } 92 93 #else 94 95 static inline void nemo_init_rtc(void) 96 { 97 } 98 #endif 99 100 #ifdef CONFIG_SMP 101 static arch_spinlock_t timebase_lock; 102 static unsigned long timebase; 103 104 static void pas_give_timebase(void) 105 { 106 unsigned long flags; 107 108 local_irq_save(flags); 109 hard_irq_disable(); 110 arch_spin_lock(&timebase_lock); 111 mtspr(SPRN_TBCTL, TBCTL_FREEZE); 112 isync(); 113 timebase = get_tb(); 114 arch_spin_unlock(&timebase_lock); 115 116 while (timebase) 117 barrier(); 118 mtspr(SPRN_TBCTL, TBCTL_RESTART); 119 local_irq_restore(flags); 120 } 121 122 static void pas_take_timebase(void) 123 { 124 while (!timebase) 125 smp_rmb(); 126 127 arch_spin_lock(&timebase_lock); 128 set_tb(timebase >> 32, timebase & 0xffffffff); 129 timebase = 0; 130 arch_spin_unlock(&timebase_lock); 131 } 132 133 static struct smp_ops_t pas_smp_ops = { 134 .probe = smp_mpic_probe, 135 .message_pass = smp_mpic_message_pass, 136 .kick_cpu = smp_generic_kick_cpu, 137 .setup_cpu = smp_mpic_setup_cpu, 138 .give_timebase = pas_give_timebase, 139 .take_timebase = pas_take_timebase, 140 }; 141 #endif /* CONFIG_SMP */ 142 143 static void __init pas_setup_arch(void) 144 { 145 #ifdef CONFIG_SMP 146 /* Setup SMP callback */ 147 smp_ops = &pas_smp_ops; 148 #endif 149 150 /* Remap SDC register for doing reset */ 151 /* XXXOJN This should maybe come out of the device tree */ 152 reset_reg = ioremap(0xfc101100, 4); 153 } 154 155 static int __init pas_setup_mce_regs(void) 156 { 157 struct pci_dev *dev; 158 int reg; 159 160 /* Remap various SoC status registers for use by the MCE handler */ 161 162 reg = 0; 163 164 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL); 165 while (dev && reg < MAX_MCE_REGS) { 166 mce_regs[reg].name = kasprintf(GFP_KERNEL, 167 "mc%d_mcdebug_errsta", reg); 168 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730); 169 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev); 170 reg++; 171 } 172 173 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); 174 if (dev && reg+4 < MAX_MCE_REGS) { 175 mce_regs[reg].name = "iobdbg_IntStatus1"; 176 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438); 177 reg++; 178 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg"; 179 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454); 180 reg++; 181 mce_regs[reg].name = "iobiom_IntStatus"; 182 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10); 183 reg++; 184 mce_regs[reg].name = "iobiom_IntDbgReg"; 185 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c); 186 reg++; 187 } 188 189 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL); 190 if (dev && reg+2 < MAX_MCE_REGS) { 191 mce_regs[reg].name = "l2csts_IntStatus"; 192 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200); 193 reg++; 194 mce_regs[reg].name = "l2csts_Cnt"; 195 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214); 196 reg++; 197 } 198 199 num_mce_regs = reg; 200 201 return 0; 202 } 203 machine_device_initcall(pasemi, pas_setup_mce_regs); 204 205 #ifdef CONFIG_PPC_PASEMI_NEMO 206 static void sb600_8259_cascade(struct irq_desc *desc) 207 { 208 struct irq_chip *chip = irq_desc_get_chip(desc); 209 unsigned int cascade_irq = i8259_irq(); 210 211 if (cascade_irq) 212 generic_handle_irq(cascade_irq); 213 214 chip->irq_eoi(&desc->irq_data); 215 } 216 217 static void __init nemo_init_IRQ(struct mpic *mpic) 218 { 219 struct device_node *np; 220 int gpio_virq; 221 /* Connect the SB600's legacy i8259 controller */ 222 np = of_find_node_by_path("/pxp@0,e0000000"); 223 i8259_init(np, 0); 224 of_node_put(np); 225 226 gpio_virq = irq_create_mapping(NULL, 3); 227 irq_set_irq_type(gpio_virq, IRQ_TYPE_LEVEL_HIGH); 228 irq_set_chained_handler(gpio_virq, sb600_8259_cascade); 229 mpic_unmask_irq(irq_get_irq_data(gpio_virq)); 230 231 irq_set_default_host(mpic->irqhost); 232 } 233 234 #else 235 236 static inline void nemo_init_IRQ(struct mpic *mpic) 237 { 238 } 239 #endif 240 241 static __init void pas_init_IRQ(void) 242 { 243 struct device_node *np; 244 struct device_node *root, *mpic_node; 245 unsigned long openpic_addr; 246 const unsigned int *opprop; 247 int naddr, opplen; 248 int mpic_flags; 249 const unsigned int *nmiprop; 250 struct mpic *mpic; 251 252 mpic_node = NULL; 253 254 for_each_node_by_type(np, "interrupt-controller") 255 if (of_device_is_compatible(np, "open-pic")) { 256 mpic_node = np; 257 break; 258 } 259 if (!mpic_node) 260 for_each_node_by_type(np, "open-pic") { 261 mpic_node = np; 262 break; 263 } 264 if (!mpic_node) { 265 pr_err("Failed to locate the MPIC interrupt controller\n"); 266 return; 267 } 268 269 /* Find address list in /platform-open-pic */ 270 root = of_find_node_by_path("/"); 271 naddr = of_n_addr_cells(root); 272 opprop = of_get_property(root, "platform-open-pic", &opplen); 273 if (!opprop) { 274 pr_err("No platform-open-pic property.\n"); 275 of_node_put(root); 276 return; 277 } 278 openpic_addr = of_read_number(opprop, naddr); 279 pr_debug("OpenPIC addr: %lx\n", openpic_addr); 280 281 mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS | MPIC_NO_RESET; 282 283 nmiprop = of_get_property(mpic_node, "nmi-source", NULL); 284 if (nmiprop) 285 mpic_flags |= MPIC_ENABLE_MCK; 286 287 mpic = mpic_alloc(mpic_node, openpic_addr, 288 mpic_flags, 0, 0, "PASEMI-OPIC"); 289 BUG_ON(!mpic); 290 291 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000); 292 mpic_init(mpic); 293 /* The NMI/MCK source needs to be prio 15 */ 294 if (nmiprop) { 295 nmi_virq = irq_create_mapping(NULL, *nmiprop); 296 mpic_irq_set_priority(nmi_virq, 15); 297 irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); 298 mpic_unmask_irq(irq_get_irq_data(nmi_virq)); 299 } 300 301 nemo_init_IRQ(mpic); 302 303 of_node_put(mpic_node); 304 of_node_put(root); 305 } 306 307 static void __init pas_progress(char *s, unsigned short hex) 308 { 309 printk("[%04x] : %s\n", hex, s ? s : ""); 310 } 311 312 313 static int pas_machine_check_handler(struct pt_regs *regs) 314 { 315 int cpu = smp_processor_id(); 316 unsigned long srr0, srr1, dsisr; 317 int dump_slb = 0; 318 int i; 319 320 srr0 = regs->nip; 321 srr1 = regs->msr; 322 323 if (nmi_virq && mpic_get_mcirq() == nmi_virq) { 324 pr_err("NMI delivered\n"); 325 debugger(regs); 326 mpic_end_irq(irq_get_irq_data(nmi_virq)); 327 goto out; 328 } 329 330 dsisr = mfspr(SPRN_DSISR); 331 pr_err("Machine Check on CPU %d\n", cpu); 332 pr_err("SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1); 333 pr_err("DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar); 334 pr_err("BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER), 335 mfspr(SPRN_PA6T_MER)); 336 pr_err("IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER), 337 mfspr(SPRN_PA6T_DER)); 338 pr_err("Cause:\n"); 339 340 if (srr1 & 0x200000) 341 pr_err("Signalled by SDC\n"); 342 343 if (srr1 & 0x100000) { 344 pr_err("Load/Store detected error:\n"); 345 if (dsisr & 0x8000) 346 pr_err("D-cache ECC double-bit error or bus error\n"); 347 if (dsisr & 0x4000) 348 pr_err("LSU snoop response error\n"); 349 if (dsisr & 0x2000) { 350 pr_err("MMU SLB multi-hit or invalid B field\n"); 351 dump_slb = 1; 352 } 353 if (dsisr & 0x1000) 354 pr_err("Recoverable Duptags\n"); 355 if (dsisr & 0x800) 356 pr_err("Recoverable D-cache parity error count overflow\n"); 357 if (dsisr & 0x400) 358 pr_err("TLB parity error count overflow\n"); 359 } 360 361 if (srr1 & 0x80000) 362 pr_err("Bus Error\n"); 363 364 if (srr1 & 0x40000) { 365 pr_err("I-side SLB multiple hit\n"); 366 dump_slb = 1; 367 } 368 369 if (srr1 & 0x20000) 370 pr_err("I-cache parity error hit\n"); 371 372 if (num_mce_regs == 0) 373 pr_err("No MCE registers mapped yet, can't dump\n"); 374 else 375 pr_err("SoC debug registers:\n"); 376 377 for (i = 0; i < num_mce_regs; i++) 378 pr_err("%s: 0x%08x\n", mce_regs[i].name, 379 in_le32(mce_regs[i].addr)); 380 381 if (dump_slb) { 382 unsigned long e, v; 383 int i; 384 385 pr_err("slb contents:\n"); 386 for (i = 0; i < mmu_slb_size; i++) { 387 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i)); 388 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i)); 389 pr_err("%02d %016lx %016lx\n", i, e, v); 390 } 391 } 392 393 out: 394 /* SRR1[62] is from MSR[62] if recoverable, so pass that back */ 395 return !!(srr1 & 0x2); 396 } 397 398 static const struct of_device_id pasemi_bus_ids[] = { 399 /* Unfortunately needed for legacy firmwares */ 400 { .type = "localbus", }, 401 { .type = "sdc", }, 402 /* These are the proper entries, which newer firmware uses */ 403 { .compatible = "pasemi,localbus", }, 404 { .compatible = "pasemi,sdc", }, 405 {}, 406 }; 407 408 static int __init pasemi_publish_devices(void) 409 { 410 /* Publish OF platform devices for SDC and other non-PCI devices */ 411 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL); 412 413 nemo_init_rtc(); 414 415 return 0; 416 } 417 machine_device_initcall(pasemi, pasemi_publish_devices); 418 419 420 /* 421 * Called very early, MMU is off, device-tree isn't unflattened 422 */ 423 static int __init pas_probe(void) 424 { 425 if (!of_machine_is_compatible("PA6T-1682M") && 426 !of_machine_is_compatible("pasemi,pwrficient")) 427 return 0; 428 429 #ifdef CONFIG_PPC_PASEMI_NEMO 430 /* 431 * Check for the Nemo motherboard here, if we are running on one 432 * change the machine definition to fit 433 */ 434 if (of_machine_is_compatible("pasemi,nemo")) { 435 pm_power_off = pas_shutdown; 436 ppc_md.name = "A-EON Amigaone X1000"; 437 } 438 #endif 439 440 iommu_init_early_pasemi(); 441 442 return 1; 443 } 444 445 define_machine(pasemi) { 446 .name = "PA Semi PWRficient", 447 .probe = pas_probe, 448 .setup_arch = pas_setup_arch, 449 .discover_phbs = pas_pci_init, 450 .init_IRQ = pas_init_IRQ, 451 .get_irq = mpic_get_irq, 452 .restart = pas_restart, 453 .get_boot_time = pas_get_boot_time, 454 .progress = pas_progress, 455 .machine_check_exception = pas_machine_check_handler, 456 }; 457