1 /* 2 * Copyright (C) 2006-2007 PA Semi, Inc 3 * 4 * Authors: Kip Walker, PA Semi 5 * Olof Johansson, PA Semi 6 * 7 * Maintained by: Olof Johansson <olof@lixom.net> 8 * 9 * Based on arch/powerpc/platforms/maple/setup.c 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 */ 24 25 #include <linux/errno.h> 26 #include <linux/kernel.h> 27 #include <linux/delay.h> 28 #include <linux/console.h> 29 #include <linux/export.h> 30 #include <linux/pci.h> 31 #include <linux/of_platform.h> 32 #include <linux/gfp.h> 33 34 #include <asm/prom.h> 35 #include <asm/iommu.h> 36 #include <asm/machdep.h> 37 #include <asm/i8259.h> 38 #include <asm/mpic.h> 39 #include <asm/smp.h> 40 #include <asm/time.h> 41 #include <asm/mmu.h> 42 #include <asm/debug.h> 43 44 #include <pcmcia/ss.h> 45 #include <pcmcia/cistpl.h> 46 #include <pcmcia/ds.h> 47 48 #include "pasemi.h" 49 50 /* SDC reset register, must be pre-mapped at reset time */ 51 static void __iomem *reset_reg; 52 53 /* Various error status registers, must be pre-mapped at MCE time */ 54 55 #define MAX_MCE_REGS 32 56 struct mce_regs { 57 char *name; 58 void __iomem *addr; 59 }; 60 61 static struct mce_regs mce_regs[MAX_MCE_REGS]; 62 static int num_mce_regs; 63 static int nmi_virq = 0; 64 65 66 static void __noreturn pas_restart(char *cmd) 67 { 68 /* Need to put others cpu in hold loop so they're not sleeping */ 69 smp_send_stop(); 70 udelay(10000); 71 printk("Restarting...\n"); 72 while (1) 73 out_le32(reset_reg, 0x6000000); 74 } 75 76 #ifdef CONFIG_PPC_PASEMI_NEMO 77 void pas_shutdown(void) 78 { 79 /* Set the PLD bit that makes the SB600 think the power button is being pressed */ 80 void __iomem *pld_map = ioremap(0xf5000000,4096); 81 while (1) 82 out_8(pld_map+7,0x01); 83 } 84 85 /* RTC platform device structure as is not in device tree */ 86 static struct resource rtc_resource[] = {{ 87 .name = "rtc", 88 .start = 0x70, 89 .end = 0x71, 90 .flags = IORESOURCE_IO, 91 }, { 92 .name = "rtc", 93 .start = 8, 94 .end = 8, 95 .flags = IORESOURCE_IRQ, 96 }}; 97 98 static inline void nemo_init_rtc(void) 99 { 100 platform_device_register_simple("rtc_cmos", -1, rtc_resource, 2); 101 } 102 103 #else 104 105 static inline void nemo_init_rtc(void) 106 { 107 } 108 #endif 109 110 #ifdef CONFIG_SMP 111 static arch_spinlock_t timebase_lock; 112 static unsigned long timebase; 113 114 static void pas_give_timebase(void) 115 { 116 unsigned long flags; 117 118 local_irq_save(flags); 119 hard_irq_disable(); 120 arch_spin_lock(&timebase_lock); 121 mtspr(SPRN_TBCTL, TBCTL_FREEZE); 122 isync(); 123 timebase = get_tb(); 124 arch_spin_unlock(&timebase_lock); 125 126 while (timebase) 127 barrier(); 128 mtspr(SPRN_TBCTL, TBCTL_RESTART); 129 local_irq_restore(flags); 130 } 131 132 static void pas_take_timebase(void) 133 { 134 while (!timebase) 135 smp_rmb(); 136 137 arch_spin_lock(&timebase_lock); 138 set_tb(timebase >> 32, timebase & 0xffffffff); 139 timebase = 0; 140 arch_spin_unlock(&timebase_lock); 141 } 142 143 static struct smp_ops_t pas_smp_ops = { 144 .probe = smp_mpic_probe, 145 .message_pass = smp_mpic_message_pass, 146 .kick_cpu = smp_generic_kick_cpu, 147 .setup_cpu = smp_mpic_setup_cpu, 148 .give_timebase = pas_give_timebase, 149 .take_timebase = pas_take_timebase, 150 }; 151 #endif /* CONFIG_SMP */ 152 153 static void __init pas_setup_arch(void) 154 { 155 #ifdef CONFIG_SMP 156 /* Setup SMP callback */ 157 smp_ops = &pas_smp_ops; 158 #endif 159 /* Lookup PCI hosts */ 160 pas_pci_init(); 161 162 #ifdef CONFIG_DUMMY_CONSOLE 163 conswitchp = &dummy_con; 164 #endif 165 166 /* Remap SDC register for doing reset */ 167 /* XXXOJN This should maybe come out of the device tree */ 168 reset_reg = ioremap(0xfc101100, 4); 169 } 170 171 static int __init pas_setup_mce_regs(void) 172 { 173 struct pci_dev *dev; 174 int reg; 175 176 /* Remap various SoC status registers for use by the MCE handler */ 177 178 reg = 0; 179 180 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, NULL); 181 while (dev && reg < MAX_MCE_REGS) { 182 mce_regs[reg].name = kasprintf(GFP_KERNEL, 183 "mc%d_mcdebug_errsta", reg); 184 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x730); 185 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa00a, dev); 186 reg++; 187 } 188 189 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); 190 if (dev && reg+4 < MAX_MCE_REGS) { 191 mce_regs[reg].name = "iobdbg_IntStatus1"; 192 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x438); 193 reg++; 194 mce_regs[reg].name = "iobdbg_IOCTbusIntDbgReg"; 195 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x454); 196 reg++; 197 mce_regs[reg].name = "iobiom_IntStatus"; 198 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc10); 199 reg++; 200 mce_regs[reg].name = "iobiom_IntDbgReg"; 201 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0xc1c); 202 reg++; 203 } 204 205 dev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa009, NULL); 206 if (dev && reg+2 < MAX_MCE_REGS) { 207 mce_regs[reg].name = "l2csts_IntStatus"; 208 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x200); 209 reg++; 210 mce_regs[reg].name = "l2csts_Cnt"; 211 mce_regs[reg].addr = pasemi_pci_getcfgaddr(dev, 0x214); 212 reg++; 213 } 214 215 num_mce_regs = reg; 216 217 return 0; 218 } 219 machine_device_initcall(pasemi, pas_setup_mce_regs); 220 221 #ifdef CONFIG_PPC_PASEMI_NEMO 222 static void sb600_8259_cascade(struct irq_desc *desc) 223 { 224 struct irq_chip *chip = irq_desc_get_chip(desc); 225 unsigned int cascade_irq = i8259_irq(); 226 227 if (cascade_irq) 228 generic_handle_irq(cascade_irq); 229 230 chip->irq_eoi(&desc->irq_data); 231 } 232 233 static void nemo_init_IRQ(struct mpic *mpic) 234 { 235 struct device_node *np; 236 int gpio_virq; 237 /* Connect the SB600's legacy i8259 controller */ 238 np = of_find_node_by_path("/pxp@0,e0000000"); 239 i8259_init(np, 0); 240 of_node_put(np); 241 242 gpio_virq = irq_create_mapping(NULL, 3); 243 irq_set_irq_type(gpio_virq, IRQ_TYPE_LEVEL_HIGH); 244 irq_set_chained_handler(gpio_virq, sb600_8259_cascade); 245 mpic_unmask_irq(irq_get_irq_data(gpio_virq)); 246 247 irq_set_default_host(mpic->irqhost); 248 } 249 250 #else 251 252 static inline void nemo_init_IRQ(struct mpic *mpic) 253 { 254 } 255 #endif 256 257 static __init void pas_init_IRQ(void) 258 { 259 struct device_node *np; 260 struct device_node *root, *mpic_node; 261 unsigned long openpic_addr; 262 const unsigned int *opprop; 263 int naddr, opplen; 264 int mpic_flags; 265 const unsigned int *nmiprop; 266 struct mpic *mpic; 267 268 mpic_node = NULL; 269 270 for_each_node_by_type(np, "interrupt-controller") 271 if (of_device_is_compatible(np, "open-pic")) { 272 mpic_node = np; 273 break; 274 } 275 if (!mpic_node) 276 for_each_node_by_type(np, "open-pic") { 277 mpic_node = np; 278 break; 279 } 280 if (!mpic_node) { 281 pr_err("Failed to locate the MPIC interrupt controller\n"); 282 return; 283 } 284 285 /* Find address list in /platform-open-pic */ 286 root = of_find_node_by_path("/"); 287 naddr = of_n_addr_cells(root); 288 opprop = of_get_property(root, "platform-open-pic", &opplen); 289 if (!opprop) { 290 pr_err("No platform-open-pic property.\n"); 291 of_node_put(root); 292 return; 293 } 294 openpic_addr = of_read_number(opprop, naddr); 295 pr_debug("OpenPIC addr: %lx\n", openpic_addr); 296 297 mpic_flags = MPIC_LARGE_VECTORS | MPIC_NO_BIAS | MPIC_NO_RESET; 298 299 nmiprop = of_get_property(mpic_node, "nmi-source", NULL); 300 if (nmiprop) 301 mpic_flags |= MPIC_ENABLE_MCK; 302 303 mpic = mpic_alloc(mpic_node, openpic_addr, 304 mpic_flags, 0, 0, "PASEMI-OPIC"); 305 BUG_ON(!mpic); 306 307 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10000); 308 mpic_init(mpic); 309 /* The NMI/MCK source needs to be prio 15 */ 310 if (nmiprop) { 311 nmi_virq = irq_create_mapping(NULL, *nmiprop); 312 mpic_irq_set_priority(nmi_virq, 15); 313 irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING); 314 mpic_unmask_irq(irq_get_irq_data(nmi_virq)); 315 } 316 317 nemo_init_IRQ(mpic); 318 319 of_node_put(mpic_node); 320 of_node_put(root); 321 } 322 323 static void __init pas_progress(char *s, unsigned short hex) 324 { 325 printk("[%04x] : %s\n", hex, s ? s : ""); 326 } 327 328 329 static int pas_machine_check_handler(struct pt_regs *regs) 330 { 331 int cpu = smp_processor_id(); 332 unsigned long srr0, srr1, dsisr; 333 int dump_slb = 0; 334 int i; 335 336 srr0 = regs->nip; 337 srr1 = regs->msr; 338 339 if (nmi_virq && mpic_get_mcirq() == nmi_virq) { 340 pr_err("NMI delivered\n"); 341 debugger(regs); 342 mpic_end_irq(irq_get_irq_data(nmi_virq)); 343 goto out; 344 } 345 346 dsisr = mfspr(SPRN_DSISR); 347 pr_err("Machine Check on CPU %d\n", cpu); 348 pr_err("SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1); 349 pr_err("DSISR 0x%016lx DAR 0x%016lx\n", dsisr, regs->dar); 350 pr_err("BER 0x%016lx MER 0x%016lx\n", mfspr(SPRN_PA6T_BER), 351 mfspr(SPRN_PA6T_MER)); 352 pr_err("IER 0x%016lx DER 0x%016lx\n", mfspr(SPRN_PA6T_IER), 353 mfspr(SPRN_PA6T_DER)); 354 pr_err("Cause:\n"); 355 356 if (srr1 & 0x200000) 357 pr_err("Signalled by SDC\n"); 358 359 if (srr1 & 0x100000) { 360 pr_err("Load/Store detected error:\n"); 361 if (dsisr & 0x8000) 362 pr_err("D-cache ECC double-bit error or bus error\n"); 363 if (dsisr & 0x4000) 364 pr_err("LSU snoop response error\n"); 365 if (dsisr & 0x2000) { 366 pr_err("MMU SLB multi-hit or invalid B field\n"); 367 dump_slb = 1; 368 } 369 if (dsisr & 0x1000) 370 pr_err("Recoverable Duptags\n"); 371 if (dsisr & 0x800) 372 pr_err("Recoverable D-cache parity error count overflow\n"); 373 if (dsisr & 0x400) 374 pr_err("TLB parity error count overflow\n"); 375 } 376 377 if (srr1 & 0x80000) 378 pr_err("Bus Error\n"); 379 380 if (srr1 & 0x40000) { 381 pr_err("I-side SLB multiple hit\n"); 382 dump_slb = 1; 383 } 384 385 if (srr1 & 0x20000) 386 pr_err("I-cache parity error hit\n"); 387 388 if (num_mce_regs == 0) 389 pr_err("No MCE registers mapped yet, can't dump\n"); 390 else 391 pr_err("SoC debug registers:\n"); 392 393 for (i = 0; i < num_mce_regs; i++) 394 pr_err("%s: 0x%08x\n", mce_regs[i].name, 395 in_le32(mce_regs[i].addr)); 396 397 if (dump_slb) { 398 unsigned long e, v; 399 int i; 400 401 pr_err("slb contents:\n"); 402 for (i = 0; i < mmu_slb_size; i++) { 403 asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i)); 404 asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i)); 405 pr_err("%02d %016lx %016lx\n", i, e, v); 406 } 407 } 408 409 out: 410 /* SRR1[62] is from MSR[62] if recoverable, so pass that back */ 411 return !!(srr1 & 0x2); 412 } 413 414 static const struct of_device_id pasemi_bus_ids[] = { 415 /* Unfortunately needed for legacy firmwares */ 416 { .type = "localbus", }, 417 { .type = "sdc", }, 418 /* These are the proper entries, which newer firmware uses */ 419 { .compatible = "pasemi,localbus", }, 420 { .compatible = "pasemi,sdc", }, 421 {}, 422 }; 423 424 static int __init pasemi_publish_devices(void) 425 { 426 /* Publish OF platform devices for SDC and other non-PCI devices */ 427 of_platform_bus_probe(NULL, pasemi_bus_ids, NULL); 428 429 nemo_init_rtc(); 430 431 return 0; 432 } 433 machine_device_initcall(pasemi, pasemi_publish_devices); 434 435 436 /* 437 * Called very early, MMU is off, device-tree isn't unflattened 438 */ 439 static int __init pas_probe(void) 440 { 441 if (!of_machine_is_compatible("PA6T-1682M") && 442 !of_machine_is_compatible("pasemi,pwrficient")) 443 return 0; 444 445 #ifdef CONFIG_PPC_PASEMI_NEMO 446 /* 447 * Check for the Nemo motherboard here, if we are running on one 448 * change the machine definition to fit 449 */ 450 if (of_machine_is_compatible("pasemi,nemo")) { 451 pm_power_off = pas_shutdown; 452 ppc_md.name = "A-EON Amigaone X1000"; 453 } 454 #endif 455 456 iommu_init_early_pasemi(); 457 458 return 1; 459 } 460 461 define_machine(pasemi) { 462 .name = "PA Semi PWRficient", 463 .probe = pas_probe, 464 .setup_arch = pas_setup_arch, 465 .init_IRQ = pas_init_IRQ, 466 .get_irq = mpic_get_irq, 467 .restart = pas_restart, 468 .get_boot_time = pas_get_boot_time, 469 .calibrate_decr = generic_calibrate_decr, 470 .progress = pas_progress, 471 .machine_check_exception = pas_machine_check_handler, 472 }; 473