1 /* 2 * Copyright 2007, Olof Johansson, PA Semi 3 * 4 * Based on arch/powerpc/sysdev/mpic_u3msi.c: 5 * 6 * Copyright 2006, Segher Boessenkool, IBM Corporation. 7 * Copyright 2006-2007, Michael Ellerman, IBM Corporation. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; version 2 of the 12 * License. 13 * 14 */ 15 16 #include <linux/irq.h> 17 #include <linux/msi.h> 18 #include <asm/mpic.h> 19 #include <asm/prom.h> 20 #include <asm/hw_irq.h> 21 #include <asm/ppc-pci.h> 22 #include <asm/msi_bitmap.h> 23 24 #include <sysdev/mpic.h> 25 26 /* Allocate 16 interrupts per device, to give an alignment of 16, 27 * since that's the size of the grouping w.r.t. affinity. If someone 28 * needs more than 32 MSI's down the road we'll have to rethink this, 29 * but it should be OK for now. 30 */ 31 #define ALLOC_CHUNK 16 32 33 #define PASEMI_MSI_ADDR 0xfc080000 34 35 /* A bit ugly, can we get this from the pci_dev somehow? */ 36 static struct mpic *msi_mpic; 37 38 39 static void mpic_pasemi_msi_mask_irq(struct irq_data *data) 40 { 41 pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq); 42 pci_msi_mask_irq(data); 43 mpic_mask_irq(data); 44 } 45 46 static void mpic_pasemi_msi_unmask_irq(struct irq_data *data) 47 { 48 pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq); 49 mpic_unmask_irq(data); 50 pci_msi_unmask_irq(data); 51 } 52 53 static struct irq_chip mpic_pasemi_msi_chip = { 54 .irq_shutdown = mpic_pasemi_msi_mask_irq, 55 .irq_mask = mpic_pasemi_msi_mask_irq, 56 .irq_unmask = mpic_pasemi_msi_unmask_irq, 57 .irq_eoi = mpic_end_irq, 58 .irq_set_type = mpic_set_irq_type, 59 .irq_set_affinity = mpic_set_affinity, 60 .name = "PASEMI-MSI", 61 }; 62 63 static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev) 64 { 65 struct msi_desc *entry; 66 67 pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev); 68 69 list_for_each_entry(entry, &pdev->msi_list, list) { 70 if (entry->irq == NO_IRQ) 71 continue; 72 73 irq_set_msi_desc(entry->irq, NULL); 74 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, 75 virq_to_hw(entry->irq), ALLOC_CHUNK); 76 irq_dispose_mapping(entry->irq); 77 } 78 79 return; 80 } 81 82 static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type) 83 { 84 unsigned int virq; 85 struct msi_desc *entry; 86 struct msi_msg msg; 87 int hwirq; 88 89 if (type == PCI_CAP_ID_MSIX) 90 pr_debug("pasemi_msi: MSI-X untested, trying anyway\n"); 91 pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n", 92 pdev, nvec, type); 93 94 msg.address_hi = 0; 95 msg.address_lo = PASEMI_MSI_ADDR; 96 97 list_for_each_entry(entry, &pdev->msi_list, list) { 98 /* Allocate 16 interrupts for now, since that's the grouping for 99 * affinity. This can be changed later if it turns out 32 is too 100 * few MSIs for someone, but restrictions will apply to how the 101 * sources can be changed independently. 102 */ 103 hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap, 104 ALLOC_CHUNK); 105 if (hwirq < 0) { 106 pr_debug("pasemi_msi: failed allocating hwirq\n"); 107 return hwirq; 108 } 109 110 virq = irq_create_mapping(msi_mpic->irqhost, hwirq); 111 if (virq == NO_IRQ) { 112 pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n", 113 hwirq); 114 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, 115 ALLOC_CHUNK); 116 return -ENOSPC; 117 } 118 119 /* Vector on MSI is really an offset, the hardware adds 120 * it to the value written at the magic address. So set 121 * it to 0 to remain sane. 122 */ 123 mpic_set_vector(virq, 0); 124 125 irq_set_msi_desc(virq, entry); 126 irq_set_chip(virq, &mpic_pasemi_msi_chip); 127 irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING); 128 129 pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \ 130 "addr 0x%x\n", virq, hwirq, msg.address_lo); 131 132 /* Likewise, the device writes [0...511] into the target 133 * register to generate MSI [512...1023] 134 */ 135 msg.data = hwirq-0x200; 136 pci_write_msi_msg(virq, &msg); 137 } 138 139 return 0; 140 } 141 142 int mpic_pasemi_msi_init(struct mpic *mpic) 143 { 144 int rc; 145 struct pci_controller *phb; 146 147 if (!mpic->irqhost->of_node || 148 !of_device_is_compatible(mpic->irqhost->of_node, 149 "pasemi,pwrficient-openpic")) 150 return -ENODEV; 151 152 rc = mpic_msi_init_allocator(mpic); 153 if (rc) { 154 pr_debug("pasemi_msi: Error allocating bitmap!\n"); 155 return rc; 156 } 157 158 pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n"); 159 160 msi_mpic = mpic; 161 list_for_each_entry(phb, &hose_list, list_node) { 162 WARN_ON(phb->controller_ops.setup_msi_irqs); 163 phb->controller_ops.setup_msi_irqs = pasemi_msi_setup_msi_irqs; 164 phb->controller_ops.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs; 165 } 166 167 return 0; 168 } 169