1 /*
2  * Copyright 2007, Olof Johansson, PA Semi
3  *
4  * Based on arch/powerpc/sysdev/mpic_u3msi.c:
5  *
6  * Copyright 2006, Segher Boessenkool, IBM Corporation.
7  * Copyright 2006-2007, Michael Ellerman, IBM Corporation.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; version 2 of the
12  * License.
13  *
14  */
15 
16 #include <linux/irq.h>
17 #include <linux/msi.h>
18 #include <asm/mpic.h>
19 #include <asm/prom.h>
20 #include <asm/hw_irq.h>
21 #include <asm/ppc-pci.h>
22 #include <asm/msi_bitmap.h>
23 
24 #include <sysdev/mpic.h>
25 
26 /* Allocate 16 interrupts per device, to give an alignment of 16,
27  * since that's the size of the grouping w.r.t. affinity. If someone
28  * needs more than 32 MSI's down the road we'll have to rethink this,
29  * but it should be OK for now.
30  */
31 #define ALLOC_CHUNK 16
32 
33 #define PASEMI_MSI_ADDR 0xfc080000
34 
35 /* A bit ugly, can we get this from the pci_dev somehow? */
36 static struct mpic *msi_mpic;
37 
38 
39 static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
40 {
41 	pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
42 	pci_msi_mask_irq(data);
43 	mpic_mask_irq(data);
44 }
45 
46 static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
47 {
48 	pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
49 	mpic_unmask_irq(data);
50 	pci_msi_unmask_irq(data);
51 }
52 
53 static struct irq_chip mpic_pasemi_msi_chip = {
54 	.irq_shutdown		= mpic_pasemi_msi_mask_irq,
55 	.irq_mask		= mpic_pasemi_msi_mask_irq,
56 	.irq_unmask		= mpic_pasemi_msi_unmask_irq,
57 	.irq_eoi		= mpic_end_irq,
58 	.irq_set_type		= mpic_set_irq_type,
59 	.irq_set_affinity	= mpic_set_affinity,
60 	.name			= "PASEMI-MSI",
61 };
62 
63 static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
64 {
65 	struct msi_desc *entry;
66 	irq_hw_number_t hwirq;
67 
68 	pr_debug("pasemi_msi_teardown_msi_irqs, pdev %p\n", pdev);
69 
70 	for_each_pci_msi_entry(entry, pdev) {
71 		if (entry->irq == NO_IRQ)
72 			continue;
73 
74 		hwirq = virq_to_hw(entry->irq);
75 		irq_set_msi_desc(entry->irq, NULL);
76 		irq_dispose_mapping(entry->irq);
77 		msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq, ALLOC_CHUNK);
78 	}
79 
80 	return;
81 }
82 
83 static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
84 {
85 	unsigned int virq;
86 	struct msi_desc *entry;
87 	struct msi_msg msg;
88 	int hwirq;
89 
90 	if (type == PCI_CAP_ID_MSIX)
91 		pr_debug("pasemi_msi: MSI-X untested, trying anyway\n");
92 	pr_debug("pasemi_msi_setup_msi_irqs, pdev %p nvec %d type %d\n",
93 		 pdev, nvec, type);
94 
95 	msg.address_hi = 0;
96 	msg.address_lo = PASEMI_MSI_ADDR;
97 
98 	for_each_pci_msi_entry(entry, pdev) {
99 		/* Allocate 16 interrupts for now, since that's the grouping for
100 		 * affinity. This can be changed later if it turns out 32 is too
101 		 * few MSIs for someone, but restrictions will apply to how the
102 		 * sources can be changed independently.
103 		 */
104 		hwirq = msi_bitmap_alloc_hwirqs(&msi_mpic->msi_bitmap,
105 						ALLOC_CHUNK);
106 		if (hwirq < 0) {
107 			pr_debug("pasemi_msi: failed allocating hwirq\n");
108 			return hwirq;
109 		}
110 
111 		virq = irq_create_mapping(msi_mpic->irqhost, hwirq);
112 		if (virq == NO_IRQ) {
113 			pr_debug("pasemi_msi: failed mapping hwirq 0x%x\n",
114 				  hwirq);
115 			msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap, hwirq,
116 					       ALLOC_CHUNK);
117 			return -ENOSPC;
118 		}
119 
120 		/* Vector on MSI is really an offset, the hardware adds
121 		 * it to the value written at the magic address. So set
122 		 * it to 0 to remain sane.
123 		 */
124 		mpic_set_vector(virq, 0);
125 
126 		irq_set_msi_desc(virq, entry);
127 		irq_set_chip(virq, &mpic_pasemi_msi_chip);
128 		irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
129 
130 		pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
131 			 "addr 0x%x\n", virq, hwirq, msg.address_lo);
132 
133 		/* Likewise, the device writes [0...511] into the target
134 		 * register to generate MSI [512...1023]
135 		 */
136 		msg.data = hwirq-0x200;
137 		pci_write_msi_msg(virq, &msg);
138 	}
139 
140 	return 0;
141 }
142 
143 int mpic_pasemi_msi_init(struct mpic *mpic)
144 {
145 	int rc;
146 	struct pci_controller *phb;
147 	struct device_node *of_node;
148 
149 	of_node = irq_domain_get_of_node(mpic->irqhost);
150 	if (!of_node ||
151 	    !of_device_is_compatible(of_node,
152 				     "pasemi,pwrficient-openpic"))
153 		return -ENODEV;
154 
155 	rc = mpic_msi_init_allocator(mpic);
156 	if (rc) {
157 		pr_debug("pasemi_msi: Error allocating bitmap!\n");
158 		return rc;
159 	}
160 
161 	pr_debug("pasemi_msi: Registering PA Semi MPIC MSI callbacks\n");
162 
163 	msi_mpic = mpic;
164 	list_for_each_entry(phb, &hose_list, list_node) {
165 		WARN_ON(phb->controller_ops.setup_msi_irqs);
166 		phb->controller_ops.setup_msi_irqs = pasemi_msi_setup_msi_irqs;
167 		phb->controller_ops.teardown_msi_irqs = pasemi_msi_teardown_msi_irqs;
168 	}
169 
170 	return 0;
171 }
172