1 /* 2 * Copyright (C) 2006-2007 PA Semi, Inc 3 * 4 * Common functions for DMA access on PA Semi PWRficient 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/export.h> 22 #include <linux/pci.h> 23 #include <linux/slab.h> 24 #include <linux/of.h> 25 #include <linux/sched.h> 26 27 #include <asm/pasemi_dma.h> 28 29 #define MAX_TXCH 64 30 #define MAX_RXCH 64 31 #define MAX_FLAGS 64 32 #define MAX_FUN 8 33 34 static struct pasdma_status *dma_status; 35 36 static void __iomem *iob_regs; 37 static void __iomem *mac_regs[6]; 38 static void __iomem *dma_regs; 39 40 static int base_hw_irq; 41 42 static int num_txch, num_rxch; 43 44 static struct pci_dev *dma_pdev; 45 46 /* Bitmaps to handle allocation of channels */ 47 48 static DECLARE_BITMAP(txch_free, MAX_TXCH); 49 static DECLARE_BITMAP(rxch_free, MAX_RXCH); 50 static DECLARE_BITMAP(flags_free, MAX_FLAGS); 51 static DECLARE_BITMAP(fun_free, MAX_FUN); 52 53 /* pasemi_read_iob_reg - read IOB register 54 * @reg: Register to read (offset into PCI CFG space) 55 */ 56 unsigned int pasemi_read_iob_reg(unsigned int reg) 57 { 58 return in_le32(iob_regs+reg); 59 } 60 EXPORT_SYMBOL(pasemi_read_iob_reg); 61 62 /* pasemi_write_iob_reg - write IOB register 63 * @reg: Register to write to (offset into PCI CFG space) 64 * @val: Value to write 65 */ 66 void pasemi_write_iob_reg(unsigned int reg, unsigned int val) 67 { 68 out_le32(iob_regs+reg, val); 69 } 70 EXPORT_SYMBOL(pasemi_write_iob_reg); 71 72 /* pasemi_read_mac_reg - read MAC register 73 * @intf: MAC interface 74 * @reg: Register to read (offset into PCI CFG space) 75 */ 76 unsigned int pasemi_read_mac_reg(int intf, unsigned int reg) 77 { 78 return in_le32(mac_regs[intf]+reg); 79 } 80 EXPORT_SYMBOL(pasemi_read_mac_reg); 81 82 /* pasemi_write_mac_reg - write MAC register 83 * @intf: MAC interface 84 * @reg: Register to write to (offset into PCI CFG space) 85 * @val: Value to write 86 */ 87 void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val) 88 { 89 out_le32(mac_regs[intf]+reg, val); 90 } 91 EXPORT_SYMBOL(pasemi_write_mac_reg); 92 93 /* pasemi_read_dma_reg - read DMA register 94 * @reg: Register to read (offset into PCI CFG space) 95 */ 96 unsigned int pasemi_read_dma_reg(unsigned int reg) 97 { 98 return in_le32(dma_regs+reg); 99 } 100 EXPORT_SYMBOL(pasemi_read_dma_reg); 101 102 /* pasemi_write_dma_reg - write DMA register 103 * @reg: Register to write to (offset into PCI CFG space) 104 * @val: Value to write 105 */ 106 void pasemi_write_dma_reg(unsigned int reg, unsigned int val) 107 { 108 out_le32(dma_regs+reg, val); 109 } 110 EXPORT_SYMBOL(pasemi_write_dma_reg); 111 112 static int pasemi_alloc_tx_chan(enum pasemi_dmachan_type type) 113 { 114 int bit; 115 int start, limit; 116 117 switch (type & (TXCHAN_EVT0|TXCHAN_EVT1)) { 118 case TXCHAN_EVT0: 119 start = 0; 120 limit = 10; 121 break; 122 case TXCHAN_EVT1: 123 start = 10; 124 limit = MAX_TXCH; 125 break; 126 default: 127 start = 0; 128 limit = MAX_TXCH; 129 break; 130 } 131 retry: 132 bit = find_next_bit(txch_free, MAX_TXCH, start); 133 if (bit >= limit) 134 return -ENOSPC; 135 if (!test_and_clear_bit(bit, txch_free)) 136 goto retry; 137 138 return bit; 139 } 140 141 static void pasemi_free_tx_chan(int chan) 142 { 143 BUG_ON(test_bit(chan, txch_free)); 144 set_bit(chan, txch_free); 145 } 146 147 static int pasemi_alloc_rx_chan(void) 148 { 149 int bit; 150 retry: 151 bit = find_first_bit(rxch_free, MAX_RXCH); 152 if (bit >= MAX_TXCH) 153 return -ENOSPC; 154 if (!test_and_clear_bit(bit, rxch_free)) 155 goto retry; 156 157 return bit; 158 } 159 160 static void pasemi_free_rx_chan(int chan) 161 { 162 BUG_ON(test_bit(chan, rxch_free)); 163 set_bit(chan, rxch_free); 164 } 165 166 /* pasemi_dma_alloc_chan - Allocate a DMA channel 167 * @type: Type of channel to allocate 168 * @total_size: Total size of structure to allocate (to allow for more 169 * room behind the structure to be used by the client) 170 * @offset: Offset in bytes from start of the total structure to the beginning 171 * of struct pasemi_dmachan. Needed when struct pasemi_dmachan is 172 * not the first member of the client structure. 173 * 174 * pasemi_dma_alloc_chan allocates a DMA channel for use by a client. The 175 * type argument specifies whether it's a RX or TX channel, and in the case 176 * of TX channels which group it needs to belong to (if any). 177 * 178 * Returns a pointer to the total structure allocated on success, NULL 179 * on failure. 180 */ 181 void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type, 182 int total_size, int offset) 183 { 184 void *buf; 185 struct pasemi_dmachan *chan; 186 int chno; 187 188 BUG_ON(total_size < sizeof(struct pasemi_dmachan)); 189 190 buf = kzalloc(total_size, GFP_KERNEL); 191 192 if (!buf) 193 return NULL; 194 chan = buf + offset; 195 196 chan->priv = buf; 197 198 switch (type & (TXCHAN|RXCHAN)) { 199 case RXCHAN: 200 chno = pasemi_alloc_rx_chan(); 201 chan->chno = chno; 202 chan->irq = irq_create_mapping(NULL, 203 base_hw_irq + num_txch + chno); 204 chan->status = &dma_status->rx_sta[chno]; 205 break; 206 case TXCHAN: 207 chno = pasemi_alloc_tx_chan(type); 208 chan->chno = chno; 209 chan->irq = irq_create_mapping(NULL, base_hw_irq + chno); 210 chan->status = &dma_status->tx_sta[chno]; 211 break; 212 } 213 214 chan->chan_type = type; 215 216 return chan; 217 } 218 EXPORT_SYMBOL(pasemi_dma_alloc_chan); 219 220 /* pasemi_dma_free_chan - Free a previously allocated channel 221 * @chan: Channel to free 222 * 223 * Frees a previously allocated channel. It will also deallocate any 224 * descriptor ring associated with the channel, if allocated. 225 */ 226 void pasemi_dma_free_chan(struct pasemi_dmachan *chan) 227 { 228 if (chan->ring_virt) 229 pasemi_dma_free_ring(chan); 230 231 switch (chan->chan_type & (RXCHAN|TXCHAN)) { 232 case RXCHAN: 233 pasemi_free_rx_chan(chan->chno); 234 break; 235 case TXCHAN: 236 pasemi_free_tx_chan(chan->chno); 237 break; 238 } 239 240 kfree(chan->priv); 241 } 242 EXPORT_SYMBOL(pasemi_dma_free_chan); 243 244 /* pasemi_dma_alloc_ring - Allocate descriptor ring for a channel 245 * @chan: Channel for which to allocate 246 * @ring_size: Ring size in 64-bit (8-byte) words 247 * 248 * Allocate a descriptor ring for a channel. Returns 0 on success, errno 249 * on failure. The passed in struct pasemi_dmachan is updated with the 250 * virtual and DMA addresses of the ring. 251 */ 252 int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size) 253 { 254 BUG_ON(chan->ring_virt); 255 256 chan->ring_size = ring_size; 257 258 chan->ring_virt = dma_alloc_coherent(&dma_pdev->dev, 259 ring_size * sizeof(u64), 260 &chan->ring_dma, GFP_KERNEL); 261 262 if (!chan->ring_virt) 263 return -ENOMEM; 264 265 return 0; 266 } 267 EXPORT_SYMBOL(pasemi_dma_alloc_ring); 268 269 /* pasemi_dma_free_ring - Free an allocated descriptor ring for a channel 270 * @chan: Channel for which to free the descriptor ring 271 * 272 * Frees a previously allocated descriptor ring for a channel. 273 */ 274 void pasemi_dma_free_ring(struct pasemi_dmachan *chan) 275 { 276 BUG_ON(!chan->ring_virt); 277 278 dma_free_coherent(&dma_pdev->dev, chan->ring_size * sizeof(u64), 279 chan->ring_virt, chan->ring_dma); 280 chan->ring_virt = NULL; 281 chan->ring_size = 0; 282 chan->ring_dma = 0; 283 } 284 EXPORT_SYMBOL(pasemi_dma_free_ring); 285 286 /* pasemi_dma_start_chan - Start a DMA channel 287 * @chan: Channel to start 288 * @cmdsta: Additional CCMDSTA/TCMDSTA bits to write 289 * 290 * Enables (starts) a DMA channel with optional additional arguments. 291 */ 292 void pasemi_dma_start_chan(const struct pasemi_dmachan *chan, const u32 cmdsta) 293 { 294 if (chan->chan_type == RXCHAN) 295 pasemi_write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno), 296 cmdsta | PAS_DMA_RXCHAN_CCMDSTA_EN); 297 else 298 pasemi_write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno), 299 cmdsta | PAS_DMA_TXCHAN_TCMDSTA_EN); 300 } 301 EXPORT_SYMBOL(pasemi_dma_start_chan); 302 303 /* pasemi_dma_stop_chan - Stop a DMA channel 304 * @chan: Channel to stop 305 * 306 * Stops (disables) a DMA channel. This is done by setting the ST bit in the 307 * CMDSTA register and waiting on the ACT (active) bit to clear, then 308 * finally disabling the whole channel. 309 * 310 * This function will only try for a short while for the channel to stop, if 311 * it doesn't it will return failure. 312 * 313 * Returns 1 on success, 0 on failure. 314 */ 315 #define MAX_RETRIES 5000 316 int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan) 317 { 318 int reg, retries; 319 u32 sta; 320 321 if (chan->chan_type == RXCHAN) { 322 reg = PAS_DMA_RXCHAN_CCMDSTA(chan->chno); 323 pasemi_write_dma_reg(reg, PAS_DMA_RXCHAN_CCMDSTA_ST); 324 for (retries = 0; retries < MAX_RETRIES; retries++) { 325 sta = pasemi_read_dma_reg(reg); 326 if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)) { 327 pasemi_write_dma_reg(reg, 0); 328 return 1; 329 } 330 cond_resched(); 331 } 332 } else { 333 reg = PAS_DMA_TXCHAN_TCMDSTA(chan->chno); 334 pasemi_write_dma_reg(reg, PAS_DMA_TXCHAN_TCMDSTA_ST); 335 for (retries = 0; retries < MAX_RETRIES; retries++) { 336 sta = pasemi_read_dma_reg(reg); 337 if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)) { 338 pasemi_write_dma_reg(reg, 0); 339 return 1; 340 } 341 cond_resched(); 342 } 343 } 344 345 return 0; 346 } 347 EXPORT_SYMBOL(pasemi_dma_stop_chan); 348 349 /* pasemi_dma_alloc_buf - Allocate a buffer to use for DMA 350 * @chan: Channel to allocate for 351 * @size: Size of buffer in bytes 352 * @handle: DMA handle 353 * 354 * Allocate a buffer to be used by the DMA engine for read/write, 355 * similar to dma_alloc_coherent(). 356 * 357 * Returns the virtual address of the buffer, or NULL in case of failure. 358 */ 359 void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size, 360 dma_addr_t *handle) 361 { 362 return dma_alloc_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL); 363 } 364 EXPORT_SYMBOL(pasemi_dma_alloc_buf); 365 366 /* pasemi_dma_free_buf - Free a buffer used for DMA 367 * @chan: Channel the buffer was allocated for 368 * @size: Size of buffer in bytes 369 * @handle: DMA handle 370 * 371 * Frees a previously allocated buffer. 372 */ 373 void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size, 374 dma_addr_t *handle) 375 { 376 dma_free_coherent(&dma_pdev->dev, size, handle, GFP_KERNEL); 377 } 378 EXPORT_SYMBOL(pasemi_dma_free_buf); 379 380 /* pasemi_dma_alloc_flag - Allocate a flag (event) for channel synchronization 381 * 382 * Allocates a flag for use with channel synchronization (event descriptors). 383 * Returns allocated flag (0-63), < 0 on error. 384 */ 385 int pasemi_dma_alloc_flag(void) 386 { 387 int bit; 388 389 retry: 390 bit = find_next_bit(flags_free, MAX_FLAGS, 0); 391 if (bit >= MAX_FLAGS) 392 return -ENOSPC; 393 if (!test_and_clear_bit(bit, flags_free)) 394 goto retry; 395 396 return bit; 397 } 398 EXPORT_SYMBOL(pasemi_dma_alloc_flag); 399 400 401 /* pasemi_dma_free_flag - Deallocates a flag (event) 402 * @flag: Flag number to deallocate 403 * 404 * Frees up a flag so it can be reused for other purposes. 405 */ 406 void pasemi_dma_free_flag(int flag) 407 { 408 BUG_ON(test_bit(flag, flags_free)); 409 BUG_ON(flag >= MAX_FLAGS); 410 set_bit(flag, flags_free); 411 } 412 EXPORT_SYMBOL(pasemi_dma_free_flag); 413 414 415 /* pasemi_dma_set_flag - Sets a flag (event) to 1 416 * @flag: Flag number to set active 417 * 418 * Sets the flag provided to 1. 419 */ 420 void pasemi_dma_set_flag(int flag) 421 { 422 BUG_ON(flag >= MAX_FLAGS); 423 if (flag < 32) 424 pasemi_write_dma_reg(PAS_DMA_TXF_SFLG0, 1 << flag); 425 else 426 pasemi_write_dma_reg(PAS_DMA_TXF_SFLG1, 1 << flag); 427 } 428 EXPORT_SYMBOL(pasemi_dma_set_flag); 429 430 /* pasemi_dma_clear_flag - Sets a flag (event) to 0 431 * @flag: Flag number to set inactive 432 * 433 * Sets the flag provided to 0. 434 */ 435 void pasemi_dma_clear_flag(int flag) 436 { 437 BUG_ON(flag >= MAX_FLAGS); 438 if (flag < 32) 439 pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 1 << flag); 440 else 441 pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 1 << flag); 442 } 443 EXPORT_SYMBOL(pasemi_dma_clear_flag); 444 445 /* pasemi_dma_alloc_fun - Allocate a function engine 446 * 447 * Allocates a function engine to use for crypto/checksum offload 448 * Returns allocated engine (0-8), < 0 on error. 449 */ 450 int pasemi_dma_alloc_fun(void) 451 { 452 int bit; 453 454 retry: 455 bit = find_next_bit(fun_free, MAX_FLAGS, 0); 456 if (bit >= MAX_FLAGS) 457 return -ENOSPC; 458 if (!test_and_clear_bit(bit, fun_free)) 459 goto retry; 460 461 return bit; 462 } 463 EXPORT_SYMBOL(pasemi_dma_alloc_fun); 464 465 466 /* pasemi_dma_free_fun - Deallocates a function engine 467 * @flag: Engine number to deallocate 468 * 469 * Frees up a function engine so it can be used for other purposes. 470 */ 471 void pasemi_dma_free_fun(int fun) 472 { 473 BUG_ON(test_bit(fun, fun_free)); 474 BUG_ON(fun >= MAX_FLAGS); 475 set_bit(fun, fun_free); 476 } 477 EXPORT_SYMBOL(pasemi_dma_free_fun); 478 479 480 static void *map_onedev(struct pci_dev *p, int index) 481 { 482 struct device_node *dn; 483 void __iomem *ret; 484 485 dn = pci_device_to_OF_node(p); 486 if (!dn) 487 goto fallback; 488 489 ret = of_iomap(dn, index); 490 if (!ret) 491 goto fallback; 492 493 return ret; 494 fallback: 495 /* This is hardcoded and ugly, but we have some firmware versions 496 * that don't provide the register space in the device tree. Luckily 497 * they are at well-known locations so we can just do the math here. 498 */ 499 return ioremap(0xe0000000 + (p->devfn << 12), 0x2000); 500 } 501 502 /* pasemi_dma_init - Initialize the PA Semi DMA library 503 * 504 * This function initializes the DMA library. It must be called before 505 * any other function in the library. 506 * 507 * Returns 0 on success, errno on failure. 508 */ 509 int pasemi_dma_init(void) 510 { 511 static DEFINE_SPINLOCK(init_lock); 512 struct pci_dev *iob_pdev; 513 struct pci_dev *pdev; 514 struct resource res; 515 struct device_node *dn; 516 int i, intf, err = 0; 517 unsigned long timeout; 518 u32 tmp; 519 520 if (!machine_is(pasemi)) 521 return -ENODEV; 522 523 spin_lock(&init_lock); 524 525 /* Make sure we haven't already initialized */ 526 if (dma_pdev) 527 goto out; 528 529 iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL); 530 if (!iob_pdev) { 531 BUG(); 532 pr_warn("Can't find I/O Bridge\n"); 533 err = -ENODEV; 534 goto out; 535 } 536 iob_regs = map_onedev(iob_pdev, 0); 537 538 dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL); 539 if (!dma_pdev) { 540 BUG(); 541 pr_warn("Can't find DMA controller\n"); 542 err = -ENODEV; 543 goto out; 544 } 545 dma_regs = map_onedev(dma_pdev, 0); 546 base_hw_irq = virq_to_hw(dma_pdev->irq); 547 548 pci_read_config_dword(dma_pdev, PAS_DMA_CAP_TXCH, &tmp); 549 num_txch = (tmp & PAS_DMA_CAP_TXCH_TCHN_M) >> PAS_DMA_CAP_TXCH_TCHN_S; 550 551 pci_read_config_dword(dma_pdev, PAS_DMA_CAP_RXCH, &tmp); 552 num_rxch = (tmp & PAS_DMA_CAP_RXCH_RCHN_M) >> PAS_DMA_CAP_RXCH_RCHN_S; 553 554 intf = 0; 555 for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, NULL); 556 pdev; 557 pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa006, pdev)) 558 mac_regs[intf++] = map_onedev(pdev, 0); 559 560 pci_dev_put(pdev); 561 562 for (pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, NULL); 563 pdev; 564 pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa005, pdev)) 565 mac_regs[intf++] = map_onedev(pdev, 0); 566 567 pci_dev_put(pdev); 568 569 dn = pci_device_to_OF_node(iob_pdev); 570 if (dn) 571 err = of_address_to_resource(dn, 1, &res); 572 if (!dn || err) { 573 /* Fallback for old firmware */ 574 res.start = 0xfd800000; 575 res.end = res.start + 0x1000; 576 } 577 dma_status = ioremap_cache(res.start, resource_size(&res)); 578 pci_dev_put(iob_pdev); 579 580 for (i = 0; i < MAX_TXCH; i++) 581 __set_bit(i, txch_free); 582 583 for (i = 0; i < MAX_RXCH; i++) 584 __set_bit(i, rxch_free); 585 586 timeout = jiffies + HZ; 587 pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, 0); 588 while (pasemi_read_dma_reg(PAS_DMA_COM_RXSTA) & 1) { 589 if (time_after(jiffies, timeout)) { 590 pr_warn("Warning: Could not disable RX section\n"); 591 break; 592 } 593 } 594 595 timeout = jiffies + HZ; 596 pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, 0); 597 while (pasemi_read_dma_reg(PAS_DMA_COM_TXSTA) & 1) { 598 if (time_after(jiffies, timeout)) { 599 pr_warn("Warning: Could not disable TX section\n"); 600 break; 601 } 602 } 603 604 /* setup resource allocations for the different DMA sections */ 605 tmp = pasemi_read_dma_reg(PAS_DMA_COM_CFG); 606 pasemi_write_dma_reg(PAS_DMA_COM_CFG, tmp | 0x18000000); 607 608 /* enable tx section */ 609 pasemi_write_dma_reg(PAS_DMA_COM_TXCMD, PAS_DMA_COM_TXCMD_EN); 610 611 /* enable rx section */ 612 pasemi_write_dma_reg(PAS_DMA_COM_RXCMD, PAS_DMA_COM_RXCMD_EN); 613 614 for (i = 0; i < MAX_FLAGS; i++) 615 __set_bit(i, flags_free); 616 617 for (i = 0; i < MAX_FUN; i++) 618 __set_bit(i, fun_free); 619 620 /* clear all status flags */ 621 pasemi_write_dma_reg(PAS_DMA_TXF_CFLG0, 0xffffffff); 622 pasemi_write_dma_reg(PAS_DMA_TXF_CFLG1, 0xffffffff); 623 624 pr_info("PA Semi PWRficient DMA library initialized " 625 "(%d tx, %d rx channels)\n", num_txch, num_rxch); 626 627 out: 628 spin_unlock(&init_lock); 629 return err; 630 } 631 EXPORT_SYMBOL(pasemi_dma_init); 632