1 /* 2 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), 3 * IBM Corp. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 8 * 2 of the License, or (at your option) any later version. 9 */ 10 11 #undef DEBUG 12 13 #include <linux/kernel.h> 14 #include <linux/pci.h> 15 #include <linux/delay.h> 16 #include <linux/string.h> 17 #include <linux/init.h> 18 #include <linux/bootmem.h> 19 #include <linux/irq.h> 20 21 #include <asm/sections.h> 22 #include <asm/io.h> 23 #include <asm/prom.h> 24 #include <asm/pci-bridge.h> 25 #include <asm/machdep.h> 26 #include <asm/iommu.h> 27 #include <asm/ppc-pci.h> 28 29 #include "maple.h" 30 31 #ifdef DEBUG 32 #define DBG(x...) printk(x) 33 #else 34 #define DBG(x...) 35 #endif 36 37 static struct pci_controller *u3_agp, *u3_ht, *u4_pcie; 38 39 static int __init fixup_one_level_bus_range(struct device_node *node, int higher) 40 { 41 for (; node != 0;node = node->sibling) { 42 const int *bus_range; 43 const unsigned int *class_code; 44 int len; 45 46 /* For PCI<->PCI bridges or CardBus bridges, we go down */ 47 class_code = of_get_property(node, "class-code", NULL); 48 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI && 49 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS)) 50 continue; 51 bus_range = of_get_property(node, "bus-range", &len); 52 if (bus_range != NULL && len > 2 * sizeof(int)) { 53 if (bus_range[1] > higher) 54 higher = bus_range[1]; 55 } 56 higher = fixup_one_level_bus_range(node->child, higher); 57 } 58 return higher; 59 } 60 61 /* This routine fixes the "bus-range" property of all bridges in the 62 * system since they tend to have their "last" member wrong on macs 63 * 64 * Note that the bus numbers manipulated here are OF bus numbers, they 65 * are not Linux bus numbers. 66 */ 67 static void __init fixup_bus_range(struct device_node *bridge) 68 { 69 int *bus_range; 70 struct property *prop; 71 int len; 72 73 /* Lookup the "bus-range" property for the hose */ 74 prop = of_find_property(bridge, "bus-range", &len); 75 if (prop == NULL || prop->value == NULL || len < 2 * sizeof(int)) { 76 printk(KERN_WARNING "Can't get bus-range for %s\n", 77 bridge->full_name); 78 return; 79 } 80 bus_range = prop->value; 81 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]); 82 } 83 84 85 static unsigned long u3_agp_cfa0(u8 devfn, u8 off) 86 { 87 return (1 << (unsigned long)PCI_SLOT(devfn)) | 88 ((unsigned long)PCI_FUNC(devfn) << 8) | 89 ((unsigned long)off & 0xFCUL); 90 } 91 92 static unsigned long u3_agp_cfa1(u8 bus, u8 devfn, u8 off) 93 { 94 return ((unsigned long)bus << 16) | 95 ((unsigned long)devfn << 8) | 96 ((unsigned long)off & 0xFCUL) | 97 1UL; 98 } 99 100 static volatile void __iomem *u3_agp_cfg_access(struct pci_controller* hose, 101 u8 bus, u8 dev_fn, u8 offset) 102 { 103 unsigned int caddr; 104 105 if (bus == hose->first_busno) { 106 if (dev_fn < (11 << 3)) 107 return NULL; 108 caddr = u3_agp_cfa0(dev_fn, offset); 109 } else 110 caddr = u3_agp_cfa1(bus, dev_fn, offset); 111 112 /* Uninorth will return garbage if we don't read back the value ! */ 113 do { 114 out_le32(hose->cfg_addr, caddr); 115 } while (in_le32(hose->cfg_addr) != caddr); 116 117 offset &= 0x07; 118 return hose->cfg_data + offset; 119 } 120 121 static int u3_agp_read_config(struct pci_bus *bus, unsigned int devfn, 122 int offset, int len, u32 *val) 123 { 124 struct pci_controller *hose; 125 volatile void __iomem *addr; 126 127 hose = pci_bus_to_host(bus); 128 if (hose == NULL) 129 return PCIBIOS_DEVICE_NOT_FOUND; 130 131 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); 132 if (!addr) 133 return PCIBIOS_DEVICE_NOT_FOUND; 134 /* 135 * Note: the caller has already checked that offset is 136 * suitably aligned and that len is 1, 2 or 4. 137 */ 138 switch (len) { 139 case 1: 140 *val = in_8(addr); 141 break; 142 case 2: 143 *val = in_le16(addr); 144 break; 145 default: 146 *val = in_le32(addr); 147 break; 148 } 149 return PCIBIOS_SUCCESSFUL; 150 } 151 152 static int u3_agp_write_config(struct pci_bus *bus, unsigned int devfn, 153 int offset, int len, u32 val) 154 { 155 struct pci_controller *hose; 156 volatile void __iomem *addr; 157 158 hose = pci_bus_to_host(bus); 159 if (hose == NULL) 160 return PCIBIOS_DEVICE_NOT_FOUND; 161 162 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset); 163 if (!addr) 164 return PCIBIOS_DEVICE_NOT_FOUND; 165 /* 166 * Note: the caller has already checked that offset is 167 * suitably aligned and that len is 1, 2 or 4. 168 */ 169 switch (len) { 170 case 1: 171 out_8(addr, val); 172 (void) in_8(addr); 173 break; 174 case 2: 175 out_le16(addr, val); 176 (void) in_le16(addr); 177 break; 178 default: 179 out_le32(addr, val); 180 (void) in_le32(addr); 181 break; 182 } 183 return PCIBIOS_SUCCESSFUL; 184 } 185 186 static struct pci_ops u3_agp_pci_ops = 187 { 188 u3_agp_read_config, 189 u3_agp_write_config 190 }; 191 192 static unsigned long u3_ht_cfa0(u8 devfn, u8 off) 193 { 194 return (devfn << 8) | off; 195 } 196 197 static unsigned long u3_ht_cfa1(u8 bus, u8 devfn, u8 off) 198 { 199 return u3_ht_cfa0(devfn, off) + (bus << 16) + 0x01000000UL; 200 } 201 202 static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose, 203 u8 bus, u8 devfn, u8 offset) 204 { 205 if (bus == hose->first_busno) { 206 if (PCI_SLOT(devfn) == 0) 207 return NULL; 208 return hose->cfg_data + u3_ht_cfa0(devfn, offset); 209 } else 210 return hose->cfg_data + u3_ht_cfa1(bus, devfn, offset); 211 } 212 213 static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, 214 int offset, int len, u32 *val) 215 { 216 struct pci_controller *hose; 217 volatile void __iomem *addr; 218 219 hose = pci_bus_to_host(bus); 220 if (hose == NULL) 221 return PCIBIOS_DEVICE_NOT_FOUND; 222 223 if (offset > 0xff) 224 return PCIBIOS_BAD_REGISTER_NUMBER; 225 226 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 227 if (!addr) 228 return PCIBIOS_DEVICE_NOT_FOUND; 229 230 /* 231 * Note: the caller has already checked that offset is 232 * suitably aligned and that len is 1, 2 or 4. 233 */ 234 switch (len) { 235 case 1: 236 *val = in_8(addr); 237 break; 238 case 2: 239 *val = in_le16(addr); 240 break; 241 default: 242 *val = in_le32(addr); 243 break; 244 } 245 return PCIBIOS_SUCCESSFUL; 246 } 247 248 static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, 249 int offset, int len, u32 val) 250 { 251 struct pci_controller *hose; 252 volatile void __iomem *addr; 253 254 hose = pci_bus_to_host(bus); 255 if (hose == NULL) 256 return PCIBIOS_DEVICE_NOT_FOUND; 257 258 if (offset > 0xff) 259 return PCIBIOS_BAD_REGISTER_NUMBER; 260 261 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset); 262 if (!addr) 263 return PCIBIOS_DEVICE_NOT_FOUND; 264 /* 265 * Note: the caller has already checked that offset is 266 * suitably aligned and that len is 1, 2 or 4. 267 */ 268 switch (len) { 269 case 1: 270 out_8(addr, val); 271 (void) in_8(addr); 272 break; 273 case 2: 274 out_le16(addr, val); 275 (void) in_le16(addr); 276 break; 277 default: 278 out_le32(addr, val); 279 (void) in_le32(addr); 280 break; 281 } 282 return PCIBIOS_SUCCESSFUL; 283 } 284 285 static struct pci_ops u3_ht_pci_ops = 286 { 287 u3_ht_read_config, 288 u3_ht_write_config 289 }; 290 291 static unsigned int u4_pcie_cfa0(unsigned int devfn, unsigned int off) 292 { 293 return (1 << PCI_SLOT(devfn)) | 294 (PCI_FUNC(devfn) << 8) | 295 ((off >> 8) << 28) | 296 (off & 0xfcu); 297 } 298 299 static unsigned int u4_pcie_cfa1(unsigned int bus, unsigned int devfn, 300 unsigned int off) 301 { 302 return (bus << 16) | 303 (devfn << 8) | 304 ((off >> 8) << 28) | 305 (off & 0xfcu) | 1u; 306 } 307 308 static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose, 309 u8 bus, u8 dev_fn, int offset) 310 { 311 unsigned int caddr; 312 313 if (bus == hose->first_busno) 314 caddr = u4_pcie_cfa0(dev_fn, offset); 315 else 316 caddr = u4_pcie_cfa1(bus, dev_fn, offset); 317 318 /* Uninorth will return garbage if we don't read back the value ! */ 319 do { 320 out_le32(hose->cfg_addr, caddr); 321 } while (in_le32(hose->cfg_addr) != caddr); 322 323 offset &= 0x03; 324 return hose->cfg_data + offset; 325 } 326 327 static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, 328 int offset, int len, u32 *val) 329 { 330 struct pci_controller *hose; 331 volatile void __iomem *addr; 332 333 hose = pci_bus_to_host(bus); 334 if (hose == NULL) 335 return PCIBIOS_DEVICE_NOT_FOUND; 336 if (offset >= 0x1000) 337 return PCIBIOS_BAD_REGISTER_NUMBER; 338 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 339 if (!addr) 340 return PCIBIOS_DEVICE_NOT_FOUND; 341 /* 342 * Note: the caller has already checked that offset is 343 * suitably aligned and that len is 1, 2 or 4. 344 */ 345 switch (len) { 346 case 1: 347 *val = in_8(addr); 348 break; 349 case 2: 350 *val = in_le16(addr); 351 break; 352 default: 353 *val = in_le32(addr); 354 break; 355 } 356 return PCIBIOS_SUCCESSFUL; 357 } 358 static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 359 int offset, int len, u32 val) 360 { 361 struct pci_controller *hose; 362 volatile void __iomem *addr; 363 364 hose = pci_bus_to_host(bus); 365 if (hose == NULL) 366 return PCIBIOS_DEVICE_NOT_FOUND; 367 if (offset >= 0x1000) 368 return PCIBIOS_BAD_REGISTER_NUMBER; 369 addr = u4_pcie_cfg_access(hose, bus->number, devfn, offset); 370 if (!addr) 371 return PCIBIOS_DEVICE_NOT_FOUND; 372 /* 373 * Note: the caller has already checked that offset is 374 * suitably aligned and that len is 1, 2 or 4. 375 */ 376 switch (len) { 377 case 1: 378 out_8(addr, val); 379 (void) in_8(addr); 380 break; 381 case 2: 382 out_le16(addr, val); 383 (void) in_le16(addr); 384 break; 385 default: 386 out_le32(addr, val); 387 (void) in_le32(addr); 388 break; 389 } 390 return PCIBIOS_SUCCESSFUL; 391 } 392 393 static struct pci_ops u4_pcie_pci_ops = 394 { 395 u4_pcie_read_config, 396 u4_pcie_write_config 397 }; 398 399 static void __init setup_u3_agp(struct pci_controller* hose) 400 { 401 /* On G5, we move AGP up to high bus number so we don't need 402 * to reassign bus numbers for HT. If we ever have P2P bridges 403 * on AGP, we'll have to move pci_assign_all_buses to the 404 * pci_controller structure so we enable it for AGP and not for 405 * HT childs. 406 * We hard code the address because of the different size of 407 * the reg address cell, we shall fix that by killing struct 408 * reg_property and using some accessor functions instead 409 */ 410 hose->first_busno = 0xf0; 411 hose->last_busno = 0xff; 412 hose->ops = &u3_agp_pci_ops; 413 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 414 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 415 416 u3_agp = hose; 417 } 418 419 static void __init setup_u4_pcie(struct pci_controller* hose) 420 { 421 /* We currently only implement the "non-atomic" config space, to 422 * be optimised later. 423 */ 424 hose->ops = &u4_pcie_pci_ops; 425 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000); 426 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000); 427 428 u4_pcie = hose; 429 } 430 431 static void __init setup_u3_ht(struct pci_controller* hose) 432 { 433 hose->ops = &u3_ht_pci_ops; 434 435 /* We hard code the address because of the different size of 436 * the reg address cell, we shall fix that by killing struct 437 * reg_property and using some accessor functions instead 438 */ 439 hose->cfg_data = ioremap(0xf2000000, 0x02000000); 440 441 hose->first_busno = 0; 442 hose->last_busno = 0xef; 443 444 u3_ht = hose; 445 } 446 447 static int __init maple_add_bridge(struct device_node *dev) 448 { 449 int len; 450 struct pci_controller *hose; 451 char* disp_name; 452 const int *bus_range; 453 int primary = 1; 454 455 DBG("Adding PCI host bridge %s\n", dev->full_name); 456 457 bus_range = of_get_property(dev, "bus-range", &len); 458 if (bus_range == NULL || len < 2 * sizeof(int)) { 459 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n", 460 dev->full_name); 461 } 462 463 hose = pcibios_alloc_controller(dev); 464 if (hose == NULL) 465 return -ENOMEM; 466 hose->first_busno = bus_range ? bus_range[0] : 0; 467 hose->last_busno = bus_range ? bus_range[1] : 0xff; 468 469 disp_name = NULL; 470 if (of_device_is_compatible(dev, "u3-agp")) { 471 setup_u3_agp(hose); 472 disp_name = "U3-AGP"; 473 primary = 0; 474 } else if (of_device_is_compatible(dev, "u3-ht")) { 475 setup_u3_ht(hose); 476 disp_name = "U3-HT"; 477 primary = 1; 478 } else if (of_device_is_compatible(dev, "u4-pcie")) { 479 setup_u4_pcie(hose); 480 disp_name = "U4-PCIE"; 481 primary = 0; 482 } 483 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n", 484 disp_name, hose->first_busno, hose->last_busno); 485 486 /* Interpret the "ranges" property */ 487 /* This also maps the I/O region and sets isa_io/mem_base */ 488 pci_process_bridge_OF_ranges(hose, dev, primary); 489 490 /* Fixup "bus-range" OF property */ 491 fixup_bus_range(dev); 492 493 /* Check for legacy IOs */ 494 isa_bridge_find_early(hose); 495 496 return 0; 497 } 498 499 500 void __devinit maple_pci_irq_fixup(struct pci_dev *dev) 501 { 502 DBG(" -> maple_pci_irq_fixup\n"); 503 504 /* Fixup IRQ for PCIe host */ 505 if (u4_pcie != NULL && dev->bus->number == 0 && 506 pci_bus_to_host(dev->bus) == u4_pcie) { 507 printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n"); 508 dev->irq = irq_create_mapping(NULL, 1); 509 if (dev->irq != NO_IRQ) 510 set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW); 511 } 512 513 /* Hide AMD8111 IDE interrupt when in legacy mode so 514 * the driver calls pci_get_legacy_ide_irq() 515 */ 516 if (dev->vendor == PCI_VENDOR_ID_AMD && 517 dev->device == PCI_DEVICE_ID_AMD_8111_IDE && 518 (dev->class & 5) != 5) { 519 dev->irq = NO_IRQ; 520 } 521 522 DBG(" <- maple_pci_irq_fixup\n"); 523 } 524 525 void __init maple_pci_init(void) 526 { 527 struct device_node *np, *root; 528 struct device_node *ht = NULL; 529 530 /* Probe root PCI hosts, that is on U3 the AGP host and the 531 * HyperTransport host. That one is actually "kept" around 532 * and actually added last as it's resource management relies 533 * on the AGP resources to have been setup first 534 */ 535 root = of_find_node_by_path("/"); 536 if (root == NULL) { 537 printk(KERN_CRIT "maple_find_bridges: can't find root of device tree\n"); 538 return; 539 } 540 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) { 541 if (!np->type) 542 continue; 543 if (strcmp(np->type, "pci") && strcmp(np->type, "ht")) 544 continue; 545 if ((of_device_is_compatible(np, "u4-pcie") || 546 of_device_is_compatible(np, "u3-agp")) && 547 maple_add_bridge(np) == 0) 548 of_node_get(np); 549 550 if (of_device_is_compatible(np, "u3-ht")) { 551 of_node_get(np); 552 ht = np; 553 } 554 } 555 of_node_put(root); 556 557 /* Now setup the HyperTransport host if we found any 558 */ 559 if (ht && maple_add_bridge(ht) != 0) 560 of_node_put(ht); 561 562 /* Setup the linkage between OF nodes and PHBs */ 563 pci_devs_phb_init(); 564 565 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We 566 * assume there is no P2P bridge on the AGP bus, which should be a 567 * safe assumptions hopefully. 568 */ 569 if (u3_agp) { 570 struct device_node *np = u3_agp->arch_data; 571 PCI_DN(np)->busno = 0xf0; 572 for (np = np->child; np; np = np->sibling) 573 PCI_DN(np)->busno = 0xf0; 574 } 575 576 /* Tell pci.c to not change any resource allocations. */ 577 pci_probe_only = 1; 578 } 579 580 int maple_pci_get_legacy_ide_irq(struct pci_dev *pdev, int channel) 581 { 582 struct device_node *np; 583 unsigned int defirq = channel ? 15 : 14; 584 unsigned int irq; 585 586 if (pdev->vendor != PCI_VENDOR_ID_AMD || 587 pdev->device != PCI_DEVICE_ID_AMD_8111_IDE) 588 return defirq; 589 590 np = pci_device_to_OF_node(pdev); 591 if (np == NULL) { 592 printk("Failed to locate OF node for IDE %s\n", 593 pci_name(pdev)); 594 return defirq; 595 } 596 irq = irq_of_parse_and_map(np, channel & 0x1); 597 if (irq == NO_IRQ) { 598 printk("Failed to map onboard IDE interrupt for channel %d\n", 599 channel); 600 return defirq; 601 } 602 return irq; 603 } 604 605 /* XXX: To remove once all firmwares are ok */ 606 static void fixup_maple_ide(struct pci_dev* dev) 607 { 608 if (!machine_is(maple)) 609 return; 610 611 #if 0 /* Enable this to enable IDE port 0 */ 612 { 613 u8 v; 614 615 pci_read_config_byte(dev, 0x40, &v); 616 v |= 2; 617 pci_write_config_byte(dev, 0x40, v); 618 } 619 #endif 620 #if 0 /* fix bus master base */ 621 pci_write_config_dword(dev, 0x20, 0xcc01); 622 printk("old ide resource: %lx -> %lx \n", 623 dev->resource[4].start, dev->resource[4].end); 624 dev->resource[4].start = 0xcc00; 625 dev->resource[4].end = 0xcc10; 626 #endif 627 #if 0 /* Enable this to fixup IDE sense/polarity of irqs in IO-APICs */ 628 { 629 struct pci_dev *apicdev; 630 u32 v; 631 632 apicdev = pci_get_slot (dev->bus, PCI_DEVFN(5,0)); 633 if (apicdev == NULL) 634 printk("IDE Fixup IRQ: Can't find IO-APIC !\n"); 635 else { 636 pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*14); 637 pci_read_config_dword(apicdev, 0xf4, &v); 638 v &= ~0x00000022; 639 pci_write_config_dword(apicdev, 0xf4, v); 640 pci_write_config_byte(apicdev, 0xf2, 0x10 + 2*15); 641 pci_read_config_dword(apicdev, 0xf4, &v); 642 v &= ~0x00000022; 643 pci_write_config_dword(apicdev, 0xf4, v); 644 pci_dev_put(apicdev); 645 } 646 } 647 #endif 648 } 649 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, 650 fixup_maple_ide); 651