1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ULI M1575 setup code - specific to Freescale boards 4 * 5 * Copyright 2007 Freescale Semiconductor Inc. 6 */ 7 8 #include <linux/stddef.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/interrupt.h> 12 #include <linux/mc146818rtc.h> 13 #include <linux/of_irq.h> 14 15 #include <asm/pci-bridge.h> 16 17 #define ULI_PIRQA 0x08 18 #define ULI_PIRQB 0x09 19 #define ULI_PIRQC 0x0a 20 #define ULI_PIRQD 0x0b 21 #define ULI_PIRQE 0x0c 22 #define ULI_PIRQF 0x0d 23 #define ULI_PIRQG 0x0e 24 25 #define ULI_8259_NONE 0x00 26 #define ULI_8259_IRQ1 0x08 27 #define ULI_8259_IRQ3 0x02 28 #define ULI_8259_IRQ4 0x04 29 #define ULI_8259_IRQ5 0x05 30 #define ULI_8259_IRQ6 0x07 31 #define ULI_8259_IRQ7 0x06 32 #define ULI_8259_IRQ9 0x01 33 #define ULI_8259_IRQ10 0x03 34 #define ULI_8259_IRQ11 0x09 35 #define ULI_8259_IRQ12 0x0b 36 #define ULI_8259_IRQ14 0x0d 37 #define ULI_8259_IRQ15 0x0f 38 39 u8 uli_pirq_to_irq[8] = { 40 ULI_8259_IRQ9, /* PIRQA */ 41 ULI_8259_IRQ10, /* PIRQB */ 42 ULI_8259_IRQ11, /* PIRQC */ 43 ULI_8259_IRQ12, /* PIRQD */ 44 ULI_8259_IRQ5, /* PIRQE */ 45 ULI_8259_IRQ6, /* PIRQF */ 46 ULI_8259_IRQ7, /* PIRQG */ 47 ULI_8259_NONE, /* PIRQH */ 48 }; 49 50 static inline bool is_quirk_valid(void) 51 { 52 return (machine_is(mpc86xx_hpcn) || 53 machine_is(mpc8544_ds) || 54 machine_is(p2020_ds) || 55 machine_is(mpc8572_ds)); 56 } 57 58 /* Bridge */ 59 static void early_uli5249(struct pci_dev *dev) 60 { 61 unsigned char temp; 62 63 if (!is_quirk_valid()) 64 return; 65 66 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO | 67 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 68 69 /* read/write lock */ 70 pci_read_config_byte(dev, 0x7c, &temp); 71 pci_write_config_byte(dev, 0x7c, 0x80); 72 73 /* set as P2P bridge */ 74 pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01); 75 dev->class |= 0x1; 76 77 /* restore lock */ 78 pci_write_config_byte(dev, 0x7c, temp); 79 } 80 81 82 static void quirk_uli1575(struct pci_dev *dev) 83 { 84 int i; 85 86 if (!is_quirk_valid()) 87 return; 88 89 /* 90 * ULI1575 interrupts route setup 91 */ 92 93 /* ULI1575 IRQ mapping conf register maps PIRQx to IRQn */ 94 for (i = 0; i < 4; i++) { 95 u8 val = uli_pirq_to_irq[i*2] | (uli_pirq_to_irq[i*2+1] << 4); 96 pci_write_config_byte(dev, 0x48 + i, val); 97 } 98 99 /* USB 1.1 OHCI controller 1: dev 28, func 0 - IRQ12 */ 100 pci_write_config_byte(dev, 0x86, ULI_PIRQD); 101 102 /* USB 1.1 OHCI controller 2: dev 28, func 1 - IRQ9 */ 103 pci_write_config_byte(dev, 0x87, ULI_PIRQA); 104 105 /* USB 1.1 OHCI controller 3: dev 28, func 2 - IRQ10 */ 106 pci_write_config_byte(dev, 0x88, ULI_PIRQB); 107 108 /* Lan controller: dev 27, func 0 - IRQ6 */ 109 pci_write_config_byte(dev, 0x89, ULI_PIRQF); 110 111 /* AC97 Audio controller: dev 29, func 0 - IRQ6 */ 112 pci_write_config_byte(dev, 0x8a, ULI_PIRQF); 113 114 /* Modem controller: dev 29, func 1 - IRQ6 */ 115 pci_write_config_byte(dev, 0x8b, ULI_PIRQF); 116 117 /* HD Audio controller: dev 29, func 2 - IRQ6 */ 118 pci_write_config_byte(dev, 0x8c, ULI_PIRQF); 119 120 /* SATA controller: dev 31, func 1 - IRQ5 */ 121 pci_write_config_byte(dev, 0x8d, ULI_PIRQE); 122 123 /* SMB interrupt: dev 30, func 1 - IRQ7 */ 124 pci_write_config_byte(dev, 0x8e, ULI_PIRQG); 125 126 /* PMU ACPI SCI interrupt: dev 30, func 2 - IRQ7 */ 127 pci_write_config_byte(dev, 0x8f, ULI_PIRQG); 128 129 /* USB 2.0 controller: dev 28, func 3 */ 130 pci_write_config_byte(dev, 0x74, ULI_8259_IRQ11); 131 132 /* Primary PATA IDE IRQ: 14 133 * Secondary PATA IDE IRQ: 15 134 */ 135 pci_write_config_byte(dev, 0x44, 0x30 | ULI_8259_IRQ14); 136 pci_write_config_byte(dev, 0x75, ULI_8259_IRQ15); 137 } 138 139 static void quirk_final_uli1575(struct pci_dev *dev) 140 { 141 /* Set i8259 interrupt trigger 142 * IRQ 3: Level 143 * IRQ 4: Level 144 * IRQ 5: Level 145 * IRQ 6: Level 146 * IRQ 7: Level 147 * IRQ 9: Level 148 * IRQ 10: Level 149 * IRQ 11: Level 150 * IRQ 12: Level 151 * IRQ 14: Edge 152 * IRQ 15: Edge 153 */ 154 if (!is_quirk_valid()) 155 return; 156 157 outb(0xfa, 0x4d0); 158 outb(0x1e, 0x4d1); 159 160 /* setup RTC */ 161 CMOS_WRITE(RTC_SET, RTC_CONTROL); 162 CMOS_WRITE(RTC_24H, RTC_CONTROL); 163 164 /* ensure month, date, and week alarm fields are ignored */ 165 CMOS_WRITE(0, RTC_VALID); 166 167 outb_p(0x7c, 0x72); 168 outb_p(RTC_ALARM_DONT_CARE, 0x73); 169 170 outb_p(0x7d, 0x72); 171 outb_p(RTC_ALARM_DONT_CARE, 0x73); 172 } 173 174 /* SATA */ 175 static void quirk_uli5288(struct pci_dev *dev) 176 { 177 unsigned char c; 178 unsigned int d; 179 180 if (!is_quirk_valid()) 181 return; 182 183 /* read/write lock */ 184 pci_read_config_byte(dev, 0x83, &c); 185 pci_write_config_byte(dev, 0x83, c|0x80); 186 187 pci_read_config_dword(dev, PCI_CLASS_REVISION, &d); 188 d = (d & 0xff) | (PCI_CLASS_STORAGE_SATA_AHCI << 8); 189 pci_write_config_dword(dev, PCI_CLASS_REVISION, d); 190 191 /* restore lock */ 192 pci_write_config_byte(dev, 0x83, c); 193 194 /* disable emulated PATA mode enabled */ 195 pci_read_config_byte(dev, 0x84, &c); 196 pci_write_config_byte(dev, 0x84, c & ~0x01); 197 } 198 199 /* PATA */ 200 static void quirk_uli5229(struct pci_dev *dev) 201 { 202 unsigned short temp; 203 204 if (!is_quirk_valid()) 205 return; 206 207 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE | 208 PCI_COMMAND_MASTER | PCI_COMMAND_IO); 209 210 /* Enable Native IRQ 14/15 */ 211 pci_read_config_word(dev, 0x4a, &temp); 212 pci_write_config_word(dev, 0x4a, temp | 0x1000); 213 } 214 215 /* We have to do a dummy read on the P2P for the RTC to work, WTF */ 216 static void quirk_final_uli5249(struct pci_dev *dev) 217 { 218 int i; 219 u8 *dummy; 220 struct pci_bus *bus = dev->bus; 221 struct resource *res; 222 resource_size_t end = 0; 223 224 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCES+3; i++) { 225 unsigned long flags = pci_resource_flags(dev, i); 226 if ((flags & (IORESOURCE_MEM|IORESOURCE_PREFETCH)) == IORESOURCE_MEM) 227 end = pci_resource_end(dev, i); 228 } 229 230 pci_bus_for_each_resource(bus, res, i) { 231 if (res && res->flags & IORESOURCE_MEM) { 232 if (res->end == end) 233 dummy = ioremap(res->start, 0x4); 234 else 235 dummy = ioremap(res->end - 3, 0x4); 236 if (dummy) { 237 in_8(dummy); 238 iounmap(dummy); 239 } 240 break; 241 } 242 } 243 } 244 245 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249); 246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575); 247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288); 248 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); 249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249); 250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575); 251 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); 252 253 static void hpcd_quirk_uli1575(struct pci_dev *dev) 254 { 255 u32 temp32; 256 257 if (!machine_is(mpc86xx_hpcd)) 258 return; 259 260 /* Disable INTx */ 261 pci_read_config_dword(dev, 0x48, &temp32); 262 pci_write_config_dword(dev, 0x48, (temp32 | 1<<26)); 263 264 /* Enable sideband interrupt */ 265 pci_read_config_dword(dev, 0x90, &temp32); 266 pci_write_config_dword(dev, 0x90, (temp32 | 1<<22)); 267 } 268 269 static void hpcd_quirk_uli5288(struct pci_dev *dev) 270 { 271 unsigned char c; 272 273 if (!machine_is(mpc86xx_hpcd)) 274 return; 275 276 pci_read_config_byte(dev, 0x83, &c); 277 c |= 0x80; 278 pci_write_config_byte(dev, 0x83, c); 279 280 pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01); 281 pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06); 282 283 pci_read_config_byte(dev, 0x83, &c); 284 c &= 0x7f; 285 pci_write_config_byte(dev, 0x83, c); 286 } 287 288 /* 289 * Since 8259PIC was disabled on the board, the IDE device can not 290 * use the legacy IRQ, we need to let the IDE device work under 291 * native mode and use the interrupt line like other PCI devices. 292 * IRQ14 is a sideband interrupt from IDE device to CPU and we use this 293 * as the interrupt for IDE device. 294 */ 295 static void hpcd_quirk_uli5229(struct pci_dev *dev) 296 { 297 unsigned char c; 298 299 if (!machine_is(mpc86xx_hpcd)) 300 return; 301 302 pci_read_config_byte(dev, 0x4b, &c); 303 c |= 0x10; 304 pci_write_config_byte(dev, 0x4b, c); 305 } 306 307 /* 308 * SATA interrupt pin bug fix 309 * There's a chip bug for 5288, The interrupt pin should be 2, 310 * not the read only value 1, So it use INTB#, not INTA# which 311 * actually used by the IDE device 5229. 312 * As of this bug, during the PCI initialization, 5288 read the 313 * irq of IDE device from the device tree, this function fix this 314 * bug by re-assigning a correct irq to 5288. 315 * 316 */ 317 static void hpcd_final_uli5288(struct pci_dev *dev) 318 { 319 struct pci_controller *hose = pci_bus_to_host(dev->bus); 320 struct device_node *hosenode = hose ? hose->dn : NULL; 321 struct of_phandle_args oirq; 322 u32 laddr[3]; 323 324 if (!machine_is(mpc86xx_hpcd)) 325 return; 326 327 if (!hosenode) 328 return; 329 330 oirq.np = hosenode; 331 oirq.args[0] = 2; 332 oirq.args_count = 1; 333 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8); 334 laddr[1] = laddr[2] = 0; 335 of_irq_parse_raw(laddr, &oirq); 336 dev->irq = irq_create_of_mapping(&oirq); 337 } 338 339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575); 340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, hpcd_quirk_uli5288); 341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, hpcd_quirk_uli5229); 342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, hpcd_final_uli5288); 343 344 int uli_exclude_device(struct pci_controller *hose, 345 u_char bus, u_char devfn) 346 { 347 if (bus == (hose->first_busno + 2)) { 348 /* exclude Modem controller */ 349 if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 1)) 350 return PCIBIOS_DEVICE_NOT_FOUND; 351 352 /* exclude HD Audio controller */ 353 if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 2)) 354 return PCIBIOS_DEVICE_NOT_FOUND; 355 } 356 357 return PCIBIOS_SUCCESSFUL; 358 } 359