1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ULI M1575 setup code - specific to Freescale boards 4 * 5 * Copyright 2007 Freescale Semiconductor Inc. 6 */ 7 8 #include <linux/stddef.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/interrupt.h> 12 #include <linux/mc146818rtc.h> 13 14 #include <asm/pci-bridge.h> 15 16 #define ULI_PIRQA 0x08 17 #define ULI_PIRQB 0x09 18 #define ULI_PIRQC 0x0a 19 #define ULI_PIRQD 0x0b 20 #define ULI_PIRQE 0x0c 21 #define ULI_PIRQF 0x0d 22 #define ULI_PIRQG 0x0e 23 24 #define ULI_8259_NONE 0x00 25 #define ULI_8259_IRQ1 0x08 26 #define ULI_8259_IRQ3 0x02 27 #define ULI_8259_IRQ4 0x04 28 #define ULI_8259_IRQ5 0x05 29 #define ULI_8259_IRQ6 0x07 30 #define ULI_8259_IRQ7 0x06 31 #define ULI_8259_IRQ9 0x01 32 #define ULI_8259_IRQ10 0x03 33 #define ULI_8259_IRQ11 0x09 34 #define ULI_8259_IRQ12 0x0b 35 #define ULI_8259_IRQ14 0x0d 36 #define ULI_8259_IRQ15 0x0f 37 38 u8 uli_pirq_to_irq[8] = { 39 ULI_8259_IRQ9, /* PIRQA */ 40 ULI_8259_IRQ10, /* PIRQB */ 41 ULI_8259_IRQ11, /* PIRQC */ 42 ULI_8259_IRQ12, /* PIRQD */ 43 ULI_8259_IRQ5, /* PIRQE */ 44 ULI_8259_IRQ6, /* PIRQF */ 45 ULI_8259_IRQ7, /* PIRQG */ 46 ULI_8259_NONE, /* PIRQH */ 47 }; 48 49 static inline bool is_quirk_valid(void) 50 { 51 return (machine_is(mpc86xx_hpcn) || 52 machine_is(mpc8544_ds) || 53 machine_is(p2020_ds) || 54 machine_is(mpc8572_ds)); 55 } 56 57 /* Bridge */ 58 static void early_uli5249(struct pci_dev *dev) 59 { 60 unsigned char temp; 61 62 if (!is_quirk_valid()) 63 return; 64 65 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO | 66 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 67 68 /* read/write lock */ 69 pci_read_config_byte(dev, 0x7c, &temp); 70 pci_write_config_byte(dev, 0x7c, 0x80); 71 72 /* set as P2P bridge */ 73 pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01); 74 dev->class |= 0x1; 75 76 /* restore lock */ 77 pci_write_config_byte(dev, 0x7c, temp); 78 } 79 80 81 static void quirk_uli1575(struct pci_dev *dev) 82 { 83 int i; 84 85 if (!is_quirk_valid()) 86 return; 87 88 /* 89 * ULI1575 interrupts route setup 90 */ 91 92 /* ULI1575 IRQ mapping conf register maps PIRQx to IRQn */ 93 for (i = 0; i < 4; i++) { 94 u8 val = uli_pirq_to_irq[i*2] | (uli_pirq_to_irq[i*2+1] << 4); 95 pci_write_config_byte(dev, 0x48 + i, val); 96 } 97 98 /* USB 1.1 OHCI controller 1: dev 28, func 0 - IRQ12 */ 99 pci_write_config_byte(dev, 0x86, ULI_PIRQD); 100 101 /* USB 1.1 OHCI controller 2: dev 28, func 1 - IRQ9 */ 102 pci_write_config_byte(dev, 0x87, ULI_PIRQA); 103 104 /* USB 1.1 OHCI controller 3: dev 28, func 2 - IRQ10 */ 105 pci_write_config_byte(dev, 0x88, ULI_PIRQB); 106 107 /* Lan controller: dev 27, func 0 - IRQ6 */ 108 pci_write_config_byte(dev, 0x89, ULI_PIRQF); 109 110 /* AC97 Audio controller: dev 29, func 0 - IRQ6 */ 111 pci_write_config_byte(dev, 0x8a, ULI_PIRQF); 112 113 /* Modem controller: dev 29, func 1 - IRQ6 */ 114 pci_write_config_byte(dev, 0x8b, ULI_PIRQF); 115 116 /* HD Audio controller: dev 29, func 2 - IRQ6 */ 117 pci_write_config_byte(dev, 0x8c, ULI_PIRQF); 118 119 /* SATA controller: dev 31, func 1 - IRQ5 */ 120 pci_write_config_byte(dev, 0x8d, ULI_PIRQE); 121 122 /* SMB interrupt: dev 30, func 1 - IRQ7 */ 123 pci_write_config_byte(dev, 0x8e, ULI_PIRQG); 124 125 /* PMU ACPI SCI interrupt: dev 30, func 2 - IRQ7 */ 126 pci_write_config_byte(dev, 0x8f, ULI_PIRQG); 127 128 /* USB 2.0 controller: dev 28, func 3 */ 129 pci_write_config_byte(dev, 0x74, ULI_8259_IRQ11); 130 131 /* Primary PATA IDE IRQ: 14 132 * Secondary PATA IDE IRQ: 15 133 */ 134 pci_write_config_byte(dev, 0x44, 0x30 | ULI_8259_IRQ14); 135 pci_write_config_byte(dev, 0x75, ULI_8259_IRQ15); 136 } 137 138 static void quirk_final_uli1575(struct pci_dev *dev) 139 { 140 /* Set i8259 interrupt trigger 141 * IRQ 3: Level 142 * IRQ 4: Level 143 * IRQ 5: Level 144 * IRQ 6: Level 145 * IRQ 7: Level 146 * IRQ 9: Level 147 * IRQ 10: Level 148 * IRQ 11: Level 149 * IRQ 12: Level 150 * IRQ 14: Edge 151 * IRQ 15: Edge 152 */ 153 if (!is_quirk_valid()) 154 return; 155 156 outb(0xfa, 0x4d0); 157 outb(0x1e, 0x4d1); 158 159 /* setup RTC */ 160 CMOS_WRITE(RTC_SET, RTC_CONTROL); 161 CMOS_WRITE(RTC_24H, RTC_CONTROL); 162 163 /* ensure month, date, and week alarm fields are ignored */ 164 CMOS_WRITE(0, RTC_VALID); 165 166 outb_p(0x7c, 0x72); 167 outb_p(RTC_ALARM_DONT_CARE, 0x73); 168 169 outb_p(0x7d, 0x72); 170 outb_p(RTC_ALARM_DONT_CARE, 0x73); 171 } 172 173 /* SATA */ 174 static void quirk_uli5288(struct pci_dev *dev) 175 { 176 unsigned char c; 177 unsigned int d; 178 179 if (!is_quirk_valid()) 180 return; 181 182 /* read/write lock */ 183 pci_read_config_byte(dev, 0x83, &c); 184 pci_write_config_byte(dev, 0x83, c|0x80); 185 186 pci_read_config_dword(dev, PCI_CLASS_REVISION, &d); 187 d = (d & 0xff) | (PCI_CLASS_STORAGE_SATA_AHCI << 8); 188 pci_write_config_dword(dev, PCI_CLASS_REVISION, d); 189 190 /* restore lock */ 191 pci_write_config_byte(dev, 0x83, c); 192 193 /* disable emulated PATA mode enabled */ 194 pci_read_config_byte(dev, 0x84, &c); 195 pci_write_config_byte(dev, 0x84, c & ~0x01); 196 } 197 198 /* PATA */ 199 static void quirk_uli5229(struct pci_dev *dev) 200 { 201 unsigned short temp; 202 203 if (!is_quirk_valid()) 204 return; 205 206 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE | 207 PCI_COMMAND_MASTER | PCI_COMMAND_IO); 208 209 /* Enable Native IRQ 14/15 */ 210 pci_read_config_word(dev, 0x4a, &temp); 211 pci_write_config_word(dev, 0x4a, temp | 0x1000); 212 } 213 214 /* We have to do a dummy read on the P2P for the RTC to work, WTF */ 215 static void quirk_final_uli5249(struct pci_dev *dev) 216 { 217 int i; 218 u8 *dummy; 219 struct pci_bus *bus = dev->bus; 220 struct resource *res; 221 resource_size_t end = 0; 222 223 for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCES+3; i++) { 224 unsigned long flags = pci_resource_flags(dev, i); 225 if ((flags & (IORESOURCE_MEM|IORESOURCE_PREFETCH)) == IORESOURCE_MEM) 226 end = pci_resource_end(dev, i); 227 } 228 229 pci_bus_for_each_resource(bus, res, i) { 230 if (res && res->flags & IORESOURCE_MEM) { 231 if (res->end == end) 232 dummy = ioremap(res->start, 0x4); 233 else 234 dummy = ioremap(res->end - 3, 0x4); 235 if (dummy) { 236 in_8(dummy); 237 iounmap(dummy); 238 } 239 break; 240 } 241 } 242 } 243 244 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249); 245 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575); 246 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288); 247 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); 248 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249); 249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575); 250 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); 251 252 static void hpcd_quirk_uli1575(struct pci_dev *dev) 253 { 254 u32 temp32; 255 256 if (!machine_is(mpc86xx_hpcd)) 257 return; 258 259 /* Disable INTx */ 260 pci_read_config_dword(dev, 0x48, &temp32); 261 pci_write_config_dword(dev, 0x48, (temp32 | 1<<26)); 262 263 /* Enable sideband interrupt */ 264 pci_read_config_dword(dev, 0x90, &temp32); 265 pci_write_config_dword(dev, 0x90, (temp32 | 1<<22)); 266 } 267 268 static void hpcd_quirk_uli5288(struct pci_dev *dev) 269 { 270 unsigned char c; 271 272 if (!machine_is(mpc86xx_hpcd)) 273 return; 274 275 pci_read_config_byte(dev, 0x83, &c); 276 c |= 0x80; 277 pci_write_config_byte(dev, 0x83, c); 278 279 pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01); 280 pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06); 281 282 pci_read_config_byte(dev, 0x83, &c); 283 c &= 0x7f; 284 pci_write_config_byte(dev, 0x83, c); 285 } 286 287 /* 288 * Since 8259PIC was disabled on the board, the IDE device can not 289 * use the legacy IRQ, we need to let the IDE device work under 290 * native mode and use the interrupt line like other PCI devices. 291 * IRQ14 is a sideband interrupt from IDE device to CPU and we use this 292 * as the interrupt for IDE device. 293 */ 294 static void hpcd_quirk_uli5229(struct pci_dev *dev) 295 { 296 unsigned char c; 297 298 if (!machine_is(mpc86xx_hpcd)) 299 return; 300 301 pci_read_config_byte(dev, 0x4b, &c); 302 c |= 0x10; 303 pci_write_config_byte(dev, 0x4b, c); 304 } 305 306 /* 307 * SATA interrupt pin bug fix 308 * There's a chip bug for 5288, The interrupt pin should be 2, 309 * not the read only value 1, So it use INTB#, not INTA# which 310 * actually used by the IDE device 5229. 311 * As of this bug, during the PCI initialization, 5288 read the 312 * irq of IDE device from the device tree, this function fix this 313 * bug by re-assigning a correct irq to 5288. 314 * 315 */ 316 static void hpcd_final_uli5288(struct pci_dev *dev) 317 { 318 struct pci_controller *hose = pci_bus_to_host(dev->bus); 319 struct device_node *hosenode = hose ? hose->dn : NULL; 320 struct of_phandle_args oirq; 321 u32 laddr[3]; 322 323 if (!machine_is(mpc86xx_hpcd)) 324 return; 325 326 if (!hosenode) 327 return; 328 329 oirq.np = hosenode; 330 oirq.args[0] = 2; 331 oirq.args_count = 1; 332 laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8); 333 laddr[1] = laddr[2] = 0; 334 of_irq_parse_raw(laddr, &oirq); 335 dev->irq = irq_create_of_mapping(&oirq); 336 } 337 338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575); 339 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, hpcd_quirk_uli5288); 340 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, hpcd_quirk_uli5229); 341 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, hpcd_final_uli5288); 342 343 int uli_exclude_device(struct pci_controller *hose, 344 u_char bus, u_char devfn) 345 { 346 if (bus == (hose->first_busno + 2)) { 347 /* exclude Modem controller */ 348 if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 1)) 349 return PCIBIOS_DEVICE_NOT_FOUND; 350 351 /* exclude HD Audio controller */ 352 if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 2)) 353 return PCIBIOS_DEVICE_NOT_FOUND; 354 } 355 356 return PCIBIOS_SUCCESSFUL; 357 } 358