1b66510cbSKumar Gala /* 2b66510cbSKumar Gala * ULI M1575 setup code - specific to Freescale boards 3b66510cbSKumar Gala * 4b66510cbSKumar Gala * Copyright 2007 Freescale Semiconductor Inc. 5b66510cbSKumar Gala * 6b66510cbSKumar Gala * This program is free software; you can redistribute it and/or modify it 7b66510cbSKumar Gala * under the terms of the GNU General Public License as published by the 8b66510cbSKumar Gala * Free Software Foundation; either version 2 of the License, or (at your 9b66510cbSKumar Gala * option) any later version. 10b66510cbSKumar Gala */ 11b66510cbSKumar Gala 12b66510cbSKumar Gala #include <linux/stddef.h> 13b66510cbSKumar Gala #include <linux/kernel.h> 14b66510cbSKumar Gala #include <linux/pci.h> 15b66510cbSKumar Gala #include <linux/interrupt.h> 16b66510cbSKumar Gala #include <linux/mc146818rtc.h> 17b66510cbSKumar Gala 18b66510cbSKumar Gala #include <asm/pci-bridge.h> 19b66510cbSKumar Gala 20b66510cbSKumar Gala #define ULI_PIRQA 0x08 21b66510cbSKumar Gala #define ULI_PIRQB 0x09 22b66510cbSKumar Gala #define ULI_PIRQC 0x0a 23b66510cbSKumar Gala #define ULI_PIRQD 0x0b 24b66510cbSKumar Gala #define ULI_PIRQE 0x0c 25b66510cbSKumar Gala #define ULI_PIRQF 0x0d 26b66510cbSKumar Gala #define ULI_PIRQG 0x0e 27b66510cbSKumar Gala 28b66510cbSKumar Gala #define ULI_8259_NONE 0x00 29b66510cbSKumar Gala #define ULI_8259_IRQ1 0x08 30b66510cbSKumar Gala #define ULI_8259_IRQ3 0x02 31b66510cbSKumar Gala #define ULI_8259_IRQ4 0x04 32b66510cbSKumar Gala #define ULI_8259_IRQ5 0x05 33b66510cbSKumar Gala #define ULI_8259_IRQ6 0x07 34b66510cbSKumar Gala #define ULI_8259_IRQ7 0x06 35b66510cbSKumar Gala #define ULI_8259_IRQ9 0x01 36b66510cbSKumar Gala #define ULI_8259_IRQ10 0x03 37b66510cbSKumar Gala #define ULI_8259_IRQ11 0x09 38b66510cbSKumar Gala #define ULI_8259_IRQ12 0x0b 39b66510cbSKumar Gala #define ULI_8259_IRQ14 0x0d 40b66510cbSKumar Gala #define ULI_8259_IRQ15 0x0f 41b66510cbSKumar Gala 42b66510cbSKumar Gala u8 uli_pirq_to_irq[8] = { 43b66510cbSKumar Gala ULI_8259_IRQ9, /* PIRQA */ 44b66510cbSKumar Gala ULI_8259_IRQ10, /* PIRQB */ 45b66510cbSKumar Gala ULI_8259_IRQ11, /* PIRQC */ 46b66510cbSKumar Gala ULI_8259_IRQ12, /* PIRQD */ 47b66510cbSKumar Gala ULI_8259_IRQ5, /* PIRQE */ 48b66510cbSKumar Gala ULI_8259_IRQ6, /* PIRQF */ 49b66510cbSKumar Gala ULI_8259_IRQ7, /* PIRQG */ 50b66510cbSKumar Gala ULI_8259_NONE, /* PIRQH */ 51b66510cbSKumar Gala }; 52b66510cbSKumar Gala 539bf8b274SKumar Gala static inline bool is_quirk_valid(void) 549bf8b274SKumar Gala { 559bf8b274SKumar Gala return (machine_is(mpc86xx_hpcn) || 569bf8b274SKumar Gala machine_is(mpc8544_ds) || 5701af9507SKumar Gala machine_is(p2020_ds) || 589bf8b274SKumar Gala machine_is(mpc8572_ds)); 599bf8b274SKumar Gala } 609bf8b274SKumar Gala 61b66510cbSKumar Gala /* Bridge */ 62cad5cef6SGreg Kroah-Hartman static void early_uli5249(struct pci_dev *dev) 63b66510cbSKumar Gala { 64b66510cbSKumar Gala unsigned char temp; 65b66510cbSKumar Gala 669bf8b274SKumar Gala if (!is_quirk_valid()) 67b66510cbSKumar Gala return; 68b66510cbSKumar Gala 69b66510cbSKumar Gala pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO | 70b66510cbSKumar Gala PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 71b66510cbSKumar Gala 72b66510cbSKumar Gala /* read/write lock */ 73b66510cbSKumar Gala pci_read_config_byte(dev, 0x7c, &temp); 74b66510cbSKumar Gala pci_write_config_byte(dev, 0x7c, 0x80); 75b66510cbSKumar Gala 76b66510cbSKumar Gala /* set as P2P bridge */ 77b66510cbSKumar Gala pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01); 78b66510cbSKumar Gala dev->class |= 0x1; 79b66510cbSKumar Gala 80b66510cbSKumar Gala /* restore lock */ 81b66510cbSKumar Gala pci_write_config_byte(dev, 0x7c, temp); 82b66510cbSKumar Gala } 83b66510cbSKumar Gala 84b66510cbSKumar Gala 85cad5cef6SGreg Kroah-Hartman static void quirk_uli1575(struct pci_dev *dev) 86b66510cbSKumar Gala { 87b66510cbSKumar Gala int i; 88b66510cbSKumar Gala 899bf8b274SKumar Gala if (!is_quirk_valid()) 90b66510cbSKumar Gala return; 91b66510cbSKumar Gala 92b66510cbSKumar Gala /* 93b66510cbSKumar Gala * ULI1575 interrupts route setup 94b66510cbSKumar Gala */ 95b66510cbSKumar Gala 96b66510cbSKumar Gala /* ULI1575 IRQ mapping conf register maps PIRQx to IRQn */ 97b66510cbSKumar Gala for (i = 0; i < 4; i++) { 98b66510cbSKumar Gala u8 val = uli_pirq_to_irq[i*2] | (uli_pirq_to_irq[i*2+1] << 4); 99b66510cbSKumar Gala pci_write_config_byte(dev, 0x48 + i, val); 100b66510cbSKumar Gala } 101b66510cbSKumar Gala 102b66510cbSKumar Gala /* USB 1.1 OHCI controller 1: dev 28, func 0 - IRQ12 */ 103b66510cbSKumar Gala pci_write_config_byte(dev, 0x86, ULI_PIRQD); 104b66510cbSKumar Gala 105b66510cbSKumar Gala /* USB 1.1 OHCI controller 2: dev 28, func 1 - IRQ9 */ 106b66510cbSKumar Gala pci_write_config_byte(dev, 0x87, ULI_PIRQA); 107b66510cbSKumar Gala 108b66510cbSKumar Gala /* USB 1.1 OHCI controller 3: dev 28, func 2 - IRQ10 */ 109b66510cbSKumar Gala pci_write_config_byte(dev, 0x88, ULI_PIRQB); 110b66510cbSKumar Gala 111b66510cbSKumar Gala /* Lan controller: dev 27, func 0 - IRQ6 */ 112b66510cbSKumar Gala pci_write_config_byte(dev, 0x89, ULI_PIRQF); 113b66510cbSKumar Gala 114b66510cbSKumar Gala /* AC97 Audio controller: dev 29, func 0 - IRQ6 */ 115b66510cbSKumar Gala pci_write_config_byte(dev, 0x8a, ULI_PIRQF); 116b66510cbSKumar Gala 117b66510cbSKumar Gala /* Modem controller: dev 29, func 1 - IRQ6 */ 118b66510cbSKumar Gala pci_write_config_byte(dev, 0x8b, ULI_PIRQF); 119b66510cbSKumar Gala 120b66510cbSKumar Gala /* HD Audio controller: dev 29, func 2 - IRQ6 */ 121b66510cbSKumar Gala pci_write_config_byte(dev, 0x8c, ULI_PIRQF); 122b66510cbSKumar Gala 123b66510cbSKumar Gala /* SATA controller: dev 31, func 1 - IRQ5 */ 124b66510cbSKumar Gala pci_write_config_byte(dev, 0x8d, ULI_PIRQE); 125b66510cbSKumar Gala 126b66510cbSKumar Gala /* SMB interrupt: dev 30, func 1 - IRQ7 */ 127b66510cbSKumar Gala pci_write_config_byte(dev, 0x8e, ULI_PIRQG); 128b66510cbSKumar Gala 129b66510cbSKumar Gala /* PMU ACPI SCI interrupt: dev 30, func 2 - IRQ7 */ 130b66510cbSKumar Gala pci_write_config_byte(dev, 0x8f, ULI_PIRQG); 131b66510cbSKumar Gala 132b66510cbSKumar Gala /* USB 2.0 controller: dev 28, func 3 */ 133b66510cbSKumar Gala pci_write_config_byte(dev, 0x74, ULI_8259_IRQ11); 134b66510cbSKumar Gala 135b66510cbSKumar Gala /* Primary PATA IDE IRQ: 14 136b66510cbSKumar Gala * Secondary PATA IDE IRQ: 15 137b66510cbSKumar Gala */ 138b66510cbSKumar Gala pci_write_config_byte(dev, 0x44, 0x30 | ULI_8259_IRQ14); 139b66510cbSKumar Gala pci_write_config_byte(dev, 0x75, ULI_8259_IRQ15); 140b66510cbSKumar Gala } 141b66510cbSKumar Gala 142cad5cef6SGreg Kroah-Hartman static void quirk_final_uli1575(struct pci_dev *dev) 143b66510cbSKumar Gala { 144b66510cbSKumar Gala /* Set i8259 interrupt trigger 145b66510cbSKumar Gala * IRQ 3: Level 146b66510cbSKumar Gala * IRQ 4: Level 147b66510cbSKumar Gala * IRQ 5: Level 148b66510cbSKumar Gala * IRQ 6: Level 149b66510cbSKumar Gala * IRQ 7: Level 150b66510cbSKumar Gala * IRQ 9: Level 151b66510cbSKumar Gala * IRQ 10: Level 152b66510cbSKumar Gala * IRQ 11: Level 153b66510cbSKumar Gala * IRQ 12: Level 154b66510cbSKumar Gala * IRQ 14: Edge 155b66510cbSKumar Gala * IRQ 15: Edge 156b66510cbSKumar Gala */ 1579bf8b274SKumar Gala if (!is_quirk_valid()) 158b66510cbSKumar Gala return; 159b66510cbSKumar Gala 160b66510cbSKumar Gala outb(0xfa, 0x4d0); 161b66510cbSKumar Gala outb(0x1e, 0x4d1); 162b66510cbSKumar Gala 163b66510cbSKumar Gala /* setup RTC */ 164b66510cbSKumar Gala CMOS_WRITE(RTC_SET, RTC_CONTROL); 165b66510cbSKumar Gala CMOS_WRITE(RTC_24H, RTC_CONTROL); 166b66510cbSKumar Gala 167b66510cbSKumar Gala /* ensure month, date, and week alarm fields are ignored */ 168b66510cbSKumar Gala CMOS_WRITE(0, RTC_VALID); 169b66510cbSKumar Gala 170b66510cbSKumar Gala outb_p(0x7c, 0x72); 171b66510cbSKumar Gala outb_p(RTC_ALARM_DONT_CARE, 0x73); 172b66510cbSKumar Gala 173b66510cbSKumar Gala outb_p(0x7d, 0x72); 174b66510cbSKumar Gala outb_p(RTC_ALARM_DONT_CARE, 0x73); 175b66510cbSKumar Gala } 176b66510cbSKumar Gala 177b66510cbSKumar Gala /* SATA */ 178cad5cef6SGreg Kroah-Hartman static void quirk_uli5288(struct pci_dev *dev) 179b66510cbSKumar Gala { 180b66510cbSKumar Gala unsigned char c; 181b66510cbSKumar Gala unsigned int d; 182b66510cbSKumar Gala 1839bf8b274SKumar Gala if (!is_quirk_valid()) 184b66510cbSKumar Gala return; 185b66510cbSKumar Gala 186b66510cbSKumar Gala /* read/write lock */ 187b66510cbSKumar Gala pci_read_config_byte(dev, 0x83, &c); 188b66510cbSKumar Gala pci_write_config_byte(dev, 0x83, c|0x80); 189b66510cbSKumar Gala 190b66510cbSKumar Gala pci_read_config_dword(dev, PCI_CLASS_REVISION, &d); 191b66510cbSKumar Gala d = (d & 0xff) | (PCI_CLASS_STORAGE_SATA_AHCI << 8); 192b66510cbSKumar Gala pci_write_config_dword(dev, PCI_CLASS_REVISION, d); 193b66510cbSKumar Gala 194b66510cbSKumar Gala /* restore lock */ 195b66510cbSKumar Gala pci_write_config_byte(dev, 0x83, c); 196b66510cbSKumar Gala 197b66510cbSKumar Gala /* disable emulated PATA mode enabled */ 198b66510cbSKumar Gala pci_read_config_byte(dev, 0x84, &c); 199b66510cbSKumar Gala pci_write_config_byte(dev, 0x84, c & ~0x01); 200b66510cbSKumar Gala } 201b66510cbSKumar Gala 202b66510cbSKumar Gala /* PATA */ 203cad5cef6SGreg Kroah-Hartman static void quirk_uli5229(struct pci_dev *dev) 204b66510cbSKumar Gala { 205b66510cbSKumar Gala unsigned short temp; 206b66510cbSKumar Gala 2079bf8b274SKumar Gala if (!is_quirk_valid()) 208b66510cbSKumar Gala return; 209b66510cbSKumar Gala 210b66510cbSKumar Gala pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE | 211b66510cbSKumar Gala PCI_COMMAND_MASTER | PCI_COMMAND_IO); 212b66510cbSKumar Gala 213b66510cbSKumar Gala /* Enable Native IRQ 14/15 */ 214b66510cbSKumar Gala pci_read_config_word(dev, 0x4a, &temp); 215b66510cbSKumar Gala pci_write_config_word(dev, 0x4a, temp | 0x1000); 216b66510cbSKumar Gala } 217b66510cbSKumar Gala 218b66510cbSKumar Gala /* We have to do a dummy read on the P2P for the RTC to work, WTF */ 219cad5cef6SGreg Kroah-Hartman static void quirk_final_uli5249(struct pci_dev *dev) 220b66510cbSKumar Gala { 221b66510cbSKumar Gala int i; 222b66510cbSKumar Gala u8 *dummy; 223b66510cbSKumar Gala struct pci_bus *bus = dev->bus; 22489a74eccSBjorn Helgaas struct resource *res; 2251fce2d01SKumar Gala resource_size_t end = 0; 2261fce2d01SKumar Gala 2271fce2d01SKumar Gala for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCES+3; i++) { 2281fce2d01SKumar Gala unsigned long flags = pci_resource_flags(dev, i); 2291fce2d01SKumar Gala if ((flags & (IORESOURCE_MEM|IORESOURCE_PREFETCH)) == IORESOURCE_MEM) 2301fce2d01SKumar Gala end = pci_resource_end(dev, i); 2311fce2d01SKumar Gala } 232b66510cbSKumar Gala 23389a74eccSBjorn Helgaas pci_bus_for_each_resource(bus, res, i) { 23489a74eccSBjorn Helgaas if (res && res->flags & IORESOURCE_MEM) { 23589a74eccSBjorn Helgaas if (res->end == end) 23689a74eccSBjorn Helgaas dummy = ioremap(res->start, 0x4); 2371fce2d01SKumar Gala else 23889a74eccSBjorn Helgaas dummy = ioremap(res->end - 3, 0x4); 239b66510cbSKumar Gala if (dummy) { 240b66510cbSKumar Gala in_8(dummy); 241b66510cbSKumar Gala iounmap(dummy); 242b66510cbSKumar Gala } 243b66510cbSKumar Gala break; 244b66510cbSKumar Gala } 245b66510cbSKumar Gala } 246b66510cbSKumar Gala } 247b66510cbSKumar Gala 248b66510cbSKumar Gala DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249); 249b66510cbSKumar Gala DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575); 250b66510cbSKumar Gala DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288); 251b66510cbSKumar Gala DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); 252b66510cbSKumar Gala DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5249, quirk_final_uli5249); 253b66510cbSKumar Gala DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x1575, quirk_final_uli1575); 2541433fa7dSJason Jin DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229); 255b66510cbSKumar Gala 256cad5cef6SGreg Kroah-Hartman static void hpcd_quirk_uli1575(struct pci_dev *dev) 25752ddd1cdSAnton Vorontsov { 25852ddd1cdSAnton Vorontsov u32 temp32; 25952ddd1cdSAnton Vorontsov 26052ddd1cdSAnton Vorontsov if (!machine_is(mpc86xx_hpcd)) 26152ddd1cdSAnton Vorontsov return; 26252ddd1cdSAnton Vorontsov 26352ddd1cdSAnton Vorontsov /* Disable INTx */ 26452ddd1cdSAnton Vorontsov pci_read_config_dword(dev, 0x48, &temp32); 26552ddd1cdSAnton Vorontsov pci_write_config_dword(dev, 0x48, (temp32 | 1<<26)); 26652ddd1cdSAnton Vorontsov 26752ddd1cdSAnton Vorontsov /* Enable sideband interrupt */ 26852ddd1cdSAnton Vorontsov pci_read_config_dword(dev, 0x90, &temp32); 26952ddd1cdSAnton Vorontsov pci_write_config_dword(dev, 0x90, (temp32 | 1<<22)); 27052ddd1cdSAnton Vorontsov } 27152ddd1cdSAnton Vorontsov 272cad5cef6SGreg Kroah-Hartman static void hpcd_quirk_uli5288(struct pci_dev *dev) 27352ddd1cdSAnton Vorontsov { 27452ddd1cdSAnton Vorontsov unsigned char c; 27552ddd1cdSAnton Vorontsov 27652ddd1cdSAnton Vorontsov if (!machine_is(mpc86xx_hpcd)) 27752ddd1cdSAnton Vorontsov return; 27852ddd1cdSAnton Vorontsov 27952ddd1cdSAnton Vorontsov pci_read_config_byte(dev, 0x83, &c); 28052ddd1cdSAnton Vorontsov c |= 0x80; 28152ddd1cdSAnton Vorontsov pci_write_config_byte(dev, 0x83, c); 28252ddd1cdSAnton Vorontsov 28352ddd1cdSAnton Vorontsov pci_write_config_byte(dev, PCI_CLASS_PROG, 0x01); 28452ddd1cdSAnton Vorontsov pci_write_config_byte(dev, PCI_CLASS_DEVICE, 0x06); 28552ddd1cdSAnton Vorontsov 28652ddd1cdSAnton Vorontsov pci_read_config_byte(dev, 0x83, &c); 28752ddd1cdSAnton Vorontsov c &= 0x7f; 28852ddd1cdSAnton Vorontsov pci_write_config_byte(dev, 0x83, c); 28952ddd1cdSAnton Vorontsov } 29052ddd1cdSAnton Vorontsov 29152ddd1cdSAnton Vorontsov /* 29252ddd1cdSAnton Vorontsov * Since 8259PIC was disabled on the board, the IDE device can not 29352ddd1cdSAnton Vorontsov * use the legacy IRQ, we need to let the IDE device work under 29452ddd1cdSAnton Vorontsov * native mode and use the interrupt line like other PCI devices. 29552ddd1cdSAnton Vorontsov * IRQ14 is a sideband interrupt from IDE device to CPU and we use this 29652ddd1cdSAnton Vorontsov * as the interrupt for IDE device. 29752ddd1cdSAnton Vorontsov */ 298cad5cef6SGreg Kroah-Hartman static void hpcd_quirk_uli5229(struct pci_dev *dev) 29952ddd1cdSAnton Vorontsov { 30052ddd1cdSAnton Vorontsov unsigned char c; 30152ddd1cdSAnton Vorontsov 30252ddd1cdSAnton Vorontsov if (!machine_is(mpc86xx_hpcd)) 30352ddd1cdSAnton Vorontsov return; 30452ddd1cdSAnton Vorontsov 30552ddd1cdSAnton Vorontsov pci_read_config_byte(dev, 0x4b, &c); 30652ddd1cdSAnton Vorontsov c |= 0x10; 30752ddd1cdSAnton Vorontsov pci_write_config_byte(dev, 0x4b, c); 30852ddd1cdSAnton Vorontsov } 30952ddd1cdSAnton Vorontsov 31052ddd1cdSAnton Vorontsov /* 31152ddd1cdSAnton Vorontsov * SATA interrupt pin bug fix 31252ddd1cdSAnton Vorontsov * There's a chip bug for 5288, The interrupt pin should be 2, 31352ddd1cdSAnton Vorontsov * not the read only value 1, So it use INTB#, not INTA# which 31452ddd1cdSAnton Vorontsov * actually used by the IDE device 5229. 31552ddd1cdSAnton Vorontsov * As of this bug, during the PCI initialization, 5288 read the 31652ddd1cdSAnton Vorontsov * irq of IDE device from the device tree, this function fix this 31752ddd1cdSAnton Vorontsov * bug by re-assigning a correct irq to 5288. 31852ddd1cdSAnton Vorontsov * 31952ddd1cdSAnton Vorontsov */ 320cad5cef6SGreg Kroah-Hartman static void hpcd_final_uli5288(struct pci_dev *dev) 32152ddd1cdSAnton Vorontsov { 32252ddd1cdSAnton Vorontsov struct pci_controller *hose = pci_bus_to_host(dev->bus); 32352ddd1cdSAnton Vorontsov struct device_node *hosenode = hose ? hose->dn : NULL; 32452ddd1cdSAnton Vorontsov struct of_irq oirq; 32552ddd1cdSAnton Vorontsov int virq, pin = 2; 32652ddd1cdSAnton Vorontsov u32 laddr[3]; 32752ddd1cdSAnton Vorontsov 32852ddd1cdSAnton Vorontsov if (!machine_is(mpc86xx_hpcd)) 32952ddd1cdSAnton Vorontsov return; 33052ddd1cdSAnton Vorontsov 33152ddd1cdSAnton Vorontsov if (!hosenode) 33252ddd1cdSAnton Vorontsov return; 33352ddd1cdSAnton Vorontsov 33452ddd1cdSAnton Vorontsov laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(31, 0) << 8); 33552ddd1cdSAnton Vorontsov laddr[1] = laddr[2] = 0; 33652ddd1cdSAnton Vorontsov of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq); 33752ddd1cdSAnton Vorontsov virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 33852ddd1cdSAnton Vorontsov oirq.size); 33952ddd1cdSAnton Vorontsov dev->irq = virq; 34052ddd1cdSAnton Vorontsov } 34152ddd1cdSAnton Vorontsov 34252ddd1cdSAnton Vorontsov DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, hpcd_quirk_uli1575); 34352ddd1cdSAnton Vorontsov DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, hpcd_quirk_uli5288); 34452ddd1cdSAnton Vorontsov DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, hpcd_quirk_uli5229); 34552ddd1cdSAnton Vorontsov DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, hpcd_final_uli5288); 34652ddd1cdSAnton Vorontsov 347b66510cbSKumar Gala int uli_exclude_device(struct pci_controller *hose, 348b66510cbSKumar Gala u_char bus, u_char devfn) 349b66510cbSKumar Gala { 350b66510cbSKumar Gala if (bus == (hose->first_busno + 2)) { 351b66510cbSKumar Gala /* exclude Modem controller */ 352b66510cbSKumar Gala if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 1)) 353b66510cbSKumar Gala return PCIBIOS_DEVICE_NOT_FOUND; 354b66510cbSKumar Gala 355b66510cbSKumar Gala /* exclude HD Audio controller */ 356b66510cbSKumar Gala if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 2)) 357b66510cbSKumar Gala return PCIBIOS_DEVICE_NOT_FOUND; 358b66510cbSKumar Gala } 359b66510cbSKumar Gala 360b66510cbSKumar Gala return PCIBIOS_SUCCESSFUL; 361b66510cbSKumar Gala } 362