133d71d26SKumar Gala /* 233d71d26SKumar Gala * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem 333d71d26SKumar Gala * ctlr/EPIC/etc. 433d71d26SKumar Gala * 533d71d26SKumar Gala * Author: Mark A. Greer 633d71d26SKumar Gala * mgreer@mvista.com 733d71d26SKumar Gala * 833d71d26SKumar Gala * 2001 (c) MontaVista, Software, Inc. This file is licensed under 933d71d26SKumar Gala * the terms of the GNU General Public License version 2. This program 1033d71d26SKumar Gala * is licensed "as is" without any warranty of any kind, whether express 1133d71d26SKumar Gala * or implied. 1233d71d26SKumar Gala */ 1333d71d26SKumar Gala #ifndef __PPC_KERNEL_MPC10X_H 1433d71d26SKumar Gala #define __PPC_KERNEL_MPC10X_H 1533d71d26SKumar Gala 1633d71d26SKumar Gala #include <linux/pci_ids.h> 1733d71d26SKumar Gala #include <asm/pci-bridge.h> 1833d71d26SKumar Gala 1933d71d26SKumar Gala /* 2033d71d26SKumar Gala * The values here don't completely map everything but should work in most 2133d71d26SKumar Gala * cases. 2233d71d26SKumar Gala * 2333d71d26SKumar Gala * MAP A (PReP Map) 2433d71d26SKumar Gala * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff 2533d71d26SKumar Gala * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff 2633d71d26SKumar Gala * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 2733d71d26SKumar Gala * 2833d71d26SKumar Gala * MAP B (CHRP Map) 2933d71d26SKumar Gala * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff 3033d71d26SKumar Gala * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff 3133d71d26SKumar Gala * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 3233d71d26SKumar Gala */ 3333d71d26SKumar Gala 3433d71d26SKumar Gala /* 3533d71d26SKumar Gala * Define the vendor/device IDs for the various bridges--should be added to 3633d71d26SKumar Gala * <linux/pci_ids.h> 3733d71d26SKumar Gala */ 3833d71d26SKumar Gala #define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ 3933d71d26SKumar Gala PCI_VENDOR_ID_MOTOROLA) 4033d71d26SKumar Gala #define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) 4133d71d26SKumar Gala #define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) 4233d71d26SKumar Gala #define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) 4333d71d26SKumar Gala 4433d71d26SKumar Gala /* Define the type of map to use */ 4533d71d26SKumar Gala #define MPC10X_MEM_MAP_A 1 4633d71d26SKumar Gala #define MPC10X_MEM_MAP_B 2 4733d71d26SKumar Gala 4833d71d26SKumar Gala /* Map A (PReP Map) Defines */ 4933d71d26SKumar Gala #define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 5033d71d26SKumar Gala #define MPC10X_MAPA_CNFG_DATA 0x80000cfc 5133d71d26SKumar Gala 5233d71d26SKumar Gala #define MPC10X_MAPA_ISA_IO_BASE 0x80000000 5333d71d26SKumar Gala #define MPC10X_MAPA_ISA_MEM_BASE 0xc0000000 5433d71d26SKumar Gala #define MPC10X_MAPA_DRAM_OFFSET 0x80000000 5533d71d26SKumar Gala 5633d71d26SKumar Gala #define MPC10X_MAPA_PCI_INTACK_ADDR 0xbffffff0 5733d71d26SKumar Gala #define MPC10X_MAPA_PCI_IO_START 0x00000000 5833d71d26SKumar Gala #define MPC10X_MAPA_PCI_IO_END (0x00800000 - 1) 5933d71d26SKumar Gala #define MPC10X_MAPA_PCI_MEM_START 0x00000000 6033d71d26SKumar Gala #define MPC10X_MAPA_PCI_MEM_END (0x20000000 - 1) 6133d71d26SKumar Gala 6233d71d26SKumar Gala #define MPC10X_MAPA_PCI_MEM_OFFSET (MPC10X_MAPA_ISA_MEM_BASE - \ 6333d71d26SKumar Gala MPC10X_MAPA_PCI_MEM_START) 6433d71d26SKumar Gala 6533d71d26SKumar Gala /* Map B (CHRP Map) Defines */ 6633d71d26SKumar Gala #define MPC10X_MAPB_CNFG_ADDR 0xfec00000 6733d71d26SKumar Gala #define MPC10X_MAPB_CNFG_DATA 0xfee00000 6833d71d26SKumar Gala 6933d71d26SKumar Gala #define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 7033d71d26SKumar Gala #define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 7133d71d26SKumar Gala #define MPC10X_MAPB_DRAM_OFFSET 0x00000000 7233d71d26SKumar Gala 7333d71d26SKumar Gala #define MPC10X_MAPB_PCI_INTACK_ADDR 0xfef00000 7433d71d26SKumar Gala #define MPC10X_MAPB_PCI_IO_START 0x00000000 7533d71d26SKumar Gala #define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) 7633d71d26SKumar Gala #define MPC10X_MAPB_PCI_MEM_START 0x80000000 7733d71d26SKumar Gala #define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) 7833d71d26SKumar Gala 7933d71d26SKumar Gala #define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ 8033d71d26SKumar Gala MPC10X_MAPB_PCI_MEM_START) 8133d71d26SKumar Gala 8233d71d26SKumar Gala /* Miscellaneous Configuration register offsets */ 8333d71d26SKumar Gala #define MPC10X_CFG_PIR_REG 0x09 8433d71d26SKumar Gala #define MPC10X_CFG_PIR_HOST_BRIDGE 0x00 8533d71d26SKumar Gala #define MPC10X_CFG_PIR_AGENT 0x01 8633d71d26SKumar Gala 8733d71d26SKumar Gala #define MPC10X_CFG_EUMBBAR 0x78 8833d71d26SKumar Gala 8933d71d26SKumar Gala #define MPC10X_CFG_PICR1_REG 0xa8 9033d71d26SKumar Gala #define MPC10X_CFG_PICR1_ADDR_MAP_MASK 0x00010000 9133d71d26SKumar Gala #define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000 9233d71d26SKumar Gala #define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000 9333d71d26SKumar Gala #define MPC10X_CFG_PICR1_SPEC_PCI_RD 0x00000004 9433d71d26SKumar Gala #define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040 9533d71d26SKumar Gala 9633d71d26SKumar Gala #define MPC10X_CFG_PICR2_REG 0xac 9733d71d26SKumar Gala #define MPC10X_CFG_PICR2_COPYBACK_OPT 0x00000001 9833d71d26SKumar Gala 9933d71d26SKumar Gala #define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0 10033d71d26SKumar Gala #define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ 10133d71d26SKumar Gala #define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ 10233d71d26SKumar Gala #define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */ 10333d71d26SKumar Gala #define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x08 /* PCI_COMPATIBILITY_HOLE */ 10433d71d26SKumar Gala #define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x04 /* PROC_COMPATIBILITY_HOLE */ 10533d71d26SKumar Gala 10633d71d26SKumar Gala /* Define offsets for the memory controller registers in the config space */ 10733d71d26SKumar Gala #define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ 10833d71d26SKumar Gala #define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ 10933d71d26SKumar Gala #define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ 11033d71d26SKumar Gala #define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ 11133d71d26SKumar Gala 11233d71d26SKumar Gala #define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ 11333d71d26SKumar Gala #define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */ 11433d71d26SKumar Gala #define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ 11533d71d26SKumar Gala #define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ 11633d71d26SKumar Gala 11733d71d26SKumar Gala #define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 11833d71d26SKumar Gala 11933d71d26SKumar Gala /* Define some offset in the EUMB */ 12033d71d26SKumar Gala #define MPC10X_EUMB_SIZE 0x00100000 /* Total EUMB size (1MB) */ 12133d71d26SKumar Gala 12233d71d26SKumar Gala #define MPC10X_EUMB_MU_OFFSET 0x00000000 /* Msg Unit reg offset */ 12333d71d26SKumar Gala #define MPC10X_EUMB_MU_SIZE 0x00001000 /* Msg Unit reg size */ 12433d71d26SKumar Gala #define MPC10X_EUMB_DMA_OFFSET 0x00001000 /* DMA Unit reg offset */ 12533d71d26SKumar Gala #define MPC10X_EUMB_DMA_SIZE 0x00001000 /* DMA Unit reg size */ 12633d71d26SKumar Gala #define MPC10X_EUMB_ATU_OFFSET 0x00002000 /* Addr xlate reg offset */ 12733d71d26SKumar Gala #define MPC10X_EUMB_ATU_SIZE 0x00001000 /* Addr xlate reg size */ 12833d71d26SKumar Gala #define MPC10X_EUMB_I2C_OFFSET 0x00003000 /* I2C Unit reg offset */ 12933d71d26SKumar Gala #define MPC10X_EUMB_I2C_SIZE 0x00001000 /* I2C Unit reg size */ 13033d71d26SKumar Gala #define MPC10X_EUMB_DUART_OFFSET 0x00004000 /* DUART Unit reg offset (8245) */ 13133d71d26SKumar Gala #define MPC10X_EUMB_DUART_SIZE 0x00001000 /* DUART Unit reg size (8245) */ 13233d71d26SKumar Gala #define MPC10X_EUMB_EPIC_OFFSET 0x00040000 /* EPIC offset in EUMB */ 13333d71d26SKumar Gala #define MPC10X_EUMB_EPIC_SIZE 0x00030000 /* EPIC size */ 13433d71d26SKumar Gala #define MPC10X_EUMB_PM_OFFSET 0x000fe000 /* Performance Monitor reg offset (8245) */ 13533d71d26SKumar Gala #define MPC10X_EUMB_PM_SIZE 0x00001000 /* Performance Monitor reg size (8245) */ 13633d71d26SKumar Gala #define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */ 13733d71d26SKumar Gala #define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */ 13833d71d26SKumar Gala 13933d71d26SKumar Gala enum ppc_sys_devices { 14033d71d26SKumar Gala MPC10X_IIC1, 14133d71d26SKumar Gala MPC10X_DMA0, 14233d71d26SKumar Gala MPC10X_DMA1, 14333d71d26SKumar Gala MPC10X_UART0, 14433d71d26SKumar Gala MPC10X_UART1, 14533d71d26SKumar Gala NUM_PPC_SYS_DEVS, 14633d71d26SKumar Gala }; 14733d71d26SKumar Gala 14833d71d26SKumar Gala int mpc10x_bridge_init(struct pci_controller *hose, 14933d71d26SKumar Gala uint current_map, 15033d71d26SKumar Gala uint new_map, 15133d71d26SKumar Gala uint phys_eumb_base); 15233d71d26SKumar Gala unsigned long mpc10x_get_mem_size(uint mem_map); 15333d71d26SKumar Gala int mpc10x_enable_store_gathering(struct pci_controller *hose); 15433d71d26SKumar Gala int mpc10x_disable_store_gathering(struct pci_controller *hose); 15533d71d26SKumar Gala 15633d71d26SKumar Gala /* For MPC107 boards that use the built-in openpic */ 15733d71d26SKumar Gala void mpc10x_set_openpic(void); 15833d71d26SKumar Gala 159*ffc331a3SMichael Ellerman void avr_uart_configure(void); 160*ffc331a3SMichael Ellerman void avr_uart_send(const char c); 161*ffc331a3SMichael Ellerman 16233d71d26SKumar Gala #endif /* __PPC_KERNEL_MPC10X_H */ 163