1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Board setup routines for the IBM 750GX/CL platform w/ TSI10x bridge 4 * 5 * Copyright 2007 IBM Corporation 6 * 7 * Stephen Winiecki <stevewin@us.ibm.com> 8 * Josh Boyer <jwboyer@linux.vnet.ibm.com> 9 * 10 * Based on code from mpc7448_hpc2.c 11 */ 12 13 #include <linux/stddef.h> 14 #include <linux/kernel.h> 15 #include <linux/pci.h> 16 #include <linux/kdev_t.h> 17 #include <linux/console.h> 18 #include <linux/delay.h> 19 #include <linux/irq.h> 20 #include <linux/seq_file.h> 21 #include <linux/root_dev.h> 22 #include <linux/serial.h> 23 #include <linux/tty.h> 24 #include <linux/serial_core.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_platform.h> 28 #include <linux/extable.h> 29 30 #include <asm/time.h> 31 #include <asm/machdep.h> 32 #include <asm/udbg.h> 33 #include <asm/tsi108.h> 34 #include <asm/pci-bridge.h> 35 #include <asm/reg.h> 36 #include <mm/mmu_decl.h> 37 #include <asm/tsi108_irq.h> 38 #include <asm/tsi108_pci.h> 39 #include <asm/mpic.h> 40 41 #undef DEBUG 42 43 #define HOLLY_PCI_CFG_PHYS 0x7c000000 44 45 static int holly_exclude_device(struct pci_controller *hose, u_char bus, 46 u_char devfn) 47 { 48 if (bus == 0 && PCI_SLOT(devfn) == 0) 49 return PCIBIOS_DEVICE_NOT_FOUND; 50 else 51 return PCIBIOS_SUCCESSFUL; 52 } 53 54 static void __init holly_remap_bridge(void) 55 { 56 u32 lut_val, lut_addr; 57 int i; 58 59 printk(KERN_INFO "Remapping PCI bridge\n"); 60 61 /* Re-init the PCI bridge and LUT registers to have mappings that don't 62 * rely on PIBS 63 */ 64 lut_addr = 0x900; 65 for (i = 0; i < 31; i++) { 66 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x00000201); 67 lut_addr += 4; 68 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x0); 69 lut_addr += 4; 70 } 71 72 /* Reserve the last LUT entry for PCI I/O space */ 73 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x00000241); 74 lut_addr += 4; 75 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x0); 76 77 /* Map PCI I/O space */ 78 tsi108_write_reg(TSI108_PCI_PFAB_IO_UPPER, 0x0); 79 tsi108_write_reg(TSI108_PCI_PFAB_IO, 0x1); 80 81 /* Map PCI CFG space */ 82 tsi108_write_reg(TSI108_PCI_PFAB_BAR0_UPPER, 0x0); 83 tsi108_write_reg(TSI108_PCI_PFAB_BAR0, 0x7c000000 | 0x01); 84 85 /* We don't need MEM32 and PRM remapping so disable them */ 86 tsi108_write_reg(TSI108_PCI_PFAB_MEM32, 0x0); 87 tsi108_write_reg(TSI108_PCI_PFAB_PFM3, 0x0); 88 tsi108_write_reg(TSI108_PCI_PFAB_PFM4, 0x0); 89 90 /* Set P2O_BAR0 */ 91 tsi108_write_reg(TSI108_PCI_P2O_BAR0_UPPER, 0x0); 92 tsi108_write_reg(TSI108_PCI_P2O_BAR0, 0xc0000000); 93 94 /* Init the PCI LUTs to do no remapping */ 95 lut_addr = 0x500; 96 lut_val = 0x00000002; 97 98 for (i = 0; i < 32; i++) { 99 tsi108_write_reg(TSI108_PCI_OFFSET + lut_addr, lut_val); 100 lut_addr += 4; 101 tsi108_write_reg(TSI108_PCI_OFFSET + lut_addr, 0x40000000); 102 lut_addr += 4; 103 lut_val += 0x02000000; 104 } 105 tsi108_write_reg(TSI108_PCI_P2O_PAGE_SIZES, 0x00007900); 106 107 /* Set 64-bit PCI bus address for system memory */ 108 tsi108_write_reg(TSI108_PCI_P2O_BAR2_UPPER, 0x0); 109 tsi108_write_reg(TSI108_PCI_P2O_BAR2, 0x0); 110 } 111 112 static void __init holly_init_pci(void) 113 { 114 struct device_node *np; 115 116 if (ppc_md.progress) 117 ppc_md.progress("holly_setup_arch():set_bridge", 0); 118 119 /* setup PCI host bridge */ 120 holly_remap_bridge(); 121 122 np = of_find_node_by_type(NULL, "pci"); 123 if (np) 124 tsi108_setup_pci(np, HOLLY_PCI_CFG_PHYS, 1); 125 126 of_node_put(np); 127 128 ppc_md.pci_exclude_device = holly_exclude_device; 129 if (ppc_md.progress) 130 ppc_md.progress("tsi108: resources set", 0x100); 131 } 132 133 static void __init holly_setup_arch(void) 134 { 135 tsi108_csr_vir_base = get_vir_csrbase(); 136 137 printk(KERN_INFO "PPC750GX/CL Platform\n"); 138 } 139 140 /* 141 * Interrupt setup and service. Interrupts on the holly come 142 * from the four external INT pins, PCI interrupts are routed via 143 * PCI interrupt control registers, it generates internal IRQ23 144 * 145 * Interrupt routing on the Holly Board: 146 * TSI108:PB_INT[0] -> CPU0:INT# 147 * TSI108:PB_INT[1] -> CPU0:MCP# 148 * TSI108:PB_INT[2] -> N/C 149 * TSI108:PB_INT[3] -> N/C 150 */ 151 static void __init holly_init_IRQ(void) 152 { 153 struct mpic *mpic; 154 #ifdef CONFIG_PCI 155 unsigned int cascade_pci_irq; 156 struct device_node *tsi_pci; 157 struct device_node *cascade_node = NULL; 158 #endif 159 160 mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | 161 MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108, 162 24, 0, 163 "Tsi108_PIC"); 164 165 BUG_ON(mpic == NULL); 166 167 mpic_assign_isu(mpic, 0, mpic->paddr + 0x100); 168 169 mpic_init(mpic); 170 171 #ifdef CONFIG_PCI 172 tsi_pci = of_find_node_by_type(NULL, "pci"); 173 if (tsi_pci == NULL) { 174 printk(KERN_ERR "%s: No tsi108 pci node found !\n", __func__); 175 return; 176 } 177 178 cascade_node = of_find_node_by_type(NULL, "pic-router"); 179 if (cascade_node == NULL) { 180 printk(KERN_ERR "%s: No tsi108 pci cascade node found !\n", __func__); 181 return; 182 } 183 184 cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0); 185 pr_debug("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq); 186 tsi108_pci_int_init(cascade_node); 187 irq_set_handler_data(cascade_pci_irq, mpic); 188 irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade); 189 190 of_node_put(tsi_pci); 191 of_node_put(cascade_node); 192 #endif 193 /* Configure MPIC outputs to CPU0 */ 194 tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0); 195 } 196 197 static void holly_show_cpuinfo(struct seq_file *m) 198 { 199 seq_printf(m, "vendor\t\t: IBM\n"); 200 seq_printf(m, "machine\t\t: PPC750 GX/CL\n"); 201 } 202 203 static void __noreturn holly_restart(char *cmd) 204 { 205 __be32 __iomem *ocn_bar1 = NULL; 206 unsigned long bar; 207 struct device_node *bridge = NULL; 208 struct resource res; 209 phys_addr_t addr = 0xc0000000; 210 211 local_irq_disable(); 212 213 bridge = of_find_node_by_type(NULL, "tsi-bridge"); 214 if (bridge) { 215 of_address_to_resource(bridge, 0, &res); 216 addr = res.start; 217 of_node_put(bridge); 218 } 219 addr += (TSI108_PB_OFFSET + 0x414); 220 221 ocn_bar1 = ioremap(addr, 0x4); 222 223 /* Turn on the BOOT bit so the addresses are correctly 224 * routed to the HLP interface */ 225 bar = ioread32be(ocn_bar1); 226 bar |= 2; 227 iowrite32be(bar, ocn_bar1); 228 iosync(); 229 230 /* Set SRR0 to the reset vector and turn on MSR_IP */ 231 mtspr(SPRN_SRR0, 0xfff00100); 232 mtspr(SPRN_SRR1, MSR_IP); 233 234 /* Do an rfi to jump back to firmware. Somewhat evil, 235 * but it works 236 */ 237 __asm__ __volatile__("rfi" : : : "memory"); 238 239 /* Spin until reset happens. Shouldn't really get here */ 240 for (;;) ; 241 } 242 243 static int ppc750_machine_check_exception(struct pt_regs *regs) 244 { 245 const struct exception_table_entry *entry; 246 247 /* Are we prepared to handle this fault */ 248 if ((entry = search_exception_tables(regs->nip)) != NULL) { 249 tsi108_clear_pci_cfg_error(); 250 regs_set_recoverable(regs); 251 regs_set_return_ip(regs, extable_fixup(entry)); 252 return 1; 253 } 254 return 0; 255 } 256 257 define_machine(holly){ 258 .name = "PPC750 GX/CL TSI", 259 .compatible = "ibm,holly", 260 .setup_arch = holly_setup_arch, 261 .discover_phbs = holly_init_pci, 262 .init_IRQ = holly_init_IRQ, 263 .show_cpuinfo = holly_show_cpuinfo, 264 .get_irq = mpic_get_irq, 265 .restart = holly_restart, 266 .machine_check_exception = ppc750_machine_check_exception, 267 .progress = udbg_progress, 268 }; 269