1 /* 2 * arch/powerpc/platforms/embedded6xx/hlwd-pic.c 3 * 4 * Nintendo Wii "Hollywood" interrupt controller support. 5 * Copyright (C) 2009 The GameCube Linux Team 6 * Copyright (C) 2009 Albert Herranz 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 2 11 * of the License, or (at your option) any later version. 12 * 13 */ 14 #define DRV_MODULE_NAME "hlwd-pic" 15 #define pr_fmt(fmt) DRV_MODULE_NAME ": " fmt 16 17 #include <linux/kernel.h> 18 #include <linux/init.h> 19 #include <linux/irq.h> 20 #include <linux/of.h> 21 #include <asm/io.h> 22 23 #include "hlwd-pic.h" 24 25 #define HLWD_NR_IRQS 32 26 27 /* 28 * Each interrupt has a corresponding bit in both 29 * the Interrupt Cause (ICR) and Interrupt Mask (IMR) registers. 30 * 31 * Enabling/disabling an interrupt line involves asserting/clearing 32 * the corresponding bit in IMR. ACK'ing a request simply involves 33 * asserting the corresponding bit in ICR. 34 */ 35 #define HW_BROADWAY_ICR 0x00 36 #define HW_BROADWAY_IMR 0x04 37 38 39 /* 40 * IRQ chip hooks. 41 * 42 */ 43 44 static void hlwd_pic_mask_and_ack(struct irq_data *d) 45 { 46 int irq = irqd_to_hwirq(d); 47 void __iomem *io_base = irq_data_get_irq_chip_data(d); 48 u32 mask = 1 << irq; 49 50 clrbits32(io_base + HW_BROADWAY_IMR, mask); 51 out_be32(io_base + HW_BROADWAY_ICR, mask); 52 } 53 54 static void hlwd_pic_ack(struct irq_data *d) 55 { 56 int irq = irqd_to_hwirq(d); 57 void __iomem *io_base = irq_data_get_irq_chip_data(d); 58 59 out_be32(io_base + HW_BROADWAY_ICR, 1 << irq); 60 } 61 62 static void hlwd_pic_mask(struct irq_data *d) 63 { 64 int irq = irqd_to_hwirq(d); 65 void __iomem *io_base = irq_data_get_irq_chip_data(d); 66 67 clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq); 68 } 69 70 static void hlwd_pic_unmask(struct irq_data *d) 71 { 72 int irq = irqd_to_hwirq(d); 73 void __iomem *io_base = irq_data_get_irq_chip_data(d); 74 75 setbits32(io_base + HW_BROADWAY_IMR, 1 << irq); 76 } 77 78 79 static struct irq_chip hlwd_pic = { 80 .name = "hlwd-pic", 81 .irq_ack = hlwd_pic_ack, 82 .irq_mask_ack = hlwd_pic_mask_and_ack, 83 .irq_mask = hlwd_pic_mask, 84 .irq_unmask = hlwd_pic_unmask, 85 }; 86 87 /* 88 * IRQ host hooks. 89 * 90 */ 91 92 static struct irq_domain *hlwd_irq_host; 93 94 static int hlwd_pic_map(struct irq_domain *h, unsigned int virq, 95 irq_hw_number_t hwirq) 96 { 97 irq_set_chip_data(virq, h->host_data); 98 irq_set_status_flags(virq, IRQ_LEVEL); 99 irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq); 100 return 0; 101 } 102 103 static const struct irq_domain_ops hlwd_irq_domain_ops = { 104 .map = hlwd_pic_map, 105 }; 106 107 static unsigned int __hlwd_pic_get_irq(struct irq_domain *h) 108 { 109 void __iomem *io_base = h->host_data; 110 int irq; 111 u32 irq_status; 112 113 irq_status = in_be32(io_base + HW_BROADWAY_ICR) & 114 in_be32(io_base + HW_BROADWAY_IMR); 115 if (irq_status == 0) 116 return NO_IRQ; /* no more IRQs pending */ 117 118 irq = __ffs(irq_status); 119 return irq_linear_revmap(h, irq); 120 } 121 122 static void hlwd_pic_irq_cascade(unsigned int cascade_virq, 123 struct irq_desc *desc) 124 { 125 struct irq_chip *chip = irq_desc_get_chip(desc); 126 struct irq_domain *irq_domain = irq_get_handler_data(cascade_virq); 127 unsigned int virq; 128 129 raw_spin_lock(&desc->lock); 130 chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */ 131 raw_spin_unlock(&desc->lock); 132 133 virq = __hlwd_pic_get_irq(irq_domain); 134 if (virq != NO_IRQ) 135 generic_handle_irq(virq); 136 else 137 pr_err("spurious interrupt!\n"); 138 139 raw_spin_lock(&desc->lock); 140 chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */ 141 if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask) 142 chip->irq_unmask(&desc->irq_data); 143 raw_spin_unlock(&desc->lock); 144 } 145 146 /* 147 * Platform hooks. 148 * 149 */ 150 151 static void __hlwd_quiesce(void __iomem *io_base) 152 { 153 /* mask and ack all IRQs */ 154 out_be32(io_base + HW_BROADWAY_IMR, 0); 155 out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff); 156 } 157 158 struct irq_domain *hlwd_pic_init(struct device_node *np) 159 { 160 struct irq_domain *irq_domain; 161 struct resource res; 162 void __iomem *io_base; 163 int retval; 164 165 retval = of_address_to_resource(np, 0, &res); 166 if (retval) { 167 pr_err("no io memory range found\n"); 168 return NULL; 169 } 170 io_base = ioremap(res.start, resource_size(&res)); 171 if (!io_base) { 172 pr_err("ioremap failed\n"); 173 return NULL; 174 } 175 176 pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base); 177 178 __hlwd_quiesce(io_base); 179 180 irq_domain = irq_domain_add_linear(np, HLWD_NR_IRQS, 181 &hlwd_irq_domain_ops, io_base); 182 if (!irq_domain) { 183 pr_err("failed to allocate irq_domain\n"); 184 return NULL; 185 } 186 187 return irq_domain; 188 } 189 190 unsigned int hlwd_pic_get_irq(void) 191 { 192 return __hlwd_pic_get_irq(hlwd_irq_host); 193 } 194 195 /* 196 * Probe function. 197 * 198 */ 199 200 void hlwd_pic_probe(void) 201 { 202 struct irq_domain *host; 203 struct device_node *np; 204 const u32 *interrupts; 205 int cascade_virq; 206 207 for_each_compatible_node(np, NULL, "nintendo,hollywood-pic") { 208 interrupts = of_get_property(np, "interrupts", NULL); 209 if (interrupts) { 210 host = hlwd_pic_init(np); 211 BUG_ON(!host); 212 cascade_virq = irq_of_parse_and_map(np, 0); 213 irq_set_handler_data(cascade_virq, host); 214 irq_set_chained_handler(cascade_virq, 215 hlwd_pic_irq_cascade); 216 hlwd_irq_host = host; 217 break; 218 } 219 } 220 } 221 222 /** 223 * hlwd_quiesce() - quiesce hollywood irq controller 224 * 225 * Mask and ack all interrupt sources. 226 * 227 */ 228 void hlwd_quiesce(void) 229 { 230 void __iomem *io_base = hlwd_irq_host->host_data; 231 232 __hlwd_quiesce(io_base); 233 } 234 235