1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 1995 Linus Torvalds 4 * Adapted from 'alpha' version by Gary Thomas 5 * Modified by Cort Dougan (cort@cs.nmt.edu) 6 */ 7 8 /* 9 * bootup setup stuff.. 10 */ 11 12 #include <linux/errno.h> 13 #include <linux/sched.h> 14 #include <linux/kernel.h> 15 #include <linux/mm.h> 16 #include <linux/stddef.h> 17 #include <linux/unistd.h> 18 #include <linux/ptrace.h> 19 #include <linux/user.h> 20 #include <linux/tty.h> 21 #include <linux/major.h> 22 #include <linux/interrupt.h> 23 #include <linux/reboot.h> 24 #include <linux/init.h> 25 #include <linux/pci.h> 26 #include <generated/utsrelease.h> 27 #include <linux/adb.h> 28 #include <linux/module.h> 29 #include <linux/delay.h> 30 #include <linux/console.h> 31 #include <linux/seq_file.h> 32 #include <linux/root_dev.h> 33 #include <linux/initrd.h> 34 #include <linux/timer.h> 35 #include <linux/of_address.h> 36 #include <linux/of_fdt.h> 37 #include <linux/of_irq.h> 38 39 #include <asm/io.h> 40 #include <asm/pci-bridge.h> 41 #include <asm/dma.h> 42 #include <asm/machdep.h> 43 #include <asm/irq.h> 44 #include <asm/hydra.h> 45 #include <asm/sections.h> 46 #include <asm/time.h> 47 #include <asm/i8259.h> 48 #include <asm/mpic.h> 49 #include <asm/rtas.h> 50 #include <asm/xmon.h> 51 52 #include "chrp.h" 53 #include "gg2.h" 54 55 void rtas_indicator_progress(char *, unsigned short); 56 57 int _chrp_type; 58 EXPORT_SYMBOL(_chrp_type); 59 60 static struct mpic *chrp_mpic; 61 62 /* Used for doing CHRP event-scans */ 63 DEFINE_PER_CPU(struct timer_list, heartbeat_timer); 64 unsigned long event_scan_interval; 65 66 extern unsigned long loops_per_jiffy; 67 68 /* To be replaced by RTAS when available */ 69 static unsigned int __iomem *briq_SPOR; 70 71 #ifdef CONFIG_SMP 72 extern struct smp_ops_t chrp_smp_ops; 73 #endif 74 75 static const char *gg2_memtypes[4] = { 76 "FPM", "SDRAM", "EDO", "BEDO" 77 }; 78 static const char *gg2_cachesizes[4] = { 79 "256 KB", "512 KB", "1 MB", "Reserved" 80 }; 81 static const char *gg2_cachetypes[4] = { 82 "Asynchronous", "Reserved", "Flow-Through Synchronous", 83 "Pipelined Synchronous" 84 }; 85 static const char *gg2_cachemodes[4] = { 86 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode" 87 }; 88 89 static const char *chrp_names[] = { 90 "Unknown", 91 "","","", 92 "Motorola", 93 "IBM or Longtrail", 94 "Genesi Pegasos", 95 "Total Impact Briq" 96 }; 97 98 static void chrp_show_cpuinfo(struct seq_file *m) 99 { 100 int i, sdramen; 101 unsigned int t; 102 struct device_node *root; 103 const char *model = ""; 104 105 root = of_find_node_by_path("/"); 106 if (root) 107 model = of_get_property(root, "model", NULL); 108 seq_printf(m, "machine\t\t: CHRP %s\n", model); 109 110 /* longtrail (goldengate) stuff */ 111 if (model && !strncmp(model, "IBM,LongTrail", 13)) { 112 /* VLSI VAS96011/12 `Golden Gate 2' */ 113 /* Memory banks */ 114 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL) 115 >>31) & 1; 116 for (i = 0; i < (sdramen ? 4 : 6); i++) { 117 t = in_le32(gg2_pci_config_base+ 118 GG2_PCI_DRAM_BANK0+ 119 i*4); 120 if (!(t & 1)) 121 continue; 122 switch ((t>>8) & 0x1f) { 123 case 0x1f: 124 model = "4 MB"; 125 break; 126 case 0x1e: 127 model = "8 MB"; 128 break; 129 case 0x1c: 130 model = "16 MB"; 131 break; 132 case 0x18: 133 model = "32 MB"; 134 break; 135 case 0x10: 136 model = "64 MB"; 137 break; 138 case 0x00: 139 model = "128 MB"; 140 break; 141 default: 142 model = "Reserved"; 143 break; 144 } 145 seq_printf(m, "memory bank %d\t: %s %s\n", i, model, 146 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]); 147 } 148 /* L2 cache */ 149 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL); 150 seq_printf(m, "board l2\t: %s %s (%s)\n", 151 gg2_cachesizes[(t>>7) & 3], 152 gg2_cachetypes[(t>>2) & 3], 153 gg2_cachemodes[t & 3]); 154 } 155 of_node_put(root); 156 } 157 158 /* 159 * Fixes for the National Semiconductor PC78308VUL SuperI/O 160 * 161 * Some versions of Open Firmware incorrectly initialize the IRQ settings 162 * for keyboard and mouse 163 */ 164 static inline void __init sio_write(u8 val, u8 index) 165 { 166 outb(index, 0x15c); 167 outb(val, 0x15d); 168 } 169 170 static inline u8 __init sio_read(u8 index) 171 { 172 outb(index, 0x15c); 173 return inb(0x15d); 174 } 175 176 static void __init sio_fixup_irq(const char *name, u8 device, u8 level, 177 u8 type) 178 { 179 u8 level0, type0, active; 180 181 /* select logical device */ 182 sio_write(device, 0x07); 183 active = sio_read(0x30); 184 level0 = sio_read(0x70); 185 type0 = sio_read(0x71); 186 if (level0 != level || type0 != type || !active) { 187 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: " 188 "remapping to level %d, type %d, active\n", 189 name, level0, type0, !active ? "in" : "", level, type); 190 sio_write(0x01, 0x30); 191 sio_write(level, 0x70); 192 sio_write(type, 0x71); 193 } 194 } 195 196 static void __init sio_init(void) 197 { 198 struct device_node *root; 199 const char *model; 200 201 root = of_find_node_by_path("/"); 202 if (!root) 203 return; 204 205 model = of_get_property(root, "model", NULL); 206 if (model && !strncmp(model, "IBM,LongTrail", 13)) { 207 /* logical device 0 (KBC/Keyboard) */ 208 sio_fixup_irq("keyboard", 0, 1, 2); 209 /* select logical device 1 (KBC/Mouse) */ 210 sio_fixup_irq("mouse", 1, 12, 2); 211 } 212 213 of_node_put(root); 214 } 215 216 217 static void __init pegasos_set_l2cr(void) 218 { 219 struct device_node *np; 220 221 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */ 222 if (_chrp_type != _CHRP_Pegasos) 223 return; 224 225 /* Enable L2 cache if needed */ 226 np = of_find_node_by_type(NULL, "cpu"); 227 if (np != NULL) { 228 const unsigned int *l2cr = of_get_property(np, "l2cr", NULL); 229 if (l2cr == NULL) { 230 printk ("Pegasos l2cr : no cpu l2cr property found\n"); 231 goto out; 232 } 233 if (!((*l2cr) & 0x80000000)) { 234 printk ("Pegasos l2cr : L2 cache was not active, " 235 "activating\n"); 236 _set_L2CR(0); 237 _set_L2CR((*l2cr) | 0x80000000); 238 } 239 } 240 out: 241 of_node_put(np); 242 } 243 244 static void __noreturn briq_restart(char *cmd) 245 { 246 local_irq_disable(); 247 if (briq_SPOR) 248 out_be32(briq_SPOR, 0); 249 for(;;); 250 } 251 252 /* 253 * Per default, input/output-device points to the keyboard/screen 254 * If no card is installed, the built-in serial port is used as a fallback. 255 * But unfortunately, the firmware does not connect /chosen/{stdin,stdout} 256 * to the built-in serial node. Instead, a /failsafe node is created. 257 */ 258 static __init void chrp_init(void) 259 { 260 struct device_node *node; 261 const char *property; 262 263 if (strstr(boot_command_line, "console=")) 264 return; 265 /* find the boot console from /chosen/stdout */ 266 if (!of_chosen) 267 return; 268 node = of_find_node_by_path("/"); 269 if (!node) 270 return; 271 property = of_get_property(node, "model", NULL); 272 if (!property) 273 goto out_put; 274 if (strcmp(property, "Pegasos2")) 275 goto out_put; 276 /* this is a Pegasos2 */ 277 property = of_get_property(of_chosen, "linux,stdout-path", NULL); 278 if (!property) 279 goto out_put; 280 of_node_put(node); 281 node = of_find_node_by_path(property); 282 if (!node) 283 return; 284 if (!of_node_is_type(node, "serial")) 285 goto out_put; 286 /* 287 * The 9pin connector is either /failsafe 288 * or /pci@80000000/isa@C/serial@i2F8 289 * The optional graphics card has also type 'serial' in VGA mode. 290 */ 291 if (of_node_name_eq(node, "failsafe") || of_node_name_eq(node, "serial")) 292 add_preferred_console("ttyS", 0, NULL); 293 out_put: 294 of_node_put(node); 295 } 296 297 static void __init chrp_setup_arch(void) 298 { 299 struct device_node *root = of_find_node_by_path("/"); 300 const char *machine = NULL; 301 302 /* init to some ~sane value until calibrate_delay() runs */ 303 loops_per_jiffy = 50000000/HZ; 304 305 if (root) 306 machine = of_get_property(root, "model", NULL); 307 if (machine && strncmp(machine, "Pegasos", 7) == 0) { 308 _chrp_type = _CHRP_Pegasos; 309 } else if (machine && strncmp(machine, "IBM", 3) == 0) { 310 _chrp_type = _CHRP_IBM; 311 } else if (machine && strncmp(machine, "MOT", 3) == 0) { 312 _chrp_type = _CHRP_Motorola; 313 } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) { 314 _chrp_type = _CHRP_briq; 315 /* Map the SPOR register on briq and change the restart hook */ 316 briq_SPOR = ioremap(0xff0000e8, 4); 317 ppc_md.restart = briq_restart; 318 } else { 319 /* Let's assume it is an IBM chrp if all else fails */ 320 _chrp_type = _CHRP_IBM; 321 } 322 of_node_put(root); 323 printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]); 324 325 rtas_initialize(); 326 if (rtas_function_token(RTAS_FN_DISPLAY_CHARACTER) >= 0) 327 ppc_md.progress = rtas_progress; 328 329 /* use RTAS time-of-day routines if available */ 330 if (rtas_function_token(RTAS_FN_GET_TIME_OF_DAY) != RTAS_UNKNOWN_SERVICE) { 331 ppc_md.get_boot_time = rtas_get_boot_time; 332 ppc_md.get_rtc_time = rtas_get_rtc_time; 333 ppc_md.set_rtc_time = rtas_set_rtc_time; 334 } 335 336 /* On pegasos, enable the L2 cache if not already done by OF */ 337 pegasos_set_l2cr(); 338 339 /* 340 * Fix the Super I/O configuration 341 */ 342 sio_init(); 343 344 /* 345 * Print the banner, then scroll down so boot progress 346 * can be printed. -- Cort 347 */ 348 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0); 349 } 350 351 static void chrp_8259_cascade(struct irq_desc *desc) 352 { 353 struct irq_chip *chip = irq_desc_get_chip(desc); 354 unsigned int cascade_irq = i8259_irq(); 355 356 if (cascade_irq) 357 generic_handle_irq(cascade_irq); 358 359 chip->irq_eoi(&desc->irq_data); 360 } 361 362 /* 363 * Finds the open-pic node and sets up the mpic driver. 364 */ 365 static void __init chrp_find_openpic(void) 366 { 367 struct device_node *np, *root; 368 int len, i, j; 369 int isu_size; 370 const unsigned int *iranges, *opprop = NULL; 371 int oplen = 0; 372 unsigned long opaddr; 373 int na = 1; 374 375 np = of_find_node_by_type(NULL, "open-pic"); 376 if (np == NULL) 377 return; 378 root = of_find_node_by_path("/"); 379 if (root) { 380 opprop = of_get_property(root, "platform-open-pic", &oplen); 381 na = of_n_addr_cells(root); 382 } 383 if (opprop && oplen >= na * sizeof(unsigned int)) { 384 opaddr = opprop[na-1]; /* assume 32-bit */ 385 oplen /= na * sizeof(unsigned int); 386 } else { 387 struct resource r; 388 if (of_address_to_resource(np, 0, &r)) { 389 goto bail; 390 } 391 opaddr = r.start; 392 oplen = 0; 393 } 394 395 printk(KERN_INFO "OpenPIC at %lx\n", opaddr); 396 397 iranges = of_get_property(np, "interrupt-ranges", &len); 398 if (iranges == NULL) 399 len = 0; /* non-distributed mpic */ 400 else 401 len /= 2 * sizeof(unsigned int); 402 403 /* 404 * The first pair of cells in interrupt-ranges refers to the 405 * IDU; subsequent pairs refer to the ISUs. 406 */ 407 if (oplen < len) { 408 printk(KERN_ERR "Insufficient addresses for distributed" 409 " OpenPIC (%d < %d)\n", oplen, len); 410 len = oplen; 411 } 412 413 isu_size = 0; 414 if (len > 0 && iranges[1] != 0) { 415 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n", 416 iranges[0], iranges[0] + iranges[1] - 1); 417 } 418 if (len > 1) 419 isu_size = iranges[3]; 420 421 chrp_mpic = mpic_alloc(np, opaddr, MPIC_NO_RESET, 422 isu_size, 0, " MPIC "); 423 if (chrp_mpic == NULL) { 424 printk(KERN_ERR "Failed to allocate MPIC structure\n"); 425 goto bail; 426 } 427 j = na - 1; 428 for (i = 1; i < len; ++i) { 429 iranges += 2; 430 j += na; 431 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n", 432 iranges[0], iranges[0] + iranges[1] - 1, 433 opprop[j]); 434 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]); 435 } 436 437 mpic_init(chrp_mpic); 438 ppc_md.get_irq = mpic_get_irq; 439 bail: 440 of_node_put(root); 441 of_node_put(np); 442 } 443 444 static void __init chrp_find_8259(void) 445 { 446 struct device_node *np, *pic = NULL; 447 unsigned long chrp_int_ack = 0; 448 unsigned int cascade_irq; 449 450 /* Look for cascade */ 451 for_each_node_by_type(np, "interrupt-controller") 452 if (of_device_is_compatible(np, "chrp,iic")) { 453 pic = np; 454 break; 455 } 456 /* Ok, 8259 wasn't found. We need to handle the case where 457 * we have a pegasos that claims to be chrp but doesn't have 458 * a proper interrupt tree 459 */ 460 if (pic == NULL && chrp_mpic != NULL) { 461 printk(KERN_ERR "i8259: Not found in device-tree" 462 " assuming no legacy interrupts\n"); 463 return; 464 } 465 466 /* Look for intack. In a perfect world, we would look for it on 467 * the ISA bus that holds the 8259 but heh... Works that way. If 468 * we ever see a problem, we can try to re-use the pSeries code here. 469 * Also, Pegasos-type platforms don't have a proper node to start 470 * from anyway 471 */ 472 for_each_node_by_name(np, "pci") { 473 const unsigned int *addrp = of_get_property(np, 474 "8259-interrupt-acknowledge", NULL); 475 476 if (addrp == NULL) 477 continue; 478 chrp_int_ack = addrp[of_n_addr_cells(np)-1]; 479 break; 480 } 481 of_node_put(np); 482 if (np == NULL) 483 printk(KERN_WARNING "Cannot find PCI interrupt acknowledge" 484 " address, polling\n"); 485 486 i8259_init(pic, chrp_int_ack); 487 if (ppc_md.get_irq == NULL) { 488 ppc_md.get_irq = i8259_irq; 489 irq_set_default_host(i8259_get_host()); 490 } 491 if (chrp_mpic != NULL) { 492 cascade_irq = irq_of_parse_and_map(pic, 0); 493 if (!cascade_irq) 494 printk(KERN_ERR "i8259: failed to map cascade irq\n"); 495 else 496 irq_set_chained_handler(cascade_irq, 497 chrp_8259_cascade); 498 } 499 } 500 501 static void __init chrp_init_IRQ(void) 502 { 503 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) 504 struct device_node *kbd; 505 #endif 506 chrp_find_openpic(); 507 chrp_find_8259(); 508 509 #ifdef CONFIG_SMP 510 /* Pegasos has no MPIC, those ops would make it crash. It might be an 511 * option to move setting them to after we probe the PIC though 512 */ 513 if (chrp_mpic != NULL) 514 smp_ops = &chrp_smp_ops; 515 #endif /* CONFIG_SMP */ 516 517 if (_chrp_type == _CHRP_Pegasos) 518 ppc_md.get_irq = i8259_irq; 519 520 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON) 521 /* see if there is a keyboard in the device tree 522 with a parent of type "adb" */ 523 for_each_node_by_name(kbd, "keyboard") 524 if (of_node_is_type(kbd->parent, "adb")) 525 break; 526 of_node_put(kbd); 527 if (kbd) { 528 if (request_irq(HYDRA_INT_ADB_NMI, xmon_irq, 0, "XMON break", 529 NULL)) 530 pr_err("Failed to register XMON break interrupt\n"); 531 } 532 #endif 533 } 534 535 static void __init 536 chrp_init2(void) 537 { 538 #if IS_ENABLED(CONFIG_NVRAM) 539 chrp_nvram_init(); 540 #endif 541 542 request_region(0x20,0x20,"pic1"); 543 request_region(0xa0,0x20,"pic2"); 544 request_region(0x00,0x20,"dma1"); 545 request_region(0x40,0x20,"timer"); 546 request_region(0x80,0x10,"dma page reg"); 547 request_region(0xc0,0x20,"dma2"); 548 549 if (ppc_md.progress) 550 ppc_md.progress(" Have fun! ", 0x7777); 551 } 552 553 static int __init chrp_probe(void) 554 { 555 const char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(), 556 "device_type", NULL); 557 if (dtype == NULL) 558 return 0; 559 if (strcmp(dtype, "chrp")) 560 return 0; 561 562 DMA_MODE_READ = 0x44; 563 DMA_MODE_WRITE = 0x48; 564 565 pm_power_off = rtas_power_off; 566 567 chrp_init(); 568 569 return 1; 570 } 571 572 define_machine(chrp) { 573 .name = "CHRP", 574 .probe = chrp_probe, 575 .setup_arch = chrp_setup_arch, 576 .discover_phbs = chrp_find_bridges, 577 .init = chrp_init2, 578 .show_cpuinfo = chrp_show_cpuinfo, 579 .init_IRQ = chrp_init_IRQ, 580 .restart = rtas_restart, 581 .halt = rtas_halt, 582 .time_init = chrp_time_init, 583 .set_rtc_time = chrp_set_rtc_time, 584 .get_rtc_time = chrp_get_rtc_time, 585 .phys_mem_access_prot = pci_phys_mem_access_prot, 586 }; 587